Inter-Integrated-Circuit-Slave interface and method for operating an inter-integrated-circuit-slave interface

Abstract

An inter-integrated circuit slave interface comprising a data line (SDA) (1) and a clock line (SCL) (2), wherein the clock line (2) has a first input buffer (3) and the data line (1) has a second input buffer (4) and an output buffer (5), wherein the data line (1) is provided for transmitting a data input signal (10) and a data output signal (11), and wherein the clock line (2) is provided for transmitting a clock signal (20), characterized in that the clock line has a first delay element (6) and the data line has a second delay element (7) and a third delay element (8), wherein the first delay element (6) is configured to delay a rising edge of the clock signal (20) by a first time (t1) and a falling edge of the clock signal by a second time (t2), and wherein the second delay element (7) is configured is,that it delays a rising edge of the data input signal (10) by a third time (t3) and a falling edge of the data input signal (10) by a fourth time (t4), wherein the third delay element (8) is configured to delay a rising edge of the data output signal (11) by a fifth time (t5) and a falling edge of the data output signal by a sixth time (t6).

Description

State of the art Inter-Integrated Circuit (I2C) interfaces are known, through which a clock generator, hereinafter also called the master device or simply master, can communicate serially with multiple slave devices. A clock signal is sent by the master via a clock line, and a data input signal and a data output signal are sent via a bidirectional data line. The data line and the clock line can be raised from a low potential to a high potential, with these potentials corresponding to two logical states. The start and end of a data transmission, as well as the data itself, are encoded by defined states or state transitions on the data line relative to the corresponding state on the clock line.The logical state change occurs instantaneously, but in reality is represented by non-zero transition times, whereby the transition times vary from component to component and may also differ for the direction of the state change (from low level to high level or vice versa) due to production tolerances, environmental influences and similar reasons. When multiple slave devices are connected to a single interface, unwanted interactions can occur. Specifically, a particular slave device might mistakenly interpret a response from another slave device as the master device's start signal, and conversely, other slave devices might mistakenly interpret a particular slave device's response as the master device's start signal. This problem is addressed in known I2C interfaces by using two delay elements: one on the data input line and one on the clock line. However, a disadvantage of this solution is that the parameters of the two delay elements, namely the delay times of the transition times, have different effects on the two problems described above, so that with only two delay elements, instead of an optimal solution, only a compromise solution can be achieved. The problem of collisions between multiple bus participants occurs when slow slave devices are operated on an I2C interface running in normal mode (100 kHz), fast mode (400 kHz), extended fast mode (1 MHz), or high-speed mode (3.4 MHz). This collision can be avoided by oversampling if the slave device's logic clock operates at a high frequency (>20 MHz). Furthermore, patent applications US 2007 / 0194824 A1 and US 6,115,318 A each disclose methods for shifting edges of data and clock signals, respectively. Disclosure of the invention One object of the present invention is to provide an I2C slave interface and a method for operating an I2C slave interface in which collisions between multiple devices on the bus are avoided, but which avoids the disadvantages of the above-mentioned prior art. This problem is solved according to the invention by a device and / or a method according to the adjacent claims. By using three delay elements, an optimal solution within the technical specifications of the I2C protocol can be achieved, since the suppression of a false start / stop signal generation is carried out by different parameters, in particular the times according to the adjacent claims, than the suppression of a false start / stop signal detection. A master device and one or more slave devices can be connected to the I2C interface according to the invention. According to the I2C protocol, an I2C interface is a serial data bus; accordingly, the clock and data lines are serial lines. The I2C bus is preferably operated in standard mode (100 kHz), but the device according to the invention can also be operated in one of the other protocol-compliant modes. Preferably, the first input buffer, the second input buffer, and the output buffer are signal drivers, wherein the input buffer receives an analog input signal and outputs a digital signal upon reaching a certain threshold, while the output buffer outputs an analog signal in response to a digital input signal, according to the specifications of the I2C protocol. This achieves the advantage of the invention that a very simple and cost-effective device, particularly in a modular design, can be built using standard components, which in turn allows for cost-effective adaptation to various requirements. The first input buffer, the second input buffer, and the output buffer particularly preferably comprise Schmitt triggers. The data input signal, data output signal, and clock signal consist of sequences of high and low potentials, which generate logical bits. The different potentials are generated at the devices connected to the bus according to methods known to those skilled in the art. The first, second, and third delay elements are preferably analog delay elements known to those skilled in the art; asynchronous analog delay elements are particularly preferred. In particular, both analog delay elements integrated into the circuit and external analog delay elements can be used. According to the present invention, this advantageously allows the device to be manufactured cost-effectively and easily modified using already known and proven components or circuits. The third and fourth times, or the fifth and sixth times, are preferably equal within the component-related and / or environmental tolerances, these tolerances being in the range of approximately 10 ns. In particular, a typical delay time for a rising flank is about 250 ns and the typical delay time for a falling flank is about 50 to 100 ns. According to a further advantageous embodiment, it is preferred according to the invention that the first and second times are equal, and / or that the third and fourth times are different, and / or that the fifth and sixth times are different, or that the times vary between equal and different within their tolerances depending on external influences. According to yet another advantageous embodiment of the device according to the invention, the first delay element, the second delay element, and the third delay element are configured such that the difference between the third and second delay times is maximized. This advantageously solves the first problem described above, namely, that a particular slave component may incorrectly interpret a response from another slave component as a start signal from the master component. The difference between the third and second delay times precisely indicates the time period by which false start and / or stop signal detection can be suppressed. Preferably, the first, second, and third delay elements are configured to also maximize the sum of the fifth and first delays. According to the present invention, this advantageously solves the second problem described above, namely that other slave components mistakenly interpret the response of a particular slave component as a start signal for the master component. The sum of the first and fifth delays indicates the time period by which false start and / or stop signal generation can be suppressed. Particularly preferably, the first delay element is configured to maximize the first time and / or the second time. According to the invention, this advantageously makes it possible to filter out transients from the clock signal. Particularly preferably, the second delay element is configured exclusively or additionally such that the third time, or, if the third and fourth times are not equal, the fourth time, is maximized. This advantageously makes it possible, according to the invention, to filter out transients from the data input signal. Maximizing the various times or time periods is preferably achieved by appropriately selecting the delay elements. The delay elements are particularly preferably controllable, so that different values ​​can be set depending on the connected devices. According to the invention, this makes it possible to achieve a particularly advantageous high degree of flexibility in the device with regard to different connected devices, especially slave components. It is particularly advantageous to combine controllable delay elements with a sensor device, so that the device adjusts the different times on the delay elements depending on the characteristics of the currently connected devices. According to an advantageous embodiment of the method according to the invention, the difference between the third time and the second time is maximized. Preferably, the sum of the fifth time and the first time is maximized, either additionally or instead. It is particularly preferred to maximize the first time and / or the second time and / or the third time in addition to or instead of the first time. All maximizations must be carried out in compliance with the I2C specifications for all time. Another object of the present invention is an application-specific integrated circuit which has an inter-integrated circuit interface according to the adjacent claims. With the device and / or method according to the invention, it is advantageously possible to solve the two problems described above, and in particular to solve them separately. Furthermore, it is possible to filter out transients from the clock signal and / or the data input signal. Another advantage is that the device according to the invention is simple, modular and cost-effective to produce and allows for easy adjustments through programming. Brief description of the drawings Fig. 1 schematically shows an advantageous embodiment of the interface according to the invention. Fig. 2 schematically shows the effect of the delay elements according to the invention. Detailed description of the drawings The present invention is described with reference to particular embodiments and the accompanying drawings, but the invention is not limited to these embodiments and drawings, but is defined by the claims. The drawings are not to be interpreted restrictively. For illustrative purposes, certain elements in the drawings may be enlarged or exaggerated, or not drawn to scale. Unless otherwise specifically stated, the use of an indefinite or definite article with reference to a singular word, for example, "a," "an," "a," "a," "the," "a," "a," also includes the plural of such a word. The terms "first," "first," "first," "second," "second," "second," and so on in the description and in the claims are used to distinguish between similar or distinguishable identical elements and not necessarily to describe a temporal or other sequence. The terms used in this way are generally to be considered interchangeable under appropriate conditions. Fig. 1 shows a schematic representation of an advantageous embodiment of the interface according to the invention. A master component is not part of the claimed I2C interface and is therefore not shown in Fig. 1, but would be located on the left in Fig. 1 and connected to a data line 1 and a clock line 2. Likewise, one or more slave components are not claimed and are therefore not shown; however, a specific slave component would be located on the right in Fig. 1 and also connected to data line 1 and clock line 2, and all other possible slave components would be located and connected in parallel to this specific slave component on the left in Fig. 1. Data line 1 is logically divided into a data input line, over which a data input signal 10 is transmitted, and a data output line, over which a data output signal 11 is transmitted. Clock line 2, separate from data line 1 and over which a clock signal 20 is transmitted, has a first input buffer 3. Data line 1 has a second input buffer 4 and an output buffer 5. Furthermore, clock line 2 has a first delay element 6, and data line 1 has a second delay element 7 and a third delay element 8. The master component provides the clock signal 20, which in particular comprises periodic signal segments of equal length occurring at equal intervals. "Equal" specifically refers to equality within given tolerances. According to the I2C protocol, the master device initiates data transmission by sending a start signal, which corresponds to a transition from high to low level on the data input line during a period of high potential on the clock line. The master then transmits the address of the slave device to be addressed, followed by information indicating whether a read or write access to the slave device is to be performed. The master or the slave device (depending on whether a read or write access is being performed) then sends an acknowledgment signal indicating that data transmission has begun. The end of the transmission is announced by the master device with another acknowledgment signal. Finally, the master can either send a stop signal indicating the end of communication or a restart signal indicating further data transmission.Furthermore, according to the I2C protocol, different points are defined for detecting a transition from high level to low level and from low level to high level. A signal segment is recognized as high level when it rises to 70% of the high level, while conversely, a signal segment is recognized as low level when it falls to 30% of the high level. Further information about the I2C protocol can be found in the online user manual. The first delay element, the second delay element, and the third delay element each delay an incoming signal by a specific time. Figure 2 shows three signal segments, each before and after passing through the first delay element 6, the second delay element 7, and the third delay element 8. The left column shows a segment of a clock signal 20. The middle column shows a segment of a data input signal 10, and the right column shows a segment of a data output signal 11. The upper section shows the original signal waveform, with solid lines indicating the points at which the transition from low level to high level or vice versa is detected, and dashed lines indicating the corresponding point after the delay by the delay element. The lower section shows the signal segments after the delay.The corresponding delay times are entered in the lower section, corresponding to the first time t1, the second time t2, the third time t3, the fourth time t4, the fifth time t5 and the sixth time t6. The first delay element 6 delays a rising edge of a clock signal 20 by a first time t1 and a falling edge of a clock signal 20 by a second time t2. The first time t1 is usually chosen to be different from the second time t2, which is due to the fact that, within the framework of the optimal solution, the second time t2 is chosen to be as small as possible, while the first time t1 is chosen to be as large as possible in order to avoid violations of the I2C protocol or the timing specifications described therein. The second delay element 7 delays a rising edge of a data input signal 10 by a third time t3 and a falling edge of a data input signal 10 by a fourth time t4. The third time t3 and the fourth time t4 are preferably equal within the tolerances attributable to production and environmental factors. The third delay element 8 delays a rising edge of a data output signal 11 by a fifth time t5 and a falling edge of a data output signal 11 by a sixth time t6. The fifth time t5 and the sixth time t6 are preferably equal within the tolerances attributable to production and environmental factors.

Claims

Inter-integrated circuit slave interface comprising a data line (SDA) (1) and a clock line (SCL) (2), wherein the clock line (2) has a first input buffer (3) and the data line (1) has a second input buffer (4) and an output buffer (5), wherein the data line (1) is provided for transmitting a data input signal (10) and a data output signal (11), and wherein the clock line (2) is provided for transmitting a clock signal (20), characterized in that the clock line has a first delay element (6) and the data line has a second delay element (7) and a third delay element (8), wherein the first delay element (6) is configured to delay a rising edge of the clock signal (20) by a first time (t1) and a falling edge of the clock signal by a second time (t2), and wherein the second delay element (7) is configuredthat it delays a rising edge of the data input signal (10) by a third time (t3) and a falling edge of the data input signal (10) by a fourth time (t4), wherein the third delay element (8) is configured to delay a rising edge of the data output signal (11) by a fifth time (t5) and a falling edge of the data output signal by a sixth time (t6). Inter-Integrated-Circuit-Slave interface according to claim 1, wherein the first time (t1) and the second time (t2) are different, wherein the third time (t3) and the fourth time (t4) are the same, and wherein the fifth time (t5) and the sixth time (t6) are the same. Inter-Integrated-Circuit-Slave interface according to claim 1 or 2, characterized in that the first input buffer (3) and / or the second input buffer (4) and / or the output buffer (5) comprise Schmitt triggers. Inter-Integrated-Circuit-Slave interface according to one of the preceding claims, characterized in that the first delay element (6) and / or the second delay element (7) and / or the third delay element (8) are analog delay elements, in particular asynchronous analog delay elements. Inter-Integrated-Circuit-Slave interface according to one of the preceding claims, characterized in that the first delay element (6) and the second delay element (7) and the third delay element (8) are configured such that, in compliance with the specifications of the Inter-Integrated-Circuit protocol for the first time (t1), the second time (t2), the third time (t3), the fourth time (t4), the fifth time (t5) and the sixth time (t6): - the difference between the third time (t3) and the second time (t2) and / or - the sum between the fifth time (t5) and the first time (t1) are maximized. Inter-Integrated-Circuit-Slave interface according to one of the preceding claims, characterized in that the first delay element (6) is configured such that, in compliance with the specifications of the Inter-Integrated-Circuit protocol for the first time (t1), the second time (t2), the third time (t3), the fourth time (t4), the fifth time (t5) and the sixth time (t6), the first time (t1) and / or the second time (t2) are maximized, and / or that the second delay element (7) is configured such that the third time (t3) is maximized. Application-specific integrated circuit comprising an inter-integrated circuit slave interface according to any of the preceding claims. A method for operating an inter-integrated circuit slave interface comprising a data line (SDA) (1) and a clock line (SCL) (2), wherein the clock line (2) has a first input buffer (3) and the data line has a second input buffer (4) and an output buffer (5), wherein the data line (1) is provided for transmitting a data input signal (10) and a data output signal (11), wherein the clock line (2) is provided for transmitting a clock signal (20), wherein the clock line has a first delay element (6) and the data line has a second delay element (7) and a third delay element (8), wherein the method comprises at least the following steps: - a rising edge of a clock signal (20) is delayed by a first time (t1), - a falling edge of a clock signal (20) is delayed by a second time (t2),- A rising edge of a data input signal (10) is delayed by a third time (t3), - A falling edge of a data input signal (10) is delayed by a fourth time (t4), - A rising edge of a data output signal (11) is delayed by a fifth time (t5), - A falling edge of a data output signal (11) is delayed by a sixth time (t6). Method according to claim 8, wherein the second time (t2) is different from the first time (t1), wherein the fourth time (t4) is equal to the third time (t3), wherein the sixth time (t6) is equal to the fifth time (t5). Method according to claim 8 or 9, characterized in that, in compliance with the specifications of the Inter-Integrated-Circuit protocol for the first time (t1), the second time (t2), the third time (t3), the fourth time (t4), the fifth time (t5) and the sixth time (t6): - the difference between the third time (t3) and the second time (t2) and / or - the sum between the fifth time (t5) and the first time (t1) are maximized. Method according to one of claims 8 to 10, characterized in that, in compliance with the specifications of the Inter-Integrated-Circuit protocol for the first time (t1), the second time (t2), the third time (t3), the fourth time (t4), the fifth time (t5) and the sixth time (t6), the first time (t1) and / or the second time (t2) and / or the third time (t3) are maximized.

Images