Methods for operating non-volatile storage devices that support efficient fault detection

Abstract

Method for operating a non-volatile storage device (100) comprising the following: a detection of errors generated during a programming operation for programming a section of a first plurality of non-volatile multibit memory cells (MC1 - MCm) in the non-volatile storage device (100), by reading the first plurality of non-volatile multibit memory cells (MC1 - MCm) and a force-bit data vector, which is verified during the programming operation to identify whether any of the first plurality of non-volatile multibit memory cells (MC1 - MCm) contain erroneous data, Target Data (TD) recovery is performed when target data (TD) recovery is needed. an output of the recovered target data (TD) to a storage controller, and a correction of an error in the recovered target data (TD) by the storage controller.

Description

AREA

[0001] This invention relates to storage devices and methods for operating them, and in particular to non-volatile storage devices and methods for operating them. BACKGROUND

[0002] Semiconductor memory devices can be volatile or non-volatile. A non-volatile semiconductor memory device retains the data it stores even when the power is turned off. Depending on the manufacturing technology used, non-volatile memory devices can be permanent or reprogrammable. Non-volatile memory devices can be used for storing user data, programs, and microcode in a wide variety of applications in the computer, avionics, telecommunications, and consumer electronics industries.

[0003] US2011 / 0182121 A1 discloses data recovery for non-volatile storage based on the number of data state-specific errors. SUMMARY

[0004] The object of the invention is to provide methods for operating a non-volatile memory device and an integrated circuit memory system according to the independent claims. Advantageous embodiments are described in the dependent claims. Methods for operating non-volatile memory devices employ several aspects of programming operations to assist in reprogramming error detection in non-volatile multibit memory cells. These error detection operations may include identifying one or more non-volatile multibit memory cells in a memory device that have undergone an unwanted reprogramming from a cleared state to an at least partially programmed state.

[0005] According to some embodiments of the invention, errors generated during an operation to program a first plurality of non-volatile multibit memory cells in a non-volatile memory device can be detected by performing a plurality of read operations to generate error detection data and then decoding the error detection data to identify specific cells containing errors. For example, a programmed first plurality of non-volatile multibit memory cells and a force-bit data vector, which was modified during the programming operation, can be read to assist in error detection.This read information, together with data read from a page buffer assigned to the first plurality of non-volatile multibit memory cells, can then be decoded to identify which of the first plurality of non-volatile multibit memory cells are erased cells that have unacceptably high threshold voltages.

[0006] To further support error detection, the programming operations can include modifying an initial force-bit data vector containing equivalent first data values ​​(for example, all "1") into a modified force-bit data vector containing a plurality of second data values, each identifying one of the first plurality of non-volatile multibit memory cells that underwent at least partial programming during the programming operation. Operations can also be performed to update data in the page buffer in response to the successful programming of one or more of the first plurality of non-volatile multibit memory cells during the programming operation.

[0007] According to further embodiments of the invention, a method for operating a non-volatile memory device may include the detection of errors generated during an operation to program a page of non-volatile multibit memory cells in the non-volatile memory device by evaluating (for example, decoding): (i) data read from the programmed page of non-volatile multibit memory cells, (ii) a force-bit data vector modified during the programming operation, and (iii) data in a page buffer associated with the page of non-volatile multibit memory cells. This evaluation is performed to identify whether any of the non-volatile multibit memory cells in the page are erased cells with unacceptably high threshold voltages (i.e., unintentionally "programmed" cells).To support these error detection operations, the programming operations may include modifying an initial force-bit data vector containing equivalent first data values ​​into a modified force-bit data vector containing a plurality of second data values. These second data values ​​identify a respective plurality of the non-volatile multibit memory cells in the page as having undergone at least partial programming during the programming operation. The programming operations may also include resetting at least some of the data in the page buffer to default values ​​in response to successful programming of one or more of the non-volatile multibit memory cells in the page during the programming operation.

[0008] According to other embodiments of the invention, a method for operating a non-volatile memory device includes changing a first multibit data value, which is assigned to a first programming state of a first non-volatile multibit memory cell in the non-volatile memory device, into a second multibit data value, which is assigned to a cleared state of the first non-volatile multibit memory cell. This data value change operation is performed in response to a verification that the first non-volatile multibit memory cell has been validly programmed into the first programming state during a programming operation.Force bit data modified during the programming operation is then read to confirm that the second multibit data value associated with the first non-volatile multibit memory cell reflects an accurately programmed cell. The programming operation may also include resetting the first multibit data value to the second multibit data value in a side buffer. Furthermore, the step of reading the modified force bit data may involve reading the side buffer, the force bit data modified during the programming operation, and a plurality of non-volatile multibit memory cells in the non-volatile storage device. This read information is then used to identify erased cells among the plurality of non-volatile multibit memory cells that exhibit unacceptably high threshold voltages.The step of reading the modified force-bit data can be preceded by an operation to load a multibit force-bit vector of equivalent logic values ​​into a force-bit register. Additionally, the operation to modify at least one section of the multibit force-bit vector in the force-bit register can be performed during the programming operation to identify a plurality of non-volatile multibit memory cells in the non-volatile storage device that have undergone intentional programming using an ISSP programming technique.

[0009] According to further embodiments of the invention, a method for operating a non-volatile memory device can include performing an error detection operation on a row of non-volatile multibit memory cells in the non-volatile memory device by reading the row of non-volatile multibit memory cells together with reading post-programming data from a page buffer and force bit data that were used during the programming of the row of non-volatile multibit memory cells. These operations are performed to identify whether any of the non-volatile multibit memory cells in the row are erased cells that have unacceptably high threshold voltages.This process can be preceded by loading the page buffer with a plurality of pages of data, followed by programming the row of non-volatile multibit memory cells with the plurality of pages of data from the page buffer. This programming of the row of non-volatile multibit memory cells can include resetting at least some of the data in the page buffer if corresponding programming states of non-volatile multibit memory cells in the row are verified as accurate. The programming of the row of non-volatile multibit memory cells can also include modifying bits of a preloaded force bit vector to demonstrate the performance of ISSP programming operations on corresponding non-volatile multibit memory cells within the row. BRIEF DESCRIPTION OF THE FIGURES

[0010] The above and other tasks and features will become apparent from the following description with reference to the following figures, wherein identical reference symbols, unless otherwise specified, refer to identical parts across the different figures, and wherein: Fig. 1 is a block diagram which schematically illustrates a non-volatile storage device according to an embodiment of the inventive concept. Fig. 2 is a block diagram which schematically shows a side buffer in Fig. Figure 1 illustrates one embodiment of the inventive concept. Fig. Figure 3 is a diagram illustrating a lower-tail data recovery procedure when a cell programming operation has failed. Fig. 4 is a diagram showing the data states of latches of a page buffer during a lower-tail data recovery operation in Fig. 3 illustrated. Fig. Figure 5 is a diagram illustrating an upper-tail data recovery procedure when a cell programming operation has been performed or has passed. Fig. 6 is a diagram showing the data states of latches of a page buffer during an upper-tail data recovery operation in Fig. 5 illustrates. Fig. Figure 7 is a diagram illustrating a data recovery procedure according to an embodiment of the inventive concept. Fig. Figure 8 is a diagram showing the data states of latches of a page buffer during a data recovery operation in Fig. 7 illustrates. Fig. 9 is a flowchart which schematically illustrates a programming procedure of a non-volatile storage device according to an embodiment of the inventive concept. Fig. 10 is a flowchart that schematically illustrates a data recovery operation, which is in Fig. 9 is described. Fig. 11 is a flowchart which schematically illustrates a programming procedure of a non-volatile storage device according to an embodiment of the inventive concept. Fig. 12 is a flowchart which schematically illustrates a programming procedure of a non-volatile storage device according to another embodiment of the inventive concept. Fig. 13 is a block diagram which schematically illustrates a side buffer according to another embodiment of the inventive concept. Fig. 14 is a diagram for describing a bit line forcing according to an embodiment of the inventive concept. Fig. 15 is a diagram which schematically illustrates a two-step verification procedure of a page buffer in Fig. 13 illustrated. Fig. 16 is a diagram which shows a variation in data of latches of a side buffer in Fig. 13 illustrates a programming operation. Fig. 17 is a diagram illustrating a variation in data of latches of a page buffer corresponding to a target state in a programming operation according to an embodiment of the inventive concept. Fig. 18 is a diagram which schematically illustrates a procedure for restoring data between a deletion state and an initial programming state. Fig. 19 is a diagram which schematically illustrates a procedure for restoring data between a deletion state and a second programming state. Fig. 20 is a diagram which schematically illustrates a procedure for restoring data between a deletion state and a third programming state. Fig. Figure 21 is a diagram which schematically illustrates an upper-bit recovery procedure during a programming operation according to an embodiment of the inventive concept. Fig. 22A and Fig. 22B Flowcharts are illustrating a multibit programming method of a non-volatile memory device according to an embodiment of the inventive concept. Fig. 23 is a flowchart illustrating a multibit programming method of a non-volatile memory device according to another embodiment of the inventive concept. Fig. 24 is a flowchart illustrating a multibit programming method of a non-volatile memory device according to yet another embodiment of the inventive concept. Fig. 25 is a flowchart illustrating a data recovery operation of a storage system according to an embodiment of the inventive concept. Fig. 26 is a flowchart illustrating a data recovery operation of a storage system according to another embodiment of the inventive concept. Fig. 27 is a flowchart illustrating a data recovery operation of a storage system according to yet another embodiment of the inventive concept. Fig. 28 is a flowchart illustrating a data recovery operation of a storage system according to yet another embodiment of the inventive concept. Fig. 29 a perspective view of a memory block according to the inventive concept. Fig. 30 is a block diagram which schematically illustrates a storage system according to an embodiment of the inventive concept. Fig. 31 is a block diagram which schematically illustrates a memory card according to an embodiment of the inventive concept. Fig. 32 is a block diagram which schematically illustrates a moviNAND according to an embodiment of the inventive concept. Fig. 33 is a block diagram which schematically illustrates a solid-state drive according to an embodiment of the inventive concept. Fig. 34 is a block diagram which schematically illustrates a communication device according to an embodiment of the inventive concept. Fig. 35 is a block diagram which schematically illustrates a smart TV system according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0011] Fig. Figure 1 is a block diagram which schematically illustrates a non-volatile storage device according to one embodiment of the inventive concept. Referring to Fig. 1. A non-volatile storage device 100 can comprise a memory cell array or arrangement 110, an address decoder 120, an input / output circuit 130, and control logic 140. The non-volatile storage device 100 can, for example, be a NAND flash memory device. However, it is understood that the non-volatile storage device 100 is not limited to NAND flash memory devices.For example, the inventive concept can be applied to a NOR flash memory device, a resistive random access memory (RRAM) device, a phase-change memory (PRAM) device, a magneto-resistive random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, a spin transfer torque random access memory (STT-RAM), and the like. Furthermore, the non-volatile memory device can be implemented such that it has a three-dimensional array structure. A non-volatile memory device with the three-dimensional array structure can be referred to as a vertical NAND flash memory device.The inventive concept can be applied to a charge-trap flash (CTF) storage device comprising a charge storage layer formed from an insulating film or a thin insulating layer, and to a flash storage device comprising a charge storage layer formed from a conductive floating gate. The inventive concept will be described below under the condition that the non-volatile storage device 100 is a NAND flash storage device.

[0012] The memory cell array 110 can contain multiple memory blocks. For ease of description, a memory block can be divided into Fig. Figure 1 illustrates this. The memory block can contain strings, each connected by bit lines BL1 to BLn (where n is a natural number). Each string can contain a string selection transistor (SST), memory cells MC1 to MCm (where m is a natural number), and a ground selection transistor (GST). The string selection transistor (SST) in each string can be driven by a voltage transmitted via a string selection line (SSL), and the ground selection transistor (GST) can be driven by a voltage transmitted via a ground selection line (GSL). Each memory cell (MC1 to MCm) can store at least one bit of data and can be driven by a voltage transmitted via a corresponding word line (WL1 to WLm).The address decoder 120 can select one from the majority of memory blocks in response to an address and can transmit word lines WL1 to WLm with word line voltages for driving (for example, a programming voltage, a pass voltage, an erase voltage, a verification voltage, a read voltage, a read pass voltage, etc.).

[0013] During a programming operation, the input / output circuit 130 can temporarily store data inputs from an external device in order to load them onto a page to be written. During a read operation, the input / output circuit 130 can read data from a page to be read in order to output it to the external device. The input / output circuit 130 can have page buffers PB1 to PBn, each corresponding to the bit lines BL1 to BLn. Each of the page buffers PB1 to PBn can have a plurality of latches for programming and read operations. In each page buffer, at least one of the plurality of latches can store target data TD for a programming operation, and the target data TD can be changed into data of a pass pattern when a programming operation of a corresponding memory cell (hereinafter referred to as a cell programming operation) is performed.Most latches can store / establish a recovery reference bit (RRB). The RRB can be a bit used to support data recovery operations and can contain information indicating a specific state to be recovered (for example, a deleted state).

[0014] The control logic 140 can control the overall operation of the non-volatile storage device 100. The control logic 140 can decode control signals and commands provided by an external memory controller and can control the address decoder 120 and the input / output circuit 130 according to the decoded result. The control logic 140 can generate a voltage generation circuit to produce voltages required to drive or operate (e.g., programming, reading, erasing, etc.) the address decoder 120, in order to transmit the voltages to the word lines WL1 to WLm and to the input / output circuit 130 for input / output of programmed page data and read page data. During a data recovery operation, the control logic 140 can perform a read operation on programmed memory cells at least once in response to a data recovery command.Control logic 140 can recover target data (TD) supplied during a programming operation using data read according to the read operation and a recovery reference bit (RRB). The data recovery instruction from the external storage controller can be provided here. A conventional non-volatile storage device can store target data in a separate location for a data recovery operation during a programming operation. For example, during a programming operation, target data can be stored in a page buffer of a non-volatile storage device or in a buffer of the external storage controller. During a conventional data recovery operation, a programming operation can be performed on a different physical page using the target data stored there.The programming operation described above may require a separate storage space to save target data for a data recovery operation.

[0015] On the other hand, the non-volatile storage device 100 of the inventive concept can restore target data using a read operation and a recovery reference bit RRB during a data recovery operation. That is, the non-volatile storage device 100 of the inventive concept may not require a separate memory location for target data TD for a data recovery operation. Therefore, it is possible to reduce the chip size using the non-volatile storage device 100 of the inventive concept.

[0016] Fig. 2 is a block diagram which schematically represents a side buffer in Fig. Figure 1 illustrates one embodiment of the inventive concept. Referring to Fig. 2. A side buffer PB1 can have a sample latch or sensier latch SL, data latches DL1 to DLk (where k is an integer) (hereinafter referred to as at least a first latch), and an additional latch AL (hereinafter referred to as a second latch). The sensier latch SL can store data indicating whether a memory cell is an "on-cell" or an "off-cell" during a programming / programming verification / read operation. For example, during a programming verification / read operation, the sensier latch SL can store data indicating an "on-cell" if a memory cell's threshold voltage is lower than a reference level, and data indicating an "off-cell" if a memory cell's threshold voltage is higher than the reference level.During a data recovery operation, the sensier latch SL can store the result of a read operation to recover target data TD, i.e., read data. Data latches DL through DLk can store target data TD that indicates a programming state during a programming operation. Data in data latches DL1 through DLk can be modified into pass pattern data when a cell programming operation is performed. This pass pattern data can represent the erasure state or erased state of a memory cell.

[0017] The additional latch AL can store a recovery reference bit RRB during a programming operation. This recovery reference bit RRB can contain information associated with a specific state for restoring an error bit. This specific state can be one previously defined by a user. For example, if a user knows that there are many error bits on a delete state, the additional latch AL can store a recovery reference bit RRB for restoring an error bit of a delete state. This means that if recovery on an error bit of a delete state is needed during a data recovery operation, the recovery reference bit RRB can be a bit indicating whether target data TD, which is fed to the page buffer PB1, corresponds to a delete state.However, a user does not need to specify a particular state. The non-volatile memory device 100 can determine a programming state in which an error bit is frequently generated and can designate that particular program state as a specific state. A page buffer PB1 can be stored in... Fig. 2 will be illustrated. The remaining page buffers PB2 to PBn, however, can be treated essentially the same as in Fig. 2 is illustrated as being configured.

[0018] A data recovery operation performed on a page buffer PB1 according to the inventive concept can be divided into a first data recovery operation and a second data recovery operation. The first data recovery operation allows data stored at data latches DL1 to DLk to be output as original target data if a cell programming operation has failed. The second data recovery operation allows target data TD to be recovered using a data recovery read operation and a recovery reference bit RRB if a cell programming operation has been performed. The page buffer PB1 of the inventive concept can be configured to recover target data TD using data stored at or near the data latches DL1 to DLk.The data latches DL1 to DLk contain the result of a data recovery read operation and a recovery reference bit RRB. A target data recovery operation (TD) will be described in more detail later.

[0019] Fig. Figure 3 is a diagram illustrating a lower-tail recovery procedure when a cell programming operation fails. In this diagram, a lower tail may not reach a target state (for example, S2), such as memory cells that are located at A and B in Fig. 3 are placed. For example, if the memory cell is a "slow" cell, it may not reach a second state S2, even though a current programming loop reaches its maximum programming loop. A memory cell placed at A may have a threshold voltage higher than a read level RD, and a memory cell placed at B may have a threshold voltage lower than the read level RD. Here, the read level RD can be a level for a data recovery operation. A memory cell placed at either A or B does not require a read operation for data recovery. The reason may be that data latches DL1 to DLk (refer to Fig. 2), which correspond to a memory cell located at A or B, store data indicating an error state of a cell programming operation. That is, data latches DL1 to DLk (refer to Fig. 2) which correspond to a memory cell located at A or B, can retain target data TD corresponding to the second state S2 that was previously loaded. Therefore, a memory cell located at A or B can be considered a lower-tail error bit, and data stored at data latches DL1 to DLk can be recovered as the original target data during a data recovery operation.

[0020] Fig. Figure 4 is a diagram showing the data states of latches of a page buffer during a lower-tail data recovery operation. Fig. Figure 3 illustrates this. Below are data states of latches during a lower-tail data recovery operation, with reference to the Fig. 2, Fig. 3 and 4 are described. For the sake of simplicity, it is assumed that the target state is a second state S2. If a target state is a second state S2, during a programming operation, data latches DL1 to DLk can receive data corresponding to the second state S2, and an additional latch AL can store a value of 0. The data latches DL1 to DLk corresponding to the second state can each store data according to whether a cell programming operation was successful or failed. If the data of the data latches DL1 to DLk has a passing pattern indicating that a cell programming operation was successful, a lower-tail data recovery operation may not be needed. On the other hand, if the data of the data latches DL1 to DLk does not have a passing pattern indicating that a cell programming operation was successful, i.e.,If data in data latches DL1 to DLk is maintained according to the second state S2, a memory cell located at A or B is considered a lower-tail error bit. Therefore, data S2 maintained at latches DL1 to DLk can be recovered as the original target data. Using the lower-tail data recovery operation described above, if data in data latches DL1 to DLk does not exhibit a pass pattern indicating a cell programming operation, it can be recovered as the original target data.

[0021] Fig. Figure 5 is a diagram illustrating an upper-tail data recovery procedure when a cell programming operation is performed. It can show an upper-tail passed or bypassed memory cell that has been overprogrammed due to a programming error (such as coupling) or a read error. An upper-tail data recovery operation can be divided into a first upper-tail recovery operation (①), which is performed during a read operation for data recovery, and a second upper-tail data recovery operation (②), which is performed using a read operation and a recovery reference bit (RRB), according to an evaluation of an upper-tail error bit. An evaluation of an upper-tail error bit can be performed according to a read operation on a memory cell that has passed the cell programming operation.For example, a memory cell located at C (judged as an ON cell based on the result of a read operation) might not be judged as an upper-tail error bit. A memory cell located at D (judged as an OFF cell) might be judged as an upper-tail error bit. A recovery reference bit (RRB) can be a value associated with an upper-tail data recovery of a first state S1. "1" can correspond to the first state S1, and "0" can correspond to the second state S2. With the first upper-tail data recovery operation, if the result of a data recovery read operation indicates an ON cell (for example, a memory cell located at C), data corresponding to the first state S1 can be recovered as target data TD.The second upper-tail data recovery operation allows data corresponding to the first state to be recovered as target data based on a value (for example, "1") of a recovery reference bit RRB in the event that a data recovery read operation results in an out cell (for example, a memory cell located at D).

[0022] Fig. Figure 6 is a diagram showing the data states of latches of a page buffer during an upper-tail recovery operation. Fig. Figure 5 illustrates this. Below are data states of latches during an upper-tail data recovery operation, with reference to the Fig. 2, Fig. 5 and Fig. 6. To simplify the description, it is assumed that a target state is a first state S1. If a target state is a first state S1, during a programming operation, data latches DL1 to DLk can receive data corresponding to the first state S1, and an additional latch AL can store a value of 1. To simplify the description, it is assumed that a cell programming operation has been performed on a memory cell corresponding to the first state S1. In this case, data from the data latches DL1 to DLk corresponding to the first state S1 can be changed into a passing pattern indicating that a cell programming operation has been performed.If a Sensier Latch SL stores data corresponding to an On cell as the result of a read operation for data recovery during an upper-tail recovery operation of the first state S1, data corresponding to the first state S1 can be recovered as target data TD based on the read data. However, a memory cell located at C may be judged not to be an upper-tail error bit. If a Sensier Latch SL stores data corresponding to an Off cell as the result of a read operation for data recovery during an upper-tail recovery operation of the first state S1, a memory cell located at D may be judged to be an upper-tail error bit of the first state S1, using the read data and a recovery reference bit RRB of 1, which is stored in the cell located at D.The additional latch AL is stored, and data S1 corresponding to the first state S1 can be restored to target data TD. In short, using the upper-tail data recovery operation described above, if data from data latches DL1 to DLk exhibits a passing pattern indicating a cell programming operation, target data TD can be restored using a data recovery read operation and a recovery reference bit RRB. A lower-tail data recovery procedure can be described with reference to the... Fig. 3 and Fig. 4 will be described, and an upper-tail data recovery procedure can be described with reference to the Fig. 5 and Fig. 6 will be described. However, it is possible to recover target data TD regardless of whether a cell programming operation was performed or failed.

[0023] Fig. Figure 7 is a diagram illustrating a data recovery procedure according to one embodiment of the inventive concept. Referring to Fig. 7. A data recovery procedure can be a combination of a lower-tail data recovery procedure and a second state S2 in Fig. 3 and an upper-tail data recovery procedure of a first state S1 in Fig. 5. Since a memory cell A / B, which is judged to be a lower-tail error bit of the second state S2, is in a state where no cell programming operation has been performed, original target data stored at data latches DL1 to DLk can be recovered as the target data TD. Since a memory cell C, which is an upper-tail of the first state S1 and is not judged to be an upper-tail error bit, is an "On" cell as a result of a read operation for data recovery, data corresponding to the first state S1 can be recovered to target data TD.Since a memory cell D, which is an upper-tail of the first state S1 and is judged to be an upper-tail bit, is an out cell as a result of a read operation for data recovery, and a recovery reference bit RRB has a value of "1", indicating a recovery of an upper-tail error bit of the first state S1, data corresponding to the first state S1 can be recovered to target data TD.

[0024] Fig. Figure 8 is a diagram showing the data states of latches of a page buffer during a data recovery operation in Fig. 7 illustrates. Referring to the Fig. 2, Fig. 7 and Fig. 8. Data states of latches can be recovered during a data recovery operation from a combination of data states of latches on a second state of S2 in Fig. 4 and data states latches on a first state S1 in Fig. 6 are formed. As in Fig. As illustrated in Figure 8, if the data from data latches DL1 to DLk on a second state S2 does not represent a passing pattern indicating a cell programming operation, a memory cell located at A or B can be judged to be a lower-tail error bit of the second state S2, and data stored at data latches DL1 to DLk can be directly recovered as the data TD. However, if the data from data latches DL1 to DLk on the first state S1 represents a passing pattern indicating a cell programming operation, and data corresponding to an "On" cell is stored at a sensier latch SL as the result of a read operation for data recovery, then data S1 corresponding to the first state can be recovered as the target data TD based on the read data.In this case, a memory cell located at B may not be judged to be an upper-tail error bit. If data from data latches DL1 to DLk on the first state S1 form a passing pattern indicating a completed cell programming operation, and data corresponding to an out cell is stored at a sensier latch SL as the result of a read operation for data recovery, then a memory cell located at D may be judged to be an upper-tail error bit of the first state S1 based on the read data and a recovery reference bit RRB. Data S1 corresponding to the first state S1 can then be recovered as target data TD. In short, using the data recovery operation described above, if a cell programming operation fails, original target data stored at data latches DL1 to DLk can be recovered as target data TD.When a cell programming operation has been performed, target data TD can be recovered using a data recovery read operation and a recovery reference bit RRB.

[0025] Fig. Figure 9 is a flowchart that schematically illustrates a programming procedure for a non-volatile memory device according to an embodiment of the inventive concept. Referring to Fig. Operation 9 allows a programming operation to be performed using target data TD. In Operation S110, page buffers PB1 to PBn, which correspond to memory cells, can each be set by a recovery reference bit RRB. Operation S120 assesses whether a data recovery operation is needed. Here, the data recovery operation can be initiated if an entire programming operation has failed or if a data recovery command is received from an external device. If a data recovery operation is not needed, a programming operation can be terminated. If a data recovery operation is needed, Operation S130 allows target data TD to be recovered using data latches DL1 to DLk, a read operation on memory cells, and a recovery reference bit RRB.

[0026] Fig. 10 is a flowchart that schematically depicts a data recovery operation which is performed in Fig. As described in section 9, this is illustrated. Referring to Fig. Operation S131 can be used to assess whether data from data latches DL1 to DLk exhibits a passage pattern indicating a cell programming operation has been performed. If data from data latches DL1 to DLk does not have a passage pattern, they can retain the original target data. This could be because a cell programming operation failed. Operation S132 allows for the direct recovery of original target data from data latches DL1 to DLk. Conversely, if data from data latches DL1 to DLk does have a passage pattern, i.e., if a cell programming operation has been performed, Operation S133 can be used to perform a read operation for data recovery. Operation S134 can then assess whether the read data is from cell data.

[0027] If the read data is not off-cell data but on-cell data, operation S135 can restore data corresponding to a first state S1 to target data TD based on a passing pattern of the data latches DL1 to DLk and the read data. If the read data is off-cell data, operation S136 can retrieve an upper-tail error bit (for example, D in Fig. 7) The first state S1 is evaluated according to the data of the data latches DL1 to DLk, the read data, and a recovery reference bit RRB, and data S1 corresponding to the first state S1 can be recovered as target data TD. The data recovery operation allows target data TD to be recovered using data from the data latches DL1 to DLk, read data, and a recovery reference bit RRB.

[0028] Fig. Figure 11 is a flowchart that schematically illustrates a programming procedure for a non-volatile memory device according to an embodiment of the inventive concept. A programming procedure for a non-volatile memory device will be described below with reference to the accompanying drawings. In operation S210, target data TD can be loaded onto at least one first latch (for example, data latches DL1 to DLk), and a recovery reference bit RRB can be stored at a second latch (for example, an additional latch AL). In operation S220, the control logic 140 can control an address decoder 120 and an input / output circuit 130 such that the loaded target data TD is programmed into selected memory cells.For example, programming voltages can be applied to word lines connected to memory cells such that threshold voltages of the memory cells reach programming states corresponding to the target data TD. In operation S230, a program verification operation can be performed to assess whether the memory cells are programmed correctly. This program verification operation can be a read operation performed using a verification level of each memory cell. Once a verification operation has been performed on each memory cell, data latches DL1 to DLk of a page buffer corresponding to a memory cell can be written with pass pattern data (for example, data indicating a cleared state).Accordingly, a pass / fail result of an overall programming verification operation can be assessed according to data stored in the data latches DL1 to DLk of each page buffer.

[0029] If the program verification operation is successful, the programming operation can be determined as completed in Operation 240. The procedure then proceeds to Operation S250. If the programming verification operation fails, the programming operation can be determined as failed in Operation S245. The procedure then proceeds to Operation S260. In Operation S250, it can be assessed whether target data recovery (TD) is required. A target data recovery (TD) operation can be performed in response to a data recovery command issued to a non-volatile storage device (100) by an external device.

[0030] As described above, although the programming operation is determined to be completed, a lower-tail error bit (for example, A and B in the Fig. 3 and Fig. 7) a second state S2 exists. The reason may be that an upper-tail error bit (for example, D in the Fig. 5 and Fig. 7) a first state S1 exists and the programming operation has been performed. Therefore, it is necessary to restore the upper- or lower-tail error bit to improve data reliability.

[0031] In exemplary embodiments, a storage system requiring high data reliability can be configured to provide a data recovery command for the non-volatile storage device 100 at any time during a programming operation for data reliability. In other exemplary embodiments, a data recovery command can be provided instantaneously for the non-volatile storage device 100 from an external device according to information associated with a programming error.

[0032] If target data recovery (TD) is required, target data (TD) can be recovered using at least one read operation and a recovery reference bit (RRB) stored at a second latch. A target data recovery operation equivalent to operation S260 can then be performed in the same way as described in the... Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9 to Fig. As described in section 10, a description of this operation is therefore omitted. In operation S280, a copy-back program operation can be performed to program the recovered target data TD on a new physical side. The procedure can then be terminated. If a data recovery operation is required, an error bit (for example, an upper-tail error bit / lower-tail error bit) of a specific state can be recovered using data from data latches DL1 to DLk, at least one read operation, and a recovery reference bit RRB. Target data TD recovered by a data recovery operation can be used directly for a new programming operation. However, the inventive concept is not limited to this.For example, an error in the recovered target data TD can be corrected and the corrected target data TD can be used for a new programming operation.

[0033] Fig. Figure 12 is a flowchart which schematically illustrates a programming procedure for a non-volatile memory device according to another embodiment of the inventive concept. A programming procedure in Fig. 12 can go directly to the one in Fig. 11, with the exception that operations S275 and S270 are added. In operation S275, recovered target data can be output to an external storage controller. In operation S270, the storage controller can correct an error in the recovered target data. For example, the storage controller can correct an error in the recovered target data using an error correction code (ECC). However, the inventive concept is not limited to this. An error correction operation can be performed by an ECC circuit provided within a non-volatile storage device 100. Using a programming method of the inventive concept, it is possible to improve data reliability by correcting an error in recovered target data. A page buffer PB1 in Fig. 2. An additional latch AL can be used to store a recovery reference bit (RRB). This additional latch AL can also be used as a latch with a different function. For example, it can be used as a forcing bit latch for bitline forcing.

[0034] As described below, a bitline forcing operation can be performed to apply a voltage to a bitline during a programming operation that uses a two-step verification procedure. This voltage is higher than a bitline programming voltage (for example, a ground voltage) and lower than a bitline inhibition voltage (for example, a power supply voltage). The two-step verification procedure can be performed to verify a programming state and may include a pre-verification operation, performed using a first voltage level, and a main verification operation, performed using a second voltage level. The two-step verification procedure is disclosed in U.S. Patents US 7692970 B2 and US 8068361 B2 and U.S. Patent Publications US 2011 / 0051520 A1 and US 2011 / 0110154 A1.

[0035] Fig. Figure 13 is a block diagram which schematically illustrates a side buffer according to another embodiment of the inventive concept. Referring to Fig. A page buffer PB1' can have a sensing latch (SL), an upper bit latch (ML), a lower bit latch (LL), and a forcing bit latch (FL). Destination data (TD) can have an upper bit (or most significant bit: MSB) and a lower bit (or least significant bit: LSB). During a programming operation, the upper bit (MSB) can be stored at the upper bit latch (ML), and a lower bit (LSB) can be stored at the lower bit latch (LL). A bitline forcing bit (BFB) can be stored at the forcing bit latch (FL). The forcing bit latch (FL) can also be used as an additional latch, storing a recovery reference bit (RRB). The bitline forcing bit (BFB) can be used as a recovery reference bit (RRB) during a data recovery operation. The reason may be that a special relationship exists between the bit line forcing bit BFB and the recovery reference bit RRB.

[0036] Since a clear state does not require a programming operation, bitline forcing may not be necessary. Similarly, the change or probability of generating an upper-tail error bit due to a programming / read error may be high. Therefore, data stored at the forcing bit latch FL can be used as a bitline forcing bit BFB, indicating whether bitline forcing is being performed, or as a recovery reference bit RRB to restore an upper-tail error bit from a clear state. On the other hand, since a programming state requires a programming operation, bitline forcing may be necessary. Likewise, the change or probability of generating an upper-tail error bit may be lower compared to the clear state. If a programming operation has been performed, pass pattern data can be stored at the upper- and lower-bit latches ML and LL, respectively.The passing data pattern can be data (for example, "11") corresponding to a delete state. If a cell programming operation is performed, target data TD, data from the upper and lower bit latches ML and LL, and data from the forcing bit latch FL can be recovered using a read operation for data recovery. If a cell programming operation fails, data stored at the upper and lower bit latches ML and LL can be directly recovered as the original target data. The page buffer PB1' of the inventive concept can be configured to recover target data TD, data from the upper and lower bit latches ML and LL, and data from the forcing bit latch FL using a read operation for data recovery.

[0037] Fig. Figure 14 is a diagram describing bit-line forcing according to an embodiment of the inventive concept. Referring to Fig. 14. If a programming voltage VWL is applied to a word line during a programming operation of a memory cell ①, which has a threshold voltage in a first region RA, a bit line programming voltage BLPV (for example, 0 volts) can be applied to a bit line. If the programming voltage VWL is applied to the word line during a programming operation of a memory cell 2, which has a threshold voltage in a second region RB, a slightly increased bit line forcing voltage BLFV can be applied to a bit line.

[0038] When a programming loop is iterated, a memory cell in area RA far from a target state P can be programmed to an adjacent area RB, and a memory cell in the adjacent area RB can be programmed to the target state P. Here, it is assumed that the bit-line programming voltage BLPV can be 0 volts and a bit-line programming inhibitor voltage BLIV can be a power supply voltage VDD. Memory cell ① in area RA can be programmed by a difference (VWL) between a word-line voltage VWL and a bit-line voltage VBL. Memory cell 2 in area RB can be programmed by a difference (VWLP-BLFV) between the word-line voltage VWL and the bit-line voltage VBL.A memory cell ③ that enters the target state P can be a program-inhibited cell, but a difference (VWL-VDD) between the word line voltage VWL and the bit line voltage VBL can be applied to memory cell ③. Compared to memory cell ① in the region RA, the memory cell in the region RB can be programmed more precisely.

[0039] A bit-forcing duration can be the length of time during which a bit-forcing voltage BLFV is applied to a memory cell in a region RB adjacent to the target state P during a programming operation. Bit-forcing can begin or occur when a threshold voltage exceeds a predetermined value but is less than a lower limit of a target state. A bit-forcing bit BFB can indicate whether or not bit-forcing should be performed. For example, if a bit-forcing bit BFB of "0" is stored at a forcing bit latch FL, bit-forcing can be performed during the next programming loop. However, if a bit-forcing bit BFB of "1" is stored at the forcing bit latch FL, no bit-forcing can be performed during the next programming loop. As described by Fig. As shown in 14, ΔISPP > (BLFV - BLPV) and ΔISPP > (BLIV-BLFV).

[0040] Fig. 15 is a diagram which schematically illustrates a two-step verification procedure of a page buffer in Fig. 13 illustrated. Fig. Figure 15 illustrates a clear state E and the first to third programming states P1, P2, and P3. If target data TD indicates a clear state E and a memory cell has a threshold voltage corresponding to clear state E, a bit line inhibitor voltage BLIV (for example, a power supply voltage) can be applied to a bit line corresponding to the memory cell during a programming operation. Here, target data TD can be the data to be programmed.

[0041] If target data TD indicates the first programming state P1 and a memory cell has a threshold voltage higher than the erase state E and lower than a first pre-verification level PVR1, a bit-line programming voltage BLPV (e.g., a ground voltage) can be applied to a bit line corresponding to the memory cell during a programming operation. Similarly, if target data TD indicates the first programming state P1 and a memory cell has a threshold voltage higher than the first pre-verification level PVR1 and lower than a first verification level VR1, a bit-line forcing voltage BLFV (e.g., 1 volt) can be applied to a bit line corresponding to the memory cell during a programming operation.

[0042] A memory cell in the EA area can reach the first programming state P1 through the EB area or can reach the first programming state P1 directly. Until a memory cell reaches the first programming state P1, a bit line voltage can be changed from a lower bit line programming voltage BLPV to a higher bit line forcing voltage BLFV, or from the bit line forcing voltage BLFV to a bit line programming inhibitor voltage BLIV, according to an increment in a programming loop. Alternatively, a bit line voltage can be changed from the bit line programming voltage BLPV to the bit line programming inhibitor voltage BLIV, according to an increment in a programming loop.

[0043] If the target data TD indicates the second programming state P2 and a memory cell has a threshold voltage higher than the first programming state P1 and lower than a second verification level PVR2, a bit-line programming voltage BLPV can be applied to a bit line corresponding to the memory cell during a programming operation. Likewise, if the target data TD indicates the second programming state P2 and a memory cell has a threshold voltage higher than the second pre-verification level PVR2 and lower than a second verification level VR2, a bit-line forcing voltage BLFV can be applied to a bit line corresponding to the memory cell during a programming operation.

[0044] If target data TD indicates the second programming state P2 and a memory cell has a threshold voltage higher than the third programming state P3 and lower than a third pre-verification level PVR3, a bit-line programming voltage BLPV can be applied to a bit line corresponding to the memory cell during a programming operation. Similarly, if target data TD indicates the third programming state P3 and a memory cell has a threshold voltage higher than the third pre-verification level PVR3 and lower than a third verification level VR3, a bit-line forcing voltage BLFV can be applied to a bit line corresponding to the memory cell during a programming operation.

[0045] In summary, during a programming operation, a bit-line programming voltage (BLPV) can be applied to a bit line in any programming state until a pre-verification operation is performed. After the pre-verification operation, a bit-line forcing voltage (BLFV) can be applied to a bit line until a full verification operation is performed. Once the full verification operation is performed, a bit-line programming inhibitor voltage (BLIV) can be applied to a bit line.

[0046] As in Fig. As illustrated in Figure 15, a memory cell to be programmed with target data TD corresponding to a clear state E does not necessarily require bitline forcing, and a memory cell to be programmed with target data TD corresponding to one of the first to third states P1 to P3 may require bitline forcing. The clear state E can be overprogrammed due to a programming error or a read error, as illustrated by a dashed line. As with reference to the Fig. 5 and Fig. As described in section 6, a value indicating whether bit line forcing is being performed can be used as a recovery reference bit RRB to recover upper-tail data from the erase state E.

[0047] A non-volatile storage device 100 of the inventive concept can perform a data recovery operation by using a bit line forcing bit BFB as a recovery reference bit RRB without an additional latch for storing the recovery reference bit RRB.

[0048] Fig. 16 is a diagram showing a variation in data of latches of a side buffer in Fig. Figure 13 illustrates a programming operation. Below is a variation in data from latches of a page buffer in Fig. 13 during a programming operation with reference to the Fig. 13, Fig. 14, Fig. 15 to Fig. 16. Here, a programming operation can be a second-page programming operation (or an upper-bit page programming operation). When a second-page programming operation begins, the states of latches ML, LL, and FL can be as follows. In the case of a page buffer corresponding to a memory location whose target state is a clear state E, the upper-bit latch ML can store a value of "1", the lower-bit latch LL can store a value of "1", and the forcing-bit latch FL can store a value of "1". In the case of a page buffer corresponding to a memory location whose target state is a first programming state P1, the upper-bit latch ML can store a value of "0", the lower-bit latch LL can store a value of "1", and the forcing-bit latch FL can store a value of "1".In the case of a side buffer corresponding to a memory cell whose target state is a second programming state P2, the upper bit latch ML can store a value of "0", the lower bit latch LL can store a value of "0", and the forcing bit latch FL can store a value of "1". In the case of a side buffer corresponding to a memory cell whose target state is a third programming state P3, the upper bit latch ML can store a value of "1", the lower bit latch LL can store a value of "0", and the forcing bit latch FL can store a value of "1".

[0049] After the second page programming operation is complete, the states of the latches ML, LL, and FL can be as follows. In the case of a page buffer corresponding to a memory location whose target state is the erase state E or a programming state, the upper bit latch ML can maintain a value of "1", the lower bit latch LL can maintain a value of "1", and the forcing bit latch FL can maintain a value of "1". In the case of a page buffer corresponding to a memory location whose target state is the first programming state P1, data in the upper bit latch ML can be changed from "0" to "1", the lower bit latch LL can maintain a value of "1", and data in the forcing bit latch FL can be changed from "1" to "0".Since a programming operation to program a memory cell into the first programming state P1 is performed, the upper bit latch ML and the lower bit latch LL can store a data pattern of "11", corresponding to the erase state E. Likewise, since bit line forcing is performed, the forcing bit latch FL can store a value of "0".

[0050] In the case of a side buffer corresponding to a memory cell whose target state is the second programming state P2, data in the upper bit latch ML can be changed from "0" to "1", data in the lower bit latch LL can be changed from "0" to "1", and data in the forcing bit latch can be changed from "1" to "0". Since a programming operation to program a memory cell into the second programming state P2 is performed, the upper bit latch ML and the lower bit latch LL can store a data pattern of "11", which corresponds to the erase state E. Likewise, since bit line forcing is performed, the forcing bit latch FL can store a value of "0".

[0051] In the case of a side buffer corresponding to a memory cell whose target state is the third programming state P3, the upper bit latch ML can retain a value of "1", data in the lower bit latch LL can be changed from "0" to "1", and data in the forcing bit latch FL can be changed from "1" to "0". Since a programming operation to program a memory cell is performed in the third programming state P3, the upper bit latch ML and the lower bit latch LL can store a data pattern of "11", which corresponds to the erase state E. Likewise, since bitline forcing is performed, the forcing bit latch FL can store a value of "0".

[0052] Fig. Figure 17 is a diagram illustrating a variation in data of latches of a page buffer corresponding to a target state during a programming operation according to an embodiment of the inventive concept. Referring to Fig. 17. A clear state E can correspond to data “11”, a first programming state P1 to data “01”, a second programming state P2 to data “00”, and a third programming state to data “10”. However, the inventive concept is not limited to this. If a target state is the clear state E, a variation in data stored at latches ML, LL, and FL of a side buffer corresponding to a memory cell will be as follows. The upper-bit latch ML and the lower-bit latch LL can store “1” regardless of a memory cell's threshold voltage. Since no bit-line forcing is required, the forcing-bit latch FL can store “1”.

[0053] If a target state is the first programming state P1, the variation in data at the latches ML, LL, and FL of a side buffer corresponding to a memory cell to be programmed will be as follows. Until a memory cell's threshold voltage exceeds a first verification level VR1 (i.e., before a first verification operation is performed), the upper bit latch ML can store "0" and the lower bit latch LL can store "1". After a memory cell's threshold voltage exceeds the first verification level VR1 (i.e., after the first verification operation is performed), both the upper bit latch ML and the lower bit latch LL can store "1". That is, after the first verification operation is performed, the upper bit latch ML can store "1", and the lower bit latch LL can store the same pass pattern data as data corresponding to the erase state E.

[0054] Until the threshold voltage of a memory cell exceeds a first pre-verification level PVR1 (i.e., before the first pre-verification operation is performed), the forcing bit latch FL can store "1". After the threshold voltage of a memory cell exceeds the first pre-verification level PVR1 (i.e., after the first pre-verification operation is performed), the forcing bit latch FL can store "0". When "0" is stored at the forcing bit latch FL, bitline forcing can be performed during the next programming loop. That is, a bitline forcing voltage BLFV can be applied to a bitline during the next programming loop.

[0055] If a target state is the second programming state P2, the variation in data at the latches ML, LL, and FL of a side buffer corresponding to a memory cell to be programmed will be as follows: Until a memory cell's threshold voltage exceeds a second verification level VR2 (i.e., before a second verification operation is performed), the upper-bit latch ML and the lower-bit latch LL can store "0". After a memory cell's threshold voltage exceeds the second verification level VR2 (i.e., after the second verification operation is performed), both the upper-bit latch ML and the lower-bit latch LL can store "1". Until a memory cell's threshold voltage exceeds a second pre-verification level PVR2 (i.e., before a second pre-verification operation is performed), the forcing-bit latch can store "1".After a memory cell's threshold voltage exceeds the second pre-verification level PVR2 (i.e., after the second pre-verification operation has been performed), the forcing bit latch FL can store "0". When "0" is stored at the forcing bit latch FL, a bit line forcing can be performed during the next programming loop (i.e., the next ISSP pulse).

[0056] If a target state is the third programming state P3, the variation in data at the latches ML, LL, and FL of a side buffer corresponding to a memory cell to be programmed will be as follows. Until a memory cell's threshold voltage exceeds a third verification level VR3 (i.e., before a third verification operation is performed), the upper-bit latch ML can store "1" and the lower-bit latch LL can store "0". After a memory cell's threshold voltage exceeds the third verification level VR2 (i.e., after the third verification operation is performed), both the upper-bit latch ML and the lower-bit latch LL can store "1". Until a memory cell's threshold voltage exceeds a third pre-verification level PVR3 (i.e., before a third pre-verification operation is performed), the forcing-bit latch FL can store "1".After a memory cell's threshold voltage exceeds the third pre-verification level PVR3 (i.e., after the third pre-verification operation has been performed), the forcing bit latch FL can store "0". When "0" is stored at the forcing bit latch FL, a bitline forcing can be performed during the next programming loop (i.e., during the next ISPP pulse). As described above, when a verification operation is performed on a target state, data from the upper bit latch ML and the lower bit latch LL can be changed to pass pattern data (for example, "11"). When a pre-verification operation is performed on a target state, data from the forcing bit latch FL can be changed to data (for example, "0") that orders the execution of a bitline forcing during the next programming loop.

[0057] Fig. Figure 18 is a diagram that schematically illustrates a procedure for restoring data between a deleted state and an initial programming state. Referring to Fig. 18 If a target state is a deletion state E, a memory cell Ea can have a threshold voltage lower than a first pre-verification voltage PV1, a memory cell Eb can have a threshold voltage higher than the first pre-verification voltage PV1 and lower than a first verification voltage V1, and a memory cell Ec can have a threshold voltage higher than the first verification voltage V1.

[0058] If a target state is a first programming state P1, a memory cell P1a can have a threshold voltage that is lower than the first pre-verification voltage PV1, a memory cell P1b can have a threshold voltage that is higher than the first pre-verification voltage PV1 and lower than the first verification voltage V1, and a memory cell P1c can have a threshold voltage that is higher than the first verification voltage V1.

[0059] Values ​​stored in latches ML, LL, SL, and FL, which are assigned to each memory cell, can be as shown in the table of Fig. Figure 18 illustrates this. The upper bit latch (ML) can store the upper bit (MSB) of a target state, the lower bit latch (LL) can store the lower bit (LSB) of the target state, the sensier latch (SL) can store a value obtained by performing a read operation using an initial read level (RD1) for a data recovery operation, and the forcing bit latch (FL) can store a bit line forcing bit (BFB). When a cell programming operation is performed, the upper bit latch (ML) and the lower bit latch (LL) can be written with logical "1" values. If the result of the read operation indicates an "on" cell, the sensier latch (SL) can store "1". If the result of the read operation indicates an "off" cell, the sensier latch (FL) can store "0". The bit line forcing bit (BFB) can be "1" if no bit line forcing is performed, and "0" if bit line forcing is performed.

[0060] If the target state is the erase state E, the upper and lower bit latches ML and LL, which are assigned to each of the memory cells Ea, Eb and Ec, can store "1", the sensier latch SL, which is assigned to memory cell Ea, can store "1", the sensier latch SL, which is assigned to the remaining memory cells Eb and Ec, can store "0", and the forcing bit latches FL, which are assigned to memory cells Ea, Eb and Ec, can store "1".

[0061] If the target state is the first programming state P1, the upper bit latch ML, which is assigned to each of memory cells P1a and P1b, can store "0", the upper bit latch ML, which is assigned to a memory cell P1c, can store "1", the lower bit latches LL, which are assigned to each of the memory cells P1a, P1b and P1c, can store "1", the sense latch SL, which is assigned to memory cell P1a, can store "1" (i.e., the on cell), the sense latches SL, which are assigned to the remaining memory cells P1b and P1c, can store "0", the forcing bit latches FL, which are assigned to memory cell P1a, can store "1" and the forcing bit latches FL, which are assigned to memory cells P1b and P1c, can store "0".

[0062] As seen through dotted rectangles in Fig. As illustrated in Figure 18, the latches ML, LL, and SL, which are assigned to memory cells Eb, Ec, and P1c, can store the same data. Therefore, it is difficult to find a target state through a read operation for data recovery using an initial read level RD1. In this case, whether a target state is a delete state E or an initial program state P1 can be determined according to a value stored at a forcing bit line FL. For example, a value stored at a forcing bit latch FL of each of memory cells Eb and Ec can be "1", and a value stored at a forcing bit latch FL of memory cell P1c can be "0".Although the latches ML, LL, and SL, which are assigned to the memory cells Eb, Ec, and P1c, store the same data, whether a target state is a clear state E or an initial programming state P1 can be restored exactly according to a value stored on a forcing bit line FL. Fig. Paragraph 18 illustrates the case where a first read level RD1 is lower than a first pre-verification level PV1. However, the inventive concept is not limited to this. For example, the first read level RD1 can be set or chosen such that it is higher than the first pre-verification level PV1 and lower than a first verification level V1.

[0063] Fig. Figure 19 is a diagram that schematically illustrates a procedure for restoring data between a deleted state and a second programming state. Referring to Fig. 19. If a target state is a clear state E, a memory cell Ed can have a threshold voltage that is lower than a second pre-verification voltage PV2, and a memory cell Ee can have a threshold voltage that is higher than the second pre-verification voltage PV2 and lower than a second verification voltage V2. If a target state is a second programming state P2, a memory cell P2a can have a threshold voltage that is lower than the second read level RD2, a memory cell P2b can have a threshold voltage that is higher than the second read level RD2 and lower than a second pre-verification voltage PV2, a memory cell P2c can have a threshold voltage that is higher than the second pre-verification voltage PV2 and lower than a second verification voltage V2, and a memory cell P2d can have a threshold voltage that is higher than the second verification voltage V2.

[0064] Values ​​stored in latches ML, LL, SL, and FL, which are assigned to each memory cell, can be, as in Fig. Figure 19 illustrates this. As shown by the dotted rectangles in Fig. As illustrated in Figure 19, the latches ML, LL, and SL, which are assigned to memory cells Ee and P2d, can store the same data. Therefore, it is difficult to find a target state for data recovery through a read operation using a second read level RD2. If a value stored at a forcing bit latch FL1 is "1", a target state can become a delete state E. If a value stored at a forcing bit latch FL is "0", a target state can become a second programming state P2.

[0065] Fig. Figure 20 is a diagram that schematically illustrates a procedure for restoring data between a deleted state and a third programming state. Referring to Fig. 20. If a target state is a delete state E, a memory cell Ef can have a threshold voltage that is lower than a third pre-verification voltage PV3, and a memory cell Eg can have a threshold voltage that is higher than the third pre-verification voltage PV3 and lower than a third verification voltage V3. If a target state is a third programming state P3, a memory cell P3a can have a threshold voltage that is lower than the third pre-verification voltage PV3, a memory cell P3b can have a threshold voltage that is higher than the third pre-verification voltage PV3 and lower than a third verification voltage V3, and a memory cell P3c can have a threshold voltage that is higher than the third verification voltage V3.

[0066] Values ​​stored in latches ML, LL, SL, and FL, which are assigned to each memory cell, can be, as in Fig. 20 is illustrated. As in Fig. As illustrated by dotted rectangles in Figure 20, the latches ML, LL, and SL, which are assigned to memory cells Eg and P3c, can store the same data. Therefore, it is difficult to find a target state for data recovery through a read operation using a third read level RD3. If a value stored at a forcing bit latch is "1", a target state can become a delete state E. If a value stored at a forcing bit latch FL is "0", a target state can become a third programming state P3.

[0067] In the Fig. Cases 18-20 illustrate situations where a data recovery operation requires three read operations. However, the inventive concept is not limited to these. Target data can be recovered in various ways by combining data from data latches ML and LL, data from a sensier latch SL according to a read operation, and data from a forcing bit latch FL. For example, it is possible to recover an upper bit through a single read operation for data recovery.

[0068] Fig. Figure 21 is a diagram that schematically illustrates an upper-bit recovery procedure during a programming operation according to an embodiment of the inventive concept. Referring to Fig. Section 21 describes an upper-bit recovery procedure for each of states E, P1, P2, and P3 during a data recovery operation as follows. First, an upper-bit recovery procedure will be described if a target state is a delete state E. If "1" is stored at an upper-bit latch ML, a lower-bit latch LL, and a forcing-bit latch FL, a target state can be determined to be the delete state E. As described in Fig. As illustrated in Figure 18, a state where "1" is stored at the upper-bit latch ML, the lower-bit latch LL, and the forcing-bit latch FL can only specify the erase state E. In this case, during a programming operation, an upper-tail error bit of the erase state E can be recovered from a data state of the latches ML, LL, and FL. The "1" stored at the forcing-bit latch FL can be output as an upper bit of the erase state E.

[0069] An upper-bit recovery operation, if the target state is a programming state P1 / P2 / P3, can be divided into two recovery operations, first RCV and second RCV. In the first recovery operation, first RCV, data of the forcing-bit latch FL can be changed from "1" to "0" if "0" is the value of the upper-bit latch ML of a page buffer corresponding to a memory location that has not undergone programming. As in Fig. As illustrated in Figure 18, if "0" is stored in the upper bit latch ML for the first and second programming states P1 and P2, the data of the forcing bit latch FL can be changed to "0" during the first recovery operation (first RCV). Therefore, if a target state is the first / second programming state P1 / P2, the forcing bit latch FL can ultimately store "0". This "0", which is ultimately stored in the forcing bit latch FL, can then be output as the upper bit of the first and second programming states P1 and P2.

[0070] During the second recovery operation (second RCV), a read operation can be performed using a third read level, RD3. If a memory cell is judged as an off cell according to the result of a read operation, the data of the forcing bit latch, FL, can be changed from "0" to "1". As described in Fig. As illustrated in Figure 18, data from the forcing bit latch FL can be changed to "1" in the third programming state P3. It is assumed that upper-tail error bits from the first and second programming states P1 and P2 are unlikely to be generated during the second recovery operation (second RCV). Based on this assumption, "1", which is ultimately stored in the forcing bit latch FL, can be output as an upper bit of the third programming state P3. Using the data recovery operation described above, it is possible to recover target data (upper bits) using data from data latches ML and LL, data from a forcing bit latch FL, and a read operation. An upper bit recovery operation can be performed with reference to... Fig. 21 can be described. Similarly, a lower bit can be recovered using data from latches ML, LL, and FL and a read operation.

[0071] The Fig. 22A and Fig. Figures 22B are flowcharts illustrating a multibit programming method for the non-volatile memory device according to an embodiment of the inventive concept. A multibit programming method for a non-volatile memory device is described with reference to the Fig. 1, Fig. 13, Fig. 22A and Fig. 22B will be described.

[0072] In operation S311, an upper bit (MSB) can be loaded onto an upper bit latch (ML), and a lower bit (LSB) can be loaded onto a lower bit latch (LL). At this time, a forcing bit latch (FL) can be set or selected with a default forcing bit (e.g., "1"). Alternatively, a default forcing bit (e.g., "1") can be stored in the forcing bit latch (FL). This default forcing bit can contain data indicating that bitline forcing is not performed.

[0073] In operation S312, a bit line voltage VBL can be determined based on data stored at the upper bit latch ML and the forcing bit latch FL, and a programming pulse VWL can be applied to a word line. For example, if the data stored at the upper bit latch ML is "0" and the data stored at the forcing latch FL is "1", the bit line voltage VBL can be set to a bit line programming voltage BLPV, i.e., a ground voltage GND. If the data stored at the upper bit latch ML is "0" and the data stored at the forcing bit latch is "1", the bit line voltage VBL can be set to a bit line forcing voltage BLFV. If the data stored at the upper bit latch ML is "1", the bit line voltage VBL can be set to a bit line inhibitor voltage BLIV, i.e., a power supply voltage VDD.The programming pulse can increase according to one iteration of programming loops.

[0074] In operation S313, a pre-verification operation can be performed, and its success can be assessed. If the pre-verification operation is deemed successful, operation S314 can change the bit line forcing bit BFB of the forcing bit latch FL from "1" to "0". If the pre-verification operation fails, operation S315 can assess whether a main verification operation has been performed. If the main verification operation is deemed successful, operation S316 can change the data of the upper and lower bit latches ML and LL to pass pattern data (for example, "11"), which is then inhibited from programming in the next programming loop. Operation S317 can assess whether a complete programming operation has been performed.

[0075] If the pre-verification operation, the main verification operation, or the overall programming operation is deemed not to have been performed, operation S318 can assess whether the current programming loop has reached its maximum programming loop length. If the current programming loop has not reached its maximum programming loop length, operation S319 can increase the number of programming loops and the level of the programming pulse can increase by a predetermined increment (for example, ΔISPP). The procedure then proceeds to operation S312.

[0076] In the event that the current programming loop reaches its maximum loop length, the programming operation may have failed. Operation S320 allows a data recovery operation to be performed immediately in response to a programming error or failed programming. Specifically, data recovery operation S321 allows a read operation on a memory cell using at least one read level (e.g., RD3). Fig. 21) be carried out as described in Fig. 22B illustrates this. The loaded upper and lower bits MSB and LSB can be recovered using read data and a forcing bit stored at the forcing bit latch FL. In operation S322, a data recovery operation can be performed in the same way as with reference to Fig. 21 is described. In operation S323, the recovered upper and lower bit data MSB and LSB can be error-corrected. The error-correction operation can be performed within a non-volatile storage device 100 or by an external storage controller. After the data recovery operation is complete, in operation S330 the recovered upper and lower bit data MSB and LSB can be copied back to a new physical page. The programming operation can then be terminated. Using the multibit programming method of the inventive concept, loaded data (MSB or LSB) can be recovered from a memory cell in response to a programming error using a forcing bit, which indicates whether bit line forcing is required, and the result of a read operation.

[0077] A complete programming error can be determined according to the number of programming loops. However, the inventive concept is not limited to this. For example, a programming error can be determined according to the number of error bits. A technique for determining programming errors according to the number of error bits is disclosed in US Patent Publication US 2011 / 0051514 A1.

[0078] Fig. Figure 23 is a flowchart illustrating a multibit programming method for a non-volatile memory device according to another embodiment of the inventive concept. A multibit programming method for a non-volatile memory device is described with reference to the Fig. 1, Fig. 13 and Fig. 23 will be described.

[0079] In operation S410, target data (TD) to be programmed can be loaded into or onto data latches (e.g., ML and LL), and a forcing bit latch (e.g., FL) can be set or populated with a forcing bit (BFB), which indicates whether bit-line forcing is being performed or not. In operation S420, memory cells can be programmed with the loaded data.

[0080] Subsequently, an on-cell verification operation can be performed with respect to memory cells. The on-cell verification operation can be performed to verify whether memory cells to be programmed are programmed. For example, in operation S430, the on-cell verification operation can be performed to verify whether a delete state E has been programmed by a programming fault. In operation S440, an off-cell verification operation can be performed with respect to memory cells. The off-cell verification operation can be performed to verify whether memory cells to be programmed reach a target state corresponding to target data. The on-cell verification operation and the off-cell verification operation are disclosed in U.S. Patent US 8050101 B2 and U.S. Patent Publication US 2010 / 0008149 A1.

[0081] Whether a programming operation has been executed or failed can be determined according to the results of the on-cell and off-cell verification operations. For example, if the error bit count resulting from the on-cell and off-cell verification operations exceeds a correctable error bit count, the programming operation can be determined as programming-failed in operation S450. If the programming operation is determined to have failed, a data recovery operation can be performed in operation S460 to recover the target data. The data recovery operation can be performed in a manner determined by reference to the Fig. 18, Fig. 19 to Fig. 20 or with reference to Fig. 21. After a data recovery operation is completed, the target data recovered in operation S470 can be copied back to a new physical page. The programming operation can then be terminated. Using the multibit programming method of the inventive concept, it can be determined, based on the results of the on-cell verification operation and the off-cell verification operation, whether a programming operation has failed, and a data recovery operation can be performed in the event of a programming error. As described in the Fig. 22 and Fig. As described in section 23, a data recovery operation can be performed in response to a programming error. However, the inventive concept is not limited to this. For example, a data recovery operation can be performed in response to a data recovery command provided by an external device.

[0082] Fig. Figure 24 is a flowchart illustrating a multibit programming method for a non-volatile memory device according to yet another embodiment of the inventive concept. A multibit programming method for a non-volatile memory device is described with reference to the Fig. 1, Fig. 13, Fig. 17 and Fig. 24 will be described.

[0083] In operation S510, target data (TD), which indicates a target state, can be loaded into or onto a page buffer during a programming operation. In operation S520, a recovery reference bit (RRB) can be stored to restore an upper-tail error bit of a clear state (E) during a bit-line forcing latch (FL). The recovery reference bit (RBB) can be a bit-line forcing bit (BFB), which indicates whether or not bit-line forcing is performed.

[0084] In operation S530, the target data (TD) can be programmed to a memory cell. A data recovery operation can be performed in response to a data recovery instruction provided by a memory controller, regardless of whether a programming operation has failed. When the data recovery instruction is received, in operation S540, the loaded target data (TD) can be recovered using at least one read operation and the recovery reference bit (RRB). After the data recovery operation is complete, in operation S550, the recovered target data can be copied back to a new physical page. The programming operation can then be terminated.Using the multibit programming method of the inventive concept, target data can be recovered using a recovery reference bit RRB and at least one read operation when a data recovery instruction is received.

[0085] Fig. Figure 25 is a flowchart illustrating a data recovery operation of a storage system according to an embodiment of the inventive concept. Below is a data recovery operation of a storage system with reference to Fig. 25. In this, a storage system can comprise at least one non-volatile storage device and a storage controller which controls the at least one non-volatile storage device.

[0086] In operation S610, the memory controller can read programmed data from the at least one non-volatile storage device where a programming operation is being programmed. In operation S620, the memory controller can correct an error in the read data. In operation S630, the memory controller can assess whether an error in the read data is correctable. If an error in the read data is uncorrectable, the procedure proceeds to operation S650, in which a data recovery operation is performed to restore programmed data. The data recovery operation can be performed in a manner specified in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23 to Fig. As described in section 24, if an error in the read data is correctable, the storage controller can assess in operation S640 whether a number of erroneous bits exceeds a predetermined value. If so, the procedure proceeds to operation S650 to ensure data reliability. If not, the data recovery operation can be terminated. As described above, a data recovery operation can be determined based on an error in the read data.

[0087] Fig. Figure 26 is a flowchart illustrating a data recovery operation of a storage system according to another embodiment of the inventive concept. Below is a data recovery operation of a storage system with reference to Fig. 26. In operation S710, a storage controller can read programming status information indicating the status of a programming operation on at least one non-volatile storage device. In operation S720, the storage controller can assess whether a data recovery operation is needed based on the read programming status information. For example, if a programming status indicates a complete programming error or malfunction, a data recovery operation may be required. In this case, in operation S730, the storage controller can issue a data recovery command to the non-volatile storage device. In operation S740, the non-volatile storage device can perform a data recovery operation in response to the data recovery command.The data recovery operation can be performed in a manner which refers to the . Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23 to Fig. 24 is described. As described above, a data recovery operation can be determined using programming status information from a non-volatile storage device.

[0088] Fig. Figure 27 is a flowchart illustrating a data recovery operation of a storage system in another embodiment of the inventive concept. Below is a data recovery operation of a storage system with reference to Fig. 27. A non-volatile storage device can perform a recovery operation for lower-tail data using data latches DL1 to DLk (see reference to Fig. 2) perform. A lower tail can be a section where a cell programming operation has failed, as described in reference to Fig. 3 is described. In operation S810, the data latches DL1 to DLk can maintain data of a target state if a cell programming operation has failed. Likewise, the non-volatile storage device can perform an upper-tail data recovery operation using a recovery reference bit RRB or at least a data recovery read operation. An upper-tail can be a section in which a cell programming operation has been performed, as described in section 3. Fig. 5 is described. As described with reference to the Fig. 5 and Fig. As described in section 6, the non-volatile storage device can restore target data TD, which indicates a target state, using a recovery reference bit RRB and a read operation. A data recovery operation of the inventive concept can perform a recovery operation for lower-tail / upper-tail data.

[0089] Fig. Figure 28 is a flowchart illustrating a data recovery operation of a storage system according to yet another embodiment of the inventive concept. Below is a data recovery operation of a storage system with reference to Fig. 28. In Operation S910, a non-volatile storage device can receive a data recovery command and an address from a storage controller. The address can point to a new page where recovered data is programmed or will be programmed. In Operation S920, the non-volatile storage device can perform a data recovery operation in response to the supplied data recovery command and address. The data recovery operation can be performed in a manner described in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 to Fig. 14 is described. As described above, target data can be recovered according to a data recovery command, and recovered data can be programmed on a new page, which is determined by an address.

[0090] With this inventive concept, state information (e.g., RRB) associated with a specific state that causes a relatively large number of error bits can be set / stored during a programming operation. During a data recovery operation, target data corresponding to the specific state can be restored using this state information.

[0091] The inventive concept is applicable to a vertical NAND flash memory device.

[0092] Fig. Figure 29 is a perspective view of a memory block according to the inventive concept. Referring to Fig. 29. At least one mass selector line (GSL), a plurality of word lines (WL), and at least one string selector line (SSL) can be stacked on a substrate between word line cuts. The at least one string selector line (SSL) can be separated by a string selector line cut. A plurality of columns can penetrate at least one mass selector line (GSL), a plurality of word lines (WL), and at least one string selector line (SSL). At least one mass selector line (SSL), a plurality of word lines (WL), and at least one string selector line (SSL) can be formed within these columns, such that they have a substrate shape. Bit lines (BL) can be connected to an upper surface of the plurality of columns. The memory block in Fig. 29 can have a merged word-lead structure. However, the inventive concept is not limited to this.

[0093] Fig. Figure 30 is a block diagram which schematically illustrates a storage system according to one embodiment of the inventive concept. Referring to Fig. 30. A storage system 1000 can comprise at least one non-volatile storage device 1100 and one storage controller 1200. The non-volatile storage device 1100 can be configured to perform a data recovery operation, which, with reference to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27 to Fig. 28 is described.

[0094] The non-volatile storage device 1100 can optionally be supplied with a high voltage Vpp from an external source. The memory controller 1200 can be connected to the non-volatile storage device 1100 via a plurality of channels. The memory controller 1200 can have at least one central processing unit (CPU) 1210, a buffer memory 1220, an ECC circuit 1230, a ROM 1240, a host interface 1250, and a memory interface 1260. Although in Fig. Although not shown in Figure 30, the memory controller 1200 may still include a randomizer circuit that arranges data randomly. The memory system 1000 according to one embodiment of the inventive concept is applicable to a Perfect Page New (PPN) memory.

[0095] The storage controller 1200 can generate a data recovery command if a programming operation of the non-volatile storage device 1100 has failed or if the reliability of a programming operation is required, and can provide the data recovery command for the non-volatile storage device 1100.

[0096] The 1200 storage controller can include the 1230 ECC circuit, which is configured to detect data errors according to an error correction code (ECC). The 1230 ECC circuit can calculate an error correction code value for data to be programmed during a write operation, correct errors in read data during a read operation based on the error correction code value, and correct errors in recovered data from the 1100 non-volatile storage device during a data recovery operation. The 1200 storage controller can also program the 1100 non-volatile storage device such that data recovered during a data recovery operation is programmed on a different physical page.

[0097] The Storage System 1000 can improve data reliability by restoring target data during a data recovery operation. Likewise, the Storage System 1000 can reduce chip size, as it eliminates the need for a separate storage area for target data during a data recovery operation.

[0098] Fig. Figure 31 is a block diagram which schematically illustrates a memory card according to an embodiment of the inventive concept. Referring to Fig. 31. A memory card 2000 can have at least one flash memory 2100, one buffer memory device 2200 and one memory controller 2300 for controlling the flash memory 2100 and the buffer memory device 2200.

[0099] The Flash Memory 2100 can optionally be powered externally with a high voltage Vpp. The Flash Memory 2100 can be configured to perform a data recovery operation, which is performed in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27 to Fig. The following is described in section 28. The buffer storage device 2200 can be used to temporarily store data generated during the operation of the memory card 2000. The buffer storage device 2200 can be implemented using DRAM or SRAM. The memory controller 2300 can be connected to the flash memory 2100 via multiple channels. The memory controller 2300 can be connected between a host and the flash memory 2100. The memory controller 2300 can be configured to access the flash memory 2100 in response to a request from the host.

[0100] The 2300 memory controller can have at least one 2310 microprocessor, one 2320 host interface, and one 2330 flash interface. The 2310 microprocessor can be configured to drive firmware. The 2320 host interface can be connected to the host via a card protocol (e.g., SD / MMC) for data exchange between the host and the 2000 memory card.

[0101] The Memory Card 2000 is applicable to Multimedia Cards (MMCs), Security Digital Cards (SDs), Mini SDs, Memory Sticks, SmartMedia, TransFlash Cards and the like.

[0102] Fig. Figure 32 is a block diagram which schematically illustrates a moviNAND according to one embodiment of the inventive concept. Referring to Fig. 32. A moviNAND device 3000 can include at least one NAND flash memory device 3100 and one controller 3200. The moviNAND device 3000 can support the MMC 4.4 (or, relatedly, the "eMMC") standard.

[0103] The NAND flash memory device 3100 can be a single-data-rate (SDR) NAND flash memory device or a double-data-rate (DDR) NAND flash memory device. In exemplary embodiments, the NAND flash memory device 3100 can include NAND flash memory chips. Here, the NAND flash memory device 3100 can be implemented by stacking the NAND flash memory chips on a package (for example, FBGA, fine-pitch ball grid array, etc.). Each NAND flash memory chip can be configured to perform a data recovery operation, which is described in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23 to Fig. 24 is described, carries out.

[0104] The controller 3200 can be connected to the flash storage device 3100 via multiple channels. The controller 3200 can have at least one controller core 3210, one host interface 3250, and one NAND interface 3260. The controller core 3210 can control the overall operation of the moviNAND device 3000. The host interface 3250 can be configured to provide an MMC interface between the controller 3210 and a host. The NAND interface 3260 can be configured to connect between the NAND flash storage device 3100 and the controller 3200. In exemplary embodiments, the host interface 3250 can be a parallel interface (for example, an MMC interface). In other exemplary embodiments, the host interface 3250 of the moviNAND device 3000 can be a serial interface (for example, UHS-II, UFS, etc.).

[0105] The moviNAND device 3000 can receive power supply voltages Vcc and Vccq from the host. The power supply voltage Vcc (approximately 3.3 volts) can be provided to the NAND flash memory device 3100 and the NAND interface 3200, while the power supply voltage Vccq (approximately 1.8 volts / 3.3 volts) can be provided to the controller 3200. In exemplary embodiments, an external high voltage Vpp can be supplied to the moviNAND device 3000.

[0106] The moviNAND device 3000 according to one embodiment of the inventive concept can be advantageous for storing large amounts of data, as it can have improved read characteristics. The moviNAND device 3000 according to one embodiment of the inventive concept is applicable to small and low-power mobile products (for example, a Galaxy S, iPhone, etc.).

[0107] Fig. Figure 33 is a block diagram which schematically illustrates a solid-state drive according to one embodiment of the inventive concept. Referring to Fig. 33. A solid-state drive (SSD) 4000 can include a plurality of flash memory devices 4100 and an SSD controller 4200. The flash memory device 4100 can optionally be supplied with a high voltage Vpp from an external source. The flash memory device 4100 can be configured to perform a data recovery operation, which refers to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27 to Fig. The SSD controller 4200, as described in section 28, can be connected to the flash memory devices 4100 via a plurality of channels CH1 to CHi. The SSD controller 4200 can have at least one CPU 4210, one host interface 4220, one buffer memory 4230, and one flash interface 4240.

[0108] The SSD 400, according to one embodiment of the inventive concept, can perform a programming operation capable of improving data reliability. A more detailed description of the SSD 4000 is disclosed in US Patent Nos. US 7,802,054 B2, US 8,027,194 B2, and US 8,122,193 B2, and US Patent Publications US 2007 / 0106836 A1 and US 2010 / 0082890 A1.

[0109] Fig. Figure 34 is a block diagram which schematically illustrates a communication device according to an embodiment of the inventive concept. Referring to Fig. 34 A communication device 8000 can include a communication unit 8100, a controller 8200, a storage unit 8300, a display unit 8400, a touchscreen unit 8500 and an audio unit 8600.

[0110] The 8300 memory unit can contain at least one 8310 DRAM, at least one 8320 OneNAND, and at least one 8330 moviNAND. At least one of the 8320 OneNAND and one of the 8330 moviNAND can be configured to form a 2700 memory system. Fig. 27 are the same. A detailed description of typical mobile devices is disclosed in US Patent Publications Nos. US 2010 / 0010040 A1, US 2010 / 0062715 A1, US 2010 / 0309237 A1 and US 2010 / 0315325 A1.

[0111] Fig. Figure 35 is a block diagram which schematically illustrates a smart TV system according to an embodiment of the inventive concept. Referring to Fig. The Smart TV System 9000 comprises a Smart TV 9110, a Revue 9200, a Set-Top Box 9300, a Wireless Router 9400, a Keyboard 9500, and a Mobile Phone / Smartphone 9600. Wireless communication is possible between the Smart TV 9100 and the Router 9400. The Smart TV 9100 can be connected to the internet via the Revue 9200, which is an open platform. The Smart TV 9100 allows a viewer to watch cable and satellite broadcasts transmitted by the Set-Top Box 9300. The Smart TV 9100 can be operated using the Keypad / Keyboard 9500 or the Smartphone 9600. The Smart TV 9100 can integrate a Storage System 1000, which is located in Fig. 30 is illustrated, included.

[0112] A storage system or storage device according to the inventive concept can be housed in various types of enclosures. Examples of the packages in the storage system or storage device according to the inventive concept may include a package-on-package (PoP), ballgrid arrays (BGAs), chip-scale packages (CSPs), a plastic-leaded chip carrier (PLCC), a plastic dual inline package (PDIP), a die-in-wavel pack, a die-in-wafer form, a chip-on-board (COB), a ceramic dual inline package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system-in-package (SIP), a multichip package (MCP), a wafer-fabricated package (WFP), and a wafer-level processed stack package (WSP).

[0113] While the inventive concept has been described with reference to exemplary embodiments, it will be obvious to those skilled in the art that various modifications and adaptations can be made without departing from the idea and scope of the present invention. Accordingly, it should be understood that the embodiments described above are not limiting but illustrative.

Claims

[1] Method for operating a non-volatile storage device (100) comprising the following: a detection of errors generated during a programming operation for programming a section of a first plurality of non-volatile multibit memory cells (MC1 - MCm) in the non-volatile storage device (100), by reading the first plurality of non-volatile multibit memory cells (MC1 - MCm) and a force-bit data vector, which is verified during the programming operation to identify whether any of the first plurality of non-volatile multibit memory cells (MC1 - MCm) contain erroneous data, Target Data (TD) recovery is performed when target data (TD) recovery is needed. an output of the recovered target data (TD) to a storage controller, and a correction of an error in the recovered target data (TD) by the storage controller. [2] Method according to claim 1, wherein the error detection further comprises reading data from a page buffer (PB1 - PBn) which is assigned to the first plurality of non-volatile multibit memory cells (MC1 - MCm) to identify which of the first plurality of non-volatile multibit memory cells (MC1 - MCm) are erased cells which have high threshold voltages. [3] Method according to claim 1, wherein the programming operation comprises verifying an initial force bit data vector which contains equivalent data values. [4] Method according to claim 1, wherein the programming operation comprises verifying an initial force-bit data vector which contains equivalent first data values, and wherein the verification comprises holding the initial force-bit vector or modifying the initial force-bit vector into a modified force-bit data vector which contains a plurality of second data values, each of which identifies one of the first plurality of non-volatile multibit memory cells (MC1 - MCm) which have undergone at least partial programming during the programming operation. [5] Method according to claim 2, wherein the programming operation comprises: a verification of an initial force-bit data vector, which contains equivalent first data values, into a modified force-bit data vector, which contains a plurality of second data values, each of which identifies one of the first plurality of non-volatile multibit memory cells (MC1 - MCm) that have undergone at least partial programming during the programming operation; and an update of data in the page buffer (PB1 - PBn) in response to a successful programming of one or more of the first plurality of non-volatile multibit memory cells (MC1 - MCm) during the programming operation. [6] Method for operating a non-volatile storage device (100) comprising the following: a detection of errors generated during a programming operation for programming a selected page of non-volatile multibit memory cells (MC1 - MCm) in the non-volatile memory device (100) by evaluating: (i) data read from the selected page of non-volatile multibit memory cells (MC1 - MCm), (ii) a force bit data vector modified during the programming operation, and (iii) data in a page buffer (PB1 - PBn) associated with the page of non-volatile multibit memory cells (MC1 - MCm) to identify whether any of the non-volatile multibit memory cells (MC1 - MCm) in the selected page are erased cells with high threshold voltages, Target Data (TD) recovery is performed when target data (TD) recovery is needed. an output of the recovered target data (TD) to a storage controller, and a correction of an error in the recovered target data (TD) by the storage controller. [7] Method according to claim 6, wherein the programming operation comprises modifying an initial force-bit data vector, which has equivalent first data values ​​therein, into a modified force-bit data vector, which has a plurality of second data values ​​therein, which identify a respective plurality of the non-volatile multibit memory cells (MC1 - MCm) in the selected page as having undergone at least partial programming during the programming operation. [8] Method according to claim 7, wherein the programming operation further comprises resetting at least some of the data in the page buffer (PB1 - PBn) to default values ​​in response to a successful programming of one or more of the non-volatile multibit memory cells (MC1 - MCm) in the selected page during the programming operation. [9] Method for operating a non-volatile storage device (100) comprising the following: a change of a first multibit data value, which is associated with a first programming state of a first non-volatile multibit memory cell in the non-volatile storage device (100), to a second multibit data value, which is associated with an erase state of the first non-volatile multibit memory cell, in response to a verification that the first non-volatile multibit memory cell has been validly programmed to the first programming state during a programming operation; and a reading of force-bit data, which was verified during the programming operation to confirm that the second multibit data value, which is assigned to the first non-volatile multibit memory cell, reflects an accurately programmed cell, Target Data (TD) recovery is performed when target data (TD) recovery is needed. an output of the recovered target data (TD) to a storage controller, and a correction of an error in the recovered target data (TD) by the storage controller. [10] Method according to claim 9, wherein the programming operation comprises resetting the first multibit data value to the second multibit data value in a page buffer (PB1 - PBn). [11] Method according to claim 10, wherein the reading comprises reading the page buffer (PB1 - PBn), the force bit data which were modified during the programming operation, and a plurality of non-volatile multibit memory cells (MC1 - MCm) in the non-volatile memory device (100) to identify erased cells in the plurality of non-volatile multibit memory cells (MC1 - MCm) which have unacceptably high threshold voltages. [12] Method according to claim 9, wherein the reading of force bit data which were modified during the programming operation is preceded by loading a multibit force bit vector of equivalent logic values ​​into a force bit register. [13] Method according to claim 12, further comprising modifying at least one section of the multibit force bit vector in the force bit register during the programming operation to identify a plurality of non-volatile multibit memory cells (MC1 - MCm) in the non-volatile storage device (100) which have undergone intentional programming using an ISSP programming technique. [14] Method for operating a non-volatile storage device (100) comprising the following: Performing an error detection operation on a row of non-volatile multibit memory cells (MC1 - MCm) in the non-volatile storage device (100) by reading the row of non-volatile multibit memory cells (MC1 - MCm) together with reading post-programming data from a page buffer (PB1 - PBn) and force bit data used during the programming of the row of non-volatile multibit memory cells (MC1 - MCm) to identify whether any of the non-volatile multibit memory cells (MC1 - MCm) in the row are erased cells that have unacceptably high threshold voltages, Target Data (TD) recovery is performed when target data (TD) recovery is needed. an output of the recovered target data (TD) to a storage controller, and a correction of an error in the recovered target data (TD) by the storage controller. [15] The method of claim 14, wherein the following precedes the execution: loading a plurality of pages of data into the page buffer (PB1 - PBn); and a programming of the line of non-volatile multibit memory cells (MC1 - MCm) with the majority of pages of data from the page buffer (PB1 - PBn). [16] Method according to claim 15, wherein the programming of the line of non-volatile multibit memory cells (MC1 - MCm) comprises resetting at least some of the data in the page buffer (PB1 - PBn) when corresponding programming states of non-volatile multibit memory cells (MC1 - MCm) in the line are verified as exactly. [17] Method according to claim 16, wherein the programming of the line of non-volatile multibit memory cells (MC1 - MCm) comprises modifying bits of a preloaded force bit vector to display the information of programming operations on corresponding non-volatile multibit memory cells (MC1 - MCm) within the line. [18] Method according to claim 16, wherein the programming of the line of non-volatile multibit memory cells (MC1 - MCm) comprises modifying bits of a preloaded force bit vector to indicate the performance of ISSP programming operations on corresponding non-volatile multibit memory cells (MC1 - MCm) within the line. [19] Integrated circuit memory system comprising: at least one non-volatile storage device (100); and a memory controller (1200, 2300, 4200) electrically coupled to the at least one non-volatile memory device (100), the memory controller (1200, 2300, 4200) comprising a central processing circuit and an ECC circuit therein, the ECC circuit being configured to perform a data recovery operation on data programmed into the at least one non-volatile memory device (100) during a programming operation by reading a first plurality of non-volatile multibit memory cells (MC1 - MCm) in the at least one non-volatile memory device (100) and a force-bit data vector modified during the programming operation to identify whether any of the first plurality of non-volatile multibit memory cells (MC1 - MCm) contains erroneous data, Target Data (TD) recovery is performed when target data (TD) recovery is needed. an output of the recovered target data (TD) to a storage controller, and a correction of an error in the recovered target data (TD) by the storage controller. [20] Storage system according to claim 19, wherein the data recovery operation comprises reading data from a side buffer (PB1 - PBn) which is allocated to the first plurality of non-volatile multibit memory cells (MC1 - MCm) to identify which of the first plurality of non-volatile multibit memory cells (MC1 - MCm) are erased cells which have high threshold voltages. [21] Storage system according to claim 19, wherein the programming operation comprises modifying an initial force-bit data vector, which has equivalent first data values ​​therein, into a modified force-bit data vector, which has a plurality of second data values ​​therein, each of which identifies one of the first plurality of non-volatile multibit memory cells (MC1 - MCm) which have undergone at least partial programming during the programming operation. [22] Storage system according to claim 20, wherein the programming operation comprises: a modification of an initial force-bit data vector, which contains equivalent first data values, into a modified force-bit data vector, which contains a plurality of second data values, each of which identifies one of the first plurality of non-volatile multibit memory cells (MC1 - MCm) that have undergone at least partial programming during the programming operation; and an update of data in the page buffer (PB1 - PBn) in response to a successful programming of one or more of the first plurality of non-volatile multibit memory cells (MC1 - MCm) during the programming operation.

Images