Wafers and processes for processing a wafer

Abstract

Wafer (400), exhibiting: at least one metallization structure having at least one contact point (403) with at least one opening (404); and at least one dividing line region (402), wherein the at least one dividing line region (402) intersects the at least one opening (404); wherein the at least one dividing line region (402) has at least one first dividing line region and one second dividing line region; wherein the at least one opening (404) has at least a first section extending in a longitudinal direction of the first dividing line region and a second section extending in a longitudinal direction of the second dividing line region; and wherein the first and second sections of the at least one opening (404) intersect at an intersection point of the first and second dividing line region.

Description

[0001] The various embodiments generally relate to a wafer and a method for processing a wafer.

[0002] Modern semiconductor devices, such as integrated circuits (ICs), are typically manufactured using wafers. A wafer typically has one or more monolithic plates and one or more parting line regions (e.g., notch-cut or scribing regions) along which the wafer can be cut to separate the plates or chips. Sometimes, one or more of the parting line regions may be at least partially filled with one or more electrical structures, such as process control monitoring (PCM) structures or other test leads or measurement structures. Metallization areas or contact points (e.g., test lead contacts) may be provided in the parting line regions to enable electrical contact with these electrical structures (e.g., test leads).

[0003] Wafer dicing is usually performed mechanically by cutting, although other dicing methods have recently emerged, such as stealth laser dicing (sometimes simply called stealth dicing or laser dicing). Stealth laser dicing can involve a two-stage process in which defective regions are first introduced into the wafer by guiding a laser beam (typically an infrared (IR) laser beam) along the discontinuity region(s), and then an underlying elastic support, such as a support membrane or strip, is expanded to cause the wafer to fracture at the discontinuity region(s).

[0004] Concealed laser slicing can be seen as a separation or slicing method capable of achieving high-quality sidewalls in wafers (e.g., silicon). However, a limitation of concealed laser slicing is currently evident in its inability to separate stacks of thick metal layers. For example, it can be difficult to cleanly separate a thick final metal layer from PCM or probe contact points in wafer discontinuity regions.

[0005] Concealed laser splitting can be used for small chips (e.g., chips with an area of ​​approximately 3 mm²). 2 up to about 5 mm 2) and small wafer thicknesses are generally very cost-effective. For small chips, test lines can typically be placed in the insertion areas of the wafer replacement chips. In this way, a cost-effective small parting line region (for example, with a width in the range of 15 to 20 µm) and / or a parting line region free of metal plates can be obtained, which can provide very good conditions for concealed sectioning.

[0006] On the other hand, it can be problematic for large chips (e.g., chips with a surface area of ​​over 5 mm). 2It is generally more effective to use wafers in which probe leads and corresponding contact points are located in the parting line region(s). For these chips, blind splitting can generally be highly effective for thin wafers, for example, less than 150 µm, where blind splitting requires, for example, only one or two laser scans at a scanning speed of over 300 m / s, whereas mechanical splitting typically involves a step cut at a speed of around 50 mm / s or even slower. In the latter case, it may be desirable for the blind splitting to be able to separate the contact points (e.g., probe lead contact points), for example, contact points with thick metal layers, in the parting line region(s).

[0007] US 2012 / 0211748 A1 discloses a method for singulating a semiconductor wafer, which includes forming a layer stack on a first major surface of a substrate. The layer stack and a portion of the substrate are etched according to a pattern that defines an intended splitting point to obtain a trench structure. The substrate is irradiated with a laser beam to locally modify the substrate between a bottom of the trench structure and a second major surface of the substrate relative to the first major surface.

[0008] US 2003 / 0124771 A1 discloses a wafer singulation process in which layers of a processed semiconductor wafer are removed using laser light from a laser gun.

[0009] US 2006 / 0040472 A1 discloses a method for separating a semiconductor substrate with an implementation element attached to it, which includes a division process for at least the implementation element on the semiconductor substrate along a division line, a placement process for a film element on the same side as the implementation element, and the formation of a process area by irradiating with a laser beam from at least one side of the semiconductor substrate.

[0010] US 2009 / 0121337 A1 discloses a method for cutting a semiconductor wafer by stealth dicing, in which a test pad in a cutting area and an alignment target are arranged together along one side in a width direction of the cutting area, and a laser beam is emitted to form a modified area at a remote position in a plane from the test area and the alignment target Am.

[0011] A wafer according to claim 1 and a method for dividing a wafer according to claim 14 are provided. Further embodiments are described in the dependent claims.

[0012] A semiconductor wafer according to various embodiments can have: at least one metallization structure having at least one opening; and at least one dividing line region along which the semiconductor wafer is to be divided, wherein the at least one dividing line region intersects the at least one opening.

[0013] In one or more embodiments, the at least one metallization structure may comprise or be at least one metal plate.

[0014] In one or more embodiments, the at least one metallization structure can have or be at least one contact point.

[0015] In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) can comprise at least one metal or metal alloy.

[0016] In one or more embodiments, the at least one dividing line region may have or be at least one notch cut region.

[0017] In one or more embodiments, the at least one dividing line region may have or be at least one scribing line region.

[0018] In one or more embodiments, the at least one opening can be located in the center of the at least one metallization structure (e.g., metal plate, e.g., contact point).

[0019] In one or more embodiments, a position of the at least one opening can correspond to a position of a center of the at least one dividing line region, for example a center of a scoring line.

[0020] In one or more embodiments, the semiconductor disk can have at least one test structure connected to the at least one metallization structure (e.g., metal plate, e.g., contact point), wherein the separation line region intersects the test structure.

[0021] In one or more embodiments, the at least one test structure can be configured as a process control management (PCM) monitoring structure.

[0022] In one or more embodiments, the at least one contact point can be configured as a contact point for monitoring the process control (PCM).

[0023] In one or more embodiments, a dimension of the at least one opening in a transverse direction of the at least one dividing line region can be smaller than a dimension of the at least one dividing line region in the transverse direction of the at least one dividing line region.

[0024] In one or more embodiments, a dimension of the at least one opening in a transverse direction of the at least one dividing line region can be equal to or less than approximately 15 µm.

[0025] In one or more embodiments, a dimension of the at least one opening in a transverse direction of the at least one dividing line region can be in the range of about 1 µm to about 15 µm.

[0026] In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) can have a thickness greater than or equal to approximately 1 µm.

[0027] In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) can have a thickness in the range of about 1 µm to about 3 µm.

[0028] In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) can comprise at least one metal from the following group of metals, wherein the group consists of: aluminum, copper, gold, silver, tin, palladium, zinc, nickel, iron, titanium, or an alloy comprising at least one of the aforementioned metals.

[0029] In one or more embodiments, the at least one opening may have or be at least one hole.

[0030] In one or more embodiments, the at least one hole can have or be at least one through hole.

[0031] In one or more embodiments, the depth of the at least one opening can be equal to the thickness of the at least one metallization structure (e.g., metal plate, e.g., contact point).

[0032] In one or more embodiments, the at least one opening can extend through the at least one metallization structure (e.g., metal plate, e.g., contact point), for example, through the entire thickness of the at least one metallization structure (e.g., metal plate, e.g., contact point).

[0033] In one or more embodiments, the at least one opening can extend from a first side (e.g. top) of the at least one metallization structure (e.g. metal plate, e.g. contact point) to a second side (e.g. bottom) of the at least one metallization structure (e.g. metal plate, e.g. contact point).

[0034] In one or more embodiments, the at least one hole may have or be at least one blind hole.

[0035] In one or more embodiments, the depth of the at least one opening can be less than the thickness of the at least one metallization structure (e.g., metal plate, e.g., contact point).

[0036] In one or more embodiments, a dimension of the at least one opening in a transverse direction of the at least one separation line region can be smaller than a dimension of the at least one metallization structure (e.g. metal plate, e.g. contact point) in the transverse direction of the at least one separation line region.

[0037] In one or more embodiments, a dimension of the at least one opening in a longitudinal direction of the at least one separation line region can be equal to a dimension of the at least one metallization structure (e.g. metal plate, e.g. contact point) in the longitudinal direction of the at least one separation line region.

[0038] In one or more embodiments, the at least one opening can have at least one slot or be at least one slot extending in a longitudinal direction of the at least one dividing line region.

[0039] In one or more embodiments, the length of the slot can be equal to a dimension of the at least one metallization structure (e.g., metal plate, e.g., contact point) in the longitudinal direction of the separation line region.

[0040] In one or more embodiments, the at least one slot can have at least one trench or be at least one trench.

[0041] In one or more embodiments, the at least one dividing line region can comprise at least a first dividing line region and a second dividing line region along which the semiconductor wafer is to be divided. The first dividing line region can intersect the at least one opening. The second dividing line region can intersect the at least one opening.

[0042] In one or more embodiments, the first and second dividing line regions can intersect each other.

[0043] In one or more embodiments, the at least one opening can have at least a first section extending in a longitudinal direction of the first dividing line region and a second section extending in a longitudinal direction of the second dividing line region.

[0044] In one or more embodiments, the first and second sections of the at least one opening can intersect at an intersection point of the first and second dividing line regions.

[0045] In one or more embodiments, the at least one opening can have at least one first opening and at least one additional opening, wherein the dividing line region can intersect the first opening and the at least one additional opening.

[0046] A semiconductor wafer according to various embodiments can comprise: at least one metallization structure; and at least one dividing line region along which the semiconductor wafer is to be cut. The at least one dividing line region can cut at least a portion of the at least one metallization structure. The at least one portion of the at least one metallization structure that is cut by the at least one dividing line region can have a smaller thickness than the at least one other portion of the at least one metallization structure.

[0047] In one or more embodiments, the at least one metallization structure may comprise or be at least one metal plate.

[0048] In one or more embodiments, the at least one metallization structure can have or be at least one contact point.

[0049] In one or more embodiments, the thickness of the at least one part of the at least one metallization structure (e.g., metal plate, e.g., contact point) that is cut by the at least one dividing line region can be less than or equal to approximately 2 µm.

[0050] In one or more embodiments, the thickness of the at least one part of the at least one metallization structure (e.g., metal plate, e.g., contact point) that is cut by the at least one dividing line region can be essentially zero.

[0051] In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) can comprise or consist of at least one metal or metal alloy.

[0052] A method for processing a semiconductor wafer according to various embodiments may include providing a semiconductor wafer. The semiconductor wafer may have at least one metallization structure and at least one separation line region along which the semiconductor wafer is to be cut. The method may further include forming at least one opening in the at least one metallization structure. The at least one separation line region may intersect the at least one opening.

[0053] In one or more embodiments, the at least one metallization structure may comprise or be at least one metal plate.

[0054] In one or more embodiments, the at least one metallization structure can have or be at least one contact point.

[0055] In one or more embodiments, the at least one opening can have or be at least one hole. In one or more embodiments, the at least one hole can have or be at least one through hole. In one or more embodiments, the at least one hole can have or be at least one blind hole. In one or more embodiments, the at least one opening can have or be at least one slot. In one or more embodiments, the at least one slot can have or be at least one trench. In one or more embodiments, the at least one opening can have or be at least one perforation.

[0056] In one or more embodiments, the method may further include dividing the semiconductor disk along the at least one separation line region after forming the at least one opening in the at least one metallization structure (e.g., metal plate, e.g., contact point).

[0057] In one or more embodiments, the dividing of the semiconductor disk along the at least one dividing line region can include a concealed dividing of the semiconductor disk along the at least one dividing line region.

[0058] In one or more embodiments, the method may further include electrical contacting of the at least one metallization structure (e.g., metal plate, e.g., contact point) after forming the at least one opening in the at least one metallization structure (e.g., metal plate, e.g., contact point) and before dividing the semiconductor disk along the at least one dividing line region.

[0059] In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) can comprise or consist of at least one metal or metal alloy.

[0060] A method for processing a semiconductor wafer according to various embodiments may comprise: providing a semiconductor wafer having at least one metallization structure with at least one opening and at least one dividing line region along which the semiconductor wafer is to be cut, wherein the at least one dividing line region intersects the at least one opening; and cutting the semiconductor wafer along the at least one dividing line region. In one or more embodiments, the at least one metallization structure may comprise or be at least one metal plate. In one or more embodiments, the at least one metallization structure may comprise or be at least one contact point. In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) may comprise or consist of at least one metal or a metal alloy.

[0061] A semiconductor wafer according to various embodiments can comprise: at least one metallization structure (e.g., metal plate, e.g., contact point) having at least one opening; and at least one dividing line region along which the semiconductor wafer is to be cut, wherein the at least one dividing line region intersects the at least one opening; wherein a dimension of the at least one opening in a longitudinal direction of the at least one dividing line region is equal to a dimension of the at least one metallization structure (e.g., metal plate, e.g., contact point) in the longitudinal direction of the at least one dividing line region. In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) can comprise or consist of at least one metal or a metal alloy.

[0062] A semiconductor wafer according to various embodiments can have: at least one metallization structure; and at least one dividing line region along which the semiconductor wafer is to be cut. The at least one dividing line region can cut at least a portion of the at least one metallization structure. The at least one portion of the at least one metallization structure that is cut by the at least one dividing line region can have a smaller thickness than the at least one other portion of the at least one metallization structure.

[0063] In one or more embodiments, the at least one metallization structure may comprise or be at least one metal plate.

[0064] In one or more embodiments, the at least one metallization structure can have or be at least one contact point.

[0065] In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) can comprise or consist of at least one metal or metal alloy.

[0066] In one or more embodiments, the thickness of the at least one part of the at least one metallization structure (e.g., metal plate, e.g., contact point) that is cut by the at least one dividing line region can be less than or equal to approximately 2 µm.

[0067] In one or more embodiments, the thickness of the at least one part of the at least one metallization structure (e.g., metal plate, e.g., contact point) that is cut by the at least one dividing line region can be essentially zero.

[0068] In the drawings, the same reference numerals generally refer to the same parts in all different views. The drawings are not necessarily to scale; instead, the emphasis is on illustrating the principles of different embodiments. The following description details various embodiments with reference to the following drawings, wherein: Fig. 1 represents a top view of a wafer to illustrate one aspect of one or more embodiments; Fig. 2A a top view of a section of the in Fig. 1 represents the wafer shown, and Fig. 2B and a cross-sectional view along line BB' in Fig. 2A represents; Fig. 3, Fig. 4A and Fig. 4B Views illustrating a hidden fragmentation process occurring on the wafer of Fig. 1 is used to illustrate one aspect of one or more embodiments; Fig. 5A represents a top view of a section of a wafer according to one or more embodiments, and Fig. 5B and a cross-sectional view along line BB' in Fig. 5A represents; Fig. 6A and Fig. 6B Different views to illustrate a hidden fragmentation process occurring on the wafer of Fig. 5A and Fig. 5B is applied to illustrate one aspect of one or more embodiments; Fig. 7A represents a top view of a section of a wafer according to one or more embodiments, and Fig. 7B and a cross-sectional view along line BB' in Fig. 7A represents; Fig. 8 represents a top view of a section of a wafer according to one or more embodiments; Fig. 9 represents a top view of a section of a wafer according to one or more embodiments; Fig. 10 represents a method for processing a wafer according to one or more embodiments; Fig. 11A to Fig. Figure 11H shows different views illustrating a method for processing a wafer according to one or more embodiments.

[0069] The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments in which the invention can be implemented. The embodiments are described in sufficient detail to enable those skilled in the art to put the invention into practice. Other embodiments may be used, and structural, logical, or electrical modifications may be made without deviating from the scope of protection of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments.

[0070] Various aspects of the disclosure are provided for processes, and various aspects of the disclosure are provided for components or manufacturers. It is self-evident that the basic properties of the processes may also apply to the components or manufacturers, and vice versa. Therefore, for the sake of brevity, a duplicate description of such properties may be omitted.

[0071] As used herein, the terms “at least one” or “one or more” can be understood to mean an integer greater than or equal to one.

[0072] As used herein, the terms “a plurality of” or “several” can be understood to mean that they represent an integer greater than or equal to two.

[0073] As used herein, the terms “coupling” or “connection” can be understood to include both direct “coupling” or direct “connection” and indirect “coupling” or indirect “connection”.

[0074] As used herein, the terms “formed over”, “applied over”, “arranged over”, “located over”, “arranged over” are to define arrangements in which a first element or layer may be formed, applied, arranged, located or arranged directly on a second element or layer without any other elements or layers in between, and arrangements in which a first element or layer may be formed, applied, arranged, located or arranged over a second element or layer with one or more additional elements or layers between the first element or layer and the second element or layer.

[0075] As used herein, the term “wafer” (hereinafter also referred to as “semiconductor disk”) can be understood to mean that it comprises a wafer (a semiconductor disk) or a wafer substrate (semiconductor disk substrate). The semiconductor disk or semiconductor disk substrate may comprise silicon (Si) or other semiconductor disk materials (including semiconductor composite materials), such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), although other materials are possible. A “semiconductor disk” may also comprise materials other than semiconductors, for example, insulating or dielectric materials and / or conductive materials.

[0076] Fig. Figure 1 shows a top view of a semiconductor disk 100, Fig. 2A shows a top view of section 200 of the in Fig. 1 represents the semiconductor disk 100 shown, and Fig. 2B shows a cross-sectional view of a section 200 of the semiconductor disk 100 along the line BB' in Fig. 2A illustrates one aspect of one or more embodiments.

[0077] The semiconductor disk 100 can have one or more, e.g., a plurality of, platelet regions 101 (which can correspond to one or more plates or chips) separated by one or more, e.g., a plurality of, separating line regions 102 (e.g., notch-cut regions or scribing line regions). The number of platelet regions 101 can be arbitrary. As in Fig. As shown in Figure 1, the platelet regions 101 can have a square shape, but one or more platelet regions 101 can also have a rectangular shape or, in general, any other shape. As shown in Fig. As shown in Figure 1, the platelet regions 101 can be arranged in a rectangular matrix, but the platelet regions 101 can also be arranged differently. As in Fig. As shown in Figure 1, the semiconductor disk 100 has a circular shape, but the semiconductor disk 100 can also have a rectangular shape or a square shape or, in general, any other shape.

[0078] The semiconductor disk 100 can have a front side 100a and a back side 100b (see Fig. 2b) opposite front side 100a.

[0079] One or more contact points 103, such as PCM or test lead contact points, can be arranged in one or more separation line regions 102 of the semiconductor disk 100, as shown in Fig. Figure 2A shows an enlarged view of section 200 of the semiconductor disk 100. The contact point(s) 103 may be made of or consist of a metal or a metal alloy. A contact point that is made of or consists of a metal or a metal alloy can also be referred to as a metal contact point.

[0080] As in Fig. 2A and Fig. As shown in Figure 2B, the contact point 103 (e.g., PCM or test lead contact point) can be located in the dividing line region 102 of the semiconductor wafer 100, for example, between a first plate region 101a and a second plate region 101b of the plate regions 101. The contact point 103 can serve to electrically connect one or more electrical components, e.g., test components (not shown), which can be located in the dividing line region 102, for example, in one or more layers or levels below the contact point 103. For this purpose, the contact point 103 can be connected to the one or more electrical components, for example, by one or more electrical intermediate connections and / or contact holes (not shown), which can be located in one or more layers or levels below the contact point 103. The contact point 103 can be located on the front face 100a of the semiconductor wafer 100, as shown.

[0081] The semiconductor disk 100 can be located along the dividing line region 102, which is in Fig. 2A is shown, and along further dividing line regions 102, which are in Fig. 1 are shown, are divided in order to separate the plates or chips that correspond to one or more plate regions 101 (e.g. plate regions 101a and 101b).

[0082] The dividing of the semiconductor wafer 100 can be carried out, for example, using a concealed laser dividing process, as shown below. Fig. 3, Fig. 4A and Fig. 4B illustrates this.

[0083] Fig. 3, Fig. 4A and Fig. Figure 4B shows views 300, 320 and 340 respectively, illustrating a hidden laser splitting process applied to the semiconductor disk 100 to demonstrate one or more embodiments.

[0084] Concealed laser slicing (sometimes simply referred to as concealed slicing or laser slicing) can be understood as referring to a slicing process which can form a modified layer in a workpiece, such as the semiconductor wafer 100, by focusing a laser 220 within the workpiece (as shown in Figure 300 of Fig. 3 and view 320 of Fig. 4A). Subsequently, the plates or chips of the semiconductor disk 100 can be separated, for example, by using a strip expander (as shown in Figure 340). Fig. 4B (shown).

[0085] In particular, a laser beam 220 at a wavelength capable of passing through the semiconductor disk 100 (typically a laser with an infrared (IR) wavelength, for example, a wavelength of about 1064 nm, 1080 nm, or 1342 nm, although other wavelengths are also possible) can be compressed by an objective lens (not shown) and focused onto a point within the semiconductor disk 100, for example, a point within the dividing line region 102 of the semiconductor disk 100, as shown in Figure 300. Fig. 3 and view 320 of Fig. Figure 4A illustrates this. The laser beam 220 can, for example, consist of short pulses that oscillate at a high repetition rate and can be highly compressed. This localized beam 220 can, for example, be compressed both temporally and spatially in the vicinity of the focal point at an extremely high peak power density. If the laser beam 220, passing through the semiconductor layer 100, exceeds a peak power density during the compression process, nonlinear absorption can cause a phenomenon in which extremely high absorption occurs at localized points.By optimizing the characteristics of the laser and the optical system to induce the effect of nonlinear absorption in the immediate vicinity of the focal point within the semiconductor wafer 100, it may be possible to selectively laser-process only localized points or regions 115 in the interface region 102 of the semiconductor wafer 100 without damaging layers or structures in the semiconductor wafer 100 that are located above or below these points or regions 115. For example, regions 115 of the semiconductor wafer 100 can be laser-processed by the laser beam 220, while other areas of the semiconductor wafer 100 can remain unaffected by the laser beam 220.

[0086] The laser beam 220 can enter the semiconductor disk 100 from the rear side 100b of the semiconductor disk 100, as shown in view 300. Fig. 3 and view 320 of Fig. 4A is shown.

[0087] It should be mentioned that view 300 of Fig. Figure 3 represents one and the same laser beam 220 at two different locations (corresponding to two different times), and arrow 221 indicates the movement of the laser beam 220's position relative to the semiconductor disk 100. It should be noted that, although typically a single laser beam is used for cutting, it is in principle possible to use multiple laser beams simultaneously.

[0088] In the example shown, the laser-processed regions 115 of the semiconductor wafer 100 are arranged in two parallel layers or planes 116. However, depending on the material and / or the thickness of the semiconductor wafer 100, it may also be possible for the regions 115 to be arranged in only one layer or plane, or in more than two layers or planes.

[0089] As shown in view 320 of Fig. As shown in Figure 4A, it is possible that one or more contact points 103 are located in the separation line region 102 of the semiconductor wafer 100, wherein the contact point(s) 103 may contain a thick or very thick metallization layer or area (e.g., a very thick final metal) which is difficult to separate well by concealed laser severing. For example, the separation of the platelet regions 101a, 101b along the separation line region 102 after application of the laser beam 220 may be difficult, e.g., by a strip expander (as shown by arrows 222 in Figure 340). Fig. 4B shown) exhibit a breaking of thick metal of the metal contact point(s) 103 located in the separation line region 102, which may be difficult and / or cause damage, e.g. cracks or chipping, in the remaining sections 102' of the separation line region 102, which may spread to the platelets or chips.

[0090] One or more embodiments may implement a concept for incorporating an easily breakable point in one or more metallization structures, e.g.

[0091] Provide metal plates, e.g., contact points (e.g., metal contact points), for example, test lead contact points, without modifying a process sequence and / or without significantly influencing probing conditions. One or more embodiments can be applied to process sequences with a thick final metal (e.g., aluminum) connected via a contact hole (e.g., aluminum contact hole) to lower metal layers (e.g., aluminum or copper).

[0092] One effect of one or more embodiments may be that a layout for a metallization structure, e.g. a metal plate, e.g. contact point (e.g. PCM or test lead contact point), for example a metal contact point with thick metal (e.g. aluminum), can be provided which is compatible with concealed laser cutting.

[0093] According to one or more embodiments, the layout of metallization structures, such as metal plates, or contact points, such as PCM (process control monitoring) or test lead contact points, can be modified to create an easily breakable point within the metallization structures (e.g., metal plates, contact points). In particular, according to one or more embodiments, at least one opening (e.g., a slot (e.g., a trench), a hole, a perforation) in a metallization structure (e.g., metal plate, contact point) can be created by appropriately modifying the layout of the metallization structure (e.g., the layout of the metal plate, e.g., the contact point layout), but without adding any additional process steps to a standard process flow.

[0094] In one or more embodiments, a metallization structure, for example a metal plate, for example a contact point, for example a metal contact point (e.g., PCM or test lead contact point), can have at least one opening, wherein a dividing line region can intersect the opening. In one or more embodiments, the at least one opening can have or be at least one hole. In one or more embodiments, the at least one hole can have or be at least one through hole. In one or more embodiments, the at least one hole can have or be at least one blind hole. In one or more embodiments, the at least one opening can have or be at least one slot. In one or more embodiments, the at least one slot can have or be at least one trench.In one or more embodiments, the at least one slot can be located in the center of the metallization structure (e.g., metal plate, contact point, metal contact point, test lead contact point). In one or more embodiments, the at least one slot can extend in a longitudinal direction of the separation line region. In one or more embodiments, the at least one opening can have or be at least one perforation.

[0095] According to one or more embodiments, the thickness of a metallization structure (e.g., metal plate, e.g., contact point), for example, the thickness of a final thick metal layer (e.g., a final thick aluminum layer) of a contact point, e.g., a PCM or test lead contact point, can be locally reduced in at least one region of the metallization structure (e.g., metal plate, e.g., contact point, e.g., metal contact point) that is intersected by at least one separation line region.

[0096] Fig. 5A represents a top view 500 of a section of a semiconductor disk 400 according to one or more embodiments, and Fig. 5B shows a cross-sectional view 550 of the section of the semiconductor disk 400 along the line BB' in Fig. 5A.

[0097] The semiconductor wafer 400 can have at least one metallization structure 403. In one or more embodiments, the metallization structure 403 can have or be a contact point 403. The contact point 403 can have at least one opening 404. The semiconductor wafer 400 can further have at least one dividing line region 402 along which the semiconductor wafer 400 is to be cut. The dividing line region 402 can intersect the opening 404.

[0098] The opening 404 can be formed at the junction 403 before the semiconductor wafer 400 is cut. In other words, the opening 404 can be formed at the junction 403 before a cutting process is carried out. In particular, the opening 404 can be formed by any process other than a cutting process.

[0099] In one or more embodiments, the contact point 403 can comprise or be made of at least one metal, such as aluminum, copper, gold, silver, tin, palladium, zinc, nickel, iron, titanium, or an alloy comprising at least one of the aforementioned metals, e.g., AlCu or AlSiCu. A contact point comprising or consisting of a metal or metal alloy can also be referred to as a metal contact point. According to other embodiments, the contact point 403 can comprise other materials, e.g., other metals or metal alloys. In one or more embodiments, the contact point 403 can comprise or be a single layer comprising or consisting of, for example, at least one of the aforementioned materials, e.g., metals or metal alloys.In one or more embodiments, the contact point 403 can have a layer stack or be a layer stack having a plurality of layers, each layer of the layer stack having, for example, at least one of the aforementioned materials, e.g., metals or metal alloys, or consisting of such material.

[0100] The semiconductor wafer 400 can, to a certain extent, resemble the semiconductor wafer 100, which is used in Fig. Figure 1 is shown. For example, the semiconductor disk 400 can have a front side 400a and a back side 400b. In one or more embodiments, the contact point 403 can be located on the front side 400a of the semiconductor disk 400, as shown. The section of the semiconductor disk 400 shown in Figure 1 is shown in Figure 1. Fig. Region 5A, as shown, can correspond, for example, to section 200 of semiconductor disk 100. Region 401a can be a first platelet region of semiconductor disk 400, and it can, for example, resemble the first platelet region 101a of semiconductor disk 100. Region 401b can be a second platelet region of semiconductor disk 400, and it can, for example, resemble the second platelet region 101b of semiconductor disk 100. The dividing line region 402 can, for example, resemble the dividing line region 102 of semiconductor disk 100.

[0101] The contact point 403 can resemble the contact point 103 of the semiconductor wafer 100 to a certain extent. For example, the contact point 403 can serve to electrically connect one or more electrical components, e.g., test components (not shown), which may be arranged in the dividing line region 402, for example, in one or more layers or levels below the contact point 403. For this purpose, the contact point 403 can be connected to the one or more electrical components, for example, by one or more electrical intermediate connections and / or contact holes (not shown), which may be located in one or more layers or levels below the contact point 403.

[0102] In contrast to contact point 103 of the semiconductor wafer 100, contact point 403 of the semiconductor wafer 400 can have the opening 404. The opening 404 can be intersected by the dividing line region 402.

[0103] In one or more embodiments, the opening 404 can be located at a center or middle of the contact point 403. For example, in one or more embodiments, the opening 404 can divide the contact point 403 into a first part 403a and a second part 403b, for example, into two halves. In one or more embodiments, the first part 403a and the second part 403b of the contact point 403 can have the same or substantially the same size (e.g., area). In one or more embodiments, the first part 403a and the second part 403b of the contact point 403 can be located on both sides of a dividing line (e.g., a scribing line) that can be generated when the semiconductor wafer 400 is cut. In other words, the first part 403a of the contact point 403 can be located on one side of the dividing line (e.g., a scribing line) and the second part 403b of the contact point 403 can be located on the other side of the dividing line (e.g., a scribing line).The second part 403b of the contact point 403 may be located on the other side of the dividing line (e.g., scribe line).

[0104] In one or more embodiments, a position of the opening 404 can correspond to a position of a center or middle of the dividing line region 402.

[0105] In one or more embodiments, the semiconductor disk 400 can have at least one test structure (not shown) which is connected to the contact point 403, wherein the separation line region 402 can intersect the test structure.

[0106] In one or more embodiments, the test structure can be configured as a process control management (PCM) monitoring structure.

[0107] In one or more embodiments, the contact point 403 can be configured as a contact point for monitoring the process control (PCM).

[0108] In one or more embodiments, a dimension 404a of the opening 404 can be defined in a transverse direction 451 (“x” direction in Fig. 5A and Fig. 5B) of the dividing line region 402 (e.g. a width of the opening 404) be smaller than a dimension of the dividing line region 402 in the transverse direction 451 of the dividing line region 402 (e.g. a width of the dividing line region 402).

[0109] In one or more embodiments, the dimension 404a of the opening 404 in the transverse direction 451 of the dividing line region 402 (e.g., the width of the opening 404) can be less than or equal to approximately 15 µm, for example, according to one embodiment, in the range of approximately 1 µm to approximately 15 µm, for example, according to one embodiment, in the range of approximately 5 µm to approximately 10 µm, although according to other embodiments, other values ​​may also be possible, for example, according to one embodiment, less than or equal to approximately 1 µm or according to one embodiment, greater than or equal to approximately 15 µm.

[0110] In one or more embodiments, the contact point 403 (for example, a metal layer (e.g., a final metal layer) of the contact point 403) can have a thickness greater than or equal to approximately 1 µm, for example, according to one embodiment, in the range of approximately 1 µm to approximately 3 µm, although according to other embodiments, other thicknesses are also possible, for example, less than 1 µm or greater than 3 µm. In one or more embodiments, the aforementioned "thickness" can refer to the thickness of a final (or topmost) metallization layer or plane (e.g., Metal-N) of a metallization layer stack. It is understood that the metallization layer stack includes one or more additional metallization layers or planes (e.g., Metal-(N-1), Metal-(N-2), ..., Metal-1) besides the final metallization layer or plane (not shown in Figure 1). Fig. 5A and Fig. 5B, see e.g. Fig. 11E) and may have one or more vertical intermediate connections (contact holes) between adjacent metallization layers or planes, e.g., between metal-N and metal-(N-1), between metal-(N-1) and metal-(N-2), etc. It is understood that the total thickness of the metallization layer stack (including all metallization layers / planes and any contact holes) may be greater than the thickness of the last metallization layer alone.

[0111] In one or more embodiments, the depth 404c of the opening 404 can be equal to or substantially equal to the thickness of the contact point 403, for example, equal to or substantially equal to the thickness of a final thick metal layer. In one or more embodiments, the depth 404c of the opening 404 or the thickness of the contact point 403 can be defined as a dimension of the opening 404 and / or a dimension of the contact point 403 in a direction 453 (the "z" direction). Fig. 5B) perpendicular to a main processing surface of the semiconductor wafer 400, for example, a direction 453 perpendicular to the front face 404a of the semiconductor wafer 400. The direction 453 can, for example, be perpendicular to the transverse direction 451 (“x” direction) as well as a longitudinal direction 452 (“y” direction in Fig. 5A) of the dividing line region 402. For example, the opening 404 can extend through the entire thickness of the contact point 403. For example, the opening 404 can extend from a top surface 413 of the contact point 403 to a bottom surface 423 of the contact point 403, as shown.

[0112] According to other embodiments, the depth 404c of the opening 404 can be less than the thickness of the contact point 403 (not shown, see figure). Fig. 7B).

[0113] In one or more embodiments, a dimension 404b of the opening 404 in the longitudinal direction 452 (“y” direction in Fig. 5A) of the dividing line region 402 (e.g., a length of the opening 404) is equal to or substantially equal to a dimension of the contact point 403 in the longitudinal direction 452 of the dividing line region 402 (e.g., a length of the contact point 403). For example, the opening 404 in the longitudinal direction 452 of the dividing line region 402 may extend over the entire contact point 403.

[0114] In one or more embodiments, the opening 404 may have a slot or be a slot extending in the longitudinal direction 452 of the dividing line region 402, as shown in view 500 of Fig. 5A is shown.

[0115] In one or more embodiments, the length of the slot can be equal to or substantially equal to a dimension (e.g., the length) of the contact point 403 in the longitudinal direction 452 of the parting line region 402, as shown in view 500 of Fig. Figure 5A is shown. In other embodiments, the length of the slot can be shorter than the length of the contact point 403.

[0116] The opening 404 in the contact point 403 can provide an easily breakable point along the separation line region 402 when the semiconductor disk 400 is cut, for example by concealed laser cutting, as described below.

[0117] Fig. 6A and Fig. Figure 6B shows views 620 and 640 respectively, illustrating a hidden laser splitting process applied to the semiconductor disk 400 to demonstrate one or more embodiments.

[0118] Similar to previous in connection with Fig. 3, Fig. 4A and Fig. As described in Figure 4B, a concealed laser sectioning of the semiconductor disk 400 can be performed by laser processing of localized points or regions 415 in the dividing line region 402 of the semiconductor disk 400 by a laser beam 220, as shown in Figure 620. Fig. 6A shown, and separation of the platelet regions 401a, 101b along the dividing line region 402 e.g. by a strip expander (as shown by arrows 222 in view 640 of Fig. 6B shown) after the application of the laser beam 220.

[0119] The laser beam 220 can enter the semiconductor disk 400 from the rear side 400b of the semiconductor disk 400, as shown in view 620. Fig. 6A is shown.

[0120] In the example shown, the laser-processed regions 415 are arranged in two parallel layers or planes 416. However, depending on the material and / or the thickness of the semiconductor wafer 400, it may also be possible for the regions 415 to be arranged in only one layer or plane, or in more than two layers or planes.

[0121] As shown in view 620 of Fig. As shown in Figure 6A, the contact point 403 with the opening 404 can be located in the separation line region 402 of the semiconductor wafer 400. The contact point 403 can, for example, have or be a thick or very thick metallization layer or area (e.g., a very thick last metal). Normally, such thick or very thick metallization layers or areas can be difficult to separate by concealed laser severing, as previously discussed in conjunction with Fig. 4A and Fig. 4B described. However, the contact point 403 of the semiconductor disk 400 has the opening 404, which can provide an easily breakable point. Accordingly, the separation of the platelet regions 401a, 401b along the separation line region 402 can be easily carried out without having to break a thick metal of the contact point 403. To illustrate, the contact point 403 can be pre-divided or separated (at least partially) by the opening 404 in the contact point 403 before the semiconductor disk 400 is cut. Therefore, the separation of the platelet regions 401a and 401b along the separation line region 402 is easily accomplished. B. by a strip expander possibly only a breaking of layers or material of the semiconductor disk 400 which can break relatively easily, for example semiconductor (e.g. silicon) layers, dielectric layers or thin metal layers (e.g. metal layers of lower metallization levels with a small thickness).Therefore, damage, e.g. cracks and / or chipping, in the remaining sections 402' of the dividing line region 402 can be prevented or significantly reduced, for example.

[0122] Fig. Figure 7A represents a top view 700 of a section of a semiconductor wafer 400' according to one or more embodiments, and Fig. 7B shows a cross-sectional view 750 of the section of the semiconductor disk 400' along line BB' in Fig. 7A.

[0123] The semiconductor disk 400' can resemble, to a certain extent, the semiconductor disk 400 that is in Fig. 5A and Fig. As shown in section 5B. In particular, the same reference symbols can denote the same or similar elements there and are not described in detail here. Instead, reference is made to the preceding description.

[0124] The semiconductor disk 400' can have at least one metallization structure 403'. In one or more embodiments, the metallization structure 403' can be a metal plate. In one or more embodiments, the metallization structure 403' can be a contact point. Hereinafter, the metallization structure 403' is described as a contact point 403'. The contact point 403' can have at least one opening 404'. The dividing line region 402 can intersect the opening 404'.

[0125] The opening 404' can be formed at the junction 403' before the semiconductor wafer 400' is cut. In other words, the opening 404' can be formed at the junction 403' before any cutting process is performed. In particular, the opening 404' can be formed by any process other than a cutting process.

[0126] The contact point 403' can be similar to the contact point 403 of the semiconductor disk 400, as shown, except that the depth 404c of the opening 404' can be less than the thickness of the contact point 403'. In some embodiments, the opening 404' can be configured as a slot (e.g., a trench) with one or more side walls 414a and a bottom wall 414b.

[0127] As shown, the opening 404' can extend only through part of the thickness of the contact point 403'. The opening 404' can extend from a top surface 413 of the contact point 403' to a bottom wall 414b of the opening 404', which may be located above the bottom surface 423 of the contact point 403'.

[0128] Accordingly, in one or more embodiments, a distance 404d between the bottom wall 414b of the opening 404' and the underside 423 of the contact point 403', which corresponds, for example, to a thickness of the contact point 403' in a region below the opening 404', can be other than zero, and it can be, for example, 2 µm, for example, less than or equal to about 1 µm, for example, less than or equal to about 500 nm, for example, less than or equal to about 200 nm, for example, less than or equal to about 100 nm, for example, less than or equal to about 50 nm, for example, less than or equal to about 10 nm, for example, in the range of about 10 nm to about 2 µm, for example, in the range of about 10 nm to about 1 µm, for example, in the range of about 10 nm to about 500 nm, for example, in the range of about 10 nm to about 200 nm, for example, in the range of about 10 nm to about 100 nm, for example in the range of about 10 nm to about 50 nm,although other values ​​may be possible according to other embodiments.

[0129] In one or more embodiments, a dimension 404b of the opening (e.g., of the slot (e.g., of the trench)) 404' in the longitudinal direction 452 (“y” direction in Fig. 6A) of the dividing line region 402 (e.g., a length of the opening 404') is equal to or substantially equal to a dimension of the contact point 403' in the longitudinal direction 452 of the dividing line region 402 (e.g., a length of the contact point 403'), as shown. For example, the opening (e.g., the slot (e.g., the trench)) 404' in the longitudinal direction 452 of the dividing line region 402 may extend over the entire contact point 403'. According to other embodiments, the dimension 404b of the opening 404' may be smaller than the dimension of the contact point 403' in the longitudinal direction 452 of the dividing line region 402.

[0130] The opening 404' in the contact point 403' can provide an easily breakable point when dividing the semiconductor wafer 400' along the separation line region 402, for example by concealed laser dividing, as described above. In particular, by forming the opening 404' in the contact point 403', a section of the contact point 403' (for example, a central section of the contact point 403') can be thinned, so that when separating the platelet regions 410a and 401b along the separation line region 402, for example in a concealed laser dividing process for dividing the semiconductor wafer 400', for example similarly to what was described above in conjunction with Fig. 6A and Fig. As described in 6B, it can be easily separated.

[0131] Fig. Figure 8 shows a top view of a section of a 400'' semiconductor wafer according to one or more embodiments.

[0132] The 400'' semiconductor disk can, to a certain extent, be used in the 400'' semiconductor disk that is in Fig. 5A and Fig. 5B is shown, and / or resemble the semiconductor disk 400' shown in Fig. 7A and Fig. Figure 7B illustrates this. In particular, the same reference symbols can denote the same or similar elements, which are not described in detail here. Instead, reference is made to the preceding description.

[0133] The semiconductor wafer 400'' can have at least one metallization structure 403''. In one or more embodiments, the metallization structure 403'' can be a metal plate. In one or more embodiments, the metallization structure 403'' can be a contact point. Hereinafter, the metallization structure 403'' is described as a contact point 403''. The contact point 403'' can have a plurality of openings 404'' (three openings 404'' are shown as an example, but the number of openings 404'' can vary, generally, for example, greater than or equal to two). The dividing line region 402 can intersect the plurality of openings 404''.

[0134] The openings 404'' can be formed at the junction 403'' before the semiconductor wafer 400'' is cut. In other words, the openings 404'' can be formed at the junction 403'' before a cutting process is performed. In particular, the openings 404'' can be formed by any process other than a cutting process.

[0135] In one or more embodiments, the openings 404'' can be holes. In one or more embodiments, one or more, e.g., all, of the holes 404'' can be through holes, i.e., extending through the entire thickness of the contact point 403'' (similar to the opening 404 in the contact point 403). In one or more embodiments, one or more, e.g., all, of the holes 404'' can be blind holes, i.e., extending only through a part of the contact point 403'' (similar to the opening 404' in the contact point 403').

[0136] In one or more embodiments, the openings 404'' can be aligned in the longitudinal direction 452 of the dividing line region 402. For example, the openings 404'' can be arranged to form a chain. In one or more embodiments, the openings 404'' can be equally spaced.

[0137] In one or more embodiments, a dimension 404a of one or more, e.g. all, of the openings 404'' in the transverse direction 451 of the dividing line region 402 can be similar to that previously described for the opening 404 in the contact point 403.

[0138] In one or more embodiments, the openings 404'' can all have the same shape (e.g., the same cross-sectional shape) and / or the same size (e.g., the same length, width, and / or depth). In one or more embodiments, at least one of the openings 404'' can have a different shape (e.g., a different cross-sectional shape) and / or size (e.g., a different length, width, and / or depth) than the other openings 404''.

[0139] To illustrate, the contact point 403'' of the semiconductor wafer 400'' can have a perforated structure with a plurality of openings 404'' (e.g., holes (e.g., through holes and / or blind holes)). The openings 404'' in the contact point 403'' can provide an easily breakable point when the semiconductor wafer 400'' is cut, for example, by concealed laser cutting, as described previously.

[0140] Fig. Figure 9 shows a top view of a section of a 400''' semiconductor disk according to one or more embodiments.

[0141] The semiconductor wafer 400''' may, to a certain extent, resemble the semiconductor wafer 400, the semiconductor wafer 400', and / or the semiconductor wafer 400''. In particular, the same reference numerals may denote the same or similar elements as those described therein and will not be further detailed here. Reference is made instead to the preceding description.

[0142] The semiconductor wafer 400''' can have at least one metallization structure 403'''. In one or more embodiments, the metallization structure 403''' can be a metal plate. In one or more embodiments, the metallization structure 403''' can have a contact point. Hereinafter, the metallization structure 403''' is described as a contact point 403'''. The contact point 403''' can have at least one opening 404'''. The semiconductor wafer 400''' can further have at least one first dividing line region 402a and a second dividing line region 402b along which the semiconductor wafer 400''' is to be divided. The opening 404''' can have a first section 424 extending in a longitudinal direction ('y' direction 452) in Fig. 9) of the first dividing line region 402a, and have a second section 425 extending in a longitudinal direction (“x” direction 451) of the second dividing line region 402b. In one or more embodiments, the first section 424 and the second section 425 of the opening 404''' can intersect at an intersection point of the first dividing line region 402a and the second dividing line region 402b. In one or more embodiments, the first section 424 and the second section 425 of the opening 404''' can be configured as first and second slots, respectively, extending, for example, over the contact point 403''', with the first and second slots being oriented along the longitudinal directions of the first and second dividing line regions 402a and 402b, respectively.

[0143] For illustrative purposes, the contact point 403''', which has the opening 404''', can be located at an intersection of the two dividing line regions 402a, 402b, along which the semiconductor disk 400''' is to be divided. In one or more embodiments, the one or more platelet regions 401 can be located adjacent to or near the intersection of the dividing line regions 402a, 402. As an example, the first to fourth platelet regions 401a, 401b, 401c, 401d in Fig. 9 is shown, but the number of adjacent platelet regions 401 can be different from four, according to some embodiments one, two or three.

[0144] The opening 404''' can be formed at the junction 403''' before the semiconductor wafer 400''' is cut. In other words, the opening 404''' can be formed at the junction 403''' before any cutting process is performed. In particular, the opening 404''' can be formed by any process other than a cutting process.

[0145] In one or more embodiments, the opening 404''' can extend through the entire thickness of the contact point 403''' (similar to the openings 404 in the contact point 403). In one or more embodiments, the opening 404''' can extend only through a part of the contact point 403''' (similar to the openings 404' in the contact point 403').

[0146] In one or more embodiments, a dimension of the first section 424 of the opening 404''' in the transverse direction (“x” direction 451) of the first dividing line region 402a and / or a dimension of the second section 425 of the opening 404''' in the transverse direction (“y” direction 452) of the second dividing line region 402b may be similar to the dimension 404a of the opening 404 in the contact point 403.

[0147] The opening 404''', which has the first section 424 (e.g. the first slot) and the second section 425 (e.g. the second slot), can provide an easily breakable point when dividing the semiconductor disk 400''', for example by concealed laser dividing along the first and / or second dividing line regions 402a, 402b.

[0148] Fig. 10 represents a method 1000 for processing a semiconductor wafer according to one or more embodiments.

[0149] At 1020, a semiconductor disk can be provided, wherein the semiconductor disk has at least one metallization structure and at least one dividing line region along which the semiconductor disk is to be cut.

[0150] At 1040, at least one opening can be formed in the at least one metallization structure, wherein the at least one dividing line region intersects the at least one opening.

[0151] In one or more embodiments, the at least one opening can have or be at least one hole. In one or more embodiments, the at least one hole can have or be at least one through hole. In one or more embodiments, the at least one hole can have or be at least one blind hole. In one or more embodiments, the at least one opening can have or be at least one slot. In one or more embodiments, the at least one slot can have or be at least one trench. In one or more embodiments, the at least one opening can have or be at least one perforation.

[0152] In one or more embodiments, the at least one metallization structure can comprise or be at least one metal plate. In one or more embodiments, the at least one metallization structure can comprise or be at least one contact point.

[0153] In one or more embodiments, the method 1000 (at 1060) may further include electrical contacting of the at least one metallization structure after forming the at least one opening in the at least one metallization structure and before dividing the semiconductor disk along the at least one dividing line region.

[0154] In one or more embodiments, the electrical contacting of the at least one metallization structure can include contacting the at least one metallization structure with a probe.

[0155] In one or more embodiments, the method 1000 (at 1080) may further include a splitting of the semiconductor disk along the at least one dividing line region after forming the at least one opening in the at least one metallization structure.

[0156] In one or more embodiments, the dividing of the semiconductor disk along the at least one dividing line region can involve or be achieved by concealed dividing of the semiconductor disk along the at least one dividing line region.

[0157] In one or more embodiments, the at least one metallization structure (e.g., metal plate, e.g., contact point) can comprise or consist of at least one metal or metal alloy.

[0158] Method 1000 can furthermore be configured according to one or more embodiments described herein.

[0159] Fig. 11A to Fig. Figure 11H presents various views illustrating a method for processing a semiconductor wafer according to one or more embodiments.

[0160] As in Fig. As shown in view 1100, a semiconductor disk 1100' can be provided. The semiconductor disk 1100' can have a dividing line region 1102, for example a notch cut region or a scribing line region, along which the semiconductor disk 1100' is to be divided.

[0161] The semiconductor wafer 1100' can have a metallization layer 1150, which may be located at least partially in the dividing line region 1102. In one or more embodiments, the metallization layer 1150 can be a penultimate metallization layer of the semiconductor wafer 1100' (also referred to as metal-(N-1), where N is a final metallization layer of the semiconductor wafer 1100'). The metallization layer 1150 can have one or more metallization structures, such as one or more electrical interconnects. The metallization layer 1150 can, for example, be electrically connected to one or more other metallization layers (e.g., N-2, N-3, ... etc.) and / or one or more electrical or electronic components or one or more electrical or electronic structures of the semiconductor wafer 1100' located beneath the metallization layer 1150 (not shown).In one or more embodiments, the metallization layer 1150 can comprise or consist of a metal or metal alloy, such as Al, Cu, AlCu, or AlSiCu, although other materials (e.g., metals or metal alloys) are also possible. In one or more embodiments, a top layer (comprising or consisting of, for example, Ti, TiN, or TaN, although other materials are also possible) can be applied at least over a portion of the metallization layer 1150, e.g., over a top surface of the metallization layer 1150 (not shown).

[0162] In one or more embodiments, the metallization layer 1150 can have a thickness in the range of about 400 nm to about 1.5 µm, although according to other embodiments, for example depending on the material(s) used for the metallization layer 1150 and / or the process technology used, other thicknesses (e.g. less than 400 nm or greater than 1.5 µm) may also be possible.

[0163] One or more intermetallic dielectric (IMD) layers 1151 can be inserted between metallization layers of the semiconductor wafer 1100''. As shown in Fig. As shown in Figure 11A, an IMD layer 1152 can be applied to the metallization layer 1150. In one or more embodiments, the IMD layer 1152 can be a final IMD layer of the semiconductor wafer 1100'.

[0164] As in Fig. As shown in Figure 11B in a view 1120, at least a portion of the IMD layer 1152 can be removed to form an opening 1153 in the IMD layer 1152. The opening 1153 can expose at least a portion of the metallization layer 1150, for example, at least a portion of a top surface 1150a of the metallization layer 1150. In one or more embodiments, the removal of at least a portion of the IMD layer 1152 can involve or be achieved by etching. For example, in one or more embodiments, the opening 1153 can be formed using a contact hole etching process.

[0165] As in Fig. As shown in view 1140, a metallization layer 1103' can be applied to the IMD layer 1152 and the exposed portion of the metallization layer 1150. In one or more embodiments, the metallization layer 1103' can include or be a final metallization layer (also referred to as metal-(N), where N is a final metallization layer of the semiconductor wafer 1100'). In one or more embodiments, the metallization layer 1103' can be aluminum (Al), although other metals or metal alloys are possible according to other embodiments.

[0166] In one or more embodiments, the metallization layer 1103' can comprise or be a thick final metal layer of the semiconductor wafer 1100'. For example, in one or more embodiments, the metallization layer 1103' can have a thickness greater than or equal to approximately 1 µm, in some embodiments, for example, in the range of approximately 1 µm to approximately 3 µm. However, other thicknesses are also possible according to other embodiments.

[0167] As in Fig. As shown in Figure 11D in a view 1160, the metallization layer 1103' can be structured to form a metallization structure 1103. In one or more embodiments, the metallization structure 1103 can comprise or be a metal plate. In one or more embodiments, the metallization structure 1103 can comprise or be a contact point. Hereinafter, the metallization structure 1103 is described as a contact point 1103. In one or more embodiments, the structuring of the metallization layer 1103' can comprise or be achieved by etching the metallization layer 1103' using an etching mask, which can be defined, for example, using a photolithography process.

[0168] Structuring the metallization layer 1103' to form the contact point 1103 can involve forming at least one opening 1104 in the metallization layer 1103'. In one or more embodiments, the opening 1104 can extend only through a portion of the thickness of the metallization layer 1103'. In this case, there can be a non-zero distance between the bottom wall 1114b of the opening 1104 and the top surface 1150a of the metallization layer 1150. In one or more embodiments, the opening 1104 can extend through the entire thickness of the metallization layer 1103'. In one or more embodiments, the opening 1104 can extend down to the top surface 1150a of the metallization layer 1150' (or to a top surface of a cover layer (not shown) arranged above the metallization layer 1150') or, in some embodiments, even at least partially into the metallization layer 1150' (as shown).In the latter case, the bottom wall 1114b can be located below the top surface 1150a of the metallization layer 1150, as shown. It is understood that the depth of the opening 1104 can be influenced or controlled by a number of factors, such as the depth of the opening 1153, over-etching during the texturing of the opening 1153, and / or the dimensioning of the opening 1104 (for example, a greater width typically results in a greater depth). In one or more embodiments, the opening 1104 can be a slot extending in a longitudinal direction of the parting line region 1102 (i.e., a direction perpendicular to the plane of the drawing). Fig. 11D) extends via contact point 1103.

[0169] Accordingly, structuring the metallization layer 1103' can provide the contact point 1103 with at least one opening 1104. Structuring the metallization layer 1103' can, for example, involve etching the metallization layer 1103' (e.g., etching the last metal layer), for instance, by using an etching mask to define the contact point 1103. In one or more embodiments, the etching mask can have at least one additional opening (compared to the number of openings in a standard etching mask used to define a contact point), which can be used to define the at least one opening 1104 of the contact point 1103. In one or more embodiments, the at least one additional opening in the etching mask can be located along a center point of the parting line region 1102 (e.g., along a scribe line center point).In other words, the position of the at least one opening in the etching mask can correspond to the center of the separation line region 1102 (e.g., the center of the scribed line). Similarly, the position of the at least one opening 1104 in the contact point 1103 can correspond to the center of the separation line region 1102 according to one or more embodiments.

[0170] As in Fig. As shown in Figure 1180, a passivation layer 1154 (e.g., a hard passivation comprising or consisting of, for example, an oxide, nitride, and / or oxynitride material, although other materials are also possible) can be formed (e.g., applied) over the contact point 1103. In one or more embodiments, the passivation layer 1154 can, for example, cover a surface of the contact point 1103, e.g., one or more side walls 1114 and / or a top surface 1113 of the contact point 1103. In one or more embodiments, the passivation layer 1154 can at least partially fill the opening 1104, as shown.

[0171] As in Fig. As shown in Figure 1200, at least part of the passivation layer 1154 can be removed to expose at least part of the contact point 1103, for example, to expose at least part of the top surface 1113 of the contact point 1103. The removal of the passivation layer 1154 can, for example, be achieved by etching (passivation release etching). Part of the passivation layer 1154 can remain over the contact point 1103, for example, over one or more side walls 1114 of the contact point 1103 and / or over part of the top surface 1113 of the contact point 1103, as shown. Furthermore, in one or more embodiments, part of the passivation layer 1154 can remain in the opening 1104 and, for example, cover the bottom wall 1114b and / or part of the side walls of the opening 1104.

[0172] In one or more embodiments, the contact point 1103 can be configured as a PCM or test lead contact point and, for example, serve to electrically connect one or more test structures (e.g., PCM structures). In one or more embodiments and as described in Fig. As shown in view 1220, the contact point 1103 (e.g., PCM or test lead contact point) can be contacted by a probe 1155 for testing purposes. In one or more embodiments, the contact point 1103 can be contacted before the semiconductor disk 1100' is cut along the dividing line region 1102. Fig. 11G shows that probing is still possible even with a contact point 1103 with one or more openings 1104.

[0173] In one or more embodiments, the semiconductor disk 1100' can be cut along the dividing line region 1102 (for example, by concealed laser cutting). In one or more embodiments, the cutting can be carried out after electrical contacting the contact point 1103 for testing purposes. In connection with the cutting, the contact point 1103 with the opening 1104 can provide an easily breakable point of the semiconductor disk 1100' in the middle of the dividing line region 1102, e.g., in the middle of a scribed line, since cutting the contact point 1103 may not require, for example, breaking a thick metal layer, as described in Fig. 11H is shown in view 1240. In the Fig.In the embodiment shown in Figures 11A to 11H, the opening 1104 is shown to extend all the way through the metallization layer 1103' of the contact point 1103 and partially into the (penultimate) metallization layer 1150, with the bottom wall 1114b of the opening 1104 being located below the top surface 1150a of the metallization layer 1150. It is understood, however, that in other embodiments the opening 1104 may extend only through a portion of the metallization layer 1103', with the bottom wall 1114b of the opening 1104 being located at or above the top surface 1150a of the metallization layer 1150 (or at or above a top surface of a cover layer provided above the metallization layer 1150). In these cases, contact point 1103 can provide an easily breakable point, which can facilitate cutting (e.g. by concealed laser cutting).

[0174] One aspect of the method for processing a semiconductor wafer according to the embodiment illustrated above is that the opening 1104 (e.g. a slot (e.g. a trench)) in the contact point 1103 (e.g. a PCM or test lead contact point) can be formed without adding additional process steps to a standard process flow by appropriately modifying the contact point layout.

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