Mobile device and method for managing data with outsourcing of the same

Abstract

Mobile device with: a memory (1300; 2300) having a non-volatile memory (1300; 2300) configured to store data; a buffer memory (1200; 2200) configured to include a swap victim buffer area (1230; 2230) and a normal data area (1250; 2250); and an application processor (1100; 2100) configured to select memory page data to be swapped out from the normal data area (1250; 2250) and to perform a swap operation on the selected memory page data, wherein, depending on the data type of the selected memory page data, the paging operation performs an immediate paging operation in which the memory page data is moved from the normal data area (1250; 2250) to the memory (1300; 2300), or a delayed paging operation in which the memory page data is moved from the normal area (1250; 2250) via the paging victim buffer area (1230; 2230) to the memory (1300; 2300).

Description

TECHNICAL FIELD

[0001] The inventive concept of the present invention relates to a mobile device and a method for managing data with offloading. DISCUSSION OF RELATED TECHNOLOGY

[0002] Mobile devices such as smartphones, tablets, or notebook computers run various application programs. Some application programs are loaded into the mobile device's volatile memory. When a new program is loaded into the volatile memory, some application programs can be swapped to non-volatile memory.

[0003] DE 694 24 767 T2 discloses a method that enables a coherent write operation to be performed for a data block that is smaller than a full cache line. A computer system comprises a memory, an input / output adapter, and a processor. The processor includes a cache. When a coherent write is performed from the input / output adapter to the memory, a data block is written from the input / output adapter to a storage location in the memory. The data block comprises less data than a full cache line in the cache. For example, a message is sent over a bus connecting the memory, the input / output adapter, and the processor. The message includes an address of the storage location and a coherence index for the storage location. A fast DMA transaction is enabled for data blocks that are smaller than a full cache line. SUMMARY

[0004] Exemplary embodiments of the inventive concept are set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] These and other features of the inventive concept will become more apparent by describing detailed exemplary embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 is a block diagram illustrating a mobile device according to an exemplary embodiment of the inventive concept; Fig. 2 is a block diagram illustrating a memory hierarchy according to an exemplary embodiment of the inventive concept; Fig. 3 is a flowchart illustrating a data management method according to an exemplary embodiment of the inventive concept; Fig. 4 is a flowchart illustrating a relocation determination method according to an exemplary embodiment of the inventive concept; Fig. 5 is a flowchart illustrating a memory page data type determination method according to an embodiment of the inventive concept; Fig. 6 is a flowchart illustrating a data type determination method according to an exemplary embodiment; Fig. 7 is a flowchart illustrating a memory page data type determination method according to an exemplary embodiment of the inventive concept; Fig. 8 is a flowchart illustrating a data type determination method according to an exemplary embodiment; Fig. 9 is a flowchart illustrating a threshold control method according to an exemplary embodiment of the inventive concept; Fig. 10 is a block diagram illustrating a mobile device according to an exemplary embodiment of the inventive concept; Fig. 11 is a block diagram illustrating a memory hierarchy according to an exemplary embodiment of the inventive concept; Fig. 12 is a flowchart illustrating a memory page data type determination method according to an exemplary embodiment of the inventive concept; Fig. 13 is a flowchart illustrating an immediate offloading method according to an exemplary embodiment of the inventive concept; Fig. 14 is a flowchart illustrating a delayed offloading method according to an exemplary embodiment of the inventive concept; Fig. 15 and Fig. 16 are diagrams illustrating an immediate or delayed swap operation performed in a DRAM according to an exemplary embodiment of the inventive concept; and Fig. 17 is a flowchart illustrating a recovery procedure for paged memory data. DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0006] Exemplary embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings. However, the inventive concept may be embodied in various forms and should not be construed as limited to the embodiments set forth below. Like reference numerals refer to like elements throughout the description and the drawings.

[0007] It will be understood that when an element is described as being "coupled to" another element, it may be directly coupled to the other element or there may be intervening elements.

[0008] Fig. 1 is a block diagram illustrating a mobile device according to an exemplary embodiment of the inventive concept. Referring to Fig. 1, a mobile device 1000 includes an application processor (AP) 1100, a DRAM (dynamic random access memory) 1200, a flash memory 1300, a modem 1400, and a user interface 1500.

[0009] The application processor 1100 controls the overall operation of the mobile device 1000 and performs logical operations. The application processor 1100 may be implemented as a system-on-chip (SoC).

[0010] The application processor 1100 includes a bus 1110, a CPU (central processor) 1120, a direct memory access (DMA) 1130, an unpacker 1140, a DRAM interface 1150, an SRAM (static random access memory) 1160, and a flash interface 1170. In Fig. 1, interfaces that enable the application processor 1100 to communicate with the modem 1400 and the user interface 1500 are not shown.

[0011] Bus 1110 provides a channel between components of application processor 1100. CPU 1120 performs a main computation operation, performs a data processing operation, and provides overall control of application processor 1100. Direct memory access 1130 controls data exchange between memories, including DRAM 1200 and flash memory 1300.

[0012] The DMA 1130 operates under the control of the CPU 1120. For example, the DMA 1130 is programmed by the CPU 1120 and operates according to the programmed state. The programmed DMA 1130 controls data flow between memory elements of the mobile device 1000 without control of the CPU 1120. For example, the DMA 1130 controls data flow between at least two of the DRAM 1200, the SRAM 1160, and the flash memory 1300.

[0013] The unpacker 1140 unpacks compressed memory page data. The unpacker 1140 can be implemented as a hardware unit. The DRAM interface 1150 supports communication with the DRAM 1200. The SRAM 1160 serves as a cache memory, buffer memory, or temporary memory of the application processor 1100. The flash interface 1170 supports communication with the flash memory 1300.

[0014] The DRAM 1200 serves as a buffer memory or as a working memory of the mobile device 1000. For example, an example is shown in which a working memory of the mobile device 1000 is formed from the DRAM 1200. However, the working memory of the mobile device 1000 may include various memories such as an SRAM, a NOR flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. The working memory may be non-volatile or volatile.

[0015] Flash memory 1300 serves as a storage device for storing data. In an exemplary embodiment, the storage device may include, but is not limited to, a hard disk drive or non-volatile memory, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0016] The modem 1400 performs wireless or wired communication under the control of the application processor 1100. The modem 1400 communicates using a communication protocol including Wi-Fi, CDMA (Code Division Multiple Access), GSM (Global System For Mobile Communication), LTE (Long Term Evolution), Bluetooth, NFC (Near Field Communication), etc. For example, the modem 1400 may be integrated with the application processor 1100 in a system-on-chip device.

[0017] The user interface 1500 exchanges signals with an external device. For example, the user interface 1500 may include user input interfaces including a keyboard, a keypad, a switch, an interactive control panel, a touch screen, a touchpad, a touch ball, a camera, a microphone, a gyroscope sensor, or a vibration sensor. The user interface 1500 may also include user output interfaces including an LCD (liquid crystal display), an OLED (organic light-emitting diode) display, an AMOLED (active matrix OLED) display, an LED, a speaker, or a motor.

[0018] Fig. 2 is a block diagram showing an architecture for data areas of the DRAM and the flash memory device of Fig. 1. With reference to Fig. 2, the DRAM 1200 contains a swap victim buffer area (SVB) 1230 and a normal data area (NDA) 1250.

[0019] When data from the normal data area 1250 is swapped to the flash memory 1300, the swapped data is temporarily stored in the swap victim buffer area 1230. For example, at least a portion of the data stored in the normal data area 1250 is moved to the swap victim buffer area 1230 and then to the flash memory 1300.

[0020] The normal data area 1250 is accessed by processes run by the application processor 1100. For example, codes of the processes or data managed by the processes are stored in the normal data area 1250.

[0021] For example, in the DRAM 1200, data is managed by a memory page unit. A memory page has a size defined by an operating system (OS) of the mobile device 1000. Codes or data of processes are stored in the DRAM 1200 by the memory page unit and are read from the DRAM 1200 by the memory page unit. Hereinafter, the data accessed by the memory page unit may be referred to as memory page data.

[0022] Flash memory 1300 serves as a storage device of mobile device 1000. Flash memory 1300 stores user data and swap data. For example, application processor 1100 stores processed data (e.g., data including process data or data managed by a process) in DRAM 1200 and swaps a portion of the processed data to flash memory 1300. Swap data may be data swapped out by application processor 1100.

[0023] Fig. 3 is a flowchart showing a data management method of the mobile device of Fig. 1 according to an exemplary embodiment of the inventive concept. For example, a data management method of an application processor 1100 is shown in Fig. 3 shown.

[0024] In step S110, it is determined whether a swap operation is required. The application processor 1100 determines whether memory page data stored in the normal data area 1250 is to be moved to the flash memory 1300. If a swap operation is not required, the method ends. If the swap operation is required, the method proceeds to step S120. Step S110 will be described more fully with reference to Fig. 4 are described.

[0025] In step S120, a type of the memory page data stored in the DRAM 1200 is determined. For example, the application processor 1100 determines a type of the memory page data selected as a swap target from the memory page data stored in the normal data area 1250. The method step S120 will be described more fully with reference to Fig. 5 to 8 and 12.

[0026] In step S130, the swap operation is performed in a delayed swap or an immediate swap according to the data type determined in step S120. Step S130 will be described more fully with reference to Fig. 13 to 16.

[0027] Fig. 4 is a flowchart showing the method step S110 of Fig. 3 in detail according to an exemplary embodiment of the inventive concept. Referring to the Fig. 1 and Fig. 4, in method step S210, it is determined whether the application processor 1100 is executing a different process than the processes that the application processor 100 has stored in the DRAM 1200, for example. In this case, the application processor 1100 allocates a memory location of the DRAM 1200 for the new process. For example, one or more memory pages of the normal data area 1250 can be assigned to the new process of the application processor 1100.

[0028] In step S220, it is determined whether DRAM 1200 has free memory space to accommodate the process of application processor 1100. Application processor 1100 allocates a predetermined number of memory pages of normal data area 1250 to the process. For example, application processor 1100 determines the number of memory pages required for the process based on a history of the process.

[0029] If the number of memory pages required by the process is less than the free space of the normal data area 1250, it is determined that the normal data area 1250 has enough free space for the process and thus no paging operation is required (S230).

[0030] If the number of memory pages required by the process exceeds the free space in the normal data area 1250, it is determined that the normal data area 1250 is insufficient for the process, and thus a swap operation is required (S240). For example, some processes stored in the DRAM 1200 are moved to the flash memory 1300 to create storage space for new processes.

[0031] Fig. 5 is a flowchart showing the method step S120 of Fig. 3 according to an exemplary embodiment of the inventive concept.

[0032] In step S310, memory page data is read from a normal data area 1250, and the read memory page data is compressed. For example, a CPU 1120 reads memory page data selected as a swap target from a normal data area 1250 of a DRAM 1200 through a DRAM interface 1150. The CPU 1120 can compress the read memory page data.

[0033] In step S320, it is determined whether a compression ratio of the compressed memory page data is higher than a threshold. For example, the CPU 1120 compresses the read memory page data and then compares the compression ratio of the compressed memory page data with the threshold.

[0034] If the compression ratio is not higher than a threshold, a data type of the read memory page data is determined to be an immediate type in step S340. For example, memory page data with the immediate type has a compression ratio less than the threshold. If a data type of the read memory page data is determined to be an immediate type, the compressed memory page data may be deleted.

[0035] If the compression ratio is higher than the threshold, a data type of the read memory page data is determined to be a delayed type in step S330. For example, memory page data with the delayed type has a compression ratio higher than the threshold. If a data type of the read memory page data is determined to be a delayed type, the compressed memory page data is shifted to the swap victim buffer area 1230. In this case, the application processor 1100 can reduce the number of swap operations, and thus, system performance can be improved.

[0036] In step S350, the data type is stored as protocol information. For example, the CPU 1120 stores the data type of the memory page data in the SRAM 1160 as the protocol information. The CPU 1120 stores an identifier of a process using the memory page data, information indicating whether the memory page data is code or data, and the data type of the memory page data as the protocol information. The protocol information stored in the SRAM 1160 is saved to a flash memory 1300 periodically according to a predetermined schedule or in response to the generation of a specific event (e.g., power off). When a power supply of a mobile device 1000 is turned on, the protocol information saved in the flash memory 1300 is copied to the SRAM 1160.

[0037] Fig. 6 is a flowchart illustrating a data type determination method of a CPU when predicting a data type according to an exemplary embodiment.

[0038] In step S360, a data type of the memory page data is read from the protocol information. The data type of the memory page data is predicted based on header information of the memory page data. The CPU 1120 reads protocol information stored in the SRAM 1160 and determines a data type of the memory page data contained in the protocol information.

[0039] In step S370, it is determined whether the read data type is a delayed type. If the read data type is not a delayed type, compression of the page data stored in the normal data area 1250 is omitted, and the process ends. If the read data type is a delayed type, in step S380, page data is read from the normal data area 1250, and the read page data is compressed. The compressed page data is paged out using a delayed paging operation.

[0040] Fig. Fig. 7 is a flowchart showing step S120 of Fig. 3 according to an exemplary embodiment of the inventive concept. Method steps S410 to S440 in Fig. 7 are carried out in a substantially similar manner as with respect to the method steps S310 to S340 in Fig. 5, and a description of it can be omitted.

[0041] In step S450, a compression ratio of memory page data selected as a swap target is stored. For example, the CPU 1120 stores a compression ratio of memory pages in the SRAM 1160 as log information. The CPU 1120 stores an identifier of a process using the memory page data, information indicating whether the memory page data is code or data, and the compression ratio of the memory page data as the log information.

[0042] Fig. Fig. 8 is a flowchart schematically illustrating a data type determination process of a CPU when a Fig. 7 specific compression ratio (or data type) is stored as protocol information and then determining the data type is needed again.

[0043] In step S460, a compression ratio of the memory page data is read from the protocol information. The CPU 1120 reads protocol information stored in the SRAM 1160 and determines a compression ratio of the memory page data contained in the protocol information.

[0044] In step S470, it is determined whether the read compression ratio is higher than a threshold value. If the read compression ratio is not higher than the threshold value, compression of the memory page data stored in the normal data area 1250 is omitted, and the process is terminated. If the read compression ratio is higher than a threshold value, in step S480, memory page data is read from the normal data area 1250, and the read memory page data is compressed. The compressed memory page data can be used for swapping.

[0045] In an exemplary embodiment, a data type is determined according to a compression ratio of memory page data. Compressed memory page data is used for paging or deleted according to a data type.

[0046] In an exemplary embodiment, a data type is predicted from memory page data, and the predicted data type is stored as protocol information. In this case, a data type is determined by reading protocol information without compressing the memory page data. Because a data type is checked and then compression is performed, unnecessary compression (e.g., compression of memory page data that does not require compression) is prevented, and the performance of a mobile device 1000 is increased.

[0047] Fig. 9 is a flowchart illustrating a threshold control method of a CPU according to an exemplary embodiment of the inventive concept.

[0048] In step S510, a characteristic of the memory page data or a process associated with the memory page data is detected. In step S520, a threshold is determined according to the detected characteristic. For example, a threshold for determining whether memory page data is swapped out using an immediate or delayed swap operation varies according to a characteristic of the memory page data selected as the swap target or a process associated with the memory page data.

[0049] When the mobile device 100 performs various processes, a predetermined threshold is varied to balance the number of delayed paging operations and the number of immediate paging operations. For example, a process and its data for editing documents may have a high compression ratio. If the mobile device 100 performs processes and data has a high compression ratio, and a threshold is predetermined, the application processor 1100 may predominantly perform a delayed paging operation. On the other hand, a method and its data for manipulating moving images may have a low compression ratio. If the application processor 1100 performs processes and data has a low compression ratio, and a threshold is predetermined, the application processor 1100 may predominantly perform an immediate paging operation.

[0050] The threshold is varied based on a characteristic of a process and a compression ratio of data, and thus a ratio of an immediate paging operation and a delayed paging operation is controlled.

[0051] Fig. 10 is a block diagram illustrating a mobile device according to an exemplary embodiment of the inventive concept. Referring to Fig. 10, a mobile device 2000 includes an application processor 2100, a DRAM 2200, a flash memory 2300, a modem 2400, and a user interface 2500. The application processor 2100 includes a bus 2110, a CPU 2120, a DMA 2130, a compressor and decompressor block 2140, a DRAM interface 2150, an SRAM 2160, and a flash interface 2170.

[0052] The mobile device 2000 compresses memory page data and decompresses compressed memory page data using the compressor and decompressor block 2140. Compared to an application processor 1100 in Fig. 1, the application processor 2100 is configured so that compression on memory page data is performed by the compressor and decompressor block 2140 and not by the CPU 2120. In Fig. 10, compression or decompression is performed by an associated hardware of the compressor and decompressor block 2140.

[0053] Fig. 11 is a block diagram showing the architecture of data areas of a DRAM, an SRAM and a flash memory of Fig. 10. With reference to Fig. 11, a DRAM 2200 is divided into a swap victim buffer area 2230 and a normal data area 2250.

[0054] When data stored in the normal data area 2250 is swapped out to a flash memory 2300, the swap victim buffer area 2230 stores the swapped out data through a delayed swap operation. Referring to Fig. 11, the swap victim buffer area 2230 contains a plurality of entries (e.g., Entry1 through Entry16), each of which has a plurality of page entries PE1 through PEm. A page entry corresponds to a page of compressed data. For example, a page of compressed data is stored in the swap victim area 2230 as a page entry.

[0055] A memory page entry (or compressed memory page data) in each of the plurality of entries Entry1 through Entry16 together form a data set DC. For example, the memory page entries PE1 through PEm are arranged in a matrix form with a plurality of row memory page entries and a plurality of column entries. A row of memory page entries PE1 through PEm forms a memory page. A column of memory page entries stored in different memory pages PE1 through PEm forms a data set DC.

[0056] For example, the memory page entries PE1 to PEm of each of the plurality of entries Entry1 to Entry16 are managed according to a linked list. For example, first compressed memory page data is stored at an entry (e.g., Entry_K) as a first memory page entry PE1. Second compressed memory page data is stored at the entry (e.g., Entry_K) as a second memory page entry PE2. The first memory page entry PE1 is concatenated with the second memory page entry PE2. Similarly, the memory page entries PE1 to PEm are concatenated with each other.

[0057] When a page entry is removed from the concatenated page entries PE1 to PEm, a concatenation relationship between the concatenated page entries PE1 to PEm is updated. For example, when a second page entry PE2 is removed, first and third page entries PE1 and PE3 are concatenated. The page entries PE3 to PEm are updated to be managed as page entries PE2 to PEm-1. After that, newly stored compressed page data is stored at a page entry PEm. For example, the first stored page entry PE1 is located on one page of each of the plurality of entries Entry1 to Entry16. The page entries PE1 of the plurality of entries Entry1 to Entry16 form a data set DC.

[0058] The normal data area 2250 is accessed by processes (or applications) running on an application processor 2100. For example, codes of processes and data handled by the processes are stored in the normal data area 2250.

[0059] For example, data in DRAM 2200 is managed by a memory page unit. A memory page has a size defined by an operating system OS of mobile device 2000. Process codes or data are stored in DRAM 2200 by a memory page unit and read from DRAM 2200 by the memory page unit.

[0060] The flash memory 2300 serves as a memory of the mobile device 2000. The application processor 2100 stores processed data (e.g., data including process data or data processed by the process) at the DRAM 2200 and swaps out a part of the processed data to the flash memory 2300.

[0061] Fig. 12 is a flowchart illustrating a memory page data type determination method of an application processor of Fig. 10 represents.

[0062] In step S610, compression of memory page data is initiated. For example, memory page data selected as a swap destination is read from the normal data area 2250, and the read memory page data is sent to the compressor and decompressor block 2140. The compressor and decompressor block 2140 can begin compressing the input memory page data.

[0063] In step S620, it is determined whether a compression ratio of a portion of the memory page data is greater than a threshold. For example, the compressor and decompressor block 2140 compares the compression ratio and the threshold before completing compression.

[0064] If the compression ratio is higher than the threshold, the memory page data is continuously compressed. In step S640, a data type of the memory page data is determined to be a delayed type. The compressed memory page data is moved to the swap victim buffer area 2230.

[0065] If the compression ratio is less than the threshold, compression of the memory page data is stopped in step S650. In step S660, a data type of the memory page data is determined to be an immediate type.

[0066] In an exemplary embodiment, compression and decompression of memory page data are performed by the compressor and decompressor block 2140, which is separate from the CPU 2120. Thus, compression and decompression of memory page data are performed without consuming a resource of the CPU 2120, and a compression ratio is determined before the compression is completed. It is possible to avoid performing unnecessary compression by comparing the compression ratio with the threshold before the compression is completed.

[0067] In an exemplary embodiment described above, a memory page data type is determined using a compression ratio of compressed memory page data. The memory page data type determination method is not limited to this. For example, a memory page data type is predicted without compression. For example, multimedia data may have a low compression ratio, and text or code may have a high compression ratio. The application processor 2100 may determine whether the memory page data is multimedia data, text data, or code data using header information read from the memory page data. Based on the determination result, the application processor 2100 determines the multimedia data as immediate type data and determines the text or code as delayed type data.

[0068] Fig. 13 is a flowchart showing an immediate swapping procedure from Fig. 12. An immediate swap operation is performed when memory page data is determined to be immediate type data. For example, if the compression ratio of the memory page data is not higher than a threshold, the immediate swap operation is performed.

[0069] With reference to the Fig. 11 and Fig. 13, in method step S710, memory page data is read from a normal data area 2250. For example, an application processor 2100 reads memory page data selected as a swap target at an upper level (e.g., an operating system) from the normal data area 2250.

[0070] In method step S720, the read memory page data is moved to the flash memory 2300. The application processor 2100 stores the read memory page data in the flash memory 2300.

[0071] In step S730, the memory page data is deleted from the normal data area 2250. In an exemplary embodiment, the application processor 2100 overwrites the memory page data with a new process or its data.

[0072] For example, an immediate type of memory page data having a compression ratio of less than a threshold is swapped out to the flash memory 2300 without using the swap victim buffer area 2230. For example, when a swap operation is needed to perform a new process and a swap target memory page is determined to be an immediate type, the application processor 2100 swaps out the swap target memory page in the flash memory 2300.

[0073] Fig. 14 is a flowchart illustrating a delayed swapping procedure from Fig. 12. A delayed paging operation is performed when a type of memory page data is determined to be a delayed type. For example, a delayed paging operation is performed when a compression ratio of memory page data is greater than a threshold.

[0074] Referring to Fig. 11 and Fig. 14, compressed page data is stored in one of a plurality of entries of the swap victim buffer area 2230. The swap victim buffer area 2230 includes the plurality of entries Entry1 through Entry16, each of which has the plurality of page entries PE1 through PEm. A page of compressed data is moved to a selected page entry in a selected entry.

[0075] In process step 820, swap victim buffer (SVB) information is stored in the SRAM 2160. The SVB information includes information about compressed memory page data stored in the swap victim buffer area 2230. For example, the SVB information includes a process identifier, an address, and LRU ("least recently used") information associated with the page data stored in the swap victim buffer area 2230. Fig. 11. The address contains a mapping relationship between an address of the normal data area 2250 where the compressed memory page data is stored and an address of the flash memory 2300 corresponding to the memory page data selected as a swap target. The LRU information contains information about the time at which the compressed memory page data was last accessed.

[0076] In step S830, it is determined whether swapping of the swap victim buffer area 2230 is required. The application processor 2100 determines whether swapping of the swap victim buffer area 2230 is required. For example, when the application processor performs a delayed swap operation, a swap target memory page is moved to the swap victim buffer area 2230. In this case, the application processor 2100 determines whether the swap victim buffer area 2230 has some entries to accommodate the swap target memory page. The application processor 2100 determines whether swapping is required based on the determination result. Whether swapping is required is determined according to a free space size of the swap victim buffer area 2230.

[0077] If swapping of the swap victim buffer area 2230 is not required, the method is terminated. A delayed swap operation is performed without moving any of the memory page entries of the swap victim buffer area 2230 to the flash memory 2300. If swapping of the swap victim buffer area 2230 is required, the method proceeds to step S840.

[0078] In step S840, compressed memory page data stored in the swap victim buffer area 2230 is selected from the plurality of entries of the swap victim buffer area 2230. For example, the application processor 2100 selects a memory page of compressed data from each of the plurality of entries. For example, the application processor 2100 selects compressed memory page data in a unit of a data set DC that was stored first among the plurality of entries.

[0079] In an exemplary embodiment, the data unit is set such that the data transfer time of the data set through direct memory access is equal to or shorter than the data transfer time of the data set through the application processor. The data transfer time of the data set through direct memory access includes the programming time of the DMA. For example, the data unit has a size of 32 KB or more.

[0080] In process step S850, the direct memory access 2130 moves from Fig. 10 the selected compressed memory page data to the flash memory 2300. The application processor 2100 programs the direct memory access 2130 to move the selected compressed memory page data in a unit of the data set DC to the flash memory 2300.

[0081] In step S860, the selected compressed memory page data is deleted from the swap victim buffer area 2230. The application processor 2100 deletes the selected compressed memory page data from the swap victim buffer area 2230. In an exemplary embodiment, the selected compressed memory page data of the swap victim buffer area 2230 is overwritten by a swap target memory page through a delayed swap operation.

[0082] In step S870, the SVB information is updated. For example, the application processor 2100 updates the SVB information to delete information about compressed memory page data that is paged out.

[0083] For example, the application processor 2100 manages the SVB information using an SVB descriptor table 2161 of the SRAM 2160 from Fig. 11 and a protocol information.

[0084] Fig. 15 and Fig. 16 are diagrams illustrating examples of an immediate swap operation and a delayed swap operation according to an exemplary embodiment of the inventive concept. In Fig. 15 and Fig. 16 the normal data range 2250 can be Fig. 11 may be configured to store a plurality of memory page data PD. For simplicity of description, the normal data area 2250 is represented in a matrix form having a plurality of rows R1 through Ri and a plurality of columns C1 through Cj.

[0085] Referring to Fig. 15, memory page data PD' in the third row R3 and the first and second columns C1 and C2 of the normal data area 2250 is selected as an immediate swap destination. The selected memory page data PD' is moved to the flash memory 2300. Thereafter, the selected memory page data PD' is assigned to a new process of the application processor 2100.

[0086] Referring to Fig. 16, memory page data PD' in the second row R2 and in first and second columns C1 and C2 of the normal data area 2250 is selected as a delayed page target. The selected memory page data PD' is compressed, and the compressed memory page data is moved to the page victim buffer area 2230. For example, the compressed memory page data is stored at second and third entries Entry2 and Entry3 as memory page entries. In this case, the application processor 2100 can reduce the number of page operations to the flash memory 2300 and thus increase system performance.

[0087] Thereafter, if a swapping condition of the swap victim buffer area 2230 is met, the compressed page data is moved to the flash memory 2300 through a delayed swapping operation. For example, if the compressed page data constitutes a data set DC as the compressed page data first stored in the swap victim buffer area 2230, the compressed page data is swapped to the flash memory 2300 through a delayed swapping operation.

[0088] Fig. 17 is a flowchart illustrating a recovery procedure for paged memory data. Referring to Fig. 10 and Fig.17, in method step S910, it is determined whether swapped memory page data is needed. For example, if either an operating system or an application running on a mobile device 2000 accesses swapped memory page data, a swapped memory page is needed. If no swapped memory page is needed, the method ends. If a swapped memory page is needed, the method proceeds to method step S920.

[0089] In step 920, it is determined whether the paged-out memory page data is delayed-type memory page data. For example, an application processor 2100 determines whether the paged-out memory page data is delayed-type memory page data using the protocol information stored in SRAM 1160.

[0090] If the swapped-out page data is not delayed-type page data, that is, if the swapped-out page data is immediate-type page data, in step S930, requested page data is read from a flash memory 2300, and the read-out page data is stored in a normal data area 2250. At this time, the requested page data is deleted from the flash memory 2300. Immediate-type page data is page data that is immediately swapped out to the flash memory 2300. Thus, the requested page data is restored by reading the requested page data from the flash memory 2300 and storing the requested page data that was read out in the normal data area 2250.

[0091] If the swapped out page data is not delayed-type page data, it is determined in step S940 whether the requested page data is stored in a swap victim buffer area 2230. As described above, delayed-type page data is stored in the swap victim buffer area 2230 and is maintained until a swap condition of the swap victim buffer area 2230 is met. Thus, a method for restoring the requested page data varies depending on whether the requested page data is stored in the swap victim buffer area 2230.

[0092] In the event that the requested memory page data is not stored in the swap victim buffer area 2230, the requested memory page data is present in the flash memory 2300. Thus, in step S950, the requested memory page data is read from the flash memory 2300, and the read memory page data is decompressed. The decompressed memory page data is stored in the normal data area 2250. The requested memory page data (i.e., the compressed memory page data) is deleted from the flash memory 2300.

[0093] In the event that the requested memory page data is not stored in a swap victim buffer area 2230, the requested memory page data is present in the flash memory 2300 in step S960. Thus, in step S950, the requested memory page data is read from the swap victim buffer area 2230, and the read memory page data is decompressed. The decompressed memory page data is stored in the normal data area 2250. At this time, the requested memory page data (i.e., compressed memory page data) is deleted from the swap victim memory area 2230. Thereafter, in step S970, swap victim buffer information and entries of the swap victim buffer area 2230 are updated.

[0094] A swap operation may cause page jitter. Page jitter occurs when the mobile device 2000 excessively consumes a resource for swapping out paged data and restoring swapped-out paged data (ie, page management).

[0095] In an exemplary embodiment of the inventive concept, compressed memory page data is stored in the swap victim buffer area 2230 of the DRAM 2200 for a predetermined time before being swapped out to the flash memory 2300. Thus, the probability of page jitter is reduced and the performance of the mobile device is increased. Furthermore, data stored in the swap victim buffer area 2230 is swapped out by the DMA 2130. The DMA consumes less power than the application processor 2100. Thus, the power consumption of the mobile device 2100 is reduced. Furthermore, when the application processor 2100 copies data, the copied data is stored in a cache memory of the application processor 2100. When data is copied by the DMA, the copied data does not need to be stored in the cache memory of the application processor 2100.Thus, the DMA avoids data violation of the cache memory of the application processor 2100 during a swap operation, and the performance of the mobile device 2000 is increased.

Claims

[1] Mobile device with: a memory (1300; 2300) having a non-volatile memory (1300; 2300) configured to store data; a buffer memory (1200; 2200) configured to include a swap victim buffer area (1230; 2230) and a normal data area (1250; 2250); and an application processor (1100; 2100) configured to select memory page data to be swapped out from the normal data area (1250; 2250) and to perform a swap operation on the selected memory page data, wherein, depending on the data type of the selected memory page data, the paging operation performs an immediate paging operation in which the memory page data is moved from the normal data area (1250; 2250) to the memory (1300; 2300), or a delayed paging operation in which the memory page data is moved from the normal area (1250; 2250) via the paging victim buffer area (1230; 2230) to the memory (1300; 2300). [2] The mobile device of claim 1, wherein the application processor (1100; 2100) for the delayed paging operation is configured to compress the memory page data, store the compressed memory page data in the paging victim buffer area (1230; 2230), and move the compressed memory page data into the memory (1300; 2300). [3] The mobile device according to claim 2, wherein the memory (1300; 2300) is a flash memory and the buffer memory (1200; 2200) is a DRAM. [4] The mobile device of claim 2, wherein when the compressed memory page data stored in the swap victim buffer area (1230; 2230) is requested, the application processor (1100; 2100) is configured to read the compressed memory page data stored in the swap victim buffer area (1230; 2230), decompress the compressed memory page data, and store the decompressed data in the normal data area (1250; 2250). [5] The mobile device of claim 1, wherein the application processor (1100; 2100) is configured for the immediate swap operation to move the memory page data from the normal data area (1250; 2250) to the memory (1300; 2300) without using the swap victim buffer area (1230; 2230). [6] The mobile device of claim 5, wherein when a compression ratio of the selected memory page data is less than a threshold, the application processor (1100; 2100) is configured to perform the immediate swap operation. [7] Mobile device with: a non-volatile memory (1300; 2300); a DRAM (1200; 2200) configured to include a swap victim buffer area (1230; 2230) and a normal data area (1250; 2250); and an application processor (1100; 2100) coupled to the non-volatile memory (1300; 2300) and the DRAM (1200; 2200), wherein, when a swap of memory page data stored in the normal data area (1250; 2250) is requested, the application processor (1100; 2100) is configured to perform an immediate swap operation or a delayed swap operation depending on the type of memory page data, wherein the immediate swap operation moves the memory page data to the non-volatile memory (1300; 2300) without using the swap victim buffer (1230; 2230), and wherein the delayed swap operation compresses the memory page data and moves the compressed data into the non-volatile memory (1300; 2300) via the swap victim buffer area (1230; 2230). [8] The mobile device according to claim 7, wherein the application processor (1100; 2100) determines a type of the memory page data depending on a compression ratio of the memory page data. [9] The mobile device of claim 7, wherein the application processor (1100; 2100) comprises a direct memory access unit (1130; 2130) configured to move the compressed memory page data stored in the swap victim buffer (1230; 2230) to the non-volatile memory (1300; 2300). [10] The mobile device of claim 7, wherein the compressed memory page data is shifted in a unit of a record from the swap victim buffer (1230; 2230) to the non-volatile memory (1300; 2300). [11] The mobile device according to claim 10, wherein the unit of the data set is set such that a data transfer time of the data set by the direct memory access unit (1130; 2130) is equal to or shorter than a data transfer time of the data set by the application processor (1100; 2100), wherein the data transfer time of the data set by the direct memory access unit (1130; 2130) includes a programming time of the DMA (1130; 2130). [12] The mobile device according to claim 10, wherein the unit of data set has a size of 32kB or more. [13] A data management method of an application processor (1100; 2100), comprising: Determining a data type of memory page data stored in a normal data area (1150; 2150) of a DRAM (1200; 2200) and Performing a delayed swap operation on the memory page data from a normal data area (1250; 2250) of a buffer memory (1200; 2200) via a swap victim buffer area (1230; 2230) of the buffer memory (1200; 2200) to a non-volatile memory (1300; 2300) if the determined data type is a delayed type and an immediate swap operation on the memory page data to the non-volatile memory (1300; 2300) if the determined data type is an immediate type. [14] The data management method of claim 13, wherein determining a data type of memory page data stored in a DRAM (1200; 2200) comprises: Compressing the memory page data; Determining a compression ratio of the memory page data; and Deciding a data type of the memory page data as the delayed type when the compression ratio of the memory page data is higher than a threshold, and as the immediate type when the compression ratio of the memory page data is not higher than the threshold. [15] The data management method according to claim 14, further comprising: Store the data type of the memory page data. [16] The data management method according to claim 13, further comprising: Predicting the data type of the memory page data using header information of the memory page data; and if the data type is a delayed type, performing a compression operation on the memory page data; and If the data type is not a delayed type, skip the compression operation on the memory page data. [17] The data management method according to claim 14, further comprising: Store the compression rate of the memory page data. [18] The data management method according to claim 17, further comprising: Reading the stored compression ratio; and if the read compression ratio is greater than the threshold value, reading the memory page data from the DRAM (1200; 2200) to compress the read memory page data, and wherein the compression of the memory page data is skipped if the read compression ratio is not higher than the threshold value. [19] A data management method according to claim 13, further comprising: Detecting a characteristic of the memory page data or a process associated with the memory page data; and Changing the threshold according to the detection result. [20] The data management method of claim 13, wherein determining the data type of memory page data stored in the DRAM (1200; 2200) comprises: Compressing a portion of the memory page data; Determining whether a compression ratio of the portion of the memory page data is higher than a threshold; and if the compression ratio is not higher than the threshold, compress the remaining memory page data and decide that the data type is a delayed type; and If the compression ratio of the memory page data is not higher than the threshold, decide the data type as the immediate type without compressing the remaining memory page data. [21] The data management method according to claim 13, wherein the immediate swapping operation further comprises: Moving the memory page data from the DRAM (1200; 2200) to a memory (1300; 2300). [22] The data management method according to claim 13, wherein the delayed swap operation comprises: Moving the memory page data in the swap victim buffer area (1230; 2230) of the DRAM (1200; 2200) in a compressed data format. [23] The data management method of claim 22, wherein the swap victim buffer area (1230; 2230) is configured to include a plurality of entries, each of which is configured to have a plurality of memory page entries (PE1-PEm), the memory page data being stored in one memory page entry of the plurality of entries, the memory page data being stored in the compressed data format. [24] A data management method according to claim 23, wherein the plurality of memory page entries (PE1-PEm) of each of the plurality of entries are managed using a linked list. [25] The data management method according to claim 23, wherein the delayed swap operation further comprises: Moving the compressed memory page data from the swap victim buffer area (1230; 2230) into a memory (1300; 2300). [26] The data management method according to claim 25, wherein the compressed memory page data is selected when the compressed memory page data is first stored in the swap victim buffer area (1230; 2230). [27] The data management method according to claim 26, further comprising: Reading compressed memory page data from the plurality of entries when the compressed memory page data stored in the swap victim buffer area (1230; 2230) is requested; Decompressing the compressed memory page data; and Store the decompressed memory page data in the normal data area (1250; 2250). [28] The data management method according to claim 13, wherein the delayed paging operation performed using direct memory access and the immediate paging operation are performed by one processor. [29] Application processor with: a DRAM interface (1150; 2150); a flash memory interface (1170;2170); a direct memory access unit (1130; 2130); and a processor (1120; 2120) configured to determine whether the swap operation is requested, configured to receive memory page data to be swapped through the DRAM interface (1150; 2150), and configured to perform the swap operation on the memory page data in an immediate swap operation or in a delayed swap operation depending on the data type of the memory page data, wherein the processor (1120; 2120) is configured, in the delayed swap operation, to compress the memory page data and output the compressed memory page data through the DRAM interface (1150; 2150), and the direct memory access unit (1130; 2130) is configured to control a data path between the DRAM interface (1150; 2150) and the flash memory interface (1170; 2170) to move the output controlled memory page data from the DRAM interface (1150; 2150) to the flash memory interface (1170; 2170). [30] The application processor of claim 29, wherein the data type of the memory page data is determined by a compression ratio of the memory page data. [31] The application processor of claim 29, wherein the data type of the memory page data is determined by header information of the memory page data without compressing the memory page data. [32] The application processor of claim 29, wherein the immediate swap operation is performed without compressing the memory page data.

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