Semiconductor assembly with temperature-compensated breakdown voltage

Abstract

Semiconductor arrangement which - a first metal layer (8) serving as a cathode (K), - a highly n-doped silicon layer (1) contacted with the first metal layer (8), - a further n-doped silicon layer (2) contacted with the highly n-doped silicon layer (1) and - has a further metal layer (7) connected to the further n-doped silicon layer (2) and serving as an anode (A), wherein - into the further n-doped silicon layer (2) grooves (3) are introduced, the edge regions (4) of which are filled with a p-doped silicon layer and which in their inner region (5) are filled with highly n-doped silicon, - the edge regions (4) of the trenches (3) are contacted via a highly p-doped layer (6) with the further metal layer (7) and the highly p-doped layer (6) forms an ohmic contact with the further metal layer (7), - the further metal layer (7) with the further n-doped layer (2) forms Schottky diodes, and - the highly n-doped inner regions (5) of the trenches (3) together with the edge regions (4) of the trenches and the further n-doped layer (2) form npn transistors, wherein the further n-doped layer (2) serves as the collector region, the highly n-doped inner regions (5) of the trenches as the emitter regions and the edge regions (4) of the trenches as the base regions and wherein a limitation of the reverse voltages for the collector-base junctions (2 - 4) forming the diodes is determined by a punch-through effect.

Description

State of the art

[0001] AC bridges (rectifiers) are used for rectification in automotive three-phase or alternating current generators (alternators). Semiconductor diodes with a silicon pn junction are typically used as rectifying elements. For example, in a three-phase generator, six semiconductor diodes are connected together to form a B6 bridge. Occasionally, diodes are connected in parallel, for example, using twelve diodes instead of six. For AC generators with a different number of phases, appropriately adapted diode bridges are used.

[0002] The diodes are designed for operation at high currents or current densities of up to 500 A / cm 2and high temperatures or a maximum junction temperature Tj of around 225°C. Typically, the voltage drop in the forward direction, i.e. the forward voltage UF, is around 1 volt at the high currents used. When operated in the reverse direction below the breakdown voltage UZ, only a very small reverse current IR flows. From the breakdown voltage UZ onwards, the reverse current increases sharply. A further voltage increase is therefore prevented. Zener diodes with reverse voltages - depending on the on-board voltage of the respective vehicle - of around 20 - 50 volts are usually used in this context. Zener diodes can be loaded with high currents for a short time during breakdown. They are therefore used to limit the excessive generator voltage during load changes (load dump). Such diodes are usually packaged in robust press-fit diode housings, as described, for example, in DE 195 49 202 B4.

[0003] The forward voltage of pn diodes leads to conduction losses and thus to a reduction in the generator's efficiency. Since, on average, two diodes are always connected in series to deliver current, the average conduction losses for a 100 A generator are approximately 200 W. These losses cause the diodes to heat up. The resulting heat must be dissipated to the ambient air or cooling air by complex cooling measures at the rectifier, for example, using heat sinks and / or a fan.

[0004] To reduce forward losses, DE 10 2004 056 663 A1 proposes using so-called high-efficiency Schottky diodes (HEDs) instead of pn diodes. High-efficiency Schottky diodes are diodes that have a low forward voltage and whose reverse current is virtually independent of the reverse voltage.

[0005] DE 10 2004 053 760 A1 describes a trench MOS barrier Schottky diode with an integrated PN diode as a possible embodiment of a HED Schottky diode. Such a diode is also referred to as a TJBS-PN. In addition to the low forward voltage in the conducting state, this also limits the excessive generator voltage, which can occur during sudden load changes, to non-critical values, typically below 30 V in 14 V systems.

[0006] High-efficiency Schottky diodes allow for significantly lower forward voltages (UF) in the range of 0.5 V to 0.7 V. The low forward losses of the diodes increase the efficiency and power output of the generator. Furthermore, the lower power losses significantly reduce the cooling requirements compared to the use of pn diodes.

[0007] The breakdown voltage of a HED limits the rising generator voltage that occurs when a load dump occurs. For a short period of time, typically less than a few hundred milliseconds, high electrical power is converted into heat at the diode. In a TJBS-PN, the integrated pn structures act as voltage-limiting Zener diodes. The pn structures are operated in avalanche breakdown mode. The power dropped across the diode corresponds to the product of the diode's reverse voltage and the generator current. Due to the high power dissipation, the diode heats up to very high temperatures during this process. Junction temperatures Tj of over 225°C can occur.Since the avalanche breakdown voltage (VZ) increases with temperature, the actual voltage during the load dump is several volts higher than the blocking voltages (VZ) measured at low current densities and at room temperature. This means that in a 14V electrical system, voltages of up to 30 volts can briefly occur in the event of a fault. Simply lowering the breakdown voltage (VZ) is limited by the voltage ripple of the generators. In modern electrical system architectures, increasing efforts are being made to limit the maximum electrical system voltage occurring in the event of a fault to low values, e.g., 27 V. Furthermore, a superjunction Schottky diode and its manufacture are known from US 2005 / 0 242 411 A1. Disclosure of the invention

[0008] A semiconductor device having the features specified in claim 1, which is also referred to below as TJBS-PT, corresponds to a high-efficiency Schottky diode whose breakdown voltage has no or only a very small temperature coefficient and in which the temperature-induced voltage increase therefore does not occur or occurs only slightly.

[0009] This TJBS-PT is a high-efficiency diode with low forward voltage and low reverse currents based on a trench junction barrier Schottky diode. Voltage limitation is achieved through a punch-through effect rather than the temperature-dependent avalanche effect. This makes the breakdown voltage virtually temperature-independent. The semiconductor device according to the invention is preferably packaged in a press-fit diode housing and used for efficient rectification in automotive AC generators. This allows the maximum on-board system voltage occurring in the event of a fault to be reduced.

[0010] Further advantageous features of the invention will become apparent from the following exemplary explanation based on the drawing. Fig. 1 is a cross-sectional view illustrating a cell of a TJBS-PT according to a first embodiment of the invention, Fig. 2 a simple equivalent circuit diagram of a TJBS-PT, Fig. 3 is a cross-sectional view illustrating a cell of a TJBS-PT according to a second embodiment of the invention and Fig. 4 is a cross-sectional view illustrating a cell of a TJBS-PT according to a third embodiment of the invention.

[0011] The Fig. Figure 1 shows a cross-sectional view illustrating a cell of a TJBS-PT according to a first embodiment of the invention. The TJBS-PT shown has a highly n+ doped silicon substrate 1, the doping of which is preferably greater than 5 × 10 19 cm -3On this silicon substrate 1 there is an n-doped silicon layer 2 (epi layer) with a doping concentration Nepi and a thickness Depi, into which a plurality of trenches 3 with a depth Dt and a width Wt are introduced. The trench bottoms are preferably rounded. A rounding radius R can be set approximately. The trench depth Dt is then defined as the distance between the silicon surface and the deepest point of the trenches. The distance between adjacent trenches is Wm. The trenches can be island-shaped, strip-shaped, or have some other shape. The side walls of the trenches 3 etched into the silicon are covered with a thin p-doped silicon layer 4 having a doping concentration NA and a thickness Wp. The interior of the trenches 3 is filled with highly n-doped silicon 5 with a doping concentration ND.In addition, a highly p-doped layer 6 is introduced into the upper part of the p-layers 4, the doping concentration NAA of which is higher than the doping concentration NA of layer 4. In particular, the surface concentration of layer 6 is chosen to be high enough that it forms an ohmic contact with a metal layer 7 lying above it. The p- or n-doped regions 4 and 5 or 6 can consist either of epitaxially grown silicon, polysilicon or a combination thereof. The metal layer 7, which covers the surface of the arrangement, forms a Schottky contact with the surface of the epi layer 2 and an ohmic contact with the n- or p-doped layers 5 and 6, respectively. For example, the metal layer 7 can consist of nickel or a nickel silicide. Other metals or silicides are also possible, depending on the desired barrier height. Further metals or silicides can be located above the metal layer 7. Fig. 1. These metal layers form the anode A of the diode. The substrate layer 1 is provided on the back with an ohmic metal layer 8 serving as the cathode K. Again, further metal layers can be located below the layer 8, Fig. 1 metal layers not shown. In addition, for packaging in press-fit diode packages, the front and back are each provided with a solderable layer system. For example, a conventional solderable metal system (also not shown), consisting of, for example, a layer sequence of Cr, NiV, and Ag, is applied over metal layers 7 and 8 on the front and back, respectively. Particularly on the front, additional metal layers may be located between layer 7 and the solderable NiV layer, for example an aluminum alloy with copper and silicon components (AlSiCu), which is common in silicon technology, or another metal system, for example AlCu over a thin barrier layer of TaN.

[0012] In simplified terms, the arrangement according to the invention can be understood as a parallel circuit of Schottky diodes and npn transistor structures, as described in the Fig. 2. The Schottky diodes are formed by the barrier metal 7 and the n-doped epilayer 2. Layers 5, 4, and 2 form the emitter, base, and collector of the npn transistor structures. The base is electrically connected to the anode and emitter metallization 7 via the resistance R of the p-doped layer 4 and the highly p-doped layer 6, respectively. The transistor region at the bottom of the trench is provided with the largest base resistance R. In the upper part, however, near the metallization 7, the base is effectively short-circuited to the emitter.

[0013] In forward polarity, current flows through the Schottky barrier in the epilayer 2 between the trench regions 3 via the substrate 1 to the cathode. By selecting a suitable barrier, the forward voltage is lower than that of a pn diode. No significant current flows through the transistor structures in the trenches.

[0014] When a reverse voltage VKA is applied, space-charge zones form in both the Schottky diode and the NPN transistor. Because the space-charge zones spread from the opposing trench walls and eventually touch each other, the electric field at the metal-semiconductor contact 7-2 is shielded. The electric field strength at the Schottky contact is therefore lower. Thus, the Schottky diodes exhibit little or no barrier-lowering behavior. The Schottky diode thus acts like a TMBS or TJBS diode, in which the reverse current increases only slightly with increasing reverse voltage. In the NPN transistor substructures, the base-collector junction is reverse-biased when VKA is applied.

[0015] In npn transistors, the space charge zone expands primarily in the less heavily n-doped region 2, but also extends into the more heavily p-doped base region 4. The electric fields and expansions of the space charge zones on npn transistors are maximum at the trench bottom, especially in the curved region.

[0016] The breakdown voltage BVCER between collector and emitter with a resistor R between base and emitter of a bipolar transistor is lower than the avalanche breakdown voltage BVCBO of the collector-base diode due to its current gain. If the breakdown voltage of the collector-base diode is determined by the avalanche effect, the breakdown voltage usually has a positive temperature coefficient. A slightly negative to neutral temperature coefficient of the BVCER voltage can be achieved if the diffusion profile of the transistors is designed in such a way that the space charge region extends through the base region 4 and abuts the emitter region 5 (punch-through) even before the avalanche breakdown voltage is reached, thereby limiting the voltage.

[0017] The doping and dimensions of the semiconductor layers are designed such that the breakdown voltage of the collector-base junction of the NPN transistor formed by layers 2 and 4 is limited by the punch-through effect. Punch-through is the state in which the space charge zone of the reverse-biased collector-base junction extends completely through base layer 4 and abuts emitter layer 5. Once the space charge zone has reached the emitter layer, current flows after overcoming another small voltage, which roughly corresponds to the forward or diffusion voltage of a diode. A further voltage increase is then no longer possible. Since the voltage limitation, in contrast to the equilibrium breakdown, is practically independent of temperature, the breakdown voltage of an arrangement according to the invention does not increase with increasing self-heating.

[0018] Since the emitter-base diode is essentially forward-biased, punch-through breakdowns even exhibit a slightly negative temperature coefficient of the breakdown voltage at low currents. At high current densities and temperatures, the electron mobility, or the saturation rate for charge carriers in the space charge region, decreases slightly, allowing for near-temperature compensation of the reverse voltage.

[0019] The transition between avalanche and punch-through operation can be influenced by selecting the base doping NA and the thickness Wp of the p-doped silicon layer 4. For a fixed thickness Wp, the avalanche effect increases with increasing base doping NA, resulting in an increasingly positive temperature coefficient. By appropriately selecting the parameters, these effects can be combined in such a way that the breakdown voltage becomes completely independent of temperature.

[0020] The following is an example of an arrangement according to Fig. 1, which at high current densities of about 400 A / cm 2 has a blocking voltage of approximately 24.5 V. The temperature coefficient is almost zero between 25°C and 200°C. According to this design example, the parameters are selected as follows. Chip thickness: Cd = 200 µm Substrate doping: Nsub ≥ 1·10 19 cm -3 ; Doping concentration of the epi layer 2: Nepi = 2.86·10 16 cm -3 ; Thickness of the epi layer: Depi = 2 µm; Depth of trenches 3: Dt = 1 µm. Dt includes a rounding radius at the trench bottom of R = 0.4 µm; Width of the trenches: Wt = 1 µm; Rounding radius at the trench bottom: R = 0.4 µm; Doping of the n-well filling: ND = 5·10 19 cm -3 ; Doping of the p-layer at the trench edge: NA = 2.7 10 17 cm -3 ; Width of the p-layer at the trench edge: Wp = 0.2 µm; Doping of the p-layer: NAA > 5·10 18 cm -3 , for example 5·10 19 cm -3 .

[0021] Of course, designs for other blocking voltages are also possible. For this purpose, doping and geometric dimensions can be varied widely. Furthermore, doping profiles can be selected that do not exhibit a constant doping level, but rather exhibit a certain doping gradient. Furthermore, arrangements in which n- and p-doped regions are interchanged can also be used.

[0022] In the Fig. 3 shows a second embodiment with particularly low reverse currents. In contrast to Fig. 1, the n-doped layer 2 consists of two different layers 2a and 2b with different thicknesses and different doping levels. The doping concentration Nepi2a of the upper layer 2a is chosen to be lower than the doping concentration Nepi2b of the lower layer 2b. The lower doping concentration Nepi2b can, for example, be approximately as high as the doping concentration Nepi from the first embodiment. Layer 2b can be created by ion implantation of donors into an epi layer with the doping concentration Nepi2a, followed by diffusion. This allows the doping concentration and thus the desired blocking voltage to be adjusted very precisely.

[0023] In the Fig. 4 shows a further embodiment with low reverse currents. The trenches 3 extend into the highly doped substrate 1. The operation of the arrangement shown is analogous to the arrangement according to Fig. 2.

[0024] The n- and p-doped layers 5 and 4, respectively, can consist of doped polysilicon or epitaxially grown layers. It is also possible to create the p-doped layers 4 by diffusing acceptors from the trench surface into the n-doped epiregion 2 and to generate the n-doped layer again by polysilicon deposition or epitaxial growth.

Claims

[1] Semiconductor device which - a first metal layer (8) serving as cathode (K), - a highly n-doped silicon layer (1) contacted with the first metal layer (8), - a further n-doped silicon layer (2) contacted with the highly n-doped silicon layer (1) and - a further metal layer (7) connected to the further n-doped silicon layer (2) and serving as an anode (A), wherein - trenches (3) are introduced into the further n-doped silicon layer (2), the edge regions (4) of which are filled with a p-doped silicon layer and which are filled in their inner region (5) with highly n-doped silicon, - the edge regions (4) of the trenches (3) are contacted with the further metal layer (7) via a highly p-doped layer (6) and the highly p-doped layer (6) forms an ohmic contact with the further metal layer (7), - the further metal layer (7) forms Schottky diodes with the further n-doped layer (2), and - the highly n-doped inner regions (5) of the trenches (3) together with the edge regions (4) of the trenches and the further n-doped layer (2) form npn transistors, wherein the further n-doped layer (2) serves as a collector region, the highly n-doped inner regions (5) of the trenches as emitter regions and the edge regions (4) of the trenches as base regions and wherein a limitation of the blocking voltages for the collector-base junctions (2 - 4) forming diodes is determined by a punch-through effect. [2] Semiconductor device according to claim 1, characterized by that the further n-doped silicon layer is divided into two differently doped regions (2a, 2b), of which one region (2a) is in contact with the further metal layer (7) and the other region (2b) is in contact with the highly n-doped silicon layer (1). [3] Semiconductor device according to claim 2, characterized by that the doping concentration of the region (2a) contacted with the further metal layer (7) is lower than the doping concentration of the region (2b) contacted with the highly n-doped silicon layer (1). [4] Semiconductor device according to claim 2 or 3, characterized by that the trenches (3) end in the region (2b) contacted with the highly n-doped silicon layer (1). [5] Semiconductor device according to claim 1, characterized by that the trenches (3) end in the highly n-doped silicon layer (1).

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