COMMUNICATION DEVICE FOR SENDING A BINARY CODED SIGNAL

Abstract

Communication device with: - a detection device (61) for detecting a boundary pattern that occurs periodically between codes in a binary coded signal transmitted over a transmission line (6), wherein the boundary pattern is information indicating a boundary occurring between codes; - a process execution device (63-66) for executing a process synchronously at the time of occurrence of the boundary pattern detected by the detection device (61); and - an area determination device (62) for determining an area of ​​authorization which is determined in such a way that it has a point in time at which the next boundary pattern is expected to occur, the point in time being counted from the point in time currently being recorded by the detection device (61), wherein - the detection device (61) is able to detect the time of occurrence of the boundary pattern during the permit area determined by the area determination device (62), and - the area determination device (62) has: - a time-counting device (71) for counting the duration between the times recorded by the recording device (61), and - a variable determination device (79, S150-S190) for a variable determination of a duration of the permit area in accordance with the duration of the boundary pattern recorded by the time-counting device (71).

Description

BACKGROUND OF THE INVENTION[Field of the Invention]

[0001] The present invention relates to a communication device, and more particularly to a communication device that executes various processes synchronously with the timing of detection of a boundary pattern that periodically appears in a binary-coded signal sent over a transmission line. [State of the art]

[0002] It is known that some communication systems installed in vehicles are designed to use PWM (pulse width modulation) codes as transmission line codes (see, for example, non-patent document SAE-J1850).

[0003] Usually, when PWM codes describing two logical values ​​are decoded, the logical values ​​are determined based on the signal level sampled after a predetermined period of time (i.e., the time at which one signal level differs from another between the codes corresponding to the respective logical values) has elapsed since a falling edge (periodically occurring boundary pattern) describing a boundary between bits, or based on the results of measuring the length of a period of time from the bit boundary to a rising edge (low-level period).

[0004] However, these decoding methods have a problem in that if an instantaneous change in a signal level due to noise or the like is mistakenly detected as a bit boundary, the decoding will be erroneous and the communication quality will be deteriorated.

[0005] DE 198 49 408 A1 discloses a method and a device for processing a received signal that transmits coded data, wherein the coding of the individual data is carried out with a specific coding clock and the signal has edges generated in accordance with the coding clock. In the method, a time constant set in accordance with the coding clock is determined from the received signal, a first signal part that has a first edge is processed at a first time set in accordance with the time constant or in a first time window set in accordance with the time constant, and a second signal part that has a second edge is processed at a second time set in accordance with the time constant and depending on the time of the first edge or in a second time window set in accordance with the time constant and depending on the time of the first edge. SUMMARY OF THE INVENTION

[0006] It is an object of the present invention to provide a communication device capable of minimizing the influence of noise in order to accurately execute processes synchronously with the timing of detection of a boundary pattern.

[0007] The problem is solved by the subject matter of the main claim. Advantageous further developments are specified in the subclaims.

[0008] The communication device according to the present invention does not erroneously detect a pattern similar to the boundary pattern that inadvertently occurred outside the permission range due to noise or the like. Consequently, the communication device of the present invention is capable of accurately executing processing synchronously with the timing of boundary pattern detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The attached drawings show: Fig. 1 is a schematic block diagram illustrating a configuration of an in-vehicle communication system according to an embodiment of the present invention; Fig. 2A is an exemplary diagram illustrating transmission codes used in communication via a transmission line according to the embodiment; Fig. 2B is an explanatory diagram illustrating a configuration of a frame transmitted / received via a transmission line according to the embodiment; Fig. 2C is an explanatory diagram illustrating a configuration of a frame transmitted / received between a UART and a transceiver according to the embodiment; Fig. 3 is a block diagram illustrating configurations of nodes according to the embodiment; Fig. 4 is a timing chart illustrating an operation of an encoding circuit according to the embodiment; Fig. 5 is a block diagram illustrating a configuration of a decoding circuit according to the embodiment; Fig. 6 is a block diagram showing a specific configuration of a permission range determining section according to the embodiment; Fig. 7 is a flowchart illustrating a process executed by a processing unit according to the embodiment; and Fig. 8 is a timing chart illustrating an operation of the permission area determining section according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] An embodiment of the present invention is described below with reference to the accompanying drawings in the Fig. 1 to 8 described. (General Configuration)

[0011] Fig. Fig. 1 is a schematic block diagram illustrating a configuration of an in-vehicle communication system (ie, a communication device) 1 to which the present invention is applied according to the embodiment. The in-vehicle communication system 1 has, as shown in Fig. 1, nodes 3 are interconnected via a bus-like transmission line 5. The nodes 3 include electronic control units (body system ECUs) that implement vehicle body system applications, and peripheral devices (lights, sensors, and the like) that detect or control vehicle states.

[0012] Of the nodes 3, the body system ECUs include a wiper ECU, a seat ECU, a sliding door ECU, a mirror ECU, a tailgate ECU, a light ECU, and a tilt-and-telescoping (electric steering position adjustment device) ECU. The peripheral devices include a light switch (SW), a wiper switch (SW), a light sensor, and a rain sensor. (Bus communication line)

[0013] The transmission line 5 is configured such that when a high-level signal (first level) and a low-level signal (second level) are simultaneously output from different nodes 3, the signal level on the transmission line 5 becomes a low level. Using this function, bus arbitration is realized on the transmission line 5.

[0014] Fig. 2A shows an exemplary diagram illustrating transmission codes used in communication via the transmission line 5. The transmission line 5 uses, as shown in Fig. 2A shows PWM (pulse width modulation) codes as transmission codes. In PWM codes, the signal level changes from high to low at a boundary between bits (bit boundary) and from low to high at any point within a bit. In PWM codes, a binary (logical 1 / logical 0) signal is described by two codes with different duty cycles.

[0015] In the following description, the code with a smaller (shorter) ratio (duration) at a low level is referred to as a recessive code (first code), and the code with a larger (longer) ratio (duration) at a low level is referred to as a dominant code (second code). In the present embodiment, the recessive code corresponds to a logical 1, and the dominant code corresponds to a logical 0. In the transmission codes, the boundary at which the signal level changes from high to low is also called a boundary edge (i.e., a boundary pattern or boundary information), and the edge at which the signal level changes from low to high is also called an intermediate edge.

[0016] In the embodiment, the term "boundary edge" describes a falling edge that represents a boundary that occurs periodically between codes, while the term "between" describes a rising edge that occurs in every code. Furthermore, the term "boundary pattern" describes the occurrence of a falling edge between codes.

[0017] Specifically, in the recessive code, 1 / 3 of the period of a bit is set to a low level and 2 / 3 of it to a high level. In the dominant code, 2 / 3 of the period of a bit is set to a low level and 1 / 3 of it to a high level. If the recessive code collides with the dominant code on transmission line 5, the dominant code is guaranteed to win the arbitration.

[0018] When the recessive code persists on the transmission line 5 for a period of time corresponding to allowable bits (11 bits in the present embodiment) or longer, the period is referred to as one IFS (frame interval). The state in which the IFS is detected is referred to as an idle state. In the in-vehicle communication system 1, the nodes 3 are controlled so that they can transmit when the transmission line 5 is in the idle state. Furthermore, the in-vehicle communication system 1 employs CSMA / CA (Carrier Sense Multiple Access with Collision Avoidance) access control. Under CSMA / CA-based access control, after starting a transmission, the node 3 that lost the arbitration immediately stops transmitting, and only the node 3 that won the arbitration continues transmitting.

[0019] Fig. Fig. 2B is an exemplary diagram illustrating a configuration of a frame transmitted / received via the transmission line 5. The frame used for communication between the nodes 3 has, as shown in Fig. 2B, a header for specifying data that may be sent and a variable-length response part for sending the data specified by the header.

[0020] The header contains an identifier (ID) of the data that may be sent. The header is determined according to the value of the ID to survive bus arbitration. In contrast, the response part, unlike the aforementioned data, contains at least size information indicating the size of the data (response part) and a CRC (Cyclic Redundancy Check) code for checking for the presence / absence of errors. (Node)

[0021] The nodes 3 include a node that supplies clocks to other nodes via the transmission line 5 (herein, the wiper ECU), and nodes that perform communication synchronized with the clocks supplied via the transmission line 5. Hereinafter, the former is also referred to as a clock master 3a, and the latter is also referred to as a normal node 3b. Although partially different from each other, the clock master 3a has substantially the same configuration as each normal node 3b. Therefore, the following description is directed to the same configuration, and the differences in the configuration are supplementarily described where necessary.

[0022] Fig. Figure 3 shows a block diagram illustrating the configurations of nodes 3. Each node 3 has, as shown in Fig. 3, a signal processor 10 and a transceiver 20. The signal processor 10 performs various processes associated with its own node 3 based on information or the like acquired through communication with other nodes 3 via the transmission line 5. The transceiver 20 receives transmission data TXD in NRZ (Non-Return-to-Zero) codes from the signal processor 10, encodes the transmission data TXD into transmission data TX in PWM codes, and outputs the encoded transmission data TX to the transmission line 5. The transceiver 20 acquires reception data RX in PWM codes via the transmission line 5, decodes the reception data RX into reception data RXD in NRZ codes, and outputs the decoded reception data RXD to the signal processor 10. (signal processor)

[0023] The signal processor 10 is essentially constructed of a microcomputer of known design, comprising a CPU, a ROM, a RAM, and an I / O port. The signal processor 10 further comprises a UART (Universal Asynchronous Receiver Transmitter) 11, which implements start-stop synchronization for (asynchronous) serial communication, and an oscillator circuit 12, which generates operating clock pulses for operating the signal processor 10.

[0024] Fig. Figure 2C shows an exemplary diagram illustrating a configuration of a frame transmitted / received between the UART 11 and the transceiver 20. The UART 11 performs transmission / reception based on a ten-bit data block as a unit. The ten-bit data block is, as shown in Fig. 2C, it is composed of a start bit (low level) indicating the start of the data, a stop bit (high level) indicating the end of the data, and eight data bits arranged between the start bit and the stop bit. The eight data bits, which form a main part of the data block, are arranged such that an LSB (Least Significant Bit) is arranged at the beginning and an MSB (Most Significant Bit) is arranged at the end.

[0025] The header of the frame mentioned above (see Fig. 2B), is composed of a single data block in which, with the exception of the start bit and the stop bit, seven of the eight data bits are used as the ID, and the remaining one bit is used as the parity bit. The response part of the frame is composed of one or more data blocks, with the size information specified in the first data block.

[0026] In the clock master 3a, in particular, the oscillator circuit 12 is designed to generate internal clocks CK in addition to the operating clocks described above. The internal clocks CK are set to have the same communication speed (such as 20 kbps) as the UART 11 and are supplied to the transceiver 20. (Transceiver)

[0027] The transceiver has, as shown in Fig. 3, a digital processor 30, an analog processor 40, and a timing generator 50. The digital processor 30 includes an encoding circuit 31 that encodes the transmitted data TXD, a decoding circuit 32 that decodes the received data RX, and an arbitration circuit 33 that detects a collision between data on a bit basis. The analog processor 40 includes a transmit buffer 41 that outputs the transmitted data TX encoded in the digital processor 30 to the transmission line 5, and a receive buffer 42 that detects data from the transmission line 5. The timing generator 50 generates various timing signals required for the operation of the digital processor 30. (Time generator)

[0028] Timing generator 50 comprises a simplified oscillation circuit, constructed, for example, from a ring oscillator. The ring oscillator is formed by connecting multiple inverters in a ring. Timing generator 50 frequency-divides a counting clock generated by the oscillation circuit to generate various timing signals synchronized with a reference clock (the internal clock CK in clock master 3a, supplied from signal processor 10, or the received data RX in each of the normal nodes 3b, acquired from transmission line 5 via receive buffer 42). (Digital Processor)

[0029] In the digital processor 30, the coding circuit 31 in the clock master 3a operates differently than in each of the normal nodes 3b.

[0030] In the coding circuit 31 of the clock master 3a, the transmit data TXD (NRZ code) supplied from the signal processor 10 and having a "logical 1" is encoded into a recessive code, and the transmit data TXD having a "logical 0" is encoded into a dominant code. The thus encoded signals are supplied to the transmit buffer 41 as the transmit data TX.

[0031] The coding circuit 31 of the clock master 3a is configured such that the input will have a "logical 1" when no transmit data TX is supplied from the signal processor 10. Specifically, when the signal processor 10 is not transmitting, the coding circuit 31 of the clock master 3a ensures that it continues to output the recessive codes as clocks to supply the other nodes.

[0032] Fig. Fig. 4 shows a timing chart illustrating the operation of the coding circuit 31 of the normal node 3b. In the coding circuit 31 of each normal node 3b, as shown in Fig. As shown in Fig. 4, when the transmission data TXD supplied from the signal processor 10 has a "logical 1", a signal having the first level over the entire period of one bit is input to the transmission buffer 41 as the coded transmission data TX. Further, when the transmission data TXD has a "logical 0", a signal that assumes the second level when the rising edge of the reception data RX is detected and assumes the first level when (at the time point at which) the duration of the low level in the dominant code has elapsed is input to the transmission buffer 41 as the coded transmission data TX.

[0033] The encoded transmission data TX is superimposed on the recessive codes on the transmission line 5 output from the clock master 3a. Subsequently, in a period corresponding to the "logical 1" of the transmission data TXD, the recessive code is transmitted as it is over the transmission line 5, and in a period corresponding to the "logical 0" of the transmission data TXD, the data is rewritten into a dominant code for transmission over the transmission line 5.

[0034] The decoding circuit 32 decodes, as in Fig. 3, the decoder circuit 32 converts the received data RX (PWM codes) received by the receive buffer 42 into NRZ codes and outputs the decoded received data RXD to the signal processor 10. Specifically, the decoding circuit 32 measures the duration of the low level in the received data RX using a boundary edge as a starting point. If the measurement result is greater than or equal to a predetermined decoding threshold Tth, the received data RX is decoded as a "logical 0," and if the measurement result is less than the threshold, the received data RX is decoded as a "logical 1."

[0035] The arbitration circuit 33 compares the transmitted data TXD with the received data RXD on a bit-by-bit basis. If the signal levels do not match, the arbitration circuit 33 stops supplying the transmitted data TXD to the coding circuit 31. (decoding circuit)

[0036] Fig. 5 shows a block diagram illustrating a configuration of the decoding circuit 32. The decoding circuit 32 has, as shown in Fig. 5, an edge detection circuit 61, a permission range determination section 62, and a level timer 63. The edge detection circuit 61 detects a boundary edge and an intermediate edge in the received data RX. The permission range determination section 62 generates enable signals EN to enable the edge detection circuit 61 to detect a boundary edge during a permission range established based on a boundary edge detection signal FE describing the timing of detection of a boundary edge. The level timer 63 counts a time corresponding to a period from the time of detection of a boundary edge to the time of detection of an intermediate edge, that is, a low-level width of a PWM code constituting the reception data RX, based on the boundary edge detection signal FE and an intermediate edge detection signal RE describing the time of detection of an intermediate edge.

[0037] The decoding circuit 32 further includes a threshold storage section 64, a comparator 65, and a latch circuit 66. The threshold storage section 64 stores the decoding threshold Tth. The comparator 65 compares the time count value, i.e., level count value TL, obtained from the level timer 63 with the decoding threshold Tth stored in the threshold storage section 64. The latch circuit 66 latches the output of the comparator 65 at the bit boundary of the reference clock and outputs the latched signal as decoded received data RXD.

[0038] If the level count TL is less than the decoding threshold Tth, the comparator 65 determines that the PWM code is the first code (recessive code), and if the level count TL is greater than or equal to the decoding threshold Tth, the comparator 65 determines that the PWM code is the second code (dominant code). Subsequently, the comparator 65 ensures that it outputs binary data (i.e., binary-coded signals) having a value corresponding to the determination result ("logical 1" in the case of the first code / "logical 0" in the case of the second code). (Permit area determination section)

[0039] Fig. 6 shows a block diagram of a specific configuration of the permission area determination section 62. The permission area determination section 62 has, as shown in Fig. 6, a bit timer 71, a range storage section 72, and a comparator 73. The bit timer 71 counts time corresponding to the cycle of the boundary edge (boundary edge cycle) based on the boundary edge detection signals FE. The range storage section 72 stores a start comparison value and an end comparison value. The start comparison value is a count value corresponding to the period from the time of detection of a boundary edge to the time of start of the permission range. The end comparison value is a count value corresponding to the duration of the permission range. The comparator 73 outputs a start timing signal when the time count value obtained from the bit timer 71 matches the start comparison value stored in the range storage section 72.

[0040] The permission range determination section 62 further includes a release timer 74, a comparator 75, and an SR flip-flop circuit 76. The release timer 74 counts the elapsed time from the time the start timing signal is input. The comparator 75 outputs an end timing signal when the time count value of the release timer 74 matches the end comparison value stored in the range storage section 72. The SR flip-flop circuit 76 is supplied with the start timing signal in response to a set input signal and with the end timing signal in response to a reset input signal.

[0041] The permission range determination section 62 further includes a reset storage section 77, a comparator 78 serving as a determination means, a processing unit 79, and an OR circuit 80. The reset storage section 77 stores a reset comparison value determined in accordance with the one-bit-wide time count value obtained from the bit timer 71. The comparator 78 outputs a reset request signal when the time count value obtained from the bit timer 71 matches the reset comparison value. The processing unit 79 acquires the time count value (boundary edge cycle) from the bit timer 71 each time the boundary edge detection signal FE is input.Subsequently, the processing unit 79 generates a start comparison value, an end comparison value, and a reset comparison value based on the detected count value, so as to update the contents of the area storage section 72 and the reset storage section 77 at a predetermined time. At the same time, when a reset request signal is input from the comparator 78, the processing unit 79 outputs a forced release signal K. The OR circuit 80 calculates a logical sum of the output of the SR flip-flop circuit 76 and the output of the forced release signal K and outputs the logical sum as an enable signal EN.

[0042] The timing signals for operating the elements of the digital processor 30 are provided by the timing generator 50, the timing signals including the counting clocks for operating the level timer 63, the bit timer 71, and the enable timer 74.

[0043] The permission range determination section 62 configured as described above outputs the enable signal EN when the forced enable signal K is at a low level after detecting a boundary edge. The enable signal EN assumes a high level after the time specified by the start comparison value has elapsed, and then a low level after the time specified by the end comparison value has elapsed. Furthermore, the permission range determination section 62 outputs a high-level enable signal EN when the forced enable signal K is at a high level. In this case, the entire area becomes a permission range. (processing unit)

[0044] The following is a process executed by the processing unit 79 with reference to the Fig. The flowchart shown in Figure 7 is described.

[0045] The processing unit 79 may be constructed from a microcomputer or from a combination of logic circuits without using a microcomputer.

[0046] The processing unit 79 starts the process when the digital processor 30 is supplied with power.

[0047] First, the processing unit 79 executes initialization processing (step S110). In the initialization processing, the processing unit 79 sets initial values ​​of the start comparison value, the end comparison value, and the reset comparison value in the area storage section 72 and the reset storage section 77. Further, the processing unit 79 turns off the forced release signal K (the processing unit 79 sets the forced release signal K to a low level) and sets a pre-prepared initial flag (that is, the processing unit 79 sets the initial flag to ON).

[0048] The initial values ​​of the start comparison value, the end comparison value, and the reset comparison value are determined based on a reference value. The reference value corresponds to the count value of a one-bit width with the count clocks, where the one-bit width is determined by the communication speed on the transmission line 5. In the present embodiment, the start comparison value is obtained by multiplying the reference value by 0.9, the end comparison value is obtained by multiplying the reference value by 1.1 and subtracting the start comparison value from the multiplication value, and the reset comparison value is obtained by multiplying the reference value by 3.

[0049] Next, the processing unit 79 determines whether or not a boundary edge has been detected by the edge detection circuit 61 (step S120). If a boundary edge has been detected, the processing unit 79 acquires the count value from the bit timer 71 (step S130) and determines whether or not the initial flag has been set (step S140).

[0050] If the initial flag has been set (ON), the processing unit 79 clears the initial flag (ie, the processing unit 79 sets the initial flag to OFF) (step S145), after which control returns to step S120. If the initial flag has been cleared, the processing unit 79 stores the count value in a predetermined memory area as a measurement value of one boundary edge cycle (ie, time width of one bit) (step S150).

[0051] Subsequently, the processing unit 79 determines whether or not the forced release signal K has been turned on (step S160). If the forced release signal K has not been turned on (has been turned off), the processing unit 79 statistically processes the measured values ​​stored in the predetermined storage area to calculate boundary edge cycle statistics (such as an average of the boundary edge cycles over a fixed period in the past) (step S170).

[0052] Subsequently, the processing unit 79 determines whether the calculated statistic deviates by a predetermined tolerance or more from the reference value used in calculating the currently determined start comparison value, end comparison value, and reset comparison value (step S180). If the deviation is within the tolerance, control returns to step S120.

[0053] In contrast, if the deviation is greater than or equal to the tolerance, the processing unit 79 sets the statistics as a reference value. Further, similar to step S110, the processing unit 79 calculates a start comparison value, an end comparison value, and a reset comparison value based on this reference value. Depending on the calculated comparison values, the processing unit 79 resets the contents of the range storage section 72 and the reset storage section 77 (step S190). Control then returns to step S120.

[0054] If it was determined in the previous step S120 that no boundary edge has been detected, the processing unit 79 determines whether or not a reset request has been input from the comparator 78 (step S200). If no reset request has been input, control returns to step S120. On the other hand, if a reset request has been input, the processing unit 79 turns on the forced release signal K and simultaneously sets the initial flag (initial flag = ON) (step S210). Control then returns to step S120.

[0055] If it has been determined in the previous step S160 that the forced release signal K has been turned on, the processing unit 79 turns off the forced release signal K (step S220). Control then proceeds to step S190. In this case, in step S190, the processing unit 79 calculates the comparison values ​​using only the measured value of the boundary edge cycle stored in step S150 as a reference value, instead of using the statistics calculated in step S170.

[0056] In the embodiment, steps S150 to S190, functionally executed by the processing unit 79, constitute variable determination means for variably determining the duration of the permission range in accordance with the detected period of the boundary edge. Furthermore, steps S200 to S220, functionally executed by the processing unit 79 and the reset storage section 77, constitute reset means for resetting the permission range and selectively permitting detection of the boundary edge only during a period lasting until the next duration of the boundary pattern is detected. (Advantages)

[0057] Fig. Fig. 8 is a timing chart illustrating an operation of the permission area determination section 62. In the in-vehicle communication system 1, as described above and in the Fig. As shown in Figure 8, a permission range is determined or established following detection of a bit boundary (boundary edge). The permission range is a time period from the point at which the time corresponding to the start comparison value elapses from the time of detection to a point at which the further time corresponding to the end comparison value elapses. Consequently, it is ensured that a falling edge occurring outside the permission range is not detected as a bit boundary.

[0058] Specifically, based on the detected bit boundary, the point at which the time corresponding to a reference value has elapsed is estimated as the time at which the subsequent bit boundary occurs. A predetermined time period before or after the time (in the present embodiment, a time period corresponding to ±10% of the reference value) is set as a permission range.

[0059] Consequently, if a falling edge occurred due to noise, the falling edge, unless it occurred within the allowable range, would not be mistakenly detected as a boundary edge. Accordingly, the PWM codes can be decoded correctly.

[0060] As can be seen from the lower part of the time diagram in the Fig. As can be seen from Figure 8, erroneous decoding may occur in a conventional device in which the timing of detection of a falling edge is not limited. In particular, such a conventional device detects a falling edge caused by the influence of noise as a boundary edge and a subsequent rising edge as an intermediate edge. Accordingly, the device erroneously detects that a recessive code (logical 1) whose low-level width is less than the decoding threshold Tth has been received, resulting in erroneous decoding (as indicated by the dashed line in RXD in the Fig. 8). In this regard, the in-vehicle communication system 1 is capable of minimizing the occurrence of such erroneous decoding.

[0061] Furthermore, according to the in-vehicle communication system 1, the measured values, which are the time counts of boundary edge cycles, are statistically processed to obtain boundary edge cycle statistics. If the deviation of the statistics from the reference value exceeds the tolerance, it is ensured that the comparison values ​​are reset.

[0062] Consequently, if a clock cycle changes for any reason, provided the change occurs within the permission range, the permission range determination is automatically changed following the change. Accordingly, manually resetting the permission range is not required, saving time and effort for maintenance.

[0063] Furthermore, according to the in-vehicle communication system 1, when the time count of the boundary edge cycle has reached the reset comparison value, it is ensured that the individual comparison values ​​are reset. At the same time, it is ensured that the individual comparison values ​​are determined based on the boundary cycle measured by temporarily removing the permission range. This can cope with the drastic change in the clock cycle to the extent that the permission range is exceeded. In this way, the communication device of the present invention can improve the reliability of the in-vehicle communication system 1. Furthermore, the communication device of the present invention can be used in various systems having a transmission line with a different communication speed and improve the overall characteristics. (Modifications)

[0064] An embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, but can be modified in various ways without departing from the scope of the invention.

[0065] In the embodiment described above, a low-level period in a bit of a transmission code is equal to 1 / 3 in a recessive code and 2 / 3 in a dominant code. However, the present invention is not limited to this. For example, the low-level period may be equal to 1 / 4 in a recessive code and 1 / 2 in a dominant code.

[0066] In the embodiment described above, the boundary edge is used as a boundary pattern, which is information describing a boundary between codes. Alternatively, a bit pattern composed of multiple bits can be used as the boundary pattern.

Claims

[1] Communication device with: - a detecting means (61) for detecting a boundary pattern periodically occurring between codes in a binary coded signal transmitted over a transmission line (6), the boundary pattern being information showing a boundary occurring between codes; - process execution means (63-66) for executing a process synchronously with a time of occurrence of the boundary pattern detected by the detection means (61); and - an area determining device (62) for determining a permission area which is determined to have a time at which the next boundary pattern is expected to occur, the time being counted from the time currently detected by the detecting device (61), wherein - the detection device (61) is capable of detecting the time of occurrence of the boundary pattern during the permission area determined by the area determination device (62), and - the area determination device (62) comprises: - a time counting device (71) for counting a duration between the times detected by the detection device (61), and - a variable determination device (79, S150-S190) for variably determining a duration of the permission area in accordance with the duration of the boundary pattern detected by the time counting device (71). [2] The communication device according to claim 1, wherein the variable determining means (79) resets the duration of the permission range using a statistic of boundary edge cycles acquired by statistically processing measured values ​​which are the time count values ​​of the boundary edge cycles. [3] Communication device according to claim 1 or 2, wherein - the binary coded signal is coded by pulse-modulated codes; and - the detection device (61) is capable of detecting the boundary pattern at an edge showing a bit boundary of a reference clock. [4] A communication device according to any one of claims 1 to 3, wherein said process executing means (63-66) is a decoding circuit for decoding the signal received via said transmission line (6). [5] Communication device according to claim 4, wherein the area determining means (62) comprises: - determining means (78) for determining whether or not the counted duration reaches a comparison value determined to be greater than the duration; and - a reset device (77, 79, S200-S220) for resetting the permission area and allowing the detection device (61) to detect the boundary pattern only during a period of time that lasts until the next duration of the boundary pattern is detected by the detection device (61).

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