VERTICAL SEMICONDUCTOR DEVICES

Abstract

Vertical semiconductor device (500), comprising: - a semiconductor body (40) comprising: a first surface (101); a second surface (102) opposite the first surface; a border (41) extending in a vertical direction substantially orthogonal to the first surface (101); an active region (110); a peripheral region (120) arranged in a horizontal direction substantially parallel to the first surface (101) between the active region (110) and the border (41); a pn junction (14) formed between a first semiconductor region (1) and a second semiconductor region (2) of the semiconductor body (40), the pn junction (14) being adjacent to the first surface (101) and extending from the active region (110) into the peripheral region (120); - a first metallization (10) arranged on the first surface (101) and in ohmic contact with the second semiconductor region (2); and - a second metallization (11) arranged on the second surface (102), wherein the semiconductor device further comprises in the peripheral area (120): - at least one field plate (20, 22) arranged on the first surface (101); and - a passivation structure (6) which at least partially covers the at least one field plate (20, 22) and, on a surface of the at least one field plate (20, 22), covers only edge regions of the at least one field plate (20, 22), wherein the vertical semiconductor device further comprises a first dielectric layer (5) arranged between the semiconductor body (40) and the at least one field plate (20, 22), and a second dielectric layer (9) arranged on the at least one field plate (20, 22).

Description

AREA OF INVENTION

[0001] Embodiments of the present invention relate to vertical semiconductor devices, in particular vertical power semiconductor devices with an active region and a peripheral region having an edge termination structure and surrounding the active region. BACKGROUND OF THE INVENTION

[0002] Semiconductor transistors, especially field-effect controlled switching devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs), are used in a variety of applications, including, but not limited to, switches in power grids and power converters, electric vehicles, air conditioners, and even stereo systems. Particularly in power components capable of switching high currents and / or operating at higher voltages, a low on-resistance (Rn) and a high breakdown voltage (Ud) are often required. bd and / or high robustness is desirable.

[0003] JP 2009-117715A describes a vertical semiconductor device with an active region and a peripheral region, which includes field plates. The field plates are partially covered by an intermediate dielectric with openings for contacting the field plates. WO 2013 / 105350A1 discloses a semiconductor device with closely spaced electrodes and a channel stopper in the peripheral region. The electrodes are intended to prevent the migration of electrical charges. US 2009 / 0079002A1 describes a semiconductor device with charge compensation columns in an active region and charge compensation columns in a peripheral region. The charge compensation columns in the active region are narrower than those in the peripheral region. DE 10 2004 059 453 A1 and DE 10 2010 011 259 A1 each describe a semiconductor device with a field plate and a channel stop electrode in the edge region of the semiconductor device.

[0004] The electrical properties of power semiconductor devices, such as HVMOS power transistors, power diodes and power IGBTs, in particular their blocking capability (breakdown voltage U). bdThese properties can change during operation. This unfavorable behavior can be attributed to mobile charges (ions, charged molecules) that penetrate the semiconductor device from the housing or external sources and / or are caused by corrosion of metal electrodes. The charges can accumulate at the most energetically favorable location, e.g., in the edge termination region, where they can drastically alter the electric field distribution. Standardized robustness tests exist for product development, in particular the HTRB (high temperature reverse bias), H3TRB (high temperature high temperature reverse bias), and HTS (high temperature storage) tests. In these tests, many components exhibit an insufficient compromise between robustness against external charges and robustness against moisture-induced corrosion.Accordingly, there is a need for the improvement of power semiconductor devices. SUMMARY

[0005] According to one embodiment of a vertical semiconductor device, the vertical semiconductor device comprises a semiconductor body comprising: a first surface, a second surface opposite the first surface, a border extending in a vertical direction substantially orthogonal to the first surface, an active region, a peripheral region arranged in a horizontal direction substantially parallel to the first surface between the active region and the border, a pn junction arranged adjacent to the first surface, extending from the active region into the peripheral region and formed between a first semiconductor region and a second semiconductor region of the semiconductor body;The semiconductor device comprises a first metallization arranged on the first surface and in ohmic contact with the second semiconductor region, and a second metallization arranged on the second surface. In the peripheral region, the semiconductor device further comprises at least one field plate arranged on the first surface and a passivation structure that at least partially covers the at least one field plate and, on one surface of the at least one field plate, covers only the edge regions of the at least one field plate. The vertical semiconductor device further comprises a first dielectric layer arranged between the semiconductor body and the at least one field plate, and a second dielectric layer arranged on the at least one field plate.

[0006] According to one embodiment of a vertical semiconductor device, the vertical semiconductor device comprises a semiconductor body comprising: a first surface, a second surface opposite the first surface, a border extending in a vertical direction substantially orthogonal to the first surface, an active region, a peripheral region arranged in a horizontal direction substantially parallel to the first surface between the active region and the border, and a pn junction located adjacent to the first surface and extending from the active region into the peripheral region. The vertical semiconductor device further comprises a first metallization arranged on the first surface and a first dielectric layer.which is arranged between the semiconductor body and the first metallization. The semiconductor device further comprises in its peripheral region: a first conductive region arranged adjacent to the first surface, wherein the first dielectric layer is arranged between the semiconductor body and the first conductive region; a second conductive region arranged adjacent to the first surface and in a horizontal direction between the first conductive region and the edge, wherein the first dielectric layer is arranged between the semiconductor body and the second conductive region; wherein the first metallization, the first conductive region, and the second conductive region each have the same vertical extent above the first dielectric layer; and a passivation structure comprising, in a vertical cross-section, a first section that at least partially covers the first conductive region,and a second section that at least partially covers the second conductive region, wherein the first section has a first thickness above the first conductive region that differs from a second thickness of the second section above the second conductive region.

[0007] Experts in the field of the invention will recognize additional features and advantages upon reading the detailed description below and upon examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The components in the drawings are not necessarily to scale, as greater emphasis has been placed on illustrating the principles of the invention. Furthermore, similar reference numerals in the drawings denote corresponding parts. In the drawings: illustrative Fig. 1 a vertical cross-section through a semiconductor body of a semiconductor device according to an embodiment; illustrative Fig. 2 a vertical cross-section through a semiconductor body of a vertical semiconductor device according to an embodiment; illustrative Fig. 3 a vertical cross-section through a semiconductor body of a vertical semiconductor device according to an embodiment; illustrative Fig. 4 a vertical cross-section through a semiconductor body of a vertical semiconductor device according to an embodiment; illustrative Fig. 5 a vertical cross-section through a semiconductor body of a vertical semiconductor device according to an embodiment; illustrative Fig. 6 a vertical cross-section through a semiconductor body of a vertical semiconductor device according to an embodiment; illustrative Fig. 7 a vertical cross-section through a semiconductor body of a vertical semiconductor device according to an embodiment; illustrative Fig. 8 a vertical cross-section through the semiconductor body of a vertical semiconductor device according to one embodiment; and illustrate Fig. 9 to Fig. 12 vertical cross-sections through a semiconductor body during the process steps of a method for manufacturing a semiconductor device according to the embodiments. DETAILED DESCRIPTION

[0009] The detailed description below refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be practically implemented. In this context, directional terms such as "top," "bottom," "front," "back," "front / right," "rear / right," etc., are used with reference to the orientation of the described drawing(s). Since components of the embodiments can be positioned in several different orientations, these directional terms serve only illustrative purposes and are in no way limiting. It is understood that other embodiments can be used and structural or logical modifications can be made without deviating from the scope of protection of the present invention.The detailed description below is therefore not to be understood as restrictive, and the scope of protection of the present invention is defined by the attached claims.

[0010] Reference is now made to different embodiments, one or more examples of which are shown in the drawings. Each example is provided for illustrative purposes and is not to be understood as limiting the invention. For example, features shown or described as part of one embodiment can be used on or in combination with other embodiments to provide a further embodiment. The present invention is intended to include such modifications and variations. The examples are described using specific terminology, which, however, is not to be interpreted as limiting the scope of protection of the appended claims. The drawings are not to scale and are for illustrative purposes only.For better understanding, the same elements or manufacturing steps in different drawings are designated with the same reference numerals unless otherwise specified.

[0011] The term "horizontal," as used in this description, refers to an orientation essentially parallel to a first horizontal surface or a main horizontal face of a semiconductor substrate or body. This could be, for example, the surface of a wafer or a chip.

[0012] The term "vertical," as used in this description, refers to an orientation substantially perpendicular to the first surface, i.e., parallel to the normal direction to the first surface of the semiconductor substrate or body. Similarly, the term "horizontal," as used in this description, refers to an orientation substantially parallel to the first surface.

[0013] In this description, a second surface of a semiconductor substrate of the semiconductor body is considered to be formed by the lower or rear surface, while the first surface is considered to be formed by the upper, front, or main surface of the semiconductor substrate. The terms "above" and "below," as used in this description, thus describe the relative arrangement of one structural feature with respect to another, taking this orientation into account.

[0014] In this description, n-doped is referred to as the first conductivity type, while p-doped is referred to as the second conductivity type. Alternatively, the semiconductor devices can be designed with opposite doping ratios, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. Furthermore, some figures indicate relative doping concentrations by specifying "-" or "+" next to the doping type. Thus, "n" denotes - “For example, a doping concentration that is lower than the doping concentration of an “n” doping region, while an “n +The “-doping region has a higher doping concentration than the “n” doping region. However, unless otherwise stated, specifying the relative doping concentration does not necessarily mean that doping regions with the same relative concentration have the same absolute doping concentration. Thus, two different n + -Doping regions, for example, may exhibit different absolute doping concentrations. The same applies, for example, to an n + -doping region and a p + -Doping region.

[0015] Specific embodiments described in this description relate, but are not limited to, field-effect semiconductor devices, in particular field-effect compensation semiconductor devices, and manufacturing methods for these. In this description, the terms "semiconductor device," "semiconductor component," and "semiconductor device" are used synonymously. The field-effect semiconductor device is typically a vertical semiconductor device, such as a vertical MOSFET, with a source metallization and an insulated gate electrode arranged on the first surface, and a drain metallization arranged on a second surface opposite the first.A field-effect semiconductor device is typically a power semiconductor device that has an active region with a plurality of MOSFET cells to conduct and / or control a load current. Furthermore, the power semiconductor device typically has a peripheral region (hereinafter also referred to as the circumferential region and edge region) with at least one edge termination structure that at least partially surrounds the active region when viewed from above.

[0016] The term "power semiconductor device," as used in this description, refers to a semiconductor device on a single chip with high-voltage and / or high-current switching capacitances. In other words, power semiconductor devices are designed for high currents, typically in the ampere range, and / or voltages greater than approximately 10 V, or even greater than approximately 100 V or 500 V. In this description, the terms "power semiconductor device" and "power semiconductor component" are used interchangeably.

[0017] The term "edge termination structure," as used in this description, refers to a structure that provides a transition region in which the strong electric fields around an active area of ​​the semiconductor device gradually approach the potential at or near the edge of the device and / or oscillate between a reference potential, such as ground, and a high voltage, such as at the edge and / or back of the semiconductor device. The edge termination structure can, for example, reduce the field strength around a termination region of a rectifying junction by distributing the electric field lines throughout the termination region.

[0018] The term "field effect," as used in this description, refers to the formation of a conductive "channel" of a first conductivity type and / or the control of conductivity and / or the shape of the channel in a semiconductor region of a second conductivity type, typically a body region of the second conductivity type, mediated by an electric field. Due to the field effect, a unipolar current path is formed through the channel region and / or controlled between a source region of the first conductivity type and a drift region of the first conductivity type. The drift region may be in contact with a drain region. The drift region and the drain region are in low-resistance contact with a drain electrode (drain metallization). The source region is in low-resistance contact with a source electrode (source metallization).In the context of this description, the term "in ohmic contact" describes the existence of a low-resistance current path between the respective elements or sections of a semiconductor device when no voltages or only very low test voltages are applied to and / or the semiconductor device. In this description, the terms "in ohmic contact," "in ohmic electrical contact," "electrically coupled," and "in ohmic electrical connection" are used synonymously.

[0019] In the context of this description, the term "MOS" (metal oxide semiconductor) is to be understood as including the more general term "MIS" (metal insulator semiconductor). For example, the term MOSFET (metal oxide semiconductor field-effect transistor) is to be understood as including FETs with a gate insulator that is not an oxide; that is, the term MOSFET is used in the more general sense of both IGFET (insulated gate field-effect transistor) and MISFET (metal insulator semiconductor field-effect transistor). The term "metal" for the gate material of the MOSFET is to be understood as including or encompassing electrically conductive materials such as metals, alloys, doped polycrystalline semiconductors, and metal-semiconductor compounds such as metal silicides.

[0020] In the context of the present description, the term "gate electrode" is used to describe an electrode that is adjacent to and isolated from the body area and is designed to form and / or control a channel area through the body area.

[0021] In the context of the present description, the term "field plate" is used to describe an electrode that is adjacent to a semiconductor region, typically the drift region, is partially insulated from the semiconductor region, and is designed to expand a depleted section in the semiconductor region by charging it to a suitable voltage, typically a negative voltage with respect to the surrounding semiconductor region in the case of an n-type semiconductor region.

[0022] In the context of the present description, the term “mesa” or “mesa region” is used to describe a semiconductor area between two adjacent trenches that extend in a vertical cross-section into the semiconductor substrate or semiconductor body.

[0023] The term "commuting," as used in this description, refers to the switching of current in a semiconductor device from a conducting direction, in which a pn load junction, such as the pn junction between the body region and the drift region of a MOSFET, is biased in the opposite direction, or reverse bias, in which the pn load junction is reverse biased. The term "hard commutation," as used in this description, refers to commutation occurring at a rate of at least approximately 10 9V / s, or more typically with a speed of at least about 5*10 9 V / s.

[0024] The following describes embodiments, semiconductor devices, and fabrication methods for forming semiconductor devices, primarily with reference to silicon (Si) semiconductor devices. Accordingly, a monocrystalline semiconductor region or layer is typically a monocrystalline Si region or layer. However, it is clear that the semiconductor body can be made from any semiconductor material suitable for fabricating a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge); semiconductor materials made from group IV compounds, such as…Silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AllnN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGalnN), or indium gallium arsenide phosphide (InGaAsP); as well as binary or ternary II-VI semiconductor materials, such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name just a few. The semiconductor materials listed above are also referred to as homojunction semiconductor materials. When two different semiconductor materials are combined, a heterojunction semiconductor is formed.Examples of heterojunction semiconductor materials include, but are not limited to: aluminum gallium nitride (AlGaN) - aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN) - aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN) - gallium nitride (GaN), aluminum gallium nitride (AlGaN) - gallium nitride (GaN), indium gallium nitride (InGaN) - aluminum gallium nitride (AlGaN), silicon-silicon carbide (Si. x C 1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor applications, Si, SiC, GaAs, and GaN materials are currently predominantly used. If the semiconductor body comprises a wide-bandgap material, such as SiC or GaN, which exhibits a high breakdown field strength or a high critical avalanche field strength, the doping of the corresponding semiconductor regions can be increased, thereby reducing the on-resistance Ron, which is also referred to below as the on-resistance Ron.

[0025] Referring to Fig. 1 A first embodiment of a semiconductor device 100 is described. Fig. Figure 1 shows a vertical cross-section through a semiconductor body 40 of the semiconductor device 100. The semiconductor body 40 extends between a first surface 101, which faces a vertical direction, and a second surface 102, which is located opposite the first surface 101. In a horizontal direction, which is substantially parallel to the first surface 101, the semiconductor body 40 is bounded by a border 41, for example a saw edge, which extends between the first surface 101 and the second surface 102. The semiconductor body 40 has an active region 110 and a circumferential region 120, which is located between the active region and the border 41. Typically, when viewed from above, the circumferential region 120 surrounds the active region 110.

[0026] A first metallization, typically forming a source metallization 10, is arranged on the first surface 101. A second metallization, typically forming a drain metallization 11, is arranged on the second surface 102, i.e., opposite the source metallization 10. Furthermore, a plurality of gate electrodes 12 can be located on the first surface 101 in the active region 110 and are isolated from the source metallization 10 and the semiconductor body 40 by corresponding gate dielectric regions 5. The gate electrodes 12 are connected to a gate metallization that is located in Fig. 1 is not shown and is typically also arranged on the first surface 101. Accordingly, the semiconductor device 100 can be operated as a device (transistor) with three terminals. For better understanding, only a few of a large number of transistor cells (unit cells) of the active area 110 are shown in Fig. 1 shown.

[0027] The semiconductor body 40 typically comprises a monocrystalline substrate material 3 and at least one epitaxial layer 1 formed on it. The use of one or more epitaxial layers 1 provides greater freedom for adjusting the background doping of the material, as the doping concentration can be adjusted during the deposition of the epitaxial layer(s).

[0028] Alternatively, a thick wafer with an initial resistance corresponding to the doping of the drift region can be used to fabricate the devices, with the final device thickness being adjusted by a thinning process performed after the device structure has been implemented on the front side of the wafer. The highly doped layers on the back side of the wafer can be implemented using the thinning process, for example, by ion implantation followed by a laser annulation process.

[0029] A pn junction 14 is formed between a first n-type semiconductor region 1, which typically forms a drift region, and a second p-type semiconductor region 2 of the semiconductor body 40. The pn junction 14 is located adjacent to the first surface 101, extends from the active region 110 into the circumferential region 120, and forms a rectifying junction between the first metallization 10 and the second metallization 11.

[0030] In the exemplary embodiment, the second semiconductor region 2 extends to the first surface 101 in both the active region 110 and the circumferential region 120. An innermost region of the second semiconductor region 2 can form a body region of an outermost transistor cell.

[0031] In embodiments relating to field-effect semiconductor devices, the active region 110 can be defined by the presence of insulated gate electrodes 5, 12 configured to form a channel region in an adjacent p-type body region 2a between an adjacent n-type source region (in Fig. 1 (not shown), which is in ohmic contact with the source metallization 10, and a drift region 1 (first semiconductor region 1). The doping ratios can also be reversed. The active region 110 can also be defined by the presence of active cells, such as diode cells, MOSFET cells, and IGBT cells, which carry a load current between the source metallization 10 and the drain metallization 11.

[0032] As in Fig. As shown in Figure 1, the body areas 2a of the active area 110 and of the second semiconductor area 2 can be connected to the source metallization 10 via corresponding conductive connectors 10a.

[0033] In the Fig. In the embodiment shown in Figure 1, the transistor cells of the active area 110 are designed as n-channel DMOS structures with corresponding gate electrodes 12 arranged on the first surface 101.

[0034] According to another embodiment, the gate electrode(s) 12 and the gate dielectric(s) 5 are formed in corresponding trenches extending from the first surface 101 into the semiconductor body 40. In this embodiment, the body region 2a and the source region border an upper part of the respective trench, while the drift region 1 borders a lower part of the respective trench. In this embodiment, the drift region 1 cannot extend to the first surface 101 in the active region 110.

[0035] In the Fig. In the embodiment shown in Figure 1, the semiconductor body 40 can comprise a highly doped drain region 3 of the n-type, which extends to the second surface 102 and is in ohmic contact with the drain metallization 11.

[0036] In addition, a field stop area of ​​type n (in Fig. (1 not shown) are located between the drain region 3 and the drift region 1. The drain region 3, the optional field-stop region 3, and the drift region 1 (first semiconductor region 1) are typically located in the active region 110 and the circumferential region 120 and may extend to the edge 41.

[0037] In embodiments relating to diodes, the semiconductor body 40 can comprise a plurality of p-type anode regions 2a arranged in the active region 110 and in ohmic contact with an anode metallization 10, as well as a highly doped n-type cathode region 3 extending to the second surface 102 and in ohmic contact with a cathode metallization 11.

[0038] In embodiments relating to IGBTs, the semiconductor body 40 comprises a highly doped p-type collector region 3 instead of an n-type drain region. In these embodiments, the first metallization 10 and the second metallization 11 form an emitter metallization 10 and a collector metallization 11, respectively.

[0039] In embodiments relating to IGBT with (a) integrated freewheeling diode(s), the semiconductor body 40 on the second surface 102 comprises a highly doped layer 3 with one or more p-type collector regions and one or more n-type cathode regions, each in ohmic contact with the second metallization 11 and forming a common collector-anode metallization 11.

[0040] The second metallization 11 is typically located in both the active area 110 and the circumferential area 120. The second metallization 11 can even completely cover the second surface 102 and extend to the edge 41.

[0041] In the Fig. In the embodiment shown in Figure 1, the semiconductor device 100 comprises two first conductive regions 20, 21 and a second conductive region 22 in the circumferential region 120, which are arranged on the first surface 101 and are separated from the semiconductor body 40 by a first dielectric layer 5, which is also arranged on the first surface 101, and are implemented as field plates. Accordingly, the semiconductor device 100 is provided with edge termination structures to ensure a sufficiently high breakdown voltage. The second conductive region 22 is, for example, arranged closest to the edge 41 and can be in ohmic contact with the second metallization 11 (drain metallization), e.g., via the semiconductor body 40, while the innermost first conductive region 20 is in ohmic contact with the gate metallization (in the Fig. 1 not shown) and a polysilicon gate contact layer 16, and the conductive areas 21 can be potential-free.

[0042] The first dielectric layer 5 is typically a silicon oxide layer, such as a thermal oxide layer.

[0043] Typically, the first conductive areas and the second conductive area 20, 21, 22 consist of the same material and / or have the same composition as the source metallization 10 or the gate metallization.

[0044] Viewed from above, the first conductive areas and the second conductive area 20, 21, 22 typically surround the active area 110.

[0045] The first conductive areas and the second conductive area 20, 21, 22 can be essentially ring-shaped, for example, ring-shaped when viewed from above. In these embodiments, the first conductive areas and the second conductive area 20, 21, 22 can form a gate ring 20, a floating ring 21, or a drain ring 22, depending on contact.

[0046] An outermost section of the source metallization 10 can form a source field plate. Depending on the design, the semiconductor device 100 can also include a separate source ring.

[0047] According to one embodiment, a passivation structure 6, 7 is provided which has a first area (inner area) covering the first conductive areas 20, 21 and a second area (outer area) covering the second conductive area 22.

[0048] In the exemplary embodiment, the first region has a first thickness that is greater than a second thickness of the second region.

[0049] The first and second areas can share at least one passivation layer 7, i.e., each comprise parts of a contiguous passivation layer 7.

[0050] The thickness of the first and second regions of the passivation structure 6, 7 is usually measured in a direction normal to the contiguous surfaces of the conductive regions 20, 21, 22 (layer thickness) and, unless explicitly stated otherwise, may refer to a minimum thickness, a maximum thickness, or an average thickness. The same definition applies when comparing the thicknesses of the passivation structure 6, 7 covering different first and second conductive regions 20, 21, 22.

[0051] Typically, the thickness of the first and the thickness of the second region of the passivation structure 6, 7 (inner and outer regions of the passivation structure 6, 7) differ by at least 50%, more typically by a factor of at least about 5, and even more typically by a factor of at least about 10. For example, the thickness of the second region of the passivation structure 6, 7 may be less than about 100 nm, for example in the range of about 5 to 15 nm or 20 nm, and the thickness of the first region of the passivation structure 6, 7 may be in the range of about 200 nm to about 800 nm.

[0052] Furthermore, the first conductive regions 20, 21 of the semiconductor device 100 are covered by a stack of two layers 6, 7, wherein a first passivation layer 6 directly covers the first conductive regions 20, 21, and a second passivation layer 7 is arranged on top of this, while the second conductive regions 22 are directly covered by the second passivation layer 7.

[0053] The first passivation layer 6 and the second passivation layer 7 typically consist of different materials, such as silicon oxide, silicon nitride, silicon oxynitride or a semi-insulating material, such as diamond-like carbon.

[0054] In the Fig. In the embodiment shown in Figure 1, the first passivation layer 6 is thicker than the second passivation layer 7. In other embodiments, the first passivation layer 6 is thinner than the second passivation layer 7. The first and second passivation layers 6, 7 can also be essentially the same thickness.

[0055] Furthermore, the passivation structure 6, 7 can have more than two passivation layers 6, 7.

[0056] As in Fig. As shown in Figure 1, the passivation structure 6, 7 or the passivation layers 7, 6 typically also cover the source metallization 10 in the active area 110.

[0057] In one embodiment, the first region of the passivation structure 6, 7 is formed as an oxide-nitride stack 6, 7 with an oxide thickness 6 of about 100 nm to about 5 µm, more typically in the range of about 100 nm to about 3 µm, and a nitride thickness 7 in the range of about 100 nm to about 1 µm, and the second region of the passivation structure 6, 7 consists of a nitride 7 with a thickness in the range of 0 to about 100 nm.

[0058] A second dielectric layer 9, such as an imide layer, is typically arranged on the passivation structure 6, 7 in the active region 110 and in the circumferential region 120. The first dielectric layer 5 and the second dielectric layer 9 are also referred to as the further dielectric layer 5 and dielectric layer 9, respectively.

[0059] In addition, a finishing layer (sealing layer, barrier layer) 19, e.g. a molded compound (mold compound, potting compound) or an insulating gel, is typically arranged on the dielectric layer 9 in the active area 110 and the circumferential area 120.

[0060] Due to the use of a thinner passivation structure on the outer conductive region 22 compared to the inner conductive regions 20, 21, good resistance to both the ingress of external charges and moisture-induced damage can be achieved. Numerical simulations confirm this.

[0061] Fig. Figure 2 shows a vertical cross-section through a vertical semiconductor device 200. The semiconductor device 200 is the one shown above with respect to Fig. The semiconductor device 200 described in Section 1 is similar to the semiconductor device 100 and can also be operated as a power field-effect transistor. However, the passivation structure 6, 7 of the semiconductor device 200 consists of only one passivation layer 6, 7, which has a smaller thickness on the second conductive region 22 (and adjacent to it) compared to the region on the first conductive regions 20, 21 and the active region 110.

[0062] Furthermore, a highly n-doped channel stop region 4 is arranged in the first semiconductor region 1 adjacent to the first surface 101 and the edge 41. In other embodiments, the channel stop region 4 is highly p-doped.

[0063] Fig. Figure 3 shows a vertical cross-section through a vertical semiconductor device 300. The semiconductor device 300 is the one shown above with respect to Fig. The semiconductor device 300 described in section 1 is similar to the semiconductor device 100 and can also be operated as a power field-effect transistor. However, no gate field plate 21 is present in the circumferential area 120 of the semiconductor device 300.

[0064] Furthermore, the first conductive area of ​​the semiconductor device 300 consists of an outermost region 20 of the first metallization 10, which forms a source field plate in the circumferential region 120.

[0065] Fig. Figure 4 shows a vertical cross-section through a vertical semiconductor device 400. The semiconductor device 400 is the one shown above with respect to Fig. The semiconductor device 400 described in Figure 1 is similar to Figure 100 and can also be operated as a power field-effect transistor. However, in the circumferential area 120 of the semiconductor device 400, there is only a first conductive region 20.

[0066] Furthermore, the thickness of the passivation structure 6, 7 varies on the second conductive region 22. In an inner boundary region of the second conductive region 22, the passivation structure 6, 7 is thicker than in regions closer to the chip edge 41. Accordingly, a thicker passivation is provided in the second conductive region 22 (field plate), where a comparatively stronger electric field is expected in a blocking mode of the semiconductor device 400 (blocking bias of the pn junction 14).

[0067] Accordingly, the compromise between resistance to external charges and resistance to moisture-induced corrosion can be further improved.

[0068] According to one embodiment, the circumferential area 120 of the semiconductor device 400 comprises a field plate 20 which is covered by a passivation structure 6, 7 of varying thickness.

[0069] Fig. Figure 5 shows a vertical cross-section through a vertical semiconductor device 500. The semiconductor device 500 is the one described above with reference to Fig. The semiconductor device 400 described in section 4 is similar and can also be operated as a power field-effect transistor. However, the passivation structure 6 consists only of the first passivation layer 6.

[0070] Furthermore, the passivation structure 6 only covers peripheral areas of the first conductive region 20.

[0071] According to one embodiment, the circumferential area 120 of the semiconductor device comprises 500 field plates 20, 22, each of which is only partially covered by a passivation structure 6.

[0072] Furthermore, the passivation structure 6 can be at least partially interrupted in a vertical cross-section, as shown in Fig. 5 is shown.

[0073] Fig. Figure 6 shows a vertical cross-section through a vertical semiconductor device 600. The semiconductor device 600 is the one described above with reference to Fig. The semiconductor device 600 is similar to the one described in Section 1. The semiconductor device 600 can be operated as a power diode or as a power field-effect transistor. However, the passivation structure 6, 7 is formed on the first conductive areas 20, 21 by regions of the first passivation layer 6 and on the second conductive area by a thinner second passivation layer 7.

[0074] The first conductive regions 20, 21 can be potential-free semiconductor regions.

[0075] Furthermore, the semiconductor device 600 has a more highly doped field-stop semiconductor region 4a, which extends to the first surface 101 and the edge 41.

[0076] In the Fig. In the embodiment shown in Figure 6, the second semiconductor region 2 and the first conductive regions 20, 21 do not overlap when viewed from above.

[0077] Fig. Figure 7 shows a vertical cross-section through a vertical semiconductor device 700. The semiconductor device 700 is the one described above with reference to Fig. The semiconductor device 600 described in Section 6 is similar. However, the second semiconductor region 2 and the first conductive regions 20, 21 overlap when viewed from above. The field plates 20, 21 can be in ohmic contact with the underlying p-doped second semiconductor region 2.

[0078] Fig. Figure 8 shows a vertical cross-section through a vertical semiconductor device 800. The semiconductor device 800 is the one described above with reference to Fig. 6 described semiconductor device 600 similar.

[0079] In the Fig. In the embodiment shown in Figure 8, three potential-free first semiconductor regions 20, 21, 21' are arranged on the first surface 101 in the circumferential region 120 of the semiconductor device 800, which overlap with three potential-free (p-type) guard rings 4b, each of which forms a pn junction with the first semiconductor region 1. The field plates 20, 21, 21' can be in ohmic contact with the respective guard rings 4b.

[0080] Referring to Fig. Figures 9 to 12 illustrate process steps of a method for forming a vertical semiconductor device 900, each in cross-sections through a semiconductor body 40. For clarity, each figure shows only the left part of a plurality of semiconductor devices 900, which are typically formed in parallel on the plane of a wafer.

[0081] In a first step, a semiconductor substrate or wafer 40, such as a Si wafer, is provided, extending between a first or top surface 101 and a second or back surface (not shown) located opposite the main surface 101. Typically, the wafer 40 comprises a first semiconductor layer 1 of a first conductivity type (n-type) extending to the first surface 101; a second (p-type) semiconductor region 2 on the first surface, forming a pn junction 14 with the first semiconductor layer 1; and a more highly doped third semiconductor layer (not shown) extending to the second surface of the semiconductor wafer 40.

[0082] Fig. Figure 10 shows the semiconductor structure 900 after the formation of a first dielectric layer 5 on the first surface 101, for example by thermal oxidation. The depicted edge 41 corresponds to a saw-cut edge formed later.

[0083] In the exemplary embodiment, the pn transition 14 to the first surface 101 extends in the circumferential region 120.

[0084] Subsequently, one or more field plates 20, 21, 22 can be formed on the first dielectric layer 5. This typically involves the deposition of a highly conductive layer, such as a metal layer, and etching using a mask.

[0085] As in Fig. As shown in Figure 10, the field plates 20, 21, 22 are typically formed together with a first metallization 10 on the first surface 101.

[0086] In embodiments relating to the formation of power field-effect semiconductor devices, a plurality of field-effect structures are typically formed, each with insulated gate electrodes in the active region 110 adjacent to the surface 101, before the field plates 20, 21, 22 or the first metallization 10 are formed.

[0087] A first passivation layer 6 can then be deposited on the field plate 20, 21, 22, for example as a structure-preserving layer using a CVD process. The resulting semiconductor structure 900 is in Fig. 11 shown.

[0088] Subsequently, the thickness of the first passivation layer 6 of at least one outermost region of the outermost field plate 22 can be reduced, e.g., by etching using a mask. The resulting semiconductor structure 900 is in Fig.Figure 12 shows an embodiment in which the thickness of the first passivation layer 6 is reduced such that the minimum thickness of the first passivation layer 6 at the outermost field plate 22 (which has a greater distance to the active area than the other field plates 20, 21 and is closest to the edge 41 after sawing) is less than a minimum thickness at the other field plate 20, 21, while the maximum thickness of the first passivation layer 6 on the field plates 20, 21, 22 is essentially the same.

[0089] In other embodiments, the first passivation layer 6 is thinned to substantially the same proportion on all adjacent surfaces of the outermost field plate 22, e.g. to less than about 50%, more typically to less than about 20% and more typically to less than about 10%.

[0090] After or before the formation of the first passivation layer 6, a second passivation layer (not shown) can be formed on the first passivation layer 6 or on the field plates 20, 21, 22, such as a structure-preserving layer. In these embodiments, the first passivation layer 6 can also be completely removed from the outermost field plate 22. The second passivation layer is typically thinner than the first passivation layer, e.g., by a factor of at least about 5 or even 10.

[0091] A second dielectric layer can then be formed on the first passivation layer 6 or the second passivation layer.

[0092] A sealing compound can then be deposited on the second dielectric layer.

[0093] Afterwards, a second metallization can be formed in ohmic contact with the second semiconductor region 2 and the outermost field plate 22 on the second surface 102.

[0094] Afterwards, the wafer 40 can be divided into separate semiconductor devices 900, e.g. by sawing.

[0095] Although various embodiments of the invention have been disclosed, it is clear to those skilled in the art that various changes and modifications can be made by which some of the advantages of the invention can be achieved without deviating from the essence and scope of protection of the invention. It is also obvious to those skilled in the art that other components can be used as substitutes in a suitable manner to perform the same functions. It should be noted that the features described with reference to a particular drawing can be combined with features from other drawings, even where this is not explicitly stated. Such modifications of the inventive concept are also covered by the appended claims.

[0096] Spatial terms such as "under," "below," "lower," "above," "upper," and the like are used to simplify descriptions and explain the positioning of one element relative to another. These terms encompass other orientations of the device in addition to those shown in the drawings. Furthermore, terms like "first," "second," and the like are also used to describe different elements, areas, regions, etc., and are not intended to be restrictive. Consistent terms throughout the description refer to the same elements.

[0097] As used herein, the terms "exhibit," "contain," "include," "comprise," and the like are open-ended and refer to the presence of the elements or characteristics mentioned, but do not exclude the presence of additional elements or characteristics. Definite and indefinite articles include both the plural and singular unless the context clearly indicates otherwise.

Claims

[1] Vertical semiconductor device (500), comprising: - a semiconductor body (40) comprising: a first surface (101); a second surface (102) opposite the first surface; a border (41) extending in a vertical direction substantially orthogonal to the first surface (101); an active region (110); a peripheral region (120) arranged in a horizontal direction substantially parallel to the first surface (101) between the active region (110) and the border (41); a pn junction (14) formed between a first semiconductor region (1) and a second semiconductor region (2) of the semiconductor body (40), the pn junction (14) being adjacent to the first surface (101) and extending from the active region (110) into the peripheral region (120); - a first metallization (10) arranged on the first surface (101) and in ohmic contact with the second semiconductor region (2); and - a second metallization (11) arranged on the second surface (102), wherein the semiconductor device further comprises in the peripheral area (120): - at least one field plate (20, 22) arranged on the first surface (101); and - a passivation structure (6) which at least partially covers the at least one field plate (20, 22) and, on a surface of the at least one field plate (20, 22), covers only edge regions of the at least one field plate (20, 22), wherein the vertical semiconductor device further comprises a first dielectric layer (5) arranged between the semiconductor body (40) and the at least one field plate (20, 22), and a second dielectric layer (9) arranged on the at least one field plate (20, 22). [2] Vertical semiconductor device according to claim 1, wherein the passivation structure (6) on a surface of the at least one field plate (20, 22) comprises a varying thickness and the thickness is greatest at least near an edge of the at least one field plate (20, 22). [3] Vertical semiconductor device according to claim 1 or 2, wherein the thickness is greatest where an electric field on a surface of the at least one field plate (20, 22) is expected to be strongest when the pn junction (14) is reverse-biased. [4] Vertical semiconductor device according to one of claims 2 to 3, wherein the ratio between a maximum value of the varying thickness and a minimum value of the varying thickness is at least about 10. [5] Vertical semiconductor device (100-400, 600-800) comprising: - a semiconductor body (40) comprising: a first surface (101), a second surface (102) opposite the first surface (101), a border (41) extending in a vertical direction substantially orthogonal to the first surface (101), an active region (110), a peripheral region (120) arranged in a horizontal direction substantially parallel to the first surface (101) between the active region (110) and the border (41), and a pn junction (14) located adjacent to the first surface (101) and extending from the active region (110) into the peripheral region (120); - a first metallization (10) arranged on the first surface (101) and a first dielectric layer (5) arranged between the semiconductor body (40) and the first metallization (10); wherein the semiconductor device further comprises in the peripheral region (120): - a first conductive region (20, 21) located adjacent to the first surface (101), wherein the first dielectric layer (5) is located between the semiconductor body (40) and the first conductive region (20, 21); - a second conductive region (22) located adjacent to the first surface (101) and in a horizontal direction between the first conductive region (20, 21) and the edge (41), wherein the first dielectric layer (5) is located between the semiconductor body (40) and the second conductive region (22); - wherein the first metallization (10), the first conductive region (20, 21) and the second conductive region (22) each have the same vertical extent above the first dielectric layer (5); and - a passivation structure (6, 7) comprising in a vertical cross-section: a first section covering at least partially the first conductive region (20, 21) and a second section covering at least partially the second conductive region (22), wherein the first section has a first thickness above the first conductive region (20, 21) which differs from a second thickness of the second section above the second conductive region (20). [6] Vertical semiconductor device according to claim 5, wherein the first section has a different layer composition than the second section. [7] Vertical semiconductor device according to claim 5 or 6, wherein at least one of the first conductive area (20) and second conductive area (22) is arranged on the first surface (101) and is designed as a field plate. [8] Vertical semiconductor device according to one of claims 5 to 7, further comprising a dielectric layer (9) arranged on the passivation structure (6). [9] Vertical semiconductor device according to any one of claims 5 to 8, wherein the second thickness is less than the first thickness. [10] Vertical semiconductor device according to any one of claims 5 to 9, wherein the second thickness and the first thickness differ by at least 50%. [11] Vertical semiconductor device according to any one of claims 5 to 10, wherein the second thickness is less than about 100 nm and wherein the first thickness is in a range of about 200 nm to about 800 nm.

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