Device and method for substrate routing with local high density

Abstract

A device (300) comprising: a medium (102B) with an intermediate connection (118) in an insulating layer, wherein the intermediate connection is located over a conductive line (120), the conductive line of the medium being a bus; a connecting element (104) above the medium, wherein the connecting element has electrically conductive pads (224) on it and the connecting element comprises a silicon chip, wherein the connecting element is vertically above and spaced apart from the conductive conductor of the medium; a conductive structure (112) that is spaced laterally from the connecting element, wherein the conductive structure lies vertically above the intermediate connection of the medium and is electrically connected to it; an insulator material (122) on the insulating layer of the medium, wherein the insulator material is laterally adjacent to the connecting element and the insulator material is in lateral contact with the conductive structure, wherein the insulator material is vertically above and spaced apart from the conductive conductor of the medium; a first chip (114B) above the connecting element, wherein the first chip is coupled to a first of the electrically conductive pads (224) of the connecting element and the first chip is electrically coupled to the conductive structure; and a second chip (114A) above the connecting element, wherein the second chip is coupled to a second of the electrically conductive pads (224) of the connecting element.

Description

Technical field

[0001] The present disclosure relates generally to electronic chip architectures. General state of the art

[0002] Semiconductor devices, such as electronic devices, may include substrate routing that has a lower density than some of the routing in a chip attached to the substrate. Such devices may contain complex routing schemes, especially in regions where the attached chip contains routing with a higher density than the routing in the substrate.

[0003] The publication DE 10 2014 108 992 A1 is a subsequently published prior art and describes the flow behavior of underfill material for reduced distances between the chip layers in semiconductor packages. Brief description of the drawings Fig. Figure 1 shows an example of a device that incorporates local high-density substrate routing. Fig. Figure 2 shows an example of a high-density connecting element according to one or more embodiments. Fig. Figure 3 shows an example of another device incorporating local high density substrate routing, according to one or more embodiments. Fig. Figure 4 shows an example of a technique for manufacturing a device with substrate routing with local high density according to one or more embodiments. Fig. Figure 5 shows an example of an electronic device according to one or more embodiments. Description of embodiments

[0004] The following description and drawings sufficiently illustrate specific embodiments to enable those skilled in the field to implement them in practice. Other embodiments may include structural, logical, electrical, process, or other modifications. Parts and features of some embodiments may be included in other embodiments or replaced by those of other embodiments.

[0005] This document describes in general embodiments of a system and method for local high-density substrate routing. In one or more embodiments, a device comprises a medium, first and second circuit elements, one or more connecting elements, and a dielectric layer. The medium may contain low-density routing. The connecting element may be embedded in the medium and may contain a plurality of electrically conductive elements, one of which may be electrically coupled to the first and second circuit elements. The connecting element may contain high-density routing. The dielectric layer may be located above the connecting element and may contain the first and second circuit elements passing through it.

[0006] Substrate solutions can be used to create chip-to-chip interconnects. The I / O (input / output) density in a package substrate can be determined by the minimum track and spatial dimensions of the substrate. These minimum track and spatial dimensions can be limited by the resolution of the lithography and coating processes used in the substrate fabrication process(s). This limitation can be a function of the economic cost of achieving the required resolution. The routing density in a multi-chip substrate can be approximately one hundred times lower than a routing density in a chip-level routing process. Problems associated with using lower routing densities can include larger areas of the substrate dedicated to I / O and reduced system performance and reliability.

[0007] A problem associated with existing multichip package substrates can be the inability to utilize chip-level routing densities for substrate routing in a cost-effective or manufacturably efficient manner. One solution to this problem can be the use of a high-density interconnect element (for example, an interconnect die or interconnect chip) embedded in a medium (for example, a substrate) that incorporates chip-level routing (for example, high-density routing). This solution can provide a locally high-density routing element, enabling the creation of locally high-bandwidth (for example, high-density) chip-to-chip connections or the ability to modify a package design and add functionality that can benefit from a high-bandwidth chip-to-chip connection without requiring significant changes to the manufacturing process.Such a solution can also provide high-density connections only when they are beneficial, thus allowing the use of more cost-effective lithography and coating processes for conventional package routing (e.g., low-density routing) in areas of the substrate where high-density connections are not useful or desired. This solution can also introduce dimensional variation in the placement of a high-density connection element if the connection element is embedded in or below the N-1 layer (e.g., the layer below the top layer of the substrate (the N-layer)). In embodiments containing more than one connection element, the orientation of one connection element can be independent of the other connection elements.Implementations that incorporate the high-density interconnect embedded beneath the substrate's top layer can unify package core routing and high-bandwidth interconnect routing into a single, mapped bump field on the substrate for subsequent chip mounting. Furthermore, such a solution can enable chips to be routed differently and potentially more economically. The high-bandwidth interconnect routing can be located separately on a portion of the chip at or near the location where the high-bandwidth interconnect coupling will physically occur, thus leaving the remainder of the chip space available for low-density routing. By incorporating pads on the interconnect that are sized or designed larger than a circuit element (for example, an electrically conductive contact hole), variations in the circuit element's placement can be tolerated.

[0008] Fig. Figure 1 shows an example of a device 100 that may include local high-density substrate routing. The device 100 may include a medium 102A, one or more high-density interconnects 104, an optional dielectric layer 108, one or more first circuit elements 110A, one or more second circuit elements 110B, an optional adhesive layer 122, or one or more chips 114A-B.

[0009] Medium 102A may contain low-density interconnect routing. Medium 102A may be a substrate, such as a semiconductor substrate (e.g., silicon, gallium, indium, germanium, or variations or combinations thereof, along with other substrates), one or more insulating layers, such as glass-reinforced epoxy (e.g., FR-4), polytetrafluoroethylene (Teflon), cotton-paper-reinforced epoxy (CEM-3), phenolic glass (G3), paper-phenol (FR-1 or FR-2), polyester glass (CEM-5), any other dielectric material, such as glass, or any combination thereof, as may be used in printed circuit boards (PCBs). Medium 102A may be fabricated using a bumpless buildup layer process (BBUL) or another technique for generating Medium 102A.A BBUL process incorporates one or more build-up layers formed beneath an element, such as a high-density interconnect 104 or a chip 114. A microcontact hole formation process, such as laser drilling, can create connections between build-up layers and chip or chip-dice bonding islands. The build-up layers can be formed using high-density integration patterning technology. The chip or chips 114 and the high-density interconnect 104 can be embedded in the substrate or electrically connected using a BBUL or another process.

[0010] The high-density interconnect 104 can contain a variety of electrically conductive elements 106 arranged, placed, formed, or otherwise housed within it. The electrically conductive elements 106 can be housed within the high-density interconnect 104, with gaps or spaces between them that may be smaller (for example, up to approximately 100 times smaller) than those achievable with conventional substrate routing techniques (for example, the high-density interconnect 104 can incorporate high-density substrate routing), such as by using a chip routing technique to create the high-density interconnect 104. The high-density interconnect 104 can be a semiconductor chip, such as a silicon chip.The high-density connecting element 104 may contain at least one layer of glass, ceramic or organic materials.

[0011] The high-density connecting element 104 can be located in the medium 102A on or at a layer below the surface (for example, the N-1 layer or below) or can be located above a top surface (for example, the N-layer) of the medium 102A, as shown in Fig. 3 shown, are located.

[0012] The high-density connecting element 104 can contain electrically conductive pads 224 arranged on or at least partially within the high-density connecting element 104, such as on or at least partially beneath a top surface 226 of the high-density connecting element 104, as for example in Fig. 2 shown. The electrically conductive pads 224 can be placed between the electrically conductive element 106 and the circuit element 110A-B, as shown in Fig. Figure 2 shows that the electrically conductive pads 224 can be electrically connected. The electrically conductive pads 224 can contain conductive metal, such as copper, gold, silver, aluminum, zinc, nickel, brass, bronze, iron, etc. The electrically conductive pads 224 (for example, high-density electrically conductive pads 224) can have a footprint larger than the corresponding footprint of a circuit element 110. Such a configuration can accommodate dimensional variations in the manufacture or arrangement of the high-density connecting element 104 in the medium 102. The electrically conductive pads 224 can have a footprint that is, among other shapes, circular, square, rectangular, triangular, or a combination thereof. The footprint of the electrically conductive pads 224 can range from approximately 175 µm². 2 up to 10,000 µm 2such as an electrically conductive pad 224 containing a base area dimension of 50 µm, such as an electrically conductive pad 224 that is square with a base area of ​​approximately 2500 µm 2 or circular with a base area of ​​approximately 1963 µm² 2 In some embodiments, the electrically conductive pads 224 can have a base area of ​​approximately 1900 µm². 2 up to 2550 µm 2 contain.

[0013] The dielectric layer 108 can be arranged above the high-density connecting element 104 (an example of a lower boundary of the dielectric layer 108 is indicated by the horizontal dashed line in the medium 102A). The dielectric layer 108 can contain circuit elements 110 passing through it. Enclosing the dielectric layer 108 can help to accommodate dimensional variations in the placement, embedding, or otherwise arranging of the high-density connecting element 104, at least partially in or on / at the medium 102A. The dielectric layer 108 can contain oxide or other materials, such as insulating materials.

[0014] The high-density interconnect 104 can contain interconnect circuitry, such as the first and second interconnects 110A-B, which can be high-density interconnects 110. The interconnects 110AB can be configured for electrical coupling with the electrically conductive element 106, for example, by electrically coupling a high-density electrically conductive pad 224A-B of the chip 114A-B with a high-density electrically conductive pad 224 of the high-density interconnect 104. The interconnects 110AB can be electrically conductive contact holes. The interconnects 110 can have a footprint of approximately 175 µm. 2 up to 3,600 µm 2 take up, for example, a circuit element 110 that contains a base area dimension of approximately 30 µm, such as a circuit element 110 that is essentially circular with a base area of ​​approximately 707 µm 2or essentially square with a base area of ​​approximately 900 µm² 2 In some embodiments, the circuit elements 110 can have a base area of ​​approximately 600 µm². 2 up to 1,000 µm 2 take.

[0015] One or more chips 114A-B can be arranged above the medium 102. The chips 114A-B can be electrically coupled to the circuit element 110A-B by an electrically conductive adhesive 112, such as solder, adhesive tape, glue, or other electrically conductive adhesive. The electrically conductive adhesive 112 can electrically couple the first chip 114A to the second chip 114B, for example, by electrically coupling a high-density electrically conductive pad 224A to / on or at least partially within the first chip 114A to an electrically conductive pad 224B to / on or at least partially within the second chip 114B. The first or second chip 114A-B can be logic, memory, a central processing unit (CPU), graphics, radio, or any other type of chip or package (enclosure).The electrically conductive pad 224 of the high-density connecting element 104 can be located between a circuit element 110 and an end 238A-B of the electrically conductive element 106.

[0016] The first and second chips 114A-B can include a low-density interconnect pad 328, which can be used for power, ground, or any other electrical coupling connected to it. The low-density interconnect pad 328 can be electrically coupled to a bus 120, such as a power, ground, or data bus, for example, by means of the low-density interconnect 118. The low-density interconnect pad 328 can be electrically coupled to an electrically conductive pad 332, for example, by means of conductive adhesive 116. The conductive adhesive 116 can be solder (for example, solder paste), electroplating, or a microsphere, such as a microsphere configured for a flip-chip connection (for example, a controlled collapse chip connection (C4) connection).

[0017] The adhesive layer 122 can be capable of preventing conductive adhesive 116 from bridging between conductors, for example, to help prevent short circuits. The adhesive layer 122 can be solder resist (for example, solder mask), electrically conductive glue resist, silica-containing capillary backing, or another type of insulator capable of preventing bridging between conductors. The adhesive layer 122 can be placed over the dielectric layer 108 and then selectively removed to expose, at least partially, circuit elements 110 or electrically conductive pads 332 or 224; or the adhesive layer 122 can be selectively placed over the dielectric layer 108 so that the electrically conductive elements, such as circuit elements 110, are not completely covered by the adhesive layer 122.The adhesive layer 122 can be applied to or near the edge of the chip 114 and guided under the chip 114, for example by using air pressure or capillary action, for example to at least partially fill spaces between conductors under the chip 114.

[0018] Fig. Figure 2 shows an example of dimensional deviation in the placement of first or second circuit elements 110 or of high-density connecting element 104. By incorporating a high-density electrically conductive pad 224 that occupies a footprint larger than the footprint of a circuit element 110 to which it is to be coupled, some errors in the placement of the circuit elements 110, the high-density electrically conductive pads 224, the holes in which the circuit elements 110 are formed, or the placement of the high-density connecting element 104 can be tolerated.

[0019] The high-density connecting element 104 can electrically couple more than two chips 114 simultaneously, such as a CPU chip coupled to one or more of a chip, logic, graphics, another CPU chip or other type of chip.

[0020] Fig. Figure 3 shows an example of a device 300 that can contain the high-density connector 104 above the top layer of the medium 102B. In such an embodiment, the high-density connector 104 can be fixed by an adhesive layer 334, such as a solder layer. The adhesive layer 334 can attach the high-density connector 104 to an optional metal pad 336, such as a copper pad, or directly to the medium 102B. The metal pad 336 can act as a stop layer for laser ablation through the adhesive layer 334, for example, to prevent a laser from penetrating the medium 102B. Such a configuration can allow for better control of the placement or attachment of the high-density connector 104.

[0021] Fig. Figure 4 shows an example of a technique 400 for manufacturing a device that can contain a high-density connecting element 104. In Figure 402, the high-density connecting element 104 can be embedded in the medium 102. The high-density connecting element 104 can contain one or more electrically conductive elements 106. In Figure 404, a dielectric layer 108 can be arranged over the high-density connecting element 104. In Figure 406, circuit elements 110 can be electrically coupled to the high-density connecting element 104, for example, to electrically couple two circuit elements 110A-B to each other.

[0022] An example of an electronic device using one or more high-density connecting element(s) 104 is included to show an example of a use of such a device for the present disclosure. Fig.Figure 5 shows an example of an electronic device 500 that includes one or more high-density connecting elements 104. The electronic device 500 is merely an example of a device in which embodiments of the present disclosure can be used. Examples of electronic devices 500 include, but are not limited to, personal computers, tablet computers, supercomputers, servers, telecommunications switches, routers, mobile phones, personal data assistants, MP3 or other digital music players, radios, etc. In this example, the electronic device 500 comprises a data processing system that includes a system bus 502 for coupling the numerous components of the system. The system bus 502 provides communication links among the various components of the electronic device 500 and can be implemented as a single bus, as a combination of buses, or in any other suitable manner.

[0023] An electronic arrangement 510 is coupled to the system bus 502. The electronic arrangement 510 may contain a circuit or combination of circuits. In one embodiment, the electronic arrangement 510 contains a processor 512, which may be of any type. As used herein, "processor" means any type of computing circuit, for example, but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CSISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a graphics processor, a digital signal processor (DSP), a multi-core processor, or any other type of processor or processing circuit.

[0024] Other types of circuits that may be included in the 510 electronic arrangement are a user-defined circuit, an application-specific integrated circuit (ASCI), or the like, such as one or more circuits (for example, a 514 communications circuit) for use in wireless devices, such as mobile phones, pagers, personal data assistants, portable computers, radios, and similar electronic systems. The IC may perform any other type of function.

[0025] The electronic device 500 may contain an external storage device 520, which in turn may contain one or more storage elements suitable for the specific application, such as main memory 522 in the form of random access memory (RAM), one or more hard disk drives 524 and / or one or more drives capable of handling removable media 526, such as compact discs (CD), digital video discs (DVD) and the like.

[0026] The electronic device 500 may also include a display device 516, one or more loudspeakers, and a keyboard and / or control device 530, which may include a mouse, a trackball, a touchscreen, a speech recognition device, or any other device that enables a system user to input information into and receive information from the electronic device 500. Additional notes and examples

[0027] In Example 1, a device comprises a medium containing low-density interconnect routing.

[0028] In Example 2, the device from Example 1 contains a first circuit element and a second circuit element.

[0029] In Example 3, the device of at least one of Examples 1-2 includes a connecting element.

[0030] In Example 4, the connecting element from at least one of Examples 1 - 3 is embedded in the medium.

[0031] In Example 5, the connecting element of at least one of Examples 1 - 4 contains high-density substrate routing.

[0032] In Example 6, the connecting element of at least one of Examples 1 - 5 contains a plurality of electrically conductive elements.

[0033] In Example 7, an electrically conductive element of the plurality of electrically conductive elements from at least one of Examples 1 - 6 is electrically coupled to the first circuit element and the second circuit element.

[0034] In Example 8, the device of at least one of Examples 1 - 7 includes a dielectric layer, the dielectric layer above the interconnect chip, wherein the dielectric layer contains the first and second circuit elements passing through it.

[0035] In Example 9, the medium of at least one of Examples 1 - 8 is a substrate.

[0036] In example 10, the medium of at least one of examples 1 - 9 is a semiconductor (e.g. silicon) substrate.

[0037] In Example 11, the connecting element of at least one of Examples 1 - 10 is a connecting chip.

[0038] In Example 12, the device of at least one of Examples 1 - 11 contains a first chip.

[0039] In Example 13, the first chip of at least one of Examples 1 - 12 is electrically coupled to the first circuit element.

[0040] In Example 14, the first chip from at least one of Examples 1-13 is positioned above the medium.

[0041] In Example 15, the device of at least one of Examples 1-14 contains a second chip.

[0042] In example 16, the second chip from at least one of examples 1-15 is electrically coupled to the second circuit element.

[0043] In Example 17, the second chip from at least one of Examples 1-16 is positioned above the medium.

[0044] In Example 18, the first chip of at least one of Examples 1 - 17 is a logic chip.

[0045] In Example 19, the second chip of at least one of Examples 1-18 is a memory chip.

[0046] In Example 20, the first circuit element of at least one of Examples 1 - 19 is a first electrically conductive contact hole.

[0047] In Example 21, the second circuit element of at least one of Examples 1 - 20 is a second electrically conductive contact hole.

[0048] In Example 22, the first electrically conductive contact hole of at least one of Examples 1 - 21 is electrically coupled to a first pad (connection surface).

[0049] In Example 23, the first pad of at least one of Examples 1 - 22 is on / at or at least partially on a top side of the interconnect chip.

[0050] In Example 24, the first pad of at least one of Examples 1 - 23 is arranged between (1) the first electrically conductive contact hole and (2) a first end of the electrically conductive element.

[0051] In Example 25, the second circuit element of at least one of Examples 1 - 24 is electrically coupled to a second pad.

[0052] In example 26, the second pad of at least one of examples 1 - 25 is on / at or at least partially on the top of the interconnect chip.

[0053] In Example 27, the second pad of at least one of Examples 1 - 26 is arranged between (1) the second electrically conductive contact hole and (2) a second end of the electrically conductive element.

[0054] In Example 28, the first pad of at least one of Examples 1 - 27 has a base area dimension of 50 micrometers.

[0055] In example 29, the first circuit element of at least one of examples 1 - 28 has a base area dimension of approximately 30 micrometers.

[0056] In Example 30, the device of at least one of Examples 1-29 contains adhesive.

[0057] In example 31, the adhesive is solder resist from at least one of examples 1-30.

[0058] In Example 32, the adhesive from at least one of Examples 1 - 31 is located above the dielectric layer.

[0059] In Example 33, the adhesive from at least one of Examples 1-32 does not completely cover the first and second circuit elements.

[0060] In Example 34, the device of at least one of Examples 1 - 33 can be arranged in a package (housing).

[0061] In Example 35, the first chip of at least one of Examples 1 - 34 is electrically coupled to the second chip through the first electrically conductive contact hole and the second electrically conductive contact hole.

[0062] In example 36, the second pad of at least one of examples 1 - 35 has a base area dimension of 50 micrometers.

[0063] In example 37, the second circuit element of at least one of examples 1 - 36 contains a base area with a dimension of approximately 30 micrometers.

[0064] In Example 38, the connecting element of at least one of Examples 1 - 37 is a silicon interconnect chip.

[0065] Example 39 includes a method of embedding a high-density connecting element 104 in a medium 102.

[0066] In Example 40, the method of at least one of Examples 1 - 39 includes an electrical coupling of first and second circuit elements 110 with an electrically conductive element 106 of the connecting element.

[0067] In Example 41, the method of at least one of Examples 1 - 40 includes arranging a dielectric layer 108 over the connecting element.

[0068] In Example 42, the method of at least one of Examples 1 - 41 includes arranging a first chip 114A above the medium.

[0069] In Example 43, the method of at least one of Examples 1 - 42 includes an electrical coupling of the first chip with the first circuit element.

[0070] In Example 44, the method of at least one of Examples 1 - 43 includes arranging a second chip 114B above the medium.

[0071] In Example 45, the method of at least one of Examples 1 - 44 includes an electrical coupling of the second chip with the second circuit element.

[0072] In Example 46, an arrangement of the first chip above the medium of at least one of Examples 1 - 45 involves an arrangement of a logic chip above the substrate.

[0073] In Example 47, arranging the second chip over the substrate of at least one of Examples 1 - 46 involves arranging a memory chip over the substrate.

[0074] In Example 48, an electrical coupling of the first and second circuit elements of at least one of Examples 1 - 47 includes an electrical coupling of the first and second electrically conductive contact holes with the electrically conductive element.

[0075] In Example 49, the method of at least one of Examples 1 - 48 includes arranging a first pad on / at or at least partially in a top surface of the connecting element.

[0076] In Example 50, an arrangement of the first pad from at least one of Examples 1 - 49 includes an arrangement of the first pad between (1) the first electrically conductive contact hole and (2) a first end of the electrically conductive element.

[0077] In Example 51, an electrical coupling of the first and second electrically conductive contact holes of at least one of Examples 1 - 50 includes an electrical coupling of the first electrically conductive contact hole with the first pad.

[0078] In Example 52, the method of at least one of Examples 1 - 51 includes arranging a second pad on / at or at least partially in the top of the connecting element.

[0079] In Example 53, an arrangement of the second pads includes an arrangement of the second pads between (1) the second electrically conductive contact hole and (2) a second end of the electrically conductive element.

[0080] In Example 54, an electrical coupling of the first and second electrically conductive contact holes of at least one of Examples 1 - 53 includes an electrical coupling of the second electrically conductive contact hole with the second pad.

[0081] In Example 55, an arrangement of the first pad of at least one of Examples 1 - 54 includes an arrangement of a first pad that occupies a base area dimension of approximately 50 micrometers.

[0082] In Example 56, an electrical coupling of the first and second circuit elements of at least one of Examples 1 - 5 includes an electrical coupling of a first circuit element that has a base area dimension of approximately 30 micrometers.

[0083] In Example 57, the method of at least one of Examples 1 - 56 includes the arrangement of an adhesive layer 122 over the dielectric layer.

[0084] The above description of embodiments includes references to the accompanying drawings, which form part of the description of embodiments. The drawings illustrate specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the present inventors also envision examples in which only those elements shown or described are provided. Furthermore, the present inventors also envision examples using any combination or permutation of such elements, either shown or described with reference to a particular example (or one or more aspects thereof) or with reference to other examples (or one or more aspects thereof) shown or described herein.

[0085] In this document, the terms “one (1)” are used, as is customary in patent documents, to include one (1) or more than one (1), irrespective of any other instances or uses of “at least one (1)” or “one (1) or more”. In this document, the term “or” is used to refer to a non-exclusive or, so that “A or B” includes “A but not B”, “B but not A”, and “A and B”, unless otherwise specified. Furthermore, in the following claims, the terms “containing” and “comprising” are open and non-exhaustive, respectively, meaning that a system, device, article, composition, formulation, or process containing elements in addition to those listed after such a term in a claim is considered to fall within the scope of protection of the claim without modification. Additionally, in the following claims, the terms “first”, “second”, and “third”, etc., are usedThey are used merely as identifiers and are not intended to impose any numerical requirements on their objects.

[0086] The above description is intended to be illustrative and not limiting. For example, the examples described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments may be used, for example, by a person skilled in the art after reviewing the above description. Furthermore, numerous features or devices may be grouped together in the above description of embodiments to streamline the disclosure. This should not be interpreted as implying that an unclaimed disclosed feature is essential for every claim. Instead, the inventive subject matter may consist of fewer than all the features of a particular disclosed embodiment.Thus, the following claims are hereby included in the description of embodiments, each claim being a separate embodiment in itself, and it is envisaged that such embodiments can be combined with any other in numerous combinations or permutations.

Claims

[1] A device (300) comprising: a medium (102B) with an intermediate connection (118) in an insulating layer, wherein the intermediate connection is located over a conductive line (120), the conductive line of the medium being a bus; a connecting element (104) above the medium, wherein the connecting element has electrically conductive pads (224) on it and the connecting element comprises a silicon chip, wherein the connecting element is vertically above and spaced apart from the conductive conductor of the medium; a conductive structure (112) that is spaced laterally from the connecting element, wherein the conductive structure lies vertically above the intermediate connection of the medium and is electrically connected to it; an insulator material (122) on the insulating layer of the medium, wherein the insulator material is laterally adjacent to the connecting element and the insulator material is in lateral contact with the conductive structure, wherein the insulator material is vertically above and spaced apart from the conductive conductor of the medium; a first chip (114B) above the connecting element, wherein the first chip is coupled to a first of the electrically conductive pads (224) of the connecting element and the first chip is electrically coupled to the conductive structure; and a second chip (114A) above the connecting element, wherein the second chip is coupled to a second of the electrically conductive pads (224) of the connecting element. [2] Device according to claim 1, wherein the intermediate connection (118) of the medium (102B) is located vertically above the conductive line (120) of the medium. [3] Device according to claim 1 or 2, wherein the intermediate connection (118) of the medium (102B) is coupled to the conductive line (120) of the medium. [4] Device according to one of claims 1 to 3, further comprising a metal pad (332) between the conductive structure (112) and the intermediate connection (118) of the medium (102B). [5] Device according to one of claims 1 to 4, further comprising an adhesive layer (334) between the connecting element (104) and the medium (102B). [6] Device according to any one of claims 1 to 5, wherein the first chip (114B) is a CPU chip and the second chip (114A) is a memory chip. [7] Device according to any one of claims 1 to 5, wherein the first chip (114B) is a memory chip and the second chip (114A) is a CPU chip. [8] A device (300) comprising: a substrate (102B) with one or more insulating layers on it; an intermediate connection (118) in one or more insulating layers; a conductive line (120) in one or more insulating layers, wherein the intermediate connection is located above the conductive line, wherein the conductive line is a bus; a first chip (104) above the one or more insulating layers, wherein the first chip comprises silicon, wherein the first chip has a first electrically conductive pad (224) and a second electrically conductive pad (224) on it, wherein the first chip is vertically above and spaced apart from the conductive line; a conductive structure (112) spaced laterally from the first chip, wherein the conductive structure lies vertically above the intermediate connection and is electrically connected to it; an insulator material (122) on one or more insulating layers, wherein the insulator material is laterally adjacent to the first die and the insulator material is in lateral contact with the conductive structure, wherein the insulator material is vertically above the conductive conductor and spaced apart from it; a second chip (114B) above the first chip, wherein the second chip is coupled to the first electrically conductive pad of the first chip and the second chip is electrically coupled to the conductive structure; and a third chip (114A) above the first chip, wherein the third chip is coupled to the second electrically conductive pad of the first chip. [9] Device according to claim 8, wherein the intermediate connection (118) lies vertically above the conductive line and is connected to it. [10] Device according to any one of claims 8 to 9, further comprising: a metal pad (332) between the conductive structure and the intermediate connection (118); and an adhesive layer (334) between the first chip (104) and the one or more insulating layers. [11] Device according to any one of claims 8 to 10, wherein the second chip (114B) is a CPU chip and the third chip (114A) is a memory chip. [12] Device according to one of claims 8 to 10, wherein the second chip (114B) is a memory chip and the third chip (114A) is a CPU chip. [13] A method for manufacturing a device (300), the method comprising: Forming a medium (102B) with an intermediate connection (118) in an insulating layer, wherein the intermediate connection is located above a conductive line (120), the conductive line of the medium being a bus; Arranging a connecting element (104) above the medium, wherein the connecting element has electrically conductive pads (224) on it and the connecting element comprises a silicon chip, wherein the connecting element is vertically above and spaced apart from the conductive conductor of the medium; Forming a conductive structure (112) that is spaced laterally from the connecting element, wherein the conductive structure is vertically above and electrically coupled to the intermediate connection of the medium; Forming an insulator material (122) on the insulating layer of the medium, wherein the insulator material is laterally adjacent to the connecting element and the insulator material is in lateral contact with the conductive structure, wherein the insulator material is vertically above and spaced apart from the conductive conductor of the medium; Arranging a first chip (114B) over the connecting element, wherein the first chip is coupled to a first of the electrically conductive pads of the connecting element and the first chip is electrically coupled to the conductive structure; and Arranging a second chip (114A) above the connecting element, wherein the second chip is coupled to a second of the electrically conductive pads of the connecting element. [14] Method according to claim 13, wherein the intermediate connection (118) of the medium (102B) lies vertically above and is connected to the conductive line (120) of the medium. [15] Method according to claim 13 or 14, further comprising forming a metal pad (332) between the conductive structure and the intermediate connection (118) of the medium (102B). [16] Method according to any one of claims 13 to 15, further comprising forming an adhesive layer (334) between the connecting element (104) and the medium (102B). [17] Method according to any one of claims 13 to 16, wherein the first chip (114B) is a CPU chip and the second chip (114A) is a memory chip. [18] Method according to any one of claims 13 to 16, wherein the first chip (114B) is a memory chip and the second chip (114A) is a CPU chip.

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