Converter circuit and method for converting an input voltage into an output voltage

Abstract

Converter circuit (100) comprising the following: a switching circuit (101) designed to to provide an output voltage (106) to a load (1405); a control circuit (102) comprising an analog control component (103) and a digital control component (104); a noise generator (105) designed to generate white noise (107); wherein the noise generator (105) is designed to supply the generated white noise (107) to the digital control component (104) of the control circuit (102); and wherein the control circuit (102) is designed to control the switching circuit (101) based on the white noise (107); wherein the noise generator (105) comprises a sigma-delta converter (603, 607), and wherein the noise generator (105) is designed to generate the white noise (107) using a quantization noise of the sigma-delta converter (603, 607).

Description

[0001] Various embodiments generally relate to converter circuits and methods for converting an input voltage into an output voltage.

[0002] System power supplies, such as switched-mode power supplies (SMPS), can be implemented as feedback loops that regulate voltage and / or current to an external load. Control loops are typically designed conservatively, i.e., to achieve a high degree of stability. For example, closed-loop control and stability spans are supported, consistent with expected operating condition ranges and tolerances for parameters of load power stages (e.g., inductors and / or capacitors of a power stage in an SMPS).

[0003] Shirazi, Mariko, et al. “Integration of frequency response measurement capabilities in digital controllers for DC-DC converters.” IEEE Transactions on Power Electronics 23.5 (2008): 2524-2535 describes the integration of fully automatic frequency response measurement capabilities in digital PWM controllers. Johansson, Bengt, and Matz Lenells. “Possibilities of obtaining smallsignal models of DC-to-DC power converters by means of system identification.” INTELEC. Twenty-Second International Telecommunications Energy Conference (Cat. No. 00CH37131). IEEE, 2000, describes system identification methods for a forward DC / DC power converter. US 2006 / 0276915A1 describes an adaptive control system. Namdar, A., and B.H. Leung. “Quantisation noise of a 1-bit double-loop sigma-delta modulator.” Proceedings of IEEE International Symposium on Circuits and Systems-ISCAS'94. Vol. 6. IEEE, 1994 describes the quantization noise of a one-bit double-loop sigma-delta modulator. Ksentini, N., et al. “Modeling Of Quantization Noise In Switched-current Sigma-delta Modulator Using VHDL-AMS.” Proceedings of the International Conference Mixed Design of Integrated Circuits and Systems, 2006. MIXDES 2006. IEEE, 2006 describes a method for behavioral modeling of a white noise source. Koski, Timo. “Statistics of the binary quantizer error in single-loop sigma-delta modulation with white gaussian input.” IEEE transactions on information theory 41.4 (2006): 931-943, describes quantization errors in single-loop sigma-delta modulation.

[0004] However, non-idealities of components outside of an SPMS can lead to performance reduction or stability losses of the closed control loop if there are significant changes in operating points that are associated with a reduction in the quality of the components.

[0005] The problem is solved by independent claims 1 and 17. Embodiments of the invention are described in the respective dependent claims.

[0006] A converter circuit is described which comprises: a switching circuit designed to provide an output voltage, a control circuit comprising an analog control component and a digital control component, and a noise generator designed to generate white noise, wherein the noise generator is designed to feed the generated white noise to the digital control component of the control circuit, wherein the control circuit is designed to regulate the switching circuit based on the white noise, wherein the noise generator comprises a sigma-delta converter, and wherein the noise generator is designed to generate the white noise using quantization noise from the sigma-delta converter.

[0007] According to various embodiments, the control circuit is designed to control the switching circuit based on the white noise in order to determine at least one property of at least one of the following: the load or the converter circuit.

[0008] The control circuit can further be designed to determine one or more elements from a group consisting of the following: an inductance of an inductor; a capacitor's capacitance; an equivalent series resistance of a capacitor; and an electrical property of the load.

[0009] According to one embodiment, the control circuit is designed to control the switching circuit to provide the output voltage based on a duty cycle; and the control circuit is designed to control the switching circuit based on white noise by adding the generated white noise to the duty cycle.

[0010] The control circuit includes, for example, an analog-to-digital converter designed to take a measurement of the output voltage and provide a digital value indicating the taken measurement of the output voltage.

[0011] For example, the analog-to-digital converter is further designed to compare the recorded output voltage measurement with a reference voltage and generate a deviation signal that represents the difference between the recorded output voltage measurement and the reference voltage. The deviation signal can, for example, be a digital value that specifies the difference between the recorded output voltage measurement and the reference voltage.

[0012] The control circuit is designed, for example, to add the generated white noise to the deviation signal.

[0013] The control circuit can be designed to increase the reference voltage sequentially.

[0014] According to one embodiment, the control circuit further includes a PID (proportional-integral-derivative) controller designed to receive the deviation signal and generate a PID output based on the received deviation signal.

[0015] The control circuit can also be designed to add the generated white noise to the PID output.

[0016] According to one embodiment, the control circuit further comprises a pulse width modulation controller designed to receive the PID output and generate a pulse width modulated control signal designed to control a power stage to provide the output voltage to the load.

[0017] The control circuit can, for example, be designed to add the generated white noise to the pulse-width modulated control signal.

[0018] According to one embodiment, the noise generator is designed to generate the white noise using a sigma-delta converter.

[0019] According to one embodiment, the noise generator is further designed to reduce the resolution of the sigma-delta converter in order to increase the amplitude of the generated white noise.

[0020] The sigma-delta converter can contain more than one feedback loop. For example, at least one zero of the sigma-delta converter is located near the resonant frequency of the load.

[0021] According to one embodiment, the control circuit further comprises an analog-to-digital (AD) converter designed to acquire a measured value of an output voltage at the load, to compare the acquired measured value of the output voltage with a reference voltage, and to generate a deviation signal representing a difference between the acquired measured value of the output voltage and the reference voltage, and the control circuit is designed to process the deviation signal to determine one or more of the following: the cutoff frequency of the control circuit or an equivalent series resistance of a capacitor.

[0022] The control circuit can also be designed to process the deviation signal in order to determine a spectral power density.

[0023] According to one embodiment, the control circuit is further designed to determine one or more of the following based on the determined spectral power density: a loop cutoff frequency of the control circuit or an equivalent series resistance of a capacitor.

[0024] According to one embodiment, the control circuit is further designed to adapt at least one coefficient of a PID controller designed to receive the deviation signal and generate a PID output based on one or more of the following: the determined loop cutoff frequency of the control circuit or the determined equivalent series resistance of a capacitor.

[0025] Furthermore, a method for converting an input voltage into an output voltage according to the converter circuit described above is provided.

[0026] In the drawings, the same reference symbols consistently denote the same parts across different views. The drawings are not necessarily to scale, as the focus is generally on illustrating the fundamentals of the invention. The following description details various embodiments of the invention with reference to the following drawings: Fig. Figure 1 shows a converter circuit according to one embodiment. Fig. Figure 2 shows a flowchart illustrating a procedure for converting an input voltage into an output voltage. Fig. Figure 3 is a block diagram showing an example of a switched-mode power supply unit (SPMS). Fig. Figure 4 is a block diagram showing another example of an SPMS according to one embodiment. Fig. Figure 5 shows an example of an addition circuit according to one embodiment. Fig. Figure 6 illustrates various examples of arrangements for adding white noise. Fig. Figure 7 shows a voltage curve of the reference voltage over time in an embodiment in which the reference voltage is increased stepwise. Fig. Figure 8 shows a state diagram for an SPMS according to one embodiment. Fig. Figure 9 is a block diagram showing an example of an SPMS that includes a state machine according to one embodiment. Fig. Figure 10 shows results for one embodiment in an exemplary operating scenario. Fig. Figure 11A illustrates the steady state taking into account ΔΣ and DPWM with the same resolution. Fig. Figure 11B illustrates the case where the noise source is a ΔΣ modulator in the loop. Fig. Figure 12 shows the PSD (power spectral density) results taking into account a ΔΣ noise source in the loop. Fig. Figure 13 illustrates the result of modifying a third-order NTF (noise transfer function) to add an in-band zero near the resonant frequency. Fig. Figure 14 shows a switched-mode power supply (SMPS) converter in a step-down converter configuration. Fig. 15A shows a control loop. Fig. Figure 15B shows a signal curve of the output signal of the control loop. Fig. 15A. Fig. Figure 15C shows a signal curve of the manipulated variable of the control loop. Fig. 15A. Fig. Figure 15D shows a Nyquist diagram for the control loop from Fig. 15A. Fig. Figure 16 shows a curve diagram illustrating the amplitude and phase of a controlled system as a function of frequency.

[0027] The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments in which the invention can be implemented.

[0028] The term "exemplary" is used here to mean "serving as an example, embodiment, or illustration." Each embodiment or design described here as "exemplary" is not necessarily to be interpreted as being preferable or advantageous over other embodiments or designs.

[0029] The word "over," used in reference to a deposited material formed "over" a side or surface, may herein be used to mean that the deposited material is formed "directly on," e.g., in direct contact with, said side or surface. The word "over," used in reference to a deposited material formed "over" a side or surface, may herein be used to mean that the deposited material is formed "indirectly on" said side or surface, with one or more additional layers arranged between said side or surface and the deposited material.

[0030] According to one embodiment, a converter circuit with a control loop, e.g., a SPMS (switching-mode power supply), is provided, which includes a white noise generator that excites the control loop over a wide frequency range. Information about external components, e.g., an output network, can be derived from the control loop's response to the excitation, which in turn can be used to configure the control loop, e.g., to adjust controller parameters.

[0031] The following will refer to Fig. 1 An example of a converter circuit 100, consistent with the techniques described herein, is described.

[0032] Fig. Figure 1 shows a converter circuit 100 according to one embodiment.

[0033] The converter circuit 100 contains a switching circuit 101 designed to provide an output voltage 106 and a control circuit 102 containing an analog control component 103 and a digital control component 104.

[0034] The converter circuit 100 further includes a noise generator 105, which is designed to generate white noise 107, wherein the noise generator is designed to supply the generated white noise to the digital control component 104 of the control circuit 102, and the control circuit 102 is designed to control the switching circuit 101 on the basis of the white noise 107.

[0035] The converter circuit is designed, for example, as a DC voltage converter circuit, for example as a switched-mode power supply circuit.

[0036] In other words, according to various embodiments, white noise can be introduced into a control loop to excite the system at different frequencies. Based on the results of these excitations, parameters such as the ESR (equivalent series resistance) and the LC resonant frequency of an output network can be determined.

[0037] White noise, for example, is noise provided by a random variable whose distribution is non-zero only over an interval equal to the quantization level. White noise can also be understood as a random signal with a planar (constant) spectral power density.

[0038] According to various embodiments, the switching circuit contains at least one switching transistor.

[0039] For example, the at least one switching transistor contains at least one switching transistor.

[0040] The at least one power switching transistor can, for example, contain at least one of the following: a field-effect transistor or a bipolar transistor with an insulated gate electrode.

[0041] According to various embodiments, the control circuit is designed to control the switching circuit based on the white noise in order to determine at least one property of at least one of the following: the load or the converter circuit. In other words, a property of the load (such as an inductance, a capacitance, and / or an equivalent series resistance) can be determined, for example, based on the response of the converter circuit to the white noise, i.e., the behavior of the converter circuit in response to the white noise.

[0042] The control circuit can further be designed to determine one or more elements from a group consisting of the following: an inductance of an inductor; a capacitor's capacitance; an equivalent series resistance of a capacitor; or an electrical property of the load.

[0043] According to one embodiment, the control circuit is designed to regulate the switching circuit to provide the output voltage based on a duty cycle, and the control circuit is designed to regulate the switching circuit based on white noise by adding the generated white noise to the duty cycle. In other words, the white noise is added, for example, to a pulse-width modulation signal, on the basis of which the converter circuit generates the output voltage according to pulse-width modulation.

[0044] The control circuit includes, for example, an analog-to-digital converter designed to take a measurement of the output voltage and provide a digital value indicating the taken measurement of the output voltage.

[0045] For example, the analog-to-digital converter is further designed to compare the recorded output voltage measurement with a reference voltage and generate a deviation signal that represents the difference between the recorded output voltage measurement and the reference voltage. The deviation signal is, for example, a digital value that specifies the difference between the recorded output voltage measurement and the reference voltage.

[0046] The control circuit is designed, for example, to add the generated white noise to the deviation signal. In other words, a digital value of the white noise is added to a digital value representing the difference between the measured output voltage and the reference voltage.

[0047] The control circuit can be designed to increase the reference voltage sequentially. For example, the reference voltage can be increased stepwise from an initial value (e.g., zero) to a setpoint. This can be carried out, for example, during an initial phase (e.g., a start-up phase).

[0048] According to one embodiment, the control circuit further includes a PID controller designed to receive the deviation signal and generate a PID output based on the received deviation signal.

[0049] The control circuit can also be designed to add the generated white noise to the PID output.

[0050] According to one embodiment, the control circuit further comprises a pulse-width modulation (PWM) controller designed to receive the PID output and generate a PWM control signal designed to control a power stage to provide the output voltage to the load. In other words, for example, a signal is determined by the PWM controller (e.g., by a digital PWM device) that specifies a pulse width for PWM modulation, and this signal is fed to a power stage that generates the output voltage according to the PWM signal.

[0051] The control circuit can, for example, be designed to add the generated white noise to the pulse-width modulated control signal.

[0052] According to one embodiment, the noise generator is designed to generate the white noise using a sigma-delta converter.

[0053] According to one embodiment, the noise generator is further designed to reduce the resolution of the sigma-delta converter in order to increase the amplitude of the generated white noise. The resolution of the sigma-delta converter is, for example, the resolution of an output quantizer of the sigma-delta converter.

[0054] The sigma-delta converter can contain more than one feedback loop. For example, at least one zero of the sigma-delta converter is located near the resonant frequency of the load.

[0055] According to one embodiment, the control circuit further comprises an analog-to-digital (AD) converter designed to acquire a measured value of an output voltage at the load, to compare the acquired measured value of the output voltage with a reference voltage, and to generate a deviation signal representing a difference between the acquired measured value of the output voltage and the reference voltage, and the control circuit is designed to process the deviation signal to determine one or more of the following: the cutoff frequency of the control circuit or an equivalent series resistance of a capacitor.

[0056] The control circuit can also be designed to process the deviation signal in order to determine a spectral power density.

[0057] According to one embodiment, the control circuit is further designed to determine one or more of the following based on the determined spectral power density: a loop cutoff frequency of the control circuit or an equivalent series resistance of a capacitor.

[0058] According to one embodiment, the control circuit is further designed to adjust at least one coefficient of a PID controller, which is designed to receive the deviation signal and generate a PID output based on one or more of the following: the determined loop cutoff frequency of the control circuit or the determined equivalent series resistance of a capacitor. In other words, based on the result of the determination, the control circuit can adjust one or more parameters of the PID controller.

[0059] For example, converter circuit 100 executes a procedure as described in Fig. 2 is illustrated.

[0060] Fig. Figure 2 shows a flowchart of 200.

[0061] Flowchart 200 illustrates a method for converting an input voltage into an output voltage.

[0062] In 201, white noise is generated.

[0063] In 202, the generated white noise is fed to a digital control component in a control circuit.

[0064] In 203, the control circuit regulates a switching circuit based on white noise to provide the output voltage.

[0065] It should be noted that the embodiments described in the context of converter circuit 100 apply analogously to the one in Fig. The two illustrated procedures apply and vice versa.

[0066] The following sections describe embodiments in more detail. It should be noted that the various concepts described below can be used together or separately.

[0067] Fig. Figure 3 shows a 300 switching power supply (SMPS).

[0068] The SMPS 300 can be a buck converter SMPS operating in a digital control loop. It can include an analog-to-digital (AD) converter 301, which takes a reference voltage Vref and the output voltage Vout. The SMPS 300 is designed to achieve an output voltage Vout that is as close as possible to the reference voltage Vref. The ADC 301 generates a deviation signal e[n], which is the digitized difference between the reference voltage Vref and the output voltage Vout. The deviation signal e[n] is then filtered by a PID controller 302. The parameters of the PID controller are set, for example, to achieve a certain level of stability and dynamic performance for the SMPS 300. The PID module 302 generates a digital representation of the duty cycle d[n] achieved by the control loop, which is fed into a digital PWM (pulse width modulation) module 303 (DPWM module).The DPWM 303 is a digital PWM with finite resolution (e.g., lower than the resolution of the PID controller 302 and the digital mapping of the duty cycle d[n] generated by the PID controller 302). Based on a digital counter, it modulates the duty cycle d(t) of a square wave according to the time the digital counter takes to reach d[n]. The duty cycle d(t) is fed into a power stage controller 304. The power stage controller 304 connects a SW node 308 via a low-impedance path (i.e., implemented by a switch) to a supply potential Vg when d(t) is high, and to ground (gnd) when d(t) is low.

[0069] An output network contains an inductor 305, which is arranged in series after the SW node 308, and a capacitor 306 and an ESR 307, which are connected in series between a ground node 309 and the output voltage node 310 (which is formed by the terminal of the inductor not connected to the SW node 308).

[0070] According to various embodiments, white noise v(n) can be added, which excites all frequencies of the output stage (i.e., the stage containing the power stage 304 and the output network, i.e., the stage formed by the inductor 305, the capacitor 306, and the ESR 307). This is described in Fig. 4 illustrates.

[0071] Fig. Figure 4 shows an SMPS 400.

[0072] Similar to the SPMS 300, the SPMS 400 contains an A / D converter 401, a PID module 402, a DPWM module 403, a power stage 404, and an output network (output filter) containing an inductor 405, a capacitor 406, and an ESR 407, which can be arranged and designed as required with respect to Fig. 3 was explained. Additionally, the SPMS 400 includes a digital processing module 408, which receives the deviation signal e[n], and an addition circuit 409 arranged after the PID module 402, which adds white noise to the output of the PID module 402. A result of this addition, i.e., an output of the addition circuit 409, is fed to the DPWM module 403. Furthermore, in this example, it is assumed that a load resistor 410 is connected between the output voltage node and the ground node, i.e., in parallel with the capacitor 406 and the ESR 407.

[0073] The addition of white noise can be achieved in various ways. The use of a second- or higher-order delta-sigma (ΔΣ) modulator in a deviation feedback configuration is described in Fig. 5 illustrates.

[0074] Fig. Figure 5 shows an addition circuit 500 according to one embodiment.

[0075] The addition circuit 500 corresponds, for example, to the addition circuit 409.

[0076] The input signal of the addition circuit 500 is the digital duty cycle d[n], as output by the PID chip 402. The adder 501 adds to this the output of a 1-NTF chip 502. The 1-NTF chip 502 is, for example, a high-pass filter used for noise shaping.

[0077] Its input is the difference (generated by a subtractor 503) between the output of the adder 501 and the output of the addition circuit 500. The output of the addition circuit 500 is the output of the adder 501, quantized by a quantizer 504. The deviation signal qe (which specifies the difference between the output of the adder 501 and the output signal of the addition circuit 500) exhibits white noise characteristics.

[0078] Fig. Figure 6 illustrates arrangements 601 and 602 for adding white noise.

[0079] The first arrangement 601 can, for example, be used as the part of the SPMS 400 that is indicated by the dashed box 411.

[0080] Similarly, the second arrangement 602 can, for example, be used as the part of the SPMS 400 that is indicated by the dashed box 411.

[0081] In the first arrangement, a ΔΣ block 603, which can be seen as being arranged outside the control loop of the SMPS 400, feeds its output (i.e., white noise) to an addition circuit 604, which corresponds to the addition circuit 409, which is arranged between a PID block 605, corresponding to the PID block 402, and a DPWM block 606, corresponding to the DPWM block 403.

[0082] In the second arrangement 602, a ΔΣ module 607 is provided instead of the addition circuit 409. This ΔΣ module can be viewed as being positioned within the control loop chain between a PID module 608 (corresponding to the PID module 402) and a DPWM module 608 (corresponding to the DPWM module 403). In this case, the ΔΣ module 607 can also be used to increase the effective average resolution of the DPWM module 403.

[0083] According to various embodiments, a small amount of noise power is added, e.g., by the addition circuit 409, to stimulate a loop response. The loop response can primarily include information about a load of the SPMS 400, which, for example, contains the load resistor 710. In the case of a configuration where delta-sigma is located within the loop in the deviation feedback (e.g., as in the second arrangement 602), adding (feeding on) noise does not introduce any delays in the signal path. In this case, the noise can be fed on in such a way that it is sufficient to stimulate the load without causing the system to become unstable. A time analysis of the steady state shows that it is possible to achieve Vout results that are close to Vref despite the noise feed-in. Load parameters can be determined by processing the output of the ADC 401.

[0084] In a ΔΣ implementation form outside the loop (e.g., as in the first arrangement 601), the steady state of the SPMS 400, taking into account the added noise, can be described as follows: Vout=1N∗dDPWM where N is the relationship between the switching period (in which, for example, a power MOS transistor is driven) and a DPWM clock signal period Tsw = N*Tclk.

[0085] Taking into account the delta-sigma conversion mode in the loop (as in the second arrangement 602), the added noise can be amplified by lowering the resolution of a quantizer of the ΔΣ block relative to the DPWM resolution. The resolution of the quantizer of the ΔΣ block can be set via a parameter res_ΔΣ. In this case, the following can be written: Vout=dDPWM∗Vin=1N∗(dPID[n]+noise)∗Vin

[0086] Here, the "noise" parameter can be 1-NTF[n]. It should be noted that the variance of the signal e[n] and / or dpid[n] can be much larger than the variance of the ΔΣ chip's quantizer. For example, the PID signal (i.e., the output signal of the PID chip 402) is quantized by a ΔΣ quantizer that has a lower resolution than the PID signal. The least significant bit of the ΔΣ chip is quantization noise. White noise, for example, is noise given by a random variable whose distribution is non-zero only over an interval equal to the quantization level. White noise can also be understood as a random signal with a planar (constant) spectral power density.

[0087] Both the DPWM 403 and the quantizer of the ΔΣ module 603, 607 can have the same final value range V FS exhibit. The resolution of the ΔΣ quantizer can be 2 a-times lower than that of the DPWM. In this case, the expression for the noise can be determined as a function of the resolution difference: Noise=|LSBΔE−LSBDPWN|=|VFS2N−a−VFS / 2N|=|VFS∗(2a−N−2−N)|

[0088] Considering that the DPWM can mainly operate as a single-stage counter from 1 to 2^N, the expression for the noise can be given taking V into account. FS = 2^N can be simplified, because: Noise = |2a−1|

[0089] In the approach illustrated by the first arrangement 601, the noise term is simply white noise resulting from the (output) quantizer of the ΔΣ module 603, as shown in Fig. 5 is modeled. Providing a ΔΣ block outside the loop (as in the first arrangement 601) as a noise source allows the noise amplitude to be dimensioned as desired and adjusted according to the loop parameters and the DPWM resolution to ensure system stability. This can be advantageous because the added noise, as described in the embodiments above, can be true white noise rather than emulation. A PRBS sequence typically has resolution problems. Quantization noise typically comes very close to ideal white noise. As in Fig. As shown in Figure 5, the hardware required to implement a ΔΣ device in a deviation feedback configuration can be kept small on the chip area, and the same circuitry can be used in compensation phases to improve the resolution of the system in steady state.

[0090] The approach illustrated by the second arrangement 602 uses the ΔΣ in the configuration within the loop. In this case, the noise could be considered in relation to d. PID [n] lower resolution of the quantizer (see Fig. 5) - and optionally, with respect to the lower DPWM resolution - can be added. Term 2 a gives the difference between the d PID [n] resolution and the resolution of the quantizer, which is part of the ΔΣ component 607.

[0091] Extending the output of the ΔΣ component 607 to the output voltage could be expressed as: Vout=1N∗(dPID[n]−NTF(z)∗(qs)+noise)∗Vin= =1N∗(dPID[n]−NTF(z)∗(dPID[n−1]−dΔΣ[n−1])±|2a−1|)∗Vin

[0092] During the loop compensation phase, the noise term (|2 a- 1|) zero, because the DPWM and ΔΣ devices have the same resolution in this embodiment. Under this condition, the averaged resolution of the output voltage by the ΔΣ device can be improved by a process consisting of dithering, oversampling, and filtering. The filtering can be performed by the output filter, which forms a buck converter power output. The dithering can be considered the noise feedforward; during an identification process, this component can be incremented, reducing the ΔΣ resolution relative to the resolution of the DPWM.

[0093] For example, if noise is to be introduced, but the amplitude of the output voltage in the steady state is to be limited, a control / processing circuit (e.g., the state machine 910 or the processing module 908, as described below with reference to Fig. (as described in 9) the parameter a may be set to “1”, which results in the following: Vout=1N∗(dPID[n]−NTF(z)∗(dPID[n−1]−dΔΣ[n−1])±)∗Vin

[0094] The approach using a ΔΣ block in the loop also allows the noise power to be influenced by considering different NTF(z) configurations. A noise-shaping filter of the ΔΣ block (e.g., corresponding to the 1-NTF block 502) can have different orders (starting with the second) and could also include one or more in-band zeros. The in-band zero can be used to focus the noise feedforward. Focusing the noise feedforward aids during parameter identification, especially during ESR determination. The noise-shaping filter, for example, has a polynomial expression that defines the order of the ΔΣ block. For example, a 3rd-order NTF can be considered, which may include one or two in-band zeros. A 3rd-order noise-shaping filter with one in-band zero, for example, is as follows: NFT(z)=(1−z−1)∗(1−K1z−1+z−2)

[0095] Taking into account f SW K1 is calculated using the switching frequency and f0 as the output resonant frequency: K1=2∗cos(2π∗A∗f0fSW)

[0096] To illustrate this, a two-stage approach can be used: First, f0 is determined (e.g., by a control / processing circuit), and then the ESR, and the determined ESR is compensated in the control loop (e.g., by the control / processing circuit).

[0097] With K1 = 1, the NTF becomes a normal third-order NTF without in-band zeros. In the formula for K1 above, the expression A represents a scaling factor that allows the in-band zero position to be adjusted with respect to the resonant frequency. By specifying the Nth order of ΔΣ, the number of in-band zeros could range from 0 to N / 2 if the order is even, or to (N-1) / 2 if the order is odd. For example, a fifth-order NTF could have 0, 1, or 2 in-band zeros, and a sixth-order NTF could have 0, 1, 2, or 3 in-band zeros. If zero(s) are used for ESR identification, they can be distributed across the frequency range.

[0098] In the case of, for example, three in-band zeros, one can be placed above the resonant frequency to limit the noise feedforward at that frequency, in order to then attempt to excite a specified range of frequencies where higher resolution is desired. This can be particularly useful when searching for the ESR contribution.

[0099] Parameter determination can be performed by the digital signal processing module 408. Fig. 4. After recording the ADC output deviation e[n], the digital signal processor 408 can perform algorithms to process the time-recorded output deviation e[n], including windowing, filtering and / or averaging, correlation (to reduce the noise contribution), FFT, and power spectral density (PSD) analysis. Any other control / processing circuit can perform this processing instead of the digital signal processor 408.

[0100] Before any processing algorithms, the digital signal processing module 408 performs downsampling and / or windowing in the time domain of the recorded (time recording) vector e[n].

[0101] For example, processing algorithms used in the time domain by the 408 digital signal processing module may include the following:

[0102] - Downsampling. By recording a sample of all N, the maximum frequency considered is reduced by a factor of 1 / N.

[0103] - Windowing. For example, a Blackman window w(n) is considered: w(n)=a0−a1 cos(2πnN−1)+a2 cos(4πnN−1) a0=1−α2;a1=12;a2=α2

[0104] The windowed result vector is given by: e[n]=e[n]∗wT[n] e[n] can be downsampled or not.

[0105] Time-domain windowing can be performed by the 408 digital signal processing module to analyze periodic behavior of the function over a short time interval. Frequency-domain windowing can be used by the 408 digital signal processing module as a bandpass filter process.

[0106] - Correlation. A correlation algorithm can be used by the 408 digital signal processing module for both signal cleaning (vectors in the time domain and frequency domain) and PSD analysis. Exx=∑n=1∞e(n)∗e(n+m)

[0107] The temporal recording e(n) could precede the downsampling and / or windowing. Taking into account the FFT of the autocorrelated vector, the PSD can be obtained as follows: E(k)=∑n=0KExx(n)∗e−j2nk2nwith K=0... ... ...N−1

[0108] The PSD could also be evaluated as the product of the deviation and its own complex conjugate: E(k)=∑n=0Ke(n)∗e−j2nk2nwith K=0... ... ...N−1 PSD=E(k)∗E*(K)

[0109] Before applying the FFT, the 408 digital signal processor can perform downsampling and / or windowing and / or autocorrelation of the time-domain recording. Windowing and autocorrelation can be applied by the 408 digital signal processor to both downsampled and normal data recordings. Each of these cases can be analyzed in the frequency domain by the 408 digital signal processor using FFT. Each vector in the frequency domain can be filtered and / or averaged by the 408 digital signal processor.

[0110] The processing algorithms used by the 408 digital signal processing module in the frequency domain can include the following: - Filtering. To clean up a vector (e.g., the vector e[n] or the result of processing this vector), the 408 digital signal processor can filter it in the frequency domain using a low-pass (TP), high-pass (HP), or band-pass (BP) filter. The vector being filtered might be, for example, the result of an FFT or PSD analysis. In either case, averaging by the 408 digital signal processor can be performed before or after filtering. Before processing the vector, it can be downsampled. During ESR identification, the filtering processing can be utilized by setting the cutoff frequency according to the previously estimated resonant frequency. Vectors undergoing averaging are all frequency-domain data recordings that can be averaged by the 408 digital signal processor before processing.

[0111] HP filter: For example, a first-order high-pass filter from the 408 digital signal processing module can be used as follows: y(k)=A∗[x(k)−x(k−1)+y(k−1)] with k=1... ... ...n−1 TP filter: For example, a first-order low-pass filter from the 408 digital signal processing module can be used as follows: y(k)=A∗[(τ / Ts)−x(k)+y(k−1)] with k=1... ... ...n−1 BP filter: Bandpass filtering can be achieved by mixing HP and TP filter structures.

[0112] The Ts factor is related to the downsampling factor. The data is processed at the switching frequency f. SW of the system (e.g., the SPMS 400). If the data recording has been downsampled by a factor N, Ts equals N / f. SW Otherwise, it is equal to 1 / f SW The factor τ is related to the cutoff frequency chosen for the processing filter; it is equal to 1 / (ω). c ), where ω cThe cutoff frequency is... For both filters under consideration, the term A is: A=(τ / Ts) / (1+τ / Ts)

[0113] - Averaging. Considering data recordings in the frequency domain, a process of averaging a single vector (e.g., e[n] or a processed version of e[n]) or two or more vectors can be used. For example, a vector in the frequency domain can be averaged. This can be done, for example, before filtering.

[0114] The above with reference to Fig. The approach described in section 4 addresses identification by noise addition. The control loop resolution is reduced to stimulate the load across many frequencies. The loop response incorporates the load frequency information, and the processing of the time-based recording of the load parameters can be determined through signal processing. The system (i.e., the SMPS 400) does not need to be put into a special state associated with identification. In both cases, the digital loop can maintain the same configuration as during normal operation. In one embodiment, for example, only the control loop resolution needs to be changed to stimulate the load; other components and parameters can remain unchanged.

[0115] Furthermore, according to the approaches mentioned above, the system must not be brought close to unstable states. The PID controller 402 is also used during the identification phase. During this phase, the PID coefficient could be attenuated (e.g., by a control / processing circuit). After parameter identification, it can be adjusted to achieve a desired control state.

[0116] It should be noted that resolution problems in a non-parametric identification approach, such as one based on PRBS (any approach that attempts to determine every impulse response of the system is considered non-parametric), typically do not allow the identification of the possible presence of the zero introduced by the ESR.

[0117] According to the approaches described above, the ESR can be identified, in particular, by working with PSD analysis and processing the deviation vector e[n] (which could be downsampled and / or windowed) through autocorrelation. The resulting vector typically shows a second peak (where the first peak corresponds to the resonance frequency).

[0118] Averaging and / or filtering time-domain data recordings helps clean the signal for parameter determination. The results of this further processing can be useful during ESR identification. Beyond the resonant frequency, the system's gain can rapidly decrease in frequency, making the ESR contribution very difficult to determine. In this case, an NTF with in-band zeros (which concentrate noise in the frequency range of interest) can be used, combined with numerical filtering and / or averaging to clean the signal in the frequency domain. The resolution of the data processing can be improved from the time domain by considering downsampling, windowing, and / or autocorrelation processing algorithms.

[0119] Even when directly processing the data recording e[n] with an FFT result, a high ESR value could be identified by the digital signal processing module 408. The resolution of the results could be improved by considering the averaging and / or filtering of frequency vectors.

[0120] Another consideration regarding ESR determination is that, once the resonant frequency is known, the ΔΣ configuration can be adjusted by a control / processing circuit (e.g., the 408 digital signal processor) to filter out the resonant frequency ω0 and highlight the ESR frequency range. The NTF of the ΔΣ module can be adjusted by a control / processing circuit that adds one or more zeros approximately at ω0. In this case, a two-stage approach can be used. First, the ΔΣ module without zeros at ω0 is used to determine ω0, as previously described. Then, in a second stage, the ΔΣ module is modified by adding zeros approximately at ω0.

[0121] Another stage that can be added, or used instead of the second part, to determine the influence of ESR is the analysis of spectral power, which increases with bandwidth.

[0122] For a signal x[n], the spectral power is defined as: E(ω)=X(ω)⋅X∗(ω).

[0123] This means that by calculating the spectral power of e[n] for a given system using signal processing, it is possible to evaluate and calculate the bandwidth. If the ESR zero frequency is close to ω0, the bandwidth increases. This can be determined from the spectral power, and this information can be used to adjust the system compensation coefficient.

[0124] Another stage that can be added, or that can be used by the 408 digital signal processing module, to determine ω0 is as follows: During system startup, Vout must reach the final set voltage. If the reference voltage is increased incrementally, the response of the output voltage Vout will include the frequency information of the output filter.

[0125] Fig. Figure 7 shows a voltage curve image of 700.

[0126] The voltage curve diagram 700 illustrates the output voltage over time in a first curve 701 as the reference voltage (shown in the second curve 702) increases in several stages 703. In the voltage curve diagram 700, the voltage increases from bottom to top along a voltage axis 704, and time runs from left to right along a time axis 705.

[0127] The resulting output voltage Vout can be processed, e.g., by the 408 digital signal processing module (e.g., similarly to how it was described above for excitation with white noise), and ω0 can be identified. In this case, the determination can be based on the system's step response. The step response is closely related to the system's impulse response: By differentiating the step response (Y(z)), the impulse response (G(z)) can be obtained. G(z)=((z−1) / z)∗Y(z)

[0128] For example, this approach is only used during startup. It can be used, for instance, by a control / processing circuit as an initial estimate, and finally, the other approaches, as described above, can be used to also determine the ESR and track system changes during system operation (i.e., in the case of low temperatures, the ESR increases by 1-2 orders of magnitude for some capacitor types).

[0129] According to one embodiment, one or more of the following are carried out: 1. White noise is added by adding it to the d[n] value. 2. The noise is applied during normal operation and with the control loop closed, without changing the frequency response of the closed control loop system. 3. ΔΣ is used to generate noise according to the first arrangement 601 or the second arrangement 602. 4. According to the second arrangement, the ΔΣ resolution is reduced to increase the noise amplitude. 5. ΔΣ of order >2 is used to place the zeros approximately at ω0 and to highlight the frequency around the ESR zero frequency. 6. The above (points 1 to 5) is combined, and by applying signal processing to the stored e[n] vector, ω0 and / or the ESR zero frequency are determined, and this information is used to adjust the PID coefficient. 7. The above (points 1 to 5) is combined, and by applying signal processing to the stored e[n] vector, the spectral power density is calculated, and the loop cutoff frequency and the ESR zero-point effect are estimated. 8. During startup, the reference voltage is increased stepwise, and the e[n] step response is analyzed. 9. Point 8 is combined with all or some of points 1 to 4.

[0130] According to various embodiments, approaches are used that can be considered to primarily incorporate a type of parametric identification process, as they focus on determining load characteristics such as resonant frequency, ESR, and bandwidth. When a low noise power is applied, the system results are far from instability, and load frequencies are more stimulated. The output filter response could be determined from the deviation influenced by the digital control loop: the added noise could be considered close to ideal white noise.

[0131] The DPWM could be considered a truncation function. In the absence of a ΔΣ (least significant bit) component, this noise can be added within the control loop. This type of noise can be related to LSB truncation. It can be very close to the resonant frequency and causes a ring oscillation whose amplitude is usually greater the closer its frequency results are to the resonant frequency. In a digital control loop, the ΔΣ component (with the same resolution as the DPWM) typically oversamples this deviation because the ring oscillation frequency is necessarily lower than the frequency at which the deviation is processed (which is the switching frequency). This process typically causes the LSB (least significant bit) truncation to not always be the same on average. Thus, the ring oscillation has a different frequency component.

[0132] When a noise source is introduced, the LSB truncation becomes random, stimulating a wide range of load frequencies, which become visible in the ADC output of the 401 ADC. By definition, white noise encompasses all frequencies and is therefore capable of stimulating the load. The ADC output is simply a digital conversion of the output filter scaled around the reference voltage Vref. e[n]=Vout[n]−Vref[n]→temporal data recording

[0133] The applied noise power can be selected so that it is not too high, thus preventing the system from entering unusual states that deviate significantly from normal behavior and approach the unstable state of the loop. The loop configuration and the basic behavior remain similar to those of a normal control delay. The added noise increases the output noise.

[0134] The approaches described above do not break the loop by adding any delay to the signal path. The same hardware can be used that could be used to improve the average resolution while operating in a steady state.

[0135] In the digital loop, which is used according to an embodiment as described with reference to Fig. As described in section 6, the added noise is represented as a summing node. This noise node source is a ΔΣ component (where the two configurations of the first arrangement 601 and the second arrangement 602 are possible), which could also be used after the identification process to improve the temporal resolution of the loop.

[0136] When working with a ΔΣ model in the loop (as illustrated by the second arrangement 602), the same loop can be used for both identification and fine-tuning. To use the ΔΣ in the loop as a noise source, the resolution can be adjusted: the resolution of the ΔΣ quantizer can be reduced compared to that of the DPWM. This further LSB truncation allows for the excitation of the range of stimulated frequencies.

[0137] Implementations can be viewed as also focusing on identifying non-idealities that could affect the system's stability. The most important non-ideal phenomenon is the equivalent series resistance (ESR), which adds a zero to the closed-loop transfer function. This problem of an additional zero is related to its position: the system's frequency response could change significantly if it turns out to be close to or even within the system's bandwidth. The ESR can be easily determined via the PSD (often there are two peaks in the PSD, the higher one around the resonant frequency and the second one related to the introduced zero).

[0138] In a two-stage approach, the noise feed can first be focused on the frequencies before and secondly on the frequencies after the resonant frequency. The applied noise can be controlled by manipulating the noise transfer function (NTF): The noise transfer function can simply be a high-pass filter of the noise (noise shaping), so this can be done based on both the order and the structure of the NTF. Based on the order of the NTF means based on the trade-off between the noise power applied at low and the noise power applied at mid-range frequencies. Based on the NTF structure means that it is possible to add some in-band zeros to avoid the noise feed at specific frequencies (increasing the number of zeros also increases the order of the NTF).

[0139] In PSD analysis, there is a peak that is related to the resonance frequency. For example, if a third-order NTF is modified by adding a zero very close to the resonance frequencies, it can excite the relative peak due to the ESR zero effect. A two-stage approach can be used because the position of the second zero is related to the resonance frequency, which usually makes the main contribution, and because it can mask the ESR contribution.

[0140] Parameter determination can be performed using signal processing algorithms on the recorded ADC deviation output, which is simply a digitized expression of the scaled output voltage Vout. Depending on the specific implementation, the signal processing process is primarily related to PSD analysis. Prior to the FFT, autocorrelation of the time-based recording can be performed. This autocorrelation could occur before downsampling and / or windowing to reduce the high-frequency content and minimize signal processing hardware requirements. To obtain lower-noise results after the FFT, the resulting signal can be cleaned by averaging and / or filtering.Parameter determination can be simple and consist of just searching for the absolute and / or relative maxima in the processed data: Normally, taking into account PSD and / or FFT (which could be averaged and / or filtered in the frequency domain, windowed and / or downsampled in the time domain), the resonant frequency can be determined as the absolute maximum and - if available - the position of the ESR frequency as a second peak.

[0141] After determining the parameters, the PID parameters can be adjusted to obtain a well-controlled system that matches the specifications for the closed-loop control system (bandwidth and phase margin).

[0142] Approaches based on noise feedforward could be combined with a startup identification method. The reference voltage (Vref) should be the voltage level required at the SMPS output. If a step-by-step reference voltage is considered, the digitized system step response can be recorded by capturing the ADC output. The step response is mathematically related to the system's impulse response. By processing the ADC output as described above, the resonant frequency (maximum of the FFT and / or PSD) and finally the ESR (as a second peak) can be determined. This approach also does not modify the digital control loop, and it could be considered to operate during normal operation: A step-by-step Vref is realistic behavior during the system's soft startup.

[0143] The approach, according to various embodiments, is described in Fig. 8 illustrates.

[0144] Fig. Figure 8 shows a state diagram 800 of a system, e.g. for an SMPS, or of a controlling state machine for an SMPS (such as the one in Fig. 9 illustrated state machine 910).

[0145] In state diagram 800, a state (or condition) IDLE 801 represents the state in which the system parameters (PID default parameters, NTF order and resolution of the ΔΣ quantizer) and the options of the identification algorithm (ΔΣ in the loop or ΔΣ outside the loop, identification process at startup by a stepwise development of the reference voltage) have settled.

[0146] In the case that the identification process is based on the presence of a ΔΣ in the loop as a noise source (as in the second arrangement 602), the signal res_ΔΣ (which indicates the resolution of the DPWM) takes on a value equal to the DPWM resolution minus one.

[0147] When the system is switched on, it transitions from the IDLE state (801) to the START-UP state (802). This is the first state in which it considers options for the algorithm: If it decides to apply the identification process during system startup (as described above, taking into account the step response resulting from the gradually developing reference voltage), the system continues with a WAIT-STEP state (803). Otherwise, the system can transition to a WAIT-SS (steady state) if it decides that the identification process should be implemented only during steady state operation.

[0148] Considering an identification process that combines steady-state and start-up analysis, the current state of the system is WAIT-STEP 803. When the reference voltage stage begins, the next state is ADC-REC-SU (SU stands for Start-Up) 805. Here, the analog-to-digital converter output (deviation signal) is recorded. At the end of the stage, the recorded data can be processed. This operation is represented by a DATA-PRO 806 state. While the system is running with the default configuration, all necessary data processing algorithms are applied by the system in this state. When the processing algorithm finishes, the first load parameter determination is available, which is performed in a PARAM-ID 807 state. In this state, the system primarily determines the absolute and relative maxima of the data recording just processed.The resonant frequency value obtained from identification during the startup process can be trusted in this state and is used as a basis. The ESR value could be determined during the initial setup of the control parameters (PID), but should not be considered.

[0149] After parameter determination, the system enters a state PID-COMP 808. In this state, the PID parameters (Ki, Kp, Kd and Kgain) are set in accordance with both the load parameters just determined and the specifications for the closed control loop that should be achieved after a successful control process.

[0150] If it is decided that the identification process to be carried out should only be implemented during the steady state of the system, the system can enter state WAIT-SS 804 after state START-UP 802, in which it waits until the startup process is complete. When the startup is considered complete, the ADC output includes the deviation during the steady state. After state WAIT-SS 804, the system enters state ADFC-REC-SS 809, in which the deviation is recorded. In this state, different downsampled data recordings of the same length can be recorded to evaluate results averaged multiple times. When data recording is complete, the same routine as described above is performed: processing (state DATA-PRO 806), load parameter determination (state PARAM-ID 807), and PID control (state PID-COMP 808).

[0151] The above describes the first identification loop, which considers either identification during startup or identification in a steady state.

[0152] In summary, this first identification loop, in the case of identification during startup, consists of the following states: IDLE → START-UP → WAIT-STEP → ADC-REC-SU → DATA-PRO → PARAM-ID → PID-COMP

[0153] The first identification loop in the case of identification in the steady state (then in the case of the absence of the identification process during startup) consists of these states: IDLE → START-UP → WAIT-SS → ADC-REC-SS → DATA-PRO → PARAM-ID → PID-COMP.

[0154] Each time new data is recorded, it is processed in the normal sequence of states (DATA-PRO → PARAM-ID → PID-COMP). In steady state, a state loop, which could be called a monitoring loop, can be introduced to evaluate any load quality degradation and calculate the compensated PID coefficients. This sequence could be repeated because load parameter identification is required. If no monitoring loop is needed, the PID-COMP state transitions to NORM-RUN 810 (where normal operation takes place) because no further data needs to be recorded.

[0155] The last possible transition from state PID-COMP 808 is directly to state NTF 811. Considering that the ΔΣ configuration is in the loop (meaning that the entire identification process has been completed using the ΔΣ configuration in the loop, or that the configuration switches from ΔΣ outside the loop to ΔΣ inside the loop when this part of the algorithm needs to be executed), it is possible to edit the structure of the ΔΣ-NTF to potentially extrapolate or highlight the ESR effect.In cases where ESR zeros have already been identified during previous identification runs (which are performed without any modification of the NTF structure, determined in state IDLE 801, where the system parameters are set), or where it is desired to ensure that no further in-band zeros are added, the algorithm provides the option of modifying the NTF structure. Modifying the NTF structure means changing the order by adding zeros to the noise-shaping function. Because ESR zero detection is performed by finding a relative maximum, the contribution of the absolute maximum, given by the resonant frequency, can be suppressed or reduced. It is possible to add one or more zeros to the NTF that are very close to the LC resonant frequency.In this way, the applied noise can be channeled in the frequency range higher than the LC resonant frequency. Because the zero location in the NTF noise-shaping function is related to the resonant frequency in this algorithm, a prior stage is required for LC identification. Therefore, the transition PID-COMP→ NTF→ADC-REC-SS occurs after a steady-state identification process, which allows both the determination of the resonant frequency and the isolation of the ESR zero contribution.

[0156] Thus, whenever the system is in state PID-COMP 808 during steady state, it is possible to change the NTF structure by adding in-band zeros (setting the zero_loc signal in Fig. 9) to excite the frequencies following the resonant frequency.

[0157] Fig. Figure 9 shows an SMPS 900.

[0158] Analogous to the SPMS 400, the SPMS 900 contains an analog-to-digital converter (ADC) 901, a PID module 902, a DPWM module 903, a power stage 904, an output network (output filter) containing an inductor 905, a capacitor 906, and an ESR 907, and a digital processing module 908. The SPMS 900 includes a ΔΣ module in the loop as in the second arrangement 602. With reference to Fig. The eight described states can be triggered by a state machine 910, which can receive the results from the digital processing unit 908. In this example, the reference voltage is supplied by a reference voltage source 911, which can increase the reference voltage in steps. Additionally, this example assumes that a load transistor 912 is connected between the output voltage node and the ground node.

[0159] In this example, the digital loop is dimensioned for the following parameters: - C load filter capacitance and its ESR, for example the main filter capacitance, and in parallel a small load capacitor CL = C / 1000. - L = filter inductor, ω0 = 1 / (LC) is at least 2 orders lower than 2π*f SW . - Vg input voltage of the power stage, where the power stage consists of drivers and switches. - Vref = target Vout, i.e. 3.3 V, it is the input of the AD converter. - Fck = fast digital clock signal and DPWM basic counter - DPWM is the digital PWM, it has a resolution of DPWM_res = 6 bits (counter from 1 to 2^6 = 64, it determines the f SW ) - ΔΣ, as with reference to Fig. As described in section 5, the resolution can be equal to the DPWM or it can be reduced by 1 during the identification process (DPWM_res-1). The ΔΣ resolution is tuned by the res_ΔΣ signal. Here, it is equal to DPWM_res-1 during identification and equal to DPWM_res while the full resolution is running. The zero_loc of the ΔΣ input, which may be needed during ESR identification, includes the target zero position for the NTF. The zero_loc signal is like a vector with a 4-point zero value for the ΔΣ zeros. - PID is the digital filter with the parameters Kp, Kd, ​​Ki, Kgain.

[0160] Taking these parameters into account, the resonant frequency in this example is ω0 = 2π*5 kHz and the ESR zero frequency is ω ESR= 2π*14 kHz. The following describes results that consider some signal processing procedures used to obtain a reliable identification process. The description focuses primarily on the identification process, without considering the results after the control. All results are based on the same configuration values ​​(including the PID coefficients).

[0161] Taking into account the identification process during startup, with reference to the Fig. Based on the 8 described states, the state machine 910 runs through the state sequence: IDLE → START-UP → WAIT-STEP → ADC-REC-SU → DATA-PRO → PARAM-ID → PID-COMP (Results of parameter identification are presented, for example, at the PARAM-ID stage, e.g., to a user).

[0162] Because the identification process in the steady state is carried out by adding noise, results in the time domain are also shown to demonstrate that our system is not disturbed too much.

[0163] During the START-UP 802 state, the system evolves to accept as input a stepwise reference voltage, as described in Fig. Figure 7 illustrates this point. During the development of the reference voltage, the algorithm (i.e., the state machine 910) waits for the voltage stage (in state WAIT-STEP 803) to begin recording the ADC output (state ADC-REC-SU 805). The WAIT-STEP 803 stage can be important because there may be multiple stages, and it might be decided to record the output at only one of them. Furthermore, to record every response from the system, a longer stage might be chosen, and the other stages could consequently be shorter.

[0164] In WAIT-STEP 803, state machine 910 decides to wait for the third stage to complete before activating ADC output recording. In this example, state machine 910 decides to stop recording when the fourth stage arrives. The algorithm then proceeds to data processing (state DATA-PRO 806).

[0165] Fig. Figure 10 shows PSD results taking ω into account. ESR = 0 (no in-band zeros).

[0166] As in the example in Fig. As shown in Figure 10, the resonant frequency can be determined from the start-up phase. By considering a stepwise development of Vref and, for example, determining the maximum of the PSD (or the FFT), the LC contributions of the output filter can be determined.

[0167] In this approach, the existence of the second peak for ESR determination cannot be easily obtained.

[0168] After processing results have been calculated, the state machine 910 moves the system into the parameter determination state (state PARAM-ID 1107), in which it searches for and determines absolute and / or relative maxima in order to define the correct PID parameters needed for correction (the correction is not shown here).

[0169] The identification process in the steady state involves the state machine 910 running through the following sequence of states, as described with reference to Fig. 8 is described: IDLE → START-UP → WAIT-SS → ADC-REC-SS → DATA-PRO → PARAM-ID → PID-COMP (Results can be submitted at the PARAM-ID stage)

[0170] After startup, the steady state (state WAIT-SS 804) is reached. Then the system begins to record the ADC output (state ADC-REC-SS 809).

[0171] As mentioned above, the case is evaluated in which the noise is switched on using the signal res_ΔΣ while reducing the resolution of ΔΣ in the loop.

[0172] Fig. Figure 11A illustrates the steady state, taking into account ΔΣ and DPWM with the same resolution.

[0173] Fig. Figure 11B illustrates the case where the noise source is a ΔΣ modulator in the loop (referring to the SMPS 900 from Fig. 9 with ΔΣ_res = DPWM _res-1).

[0174] Fig. 11A and Fig. Figure 11B shows the corresponding output voltage of the SMPS over time.

[0175] In Fig. Section 11B considers the case of noise applied by a 5-bit ΔΣ quantizer. Fig. 11A features both DPWM and ΔΣ 6-bit quantizer resolutions. Both in Fig. 11A as well as in Fig. Figure 11B shows the following: Because a wide range of load frequencies is excited when noise is applied, these frequencies are filtered out by an LC filter, which forms a buck converter. By analyzing the digitized deviation coming from the A / D converter, load parameters can be determined.

[0176] After recording the ADC output in steady state (in this case, only one time recording is made, but multiple recordings can be made to implement multiple averaging processing), the state machine 910 calculates the processing results in state DATA-PRO 806. When processing is complete, the state machine 910 enters state PARAM-ID 807, in which load parameters are determined by the normal search for absolute (resonance frequency) and relative maxima (ESR contribution).

[0177] Fig. Figure 12 shows PSD results in two curves, 1201 and 1202, taking into account a ΔΣ noise source in the loop. The two curves, 1201 and 1202, differ because ESR contributions are not considered in the upper curve, 1201 (there is only the absolute maximum, which relates to the resonance frequency; in the lower curve, 1202, the additional relative maximum relates to the ESR).

[0178] From the in Fig. The 12 results presented show that it is possible to evaluate ESR effects taking into account the relative maximum in the PSD.

[0179] Furthermore, it is possible to excite the ESR effects with respect to the resonance frequency effects (absolute maximum) by manipulating the noise feedforward. In this case, the two external inputs of the ΔΣ device have this possible configuration: - zero_loc = [0,9 0 0 0]. This means that a zero is added at 90% of the resonant frequency. This confirms that the approach can consist of two stages: It may be necessary to know the resonant frequency in order to place the NTF zero(s) close to it. At least one of the following can be used beforehand: an identification process during startup and / or in steady state. It might be useful to have an initial identification stage to capture and / or isolate the in-band ESR, and it is then possible to be certain about the ESR location with a second stage (in which the NTF expression is modified).

[0180] Fig. Figure 13 illustrates the result of modifying a third-order NTF to add an in-band zero near the resonance frequency (Z1 = 0.9*f0). A first curve 1301 (ESR contribution) shows a difference between the absolute and relative maximums, which is lower than in Fig. Curve 12 is where no in-band zeros have been introduced. A second curve, 1302, corresponds to the case without ESR contributions.

[0181] If the resonant frequency and the ESR position are known, the expected idle bandwidth of the system can be determined.

[0182] The time-based recording can then be processed to determine the resonant frequency, and in a second stage, the NTF can be modified by adding one or more in-band zeros to determine the ESR zero. Two stages can be used to position the in-band zeros relative to the resonant frequency. However, the PSD analysis shows that the ESR could also be extrapolated without any modification of the NTF structure. Modifying the NTF leads to a process that could be used to confirm and / or isolate minimum ESR contributions. Averaging and / or filtering processing functions, both in combination with downsampling and windowing, could enhance these effects to obtain truly reliable, determined data.

[0183] The following describes conventional approaches for determining parameters of external components, such as an output network.

[0184] Fig. Figure 14 shows an example of a typical SMPS 1400 converter in a buck converter configuration. The 1400 converter is a voltage regulator that regulates an output voltage Vout.

[0185] The SMPS converter 1400 includes an input voltage source 1401, the positive output of which is connected to an inductor 1403 via a field-effect transistor 1402. The field-effect transistor 1402 includes a gate. The cathode of a diode 1404 is connected between the field-effect transistor 1402 and the inductor 1403. The anode of the diode 1404 is connected to the negative output of the input voltage source 1401 (this is, for example, a ground connection). The inductor 1403 is located between the cathode of the diode 1404 and the connection point of a load 1405. The other connection point for the load is the anode of the diode 1404. The voltage across the load 1405 is the output voltage Vout. A capacitor 1406 is connected in parallel to the load 1405. The output voltage Vout is fed into a multiplier 1407, which generates a multiplied output voltage.The multiplied output voltage is fed into a regulator 1408, which contains a subtractor 1409 that determines a difference e(t) between the multiplied output voltage and a reference voltage Vref. This difference (deviation signal) can be fed into an error amplifier and compensator 1410, which controls a pulse width modulator 1411, which controls a driver 1412, which controls a voltage of the gate of the field-effect transistor 1402 and thus the output voltage.

[0186] Inductor 1403 and capacitor 1406 are external components for the SMPS converter 1400. Transistor 1402 is a reference switch. The system regulates Vout based on the voltage Vref. The output network (including inductor 1403 and capacitor 1406) generates a pair of complex poles. Regulator 1408 is designed to maintain loop stability and high open-loop gain of the system to increase the accuracy of Vout.

[0187] The controller 1408 generates one low-frequency pole and two zeros to achieve the desired loop transfer function.

[0188] A fluctuation of the inductor 1403, the capacitor 1406 or the equivalent series resistance (ESR, in Fig. (Figure 14 not shown) could cause the system to become unstable. The controller 1408 should be able to accommodate these fluctuations. To this end, it can be designed conservatively, i.e., in a safe manner that makes it robust against instability. However, if the controller 1408 is designed in this way, the dynamic performance of the system loop (i.e., the load step response) may be too low and may not meet the system requirements.

[0189] Parameter drift in the power stage, such as fluctuations in inductor 1403, capacitor 1406, or other components, can be mitigated by offline recalibration of the controller to maintain target dynamic power specifications. These techniques are often called auto-tuning or self-tuning. Typically, it may be desirable to identify an external component (e.g., an inductor and / or capacitor) or the output power filter frequency characteristics (poles and zeros). Such procedures can require complex numerical calculations; therefore, they are suitable for digitized systems and advanced silicon technologies that allow for high chip integration, requiring a small chip area to provide the computational resources for the calculations (e.g., computationally intensive calculations may be required on a small silicon area).

[0190] The following describes two typical approaches for a SMPS (switching power supply) that uses an external filter (implemented, for example, by both an inductor and a capacitor, such as the inductor 1403 and the capacitor 1406, illustrated in Fig. 14) is interconnected, which lies outside the SMPS, introducing a few complex conjugated poles.

[0191] The first approach is based on induced control loop oscillations caused by introducing both a relay and an integrator into the control loop. This is described in Fig. 15 illustrated.

[0192] Fig. 15 shows a control loop 1501.

[0193] The control loop 1501 contains a subtractor 1505, which is designed to generate the signal of the difference between a reference signal yref (e.g., a reference voltage) and an output signal y (e.g., an output voltage). A relay 1506 generates a control signal u from the difference signal e. The relay (e.g., a latching relay) 1506 is used in this example to provide hysteresis. The control signal u results in the output voltage y according to the controlled system 1507. Fig. Figure 15B shows a signal curve 1502 of the output signal y of the control loop. Fig. 15A.

[0194] Signal curve 1502 shows the induced oscillations of the output signal y over time.

[0195] Fig. Figure 15C shows a signal curve 1503 of the manipulated variable u of the control loop. Fig. 15A.

[0196] The second signal curve 1503 shows the control signal u (manipulated variable), i.e. the output of relay 1506, over time.

[0197] A user can utilize both frequency and / or amplitude of the vibrations to identify system characteristics, particularly the load. For example, a user can induce vibrations in the system through appropriate excitation. Relay 1506 introduces a nonlinearity.

[0198] Fig. Figure 15D shows a Nyquist diagram 1504 for the control loop from Fig. 15A.

[0199] The Nyquist diagram 1504 shows a graph 1505 of G(jω) (i.e. the function that describes the controlled system 1507 in the frequency domain) of the control loop from Fig. 15A. Graph 1505 is mainly characterized by a real part with a phase of -180° (the imaginary part could be considered negligible because it is related to the small delay introduced by the relay hysteresis). When the loop is closed, the system oscillates at a frequency given by the intersection of graph 1505 with the characterizing function of the relay curve 1506. This means that it oscillates at a frequency with a phase of -180°, because in this case the feedback signal amplifies the input signal.

[0200] Fig. Figure 16 shows a curve image 1600, which shows an amplitude (shown as a solid line 1604, referenced to a first axis 1601) and a phase (shown as a dashed line 1605, referenced to a second axis 1602) of G(jω) as a function of the frequency (given by a third axis 1603).

[0201] In this example, G(jω) consists of a low-frequency pole (integrator) and the complex poles of an output power network (including the inductor L and the capacitor C, e.g., similar to inductor 1403 and capacitor 1406, illustrated in Fig. 14) of the regulated system 1507. The regulated system 1507 oscillates at approximately the frequency f0 of the complex poles, as shown by the peak 1608. This frequency can be determined and ascertained from the processing of the relay output.

[0202] The relay 1506 can be replaced by a component that provides a special phenomenon induced in a digital loop, known as limit cycle oscillation (LCO). In this case, the pulse width modulator (PWM) of the controlled system 1507 can be implemented by a digital counter. If the controlled system 1507 includes an analog-to-digital converter (ADC) connected to the PWM, the resolution of the duty cycle generated by the PWM may be too coarse, and the deviation related to the output voltage (i.e., in this example, the output signal y) may not be reflected in the zero-point error class of the ADC. In this case, the output voltage may oscillate between ±1 LSB (least significant bit) of the ADC. The oscillation frequency of this oscillation typically correlates with the complex pole frequency of the LC.

[0203] The aforementioned (first) approach does not consider the effects of non-idealities, such as ESR contributions. Large ESRs typically impair the identification process, which can lead to erroneous results. Furthermore, its use may reduce the bandwidth of control loop 1501 and decrease its dynamic performance. Vibration introduced into control loop 1501 (usually at a low frequency) could interfere with other sensitive devices.

[0204] A second approach involves introducing a multi-period pseudorandom binary sequence (PRBS), which can be viewed as a digital emulation of white noise. The response of a system, such as a control-loop SMPS, to ideal white noise is related to the system's impulse response. Frequency-space analysis of the impulse response can encompass all the frequency information needed to characterize the system. System parameters can be determined through signal processing.

[0205] However, PRBS is typically not exactly ideal white noise. A spectrum obtained through PRBS is very noisy, mainly at mid-frequencies. Therefore, the results of determining the system's parameters can be affected, leading to misidentification. For example, it may not be possible to evaluate the ESR contribution.

Claims

[1] Converter circuit (100) comprising the following: a switching circuit (101) designed to to provide an output voltage (106) to a load (1405); a control circuit (102) comprising an analog control component (103) and a digital control component (104); a noise generator (105) designed to generate white noise (107); wherein the noise generator (105) is designed to supply the generated white noise (107) to the digital control component (104) of the control circuit (102); and wherein the control circuit (102) is designed to control the switching circuit (101) based on the white noise (107); wherein the noise generator (105) comprises a sigma-delta converter (603, 607), and wherein the noise generator (105) is designed to generate the white noise (107) using a quantization noise of the sigma-delta converter (603, 607). [2] Converter circuit (100) according to claim 1, wherein the control circuit (102) is designed to control the switching circuit (101) on the basis of the white noise (107) in order to determine at least one property of at least one of the following: the load (1405) or the converter circuit (100). [3] Converter circuit (100) according to claim 2, wherein the control circuit (102) is further configured to select one or more elements from a group consisting of the following: an inductance of an inductor (1403); a capacitance of a capacitor (1406); an equivalent series resistance of the capacitor (1406); and an electrical property of the load (1405). [4] Converter circuit (100) according to any one of claims 1 to 3, wherein the control circuit (102) is designed to control the switching circuit (101) to provide the output voltage (106) on the basis of a duty cycle; and wherein the control circuit (102) is designed to control the switching circuit (101) on the basis of the white noise (107) by adding the generated white noise (107) to the duty cycle. [5] Converter circuit (100) according to one of claims 1 to 4, wherein the control circuit (102) comprises: an analog-to-digital converter (401, 901) designed to take a measurement of the output voltage (106) and provide a digital value indicating the taken measurement of the output voltage (106). [6] Converter circuit (100) according to claim 5, wherein the analog-to-digital converter (401, 901) is further configured as follows, to compare the recorded measured value of the output voltage (106) with a reference voltage; and to generate a deviation signal that represents a difference between the recorded measured value of the output voltage (106) and the reference voltage. [7] Converter circuit (100) according to claim 6, wherein the control circuit (102) is designed to add the generated white noise (107) to the deviation signal. [8] Converter circuit (100) according to claim 6 or 7, wherein the control circuit (102) is designed to sequentially increase the reference voltage. [9] Converter circuit (100) according to one of claims 6 to 8, wherein the control circuit (102) further comprises a Proportional-Integral Derivative (PID) controller (402, 902) designed to receive the deviation signal and generate a PID output based on the received deviation signal. [10] Converter circuit (100) according to claim 9, wherein the control circuit (102) is further configured to add the generated white noise (107) to the PID output. [11] Converter circuit (100) according to claim 9 or 10, wherein the control circuit (102) further comprises a pulse width modulation controller (403, 903) designed to receive the PID output and generate a pulse width modulated control signal designed to control a power stage (404, 904) to provide the output voltage (106) to the load (1405). [12] Converter circuit (100) according to claim 11, wherein the noise generator (105) is further designed to reduce the resolution of the sigma-delta converter (603, 607) in order to increase the amplitude of the generated white noise (107). [13] Converter circuit (100) according to claim 11 or 12, where the sigma-delta converter (603, 607) contains more than one feedback loop; and wherein at least one zero of the sigma-delta converter (603, 607) is located near the resonant frequency of the load (1405). [14] Converter circuit (100) according to one of claims 11 to 13, wherein the control circuit (102) further comprises: an analog-to-digital (AD) converter (401, 901) designed to: to record a measured value of an output voltage (106) at the load (1405); to compare the recorded measured value of the output voltage (106) with a reference voltage; and to generate a deviation signal that represents a difference between the recorded measured value of the output voltage (106) and the reference voltage; and wherein the control circuit (102) is designed as follows: to process the deviation signal in order to determine one or more of the following: the cutoff frequency of the control circuit (102) or an equivalent series resistance of the capacitor (1406). [15] Converter circuit (100) according to claim 14, wherein the control circuit (102) is further designed to process the deviation signal in order to determine a spectral power density, and wherein the control circuit (102) is preferably further designed to determine one or more of the following based on the determined spectral power density: a loop cutoff frequency of the control circuit (102) or an equivalent series resistance of the capacitor (1406). [16] Converter circuit (100) according to claim 14 or 15, wherein the control circuit (102) is further configured to adapt at least one coefficient of a PID controller (402, 902) which is configured to receive the deviation signal and generate a PID output based on one or more of the following: the determined loop cutoff frequency of the control circuit (102) or the determined equivalent series resistance of the capacitor (1406). [17] Method (200) for converting an input voltage into an output voltage (106), wherein the method (200) comprises the following: the generation (201) of white noise (107); the feeding (202) of the generated white noise (107) to a digital control component (104) of a control circuit (102); and the control (203) of a switching circuit (101) based on the white noise (107) to provide the output voltage (106); where the white noise (107) is generated using quantization noise from a sigma-delta converter (603, 607). [18] Method (200) according to claim 17, wherein the switching circuit (101) is controlled on the basis of the white noise (107) to determine at least one property of at least one of the following: the load (1405) or the converter circuit (100); and wherein the at least one property comprises at least one of the following: the load (1405) or the converter circuit (100), preferably one or more elements from a group consisting of the following: an inductance of an inductor (1403); a capacitance of a capacitor (1406); an equivalent series resistance of the capacitor (1406); and an electrical property of the load (1405). [19] Method (200) according to claim 17 or 18, wherein the switching circuit (101) is controlled to provide the output voltage (106) based on a duty cycle; and wherein the switching circuit (101) is controlled on the basis of the white noise (107) by adding the generated white noise (107) to the duty cycle. [20] Method (200) according to any one of claims 17 to 19, further comprising: the analog-to-digital conversion of a recorded measurement of the output voltage to provide a digital value, which indicates the recorded measured value of the output voltage (106), where the analog-to-digital conversion preferably includes the following: comparing the recorded measured value of the output voltage (106) with a reference voltage; and generating a deviation signal that represents a difference between the recorded measured value of the output voltage (106) and the reference voltage and wherein the generated white noise (107) is preferably added to the deviation signal and where the reference voltage is preferably increased sequentially. [21] Method (200) according to claim 20, further comprising: the recording of the deviation signal; and generating a PID output based on the recorded deviation signal using a PID controller in the control circuit, where the generated white noise (107) is preferably added to the PID output. [22] Method (200) according to claim 21, comprising: the acquisition of the PID output by a pulse width modulation controller (403, 903) of the control circuit (102); and the generation of a pulse width modulated control signal by the pulse width modulation controller (403, 903) to control a power stage (404, 904) to provide the output voltage (106) to the load (1405). [23] Method (200) according to any one of claims 17 to 22, further comprising: reducing the resolution of the sigma-delta converter (603, 607) to increase the amplitude of the generated white noise (107).

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