Gain-ranging charge amplifier

Abstract

System that includes the following: a pixel array (110) that generates multiple output signals representing radiation incident on the pixel array; a voter (130) who selects one of the several output signals; and a sampler (120) that samples one of the several output signals, wherein the sampler comprises a charge integrator (122), wherein the charge integrator is configured to compensate a parasitic capacitance of the selector by selecting a first feedback capacitance (124, 126) of the charge integrator to obtain a first sample of one of the several of the output signals, and after obtaining the first sample, selecting a second feedback capacitance (124) of the charge integrator to obtain a second sample of one of the several of the output signals, and where the first feedback capacity is larger than the second feedback capacity.

Description

GENERAL STATE OF THE ART

[0001] A charge amplifier can be driven by an electrical signal source of a capacitive nature, such as a piezoelectric sensor or a charge-capacitance device (CCD). The charge amplifier can transfer the charge from a charge signal to a reference capacitor (also called an integrating capacitor) to generate an output voltage that correlates with the voltage across the reference capacitor. The output voltage can be based on the charge of the reference capacitor and the input charge. Charge amplifiers can be used in readout circuits of optical imaging devices and flat-panel X-ray detector arrays to measure a small charge stored in small capacitors of individual pixels in arrays of pixels.

[0002] In charge-based circuits with multiple inputs, a selector circuit or multiplexer (MUX) can be used to channel specific measurement capacitors to the charge amplifier for signal processing. The input charge signal, which may be stored in the capacitor for each pixel, may be much smaller than the error charge induced by the parasitic capacitance of the thin-film transistor (TFT) selector switch during a selector switch transition.As a result, when a pixel is selected, the pixel's smaller input charge signal can be added to the larger, selection-induced error charge and can cause the charge amplifier to saturate early, limiting its dynamic range, or can cause the automatic gain selector circuit to select a lower gain early, limiting the full advantage of the allowable dynamic range available to measure or amplify the smaller input charge signal. When the selector switch is off, the charge amplifier should only display the input charge signal, but the larger error charge induced by the selector switch can degrade the output voltage signal.

[0003] DE 10 2007 030 985 B4 relates to an image sensor comprising a plurality of pixels configured to deliver associated pixel signals that depend on light intensities incident on the pixels. The image sensor comprises an accumulation circuit having a plurality of charge storage elements, wherein the accumulation circuit is configured to change charges on the charge storage elements during a phase as a function of pixel signals of respectively associated pixels. The accumulation circuit is further configured to change an association between charge storage elements and associated pixels in successive phases, such that, during operation, a charge on one of the charge storage elements depends on pixel signals of a plurality of pixels in a plurality of phases.

[0004] US 7,123,301 B1 relates to a correlated double-sampling pixel amplifier comprising an operational amplifier, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase, and the feedback capacitor receives the signal charge from the input capacitor. There is no sampling switch between the input capacitor and the input terminal. The feedback capacitor may comprise a capacitor array.

[0005] Thus, there is a need for an improved charge amplifier that compensates for errors without significantly increasing device complexity and size or significantly reducing performance. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a system diagram illustrating a sensor processing system according to an embodiment of the present invention. Fig. Figure 2 shows a simulated timing diagram of signals during operation of the system according to an embodiment of the present invention. Fig. 3 shows a method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0006] Fig. 1 is a sensor processing system 100 according to an embodiment of the present invention. The system 100 may include a variety of circuitry, including a pixel array 110, a sampling stage 120, a selecting stage 130, and an ADC stage 150. The pixel array 110 may include multiple pixel circuits (not shown) arranged in an ordered array. Pixel circuits within the array may generate output signals representing radiation incident on the detector(s) of the circuits, such as visible light or x-rays. The selecting stage 130 may select one of the pixels. When one of the pixels is selected, it may separately output reset and signal charges to the sampling stage 120. The sampling stage 120 may generate output voltages CDS1, CDS2 for use by the ADC stage 150 in digital conversion. The ADC stage 150 may generate a digital output code D OUTwhich represents a signal level of the incident radiation on the pixel circuit and can thereby perform scanning operations.

[0007] As indicated, pixel array 110 may include multiple pixel elements that generate an electrical output in response to incident energy (e.g., light, x-rays, etc.). Pixel circuits may be organized into a regular array of addressable pixel circuits, for example, in a row of pixels, Cartesian or hexagonal. Each row may have its own sensing stage. For purposes of the present discussion, it is convenient to consider the arrays as containing a plurality of pixels in columns and rows. Each pixel p(x,y) may include thin-film transistor (“TFT”) components that can generate a charge when excited by incident radiation. For example, x-rays illuminating a pixel p(x,y) may generate the charge signal C x,ygenerate. The degree of illumination can cause a corresponding variation in the charge output (i.e., stronger illumination results in a larger charge).

[0008] In one embodiment, pixel array 110 may be provided on a substrate, separate from other components (e.g., sampling stage 120 and ADC stage 150). Such an implementation may be appropriate for an x-ray sensor system. Sampling stage 120 and ADC stage 150 may be provided on a common integrated circuit (IC) to each other. Alternatively, in another embodiment, pixel array 110 may be provided on a common IC substrate like other components, which may be appropriate in a digital camera embodiment.

[0009] The selection stage 130 may include one or more selection switches 132. The selection switches 132 may select one pixel from a plurality of pixels based on an addressing signal V GATEWhen a pixel p(x,y) is addressed, the selector stage 130 can output its corresponding charge signal C x,y to the sampling stage 120. During operation, a selected pixel p(x,y) can be addressed for sampling twice—once immediately after the pixel is reset to output a reset level, and a second time after an exposure period to output the signal level. Alternatively, the reset level can be assumed to be at the same stable reference voltage, and thus sampling of the reset level can be skipped. The selection stage 130 can include a parasitic capacitance C PARASITIC The parasitic capacitance C PARASITIC can be combined with the voltage V GATE large enough to cause a significant error signal to be generated to affect the measurement of the charge signal C x,y of pixel p(x,y).

[0010] The sampling stage 120 may include an integrator 122, a comparator 123, a first integrating capacitor 124, a second integrating capacitor 125, a reset switch 126, a full-scale switch (FS) 127, a switch 128, and sampling capacitors 130, 131, 132. The integrator 122 may have an input coupled to the pixel array 110 via the selection stage 130 and an input coupled to a reset voltage V RES (which may be set to 4 V, for example). The comparator 123 may have an input coupled to the output of the integrator 122 and an input coupled to a saturation threshold voltage V SAT(which may be set to 0.5 V, for example) to determine whether the integrator 122 is saturated (i.e., by the output falling below the saturation threshold voltage), generating a CLAMP signal to indicate whether a selected range of the integrator 122 is exceeded. The first integrating capacitor 124 may be coupled to an output and to an input of the integrator 122 in a feedback configuration. The second integrating capacitor 125 may be coupled to an input of the integrator 122, in series with the FS switch 127 and in parallel with the first integrating capacitor 124. The reset switch 126 may be connected to the first integrating capacitor 124 and may be controlled by a RESET signal to reset the first integrating capacitor 124.The FS switch 127 may be coupled in series with the second integrating capacitor 125 to be parallel with the first integrating capacitor 124. The FS switch 127 may be controlled by an FS signal and, in a first state, to connect the second integrating capacitor 125 to the output of the integrator 122 (e.g., when the FS signal is high). The FS switch 127 in a second state may connect the second integrating capacitor 125 to the reset voltage V. RESconnect (e.g., when the FS signal is in a low state). Switch 128 may be coupled between an output of integrator 122 and first terminals of storage capacitors 130, 131, 132. Second terminals of storage capacitors 130, 131, 132 may be connected to ground. The first terminals of storage capacitors 130, 131, 132 may be selectively connected by switch 128 to an output of sampling stage 120. Switch 128 may be controlled to select the output of sampling stage 120 from storage capacitors 130, 131, 132 based on the RESET signal (for reset level sampling) and the clamp signal from the output of comparator 123.

[0011] The sampling stage 120 can input charges C x,y from the pixel array 110 at different times for sampling and can sample / accumulate the charge to provide a corresponding input voltage V x,yto generate. The sample values ​​can be stored as CDS1, CDS2.1, and CDS2.2 on capacitors 130, 131, and 132, respectively. CDS1 can correspond to a sample time with known conditions (e.g., reset level at reset time), and CDS2.1 and CDS2.2 can correspond to sample times with unknown conditions (e.g., sensor readings).

[0012] The storage capacitors 130, 131, 132 can store the accumulated voltage for the sample values ​​CDS1, CDS2.1, and CDS2.2, respectively. Typically, the storage capacitors 130, 131, 132 will have common capacitances. The switch 128 can connect the capacitors 130, 131, 132 to the input voltage V at appropriate times. x,yto sense the voltages CDS1, CDS2.1, and CDS2.2 on the respective capacitors. Furthermore, switch 128 can be controlled to select the output of sampling stage 120 from storage capacitors 130, 131, 132 based on the CLAMP signal from the output of comparator 123. In particular, for example, switch 128 can be controlled to select one of CDS2.1 and CDS2.2 as CDS2 based on the CLAMP signal from the output of comparator 123 for output to ADC stage 150. In other words, sampling stage 120 can sample the sensor readings at least twice, for example, as CDS2.1 and CDS2.2, and then select one of the sensor readings based on the state of the CLAMP signal, which indicates whether one of the ranges is saturated.

[0013] The sampling stage 120 may first sample the sensor reading with a wider range, with both integrating capacitors 124 and 125 connected to the feedback loop of the integrator 122, and then sample the sensor reading with a narrower range, with the first integrating capacitor 124 connected to the feedback loop of the integrator 122, but the second integrating capacitor 125 removed from it. The first sample, taken with a larger integrating capacitance, may be selectively stored by switch 128 as CDS2.1 in the storage capacitor 131. The second sample, taken with less integrating capacitance, may be selectively stored by switch 128 as CDS2.2 in the storage capacitor 132. After the two samples, the comparator 123 determines whether the second sample caused the integrator 122 to saturate, ie, whether the input voltage V x,y below the saturation threshold voltage V SATdropped. If saturation occurred during the second sample, the CLAMP signal can be held high, thus also indicating that the narrower range was exceeded. Switch 128 can then select CDS2.1 as CDS2 if saturation occurred in the narrower range, or select CDS2.2 as CDS2 if saturation did not occur in the narrower range.

[0014] Furthermore, it is possible that saturation may occur in both the wider and narrower ranges. In such a case, the sensor input signal may be too large, and saturation in the wider range can be expected. Switch 128 can select either CDS2.1 or CDS2.2 as CDS2, because both signals represent a saturated output.

[0015] The sampling stage 124 can detect that saturation occurred in both the wider range and the narrower range and can force the ADC stage 150 to output the digital code DOUT with a maximum value. The sampling stage 124 may only need to detect that saturation occurred in the wider range, skip sampling in the narrow range, and force the ADC stage 150 to output the digital output code D OUT with a maximum value. The CLAMP signal can be used to clamp a portion of the digital output code D in other parts of the system 100, for example in the ADC stage 150. OUT to generate.

[0016] Through the operation described above, the system 100 can avoid the effect of an error signal induced by a parasitic capacitance and maintain the accuracy of the measurement while dynamically selecting the appropriate range for measuring the charge signal on a pixel.

[0017] The ADC stage 150 may include a pair of capacitors 152, 154, a pair of sample and hold amplifiers (“SHAs”) 156, 158, and an ADC 160. The capacitors 152, 154 may each be provided in a feedback configuration around a respective SHA 156, 158. The ADC stage 150 may receive the sample values ​​CDS1 and CDS2 from the sampling stage 120 and convert the difference between the samples, ΔCDS, directly into a digital value in a single conversion operation. The SHAs 156, 158 may buffer the voltages CDS1 and CDS2 output by the sampling stage 120, respectively. A pair of storage capacitors 152, 154, respectively, may store the sample values ​​CDS1 and CDS2. In one embodiment, the storage capacitors 152, 154 of the ADC stage and the storage capacitors 130, 131, 132 of the sampling stage may be provided as common devices.

[0018] The input voltage V x,yof the pixel array 110 can vary over several operating phases. In a first phase, V x,y be at a reset level, which represents a pixel's voltage before it is exposed to incident energy. In another phase, V x,y be at a signal level that represents a voltage of the same pixel after it has been exposed to the incident energy. Different phases may be needed to address different pixels within the array.

[0019] In one embodiment, sampling in the first phase for the reset level may be skipped to assume that the reset level is at some predetermined signal level, for example, ground voltage level or 0 V. In this case, CDS1 may be assumed to be 0 V, storage capacitor 130 may be omitted, sampling stage 120 may not need to sample or output CDS1, and SHA 156 and storage capacitor 152 may be omitted. ADC stage 150 may perform digitization using only the CDS2 signal with reference to a reference signal.

[0020] Additionally or alternatively, sampling of CDS2.1 may be skipped at the wide range to assume that the input from pixel p(x,y) may be small. In such a case, sampling stage 120 may connect parallel integrating capacitors 124 and 125 during integration, skip sampling at the wide range, disconnect the second integrating capacitor 125, and then sample CDS2.2 only at a narrow range to output as CDS2. In such a case, storage capacitor 131 may be omitted.

[0021] Fig. Figure 1 also illustrates the structure of an ADC 160 in one embodiment of the present invention. The ADC 160 may receive the voltage CDS1 from the SHA 156 at a first terminal (e.g., a negative terminal) and may receive the voltage CDS2 from the SHA 158 at another input terminal (e.g., a positive terminal). The ADC 160 may generate a digital output code in response to a difference between the voltages CDS1 and CDS2.

[0022] The architecture of Fig. 1 provides an architecture that rejects offsets induced by common path components by performing comparisons CDS1 to CDS2 within the ADC. As noted, component variations among the pixel circuits can cause inter-pixel variations in the reset and signal levels generated by the pixel array. Furthermore, component variations within the integrator 122 or the feedback capacitor 124 can induce signal offsets in the reset and signal levels. The architecture of Fig. 1 rejects degraded signals that could potentially affect CDS1 and CDS2 together by integrating CDS operation with digitization.

[0023] Alternatively, CDS1 may be assumed to be at some predetermined voltage level (e.g., 0 V), and the storage capacitor 130, the SHA 156, and the storage capacitor 152 may be omitted. The ADC stage 150 may perform digitization using only the CDS2 signal with reference to a reference signal.

[0024] Fig. 2 shows a simulated timing diagram of signals during operation of system 100 according to one embodiment.

[0025] For example, in Fig. 1 assume that a pixel of charges has a capacity of 1 picofarad (pF) and the reset voltage V RES4 volts (V), which represents a zero signal. At time 0, a pixel charge signal for pixels p(x,y) may be (4.75 - 4.0)*1pF = 0.75 picocoulombs (pC). At time 0, the reset switch 126 may be closed, and the FS switch 127 may be closed, shorting the integration capacitors 124 and 125 and reducing the input voltage V x,y at the output of the integrator 122 is forced to 4 V.

[0026] At the time of 1 microsecond (µs) (or at any predetermined time before measuring), the reset switch 126 can be opened by changing the RESET signal state in preparation for measuring.

[0027] At the time of 2 µs (or at a certain predetermined time set for starting the measurement), the addressing signal V GATEclose the selector switches 132 to select the pixel p(x,y) above. While charge is being transferred from pixel p(x,y), the integrator 122 can integrate the charge and determine the input voltage V x,y at the output of the integrator 122 may decrease proportionally to the charge signal for pixel p(x,y).

[0028] When the selector switches 132 close, the parasitic capacitance C PARASITIC a certain error charge in the charge signal C x,y In this example, assume that when the selector switches 132 close, 0.5 pC of fault charge is injected into the charge signal C x,y can be coupled in. The charge signal C x,y can rise to (0.75 pC + 0.5 pC) = 1.25 pC.

[0029] When the selector switches 132 close, the integrator 122 can begin to integrate by detecting the 1.25 pC of the charge signal C x,ytransferred to both integrating capacitors 124 and 125 (in the wide range), where the first integrating capacitor 124 may have a capacitance of 0.25 pF and the second integrating capacitor 125 may have a capacitance of 0.75 pF. The total integrating capacitance of these two integrating capacitors 124 and 125 may be 1 pF. While the charge signal C x,y of 1.25 pC is transferred to the two integrating capacitors 124 and 125, the input voltage V x,y at the output of the integrator 122 to (4 V - 1.25 pC / 1 pF) = 2.75 V.

[0030] At the instant of 7 µs (or after a certain predetermined period after the start of the measurement), when the selector switches 132 open, the fault charge effect can be considered eliminated. The charge signal C x,y can be considered as returning to 0.75 pC for measurement purposes. As a result, the input voltage V x,yat the output of the integrator 122 to (4 V - 0.75 pC / 1 pF) = 3.25 V.

[0031] At the time of approximately 7.75 µs (or after any predetermined period after the opening of the selector switches 132), the switch 128 may switch the input voltage V x,y of 3.25 V as CDS2.1 to the storage capacitor 131 and store it there.

[0032] At the instant of 8 µs (or after a certain predetermined duration after opening the selector switches 132 and / or after sampling CDS2.1), the FS switch 127 may open while the FS signal goes low. This disconnects the second integrating capacitor 125 from the feedback loop of the integrator 122. As a result, the total integrating capacitance of the integrator 122 may be reduced to 0.25 pF of the first integrating capacitor 124. The charge signal C x,y can be considered to remain at 0.75 pC for measurement purposes. As a result, the input voltage V x,yat the output of the integrator 122 to (4 V - 0.75 pC / 0.25 pF) = 1 V.

[0033] At the time of approximately 8.75 µs (or after a certain predetermined period after the opening of the FS switch 127), the switch 128 can switch the input voltage V x,y of 1 V as CDS2.2 to the storage capacitor 132 and store it there.

[0034] Throughout the above sequence and thereafter, the comparator 123 compares the input voltage V x,y with the saturation threshold voltage V SAT (which can be set to 0.5 V, for example). Because the input voltage V x,y never below the saturation threshold voltage V SATof 0.5 V, the CLAMP signal may be low, indicating that the integrator 122 has not saturated in either the wider range or the narrow range. As a result, the switch 128 may select CDS2.2 of 1 V on the storage capacitor 132 for output to the ADC stage 150 as the CDS2 signal. The ADC stage 150 may then digitize the difference between CDS1 and CDS2 to produce a digital output code D OUT while also taking into account the CLAMP signal, which indicates the range of the measurement.

[0035] Through the operation described above, the system 100 can avoid the effect of an error signal induced by parasitic capacitance and maintain measurement accuracy while dynamically selecting the mounted area for measuring the charge signal on a pixel.

[0036] Fig. 3 shows a method 300 according to an embodiment of the present invention.

[0037] At block 310, more than one capacitance branch of the integrator may be connected before or at the time of selecting a charge signal.

[0038] In block 320, a charge signal can be selected for measurement.

[0039] In block 330 the charge signal can be deselected.

[0040] At block 340, the system may sample and hold the stabilized output of the integrator as a wide range output.

[0041] At block 345, the system may determine whether the integrator saturated at the wide range output, for example, by comparing the wide range output to a predetermined or preset threshold voltage.

[0042] In one embodiment, the system may proceed from block 345 to block 350.

[0043] In one embodiment, the system may proceed from block 345 to blocks 350 and 380 in parallel.

[0044] In one embodiment, the system may skip blocks 340 and 345, ie, skip the wide range scanning, and go to block 350.

[0045] In one embodiment, at block 380, if the integrator saturated in the wide range, proceeding to block 390, the system may force the digital output to a maximum value.

[0046] In one embodiment, at block 380, regardless of whether the integrator saturated in a wide range, proceed to block 350.

[0047] At block 350, the system may disconnect at least one capacitance branch of the integrator.

[0048] At block 360, the system may sample and hold the stabilized output of the integrator as a narrow range output.

[0049] At block 370, the system may determine whether the integrator saturated at the narrow range output, for example, by comparing the narrow range output to a predetermined or preset threshold voltage.

[0050] At block 385, if the integrator saturated in the narrow range, go to block 390, otherwise go to block 395.

[0051] At block 392, the system may output the wide range output of the integrator as the measurement signal.

[0052] At block 395, the system may output the narrow range output of the integrator as the measurement signal.

[0053] Through the method described above, the system 100 can avoid the effect of an error signal induced by a parasitic capacitance and maintain the accuracy of detection while dynamically selecting the correct area for detecting the charge signal on a pixel.

Claims

[1] System comprising: a pixel array (110) generating a plurality of output signals representing radiation incident on the pixel array; a selector (130) that selects one of the plurality of output signals; and a sampler (120) which samples one of the plurality of output signals, wherein the sampler comprises a charge integrator (122), wherein the charge integrator is configured to compensate for a parasitic capacitance of the selector by selecting a first feedback capacitance (124, 126) of the charge integrator to obtain a first sample value of the one of the plurality of output signals, and after obtaining the first sample value, selecting a second feedback capacitance (124) of the charge integrator to obtain a second sample value of the one of the plurality of output signals, and wherein the first feedback capacitance is greater than the second feedback capacitance. [2] The system of claim 1, further comprising: a converter (160) that generates a digital signal based on the one of the plurality of output signals. [3] The system of claim 1 or 2, wherein the charge integrator comprises an amplifier (122) having a feedback path connecting an output of the amplifier to an input of the amplifier. [4] The system of any preceding claim, wherein the charge integrator comprises an amplifier (122) having a feedback path connecting an output of the amplifier to an input of the amplifier, the feedback path being controlled to select one of the first feedback capacitance and the second feedback capacitance. [5] A system according to any preceding claim, wherein the sampler comprises a switch (127) controlling a feedback path in the charge integrator to select the first feedback capacitance or the second feedback capacitance. [6] A system according to any preceding claim, wherein the sampler obtains a reset sample before obtaining the first sample and stores the reset sample as a voltage signal in a capacitor (130). [7] A system according to any preceding claim, wherein the sampler stores the first sample and the second sample as voltage signals in a plurality of capacitors (131, 132). [8] Procedure comprising: generating, by a pixel array (110), a plurality of output signals representing radiation incident on the pixel array; Selecting, by a selector (130), one of the plurality of output signals; and Sampling, by a sampler (120), the one of the plurality of output signals, wherein the sampler comprises a charge integrator (122), wherein the charge integrator is configured to compensate for a parasitic capacitance of the selector by selecting a first feedback capacitance (124, 126) of the charge integrator to obtain a first sample value of the one of the plurality of output signals, and after obtaining the first sample value, selecting a second feedback capacitance (124) of the charge integrator to obtain a second sample value of the one of the plurality of output signals, and wherein the first feedback capacitance is greater than the second feedback capacitance. [9] The method of claim 8, further comprising: generating, by a converter (160), a digital signal based on the one of the plurality of output signals. [10] The method of claim 8 or 9, wherein the charge integrator comprises an amplifier (122) having a feedback path connecting an output of the amplifier to an input of the amplifier. [11] The method of claim 8, 9 or 10, wherein the charge integrator comprises an amplifier (122) having a feedback path connecting an output of the amplifier to an input of the amplifier, the feedback path being controlled to select the first feedback capacitance or the second feedback capacitance. [12] The method of claim 8, 9, 10 or 11, wherein the sampler comprises a switch (127) controlling a feedback path in the charge integrator to select the first feedback capacitance or the second feedback capacitance. [13] The method of claim 8, 9, 10, 11 or 12, wherein the sampler obtains a reset sample before obtaining the first sample and stores the reset sample as a voltage signal in a capacitor (130). [14] The method of claim 8, 9, 10, 11, 12 or 13, wherein the sampler stores the first sample value and the second sample value as voltage signals in a plurality of capacitors (131, 132). [15] A non-transient computer-readable medium storing computer program instructions executable by a processor to control a system to perform the method of any one of claims 8 to 14.

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