Characterization of a cell using an input wave generation system, taking into account different circuit topologies

Abstract

A method for designing an IC chip, comprising: characterizing by at least one processor of a cell (504) with respect to input transition characteristics, taking into account different circuit topologies of a pre-driver (502) driving the cell (504) that result in the same input transition characteristics, wherein the characterization comprises: obtaining different input waveforms with the input transition characteristics taking into account the different circuit topologies (302); and characterizing the cell using the different input waveforms to create entries in a library (304) associated with the input transition characteristics and the different circuit topologies, wherein the characterization of the cell using the different input waveforms to create entries associated with the input transition characteristics,in a library (304) comprises: for each of the different input waveforms, creating one of the entries that is used independently of the other entries in the library (150); and wherein the procedure further comprises: performing a time-of-flight analysis on a netlist such that a common input waveform with the input transition characteristics is matched to the cell with the different input waveforms in order to identify one of the entries in the library to generate an output response of the cell (1452, 1454, 1456), wherein obtaining different input waveforms with the input transition characteristics, taking into account the different circuit topologies (302), involves obtaining different input waveforms with the input transition characteristics and different first characteristics, wherein the different circuit topologies of the pre-driver driving the cell lead to the different first characteristics.and the various first characteristics are selected from the first characteristics collected from at least one chip comprising circuit topologies representative of the various circuit topologies of the pre-driver driving the cell, wherein the first characteristics are tail characteristics, the input transition characteristics include a first section of the corresponding input waveforms, and the tail characteristics include a second section of the corresponding waveform after the first section of the corresponding waveform, and wherein each of the input waveforms is a rising transition of a voltage Vin with respect to a time t at an input of the cell (504) in a corresponding netlist (500, 520, 540) of the pre-driver, wherein the rising transition of the voltage Vin for each of the input waveforms (600, 620,640) a voltage Vlower equal to 30% of a difference between a steady-state voltage Vfinal and an initial voltage Vinitial is reached at time tlower and a voltage Vupper equal to 70% of the difference between the steady-state voltage Vfinal and the initial voltage Vinitial is reached at time tupper, and wherein the input transition characteristics are an input transition time equal to tupper-tlower, or wherein each of the input waveforms is a decaying input waveform which also has an input transition time between times tupper and tlower when the decaying input waveform reaches a voltage Vupper or a voltage Vlower, and has a tail section from the voltage Vlower to a steady-state voltage Vfinal.

Description

BACKGROUND In the design process for an integrated circuit (IC) chip, static delay analysis is used at various stages to estimate delays in electronic circuits, for example, to verify correct operations and optimize the performance of the IC chip design. One factor influencing the accuracy of a delay calculation in static delay analysis is the similarity of a predetermined input waveform, used to characterize a cell for a delay calculation, to a common input waveform of the cell in the circuit where a static delay calculation is performed.However, with increasing technological development, factors such as increased length in interconnects for circuit connections and increased Miller capacitance in miniaturized and non-planar transistors cause distortion in the propagated input waveform relative to the predetermined input waveform. If this distortion in the propagated input waveform is ignored, the accuracy of the delay calculation is compromised. Publication JP 2000 - 276 501 A discloses a method for calculating the delay of IC chips, which takes into account the non-linearity of the input transition waveform. Publication US 2005 / 0232066A1 discloses a method for characterizing a cell to which a predetermined drive load is connected, wherein the characterization takes into account a distortion of an input waveform caused by the Miller effect. BRIEF DESCRIPTION OF THE DRAWINGS The details of one or more embodiments of the disclosure are illustrated in the accompanying drawings and the following description. Other features and advantages of the disclosure will become apparent from the description, the drawings, and the claims. Fig. 1 is a flowchart of a cell design process and a chip design process of an IC chip according to some embodiments. Fig. 2 is a functional block diagram of a software system for creating a runtime library and for performing a runtime analysis using the runtime library according to some embodiments. Fig. 3 is a flowchart of a method for characterizing a cell for delay calculation using input waveform generation, taking into account different circuit topologies that generate the same input transition characteristics, according to some embodiments.Figure 4 is a flowchart of a method according to some embodiments that implements operation 302 in Figure 3. Figure 5 contains schematic circuit diagrams of various netlists of the pre-driver driving the cell, configured in the different circuit topologies according to some embodiments. Figure 6 contains schematic waveform diagrams of the various input waveforms that have the same input transition characteristics and are constructed using the various netlists of the pre-driver driving the cell, according to some embodiments. Figure 7 is a flowchart of another method according to some embodiments that implements operations 302 in Figure 3. Figure 8 is a schematic representation showing a waveform collection performed on an exemplary propagation path in a chip according to some embodiments.Figure 9 shows schematic waveform diagrams of waveforms obtained by operations in Figure 7 according to some embodiments. Figure 10 is a flowchart of another method according to some embodiments implementing operations 302 in Figure 3. Figure 11 is a schematic waveform diagram of an exemplary waveform for representing a tail ratio. Figure 12 is a schematic probability density function of a tail ratio distribution of input waveforms to cells in a chip according to some embodiments. Figure 13 is a schematic circuit diagram of a circuit for deriving a linear Y-MOS equation according to some embodiments. Figure 14 shows flowcharts of a method implementing operations 304 in Figure 3 and of a corresponding method for performing waveform propagation while performing a propagation delay analysis on a physical netlist according to some embodiments.Fig. 15 is a schematic representation of a cell delay library according to some embodiments. Fig. 16 shows flowcharts of another method implementing the operations 304 in Fig. 3, and of a corresponding method for performing waveform propagation while performing a delay analysis on a physical netlist according to some embodiments. Fig. 17 is a schematic representation of a cell delay library according to some embodiments. Fig. 18 is a schematic representation of a space of input waveforms corresponding to different circuit topologies according to some embodiments. Fig. 19 is a schematic waveform diagram of output responses without sensitivity correction, with high resistance sensitivity correction, and further with high fanout sensitivity correction according to some embodiments.Figure 20 is a schematic representation of another runtime library of the cell according to some embodiments. Figure 21 is a schematic representation of a space of input waveforms corresponding to different circuit topologies according to some embodiments. Figure 22 is a flowchart of another method for characterizing a cell for delay computation using input waveform generation, taking into account different circuit topologies that generate the same input transition characteristics, according to some embodiments. Figure 23 is a flowchart of a method according to some embodiments that implements operation 2202 in Figure 22. Figure 24 is another flowchart of a method according to some embodiments that implements operation 2202 in Figure 22.Figure 25 is a flowchart of a method for performing waveform propagation during a runtime analysis on a physical netlist according to some embodiments. Figure 26 is a block diagram of a hardware system for implementing the software system implementations described with reference to Figure 2 and of method implementations described with reference to Figures 3-25, according to some embodiments. Identical reference symbols in different drawings indicate similar elements. DETAILED DESCRIPTION Embodiments or examples of the disclosure illustrated in the drawings are now described using special terms. It is nevertheless clear that this is not intended to limit the scope of protection of the disclosure. It is assumed that all changes and modifications in the described embodiments and all further applications of principles described in this document will be obvious to a person skilled in the art in the field to which the disclosure relates. Reference numerals may be repeated in all embodiments, but this does not necessarily mean that the feature or features of one embodiment apply to another embodiment, even if they share the same reference numeral. Some embodiments have one or a combination of the following features and / or advantages. In some embodiments, a cell is characterized with respect to input transition characteristics by considering different circuit topologies of a pre-driver driving the cell, which result in the same input transition characteristics. In some embodiments, by further performing waveform tuning considering the different circuit topologies, an output response of the cell, generated using a model characterized by an input waveform, is more similar to and accurate of the distorted propagated input waveform.In some embodiments, further application of sensitivity correction, taking into account the various circuit topologies, corrects the cell's output response with respect to the effects of distortion in the propagated input waveform and makes it more accurate. In some embodiments, by adopting an input waveform with representative tail characteristics obtained by considering the various circuit topologies, the cell's output response, generated using a model characterized by an input waveform, is more likely to resemble the distorted propagated input waveform and is more likely to be accurate. Fig. 1 is a flowchart of a cell design process 100 and a chip design process 150 of an integrated circuit (IC) chip according to some embodiments. The processes 100 and 150 use one or more electronic design automation (EDA) tools to perform one or more stages or operations in the processes 100 and 150. Chip design process 150 aims to implement the IC chip design from high-quality specification to a physical layout, which is then verified for functionality, performance, and power. Cell design process 100 provides a physical design of cells and an abstraction of the physically designed cells for use as building blocks in chip design process 150. In some embodiments, cell design process 100 is performed separately from and prior to certain stages of chip design process 150, as shown in Fig. 1. In other embodiments, cell design process 100 is integrated into chip design process 150. In some embodiments, the cell design process 100 includes a cell design stage 102 and a cell characterization stage 104. In cell design stage 102, cell design is carried out at the transistor level, and the cell circuits are physically arranged and checked against specifications, technology-related information, and design rules. In cell characterization stage 104, the physically implemented cells are characterized to create, for example, runtime models and performance models for the cells. In some embodiments, netlists of the cells, the physically implemented cells, and the models for the cells are collected in a standard cell library and are available for use. The term "netlist," as used here and throughout this disclosure, refers to a representation of a circuit based on a graphic and / or text. Some embodiments of this disclosure may be used in this stage or in other stages of the cell design process 100. In some embodiments, the chip design process 140 includes a system design stage 152, a logic design stage 154, a logic synthesis stage 156, a physical implementation 158, a parasitic extraction stage 160, and a physical verification and electrical sign-off stage 162. In system design stage 152, the designer describes the IC chip in terms of larger modules, each fulfilling specific functions. Furthermore, an examination of options, including design architecture, is conducted to consider trade-offs in optimizing design specifications and costs, for example. Runtime requirements for the IC chip are specified in this stage. In logical design stage 165, the modules for the IC chip are described at the register transfer level (RTL) using VHDL or Verilog and are checked for functional accuracy. In logic synthesis stage 156, the modules for the IC chip, described in RTL, are translated into a gate-level netlist. In some embodiments, this stage also includes technology mapping of the logic gates and registers to available cells in the standard cell library created in cell design process 100. After logic synthesis, the IC chip design has completed the front-end design process and proceeds to the physical back-end design process in the following stages. In the physical implementation stage 158, the netlist is divided into blocks at the gate level, and a floor plan for the blocks is created. Mapped cells of logic gates and registers within the blocks are placed at specific locations on a chip area of ​​the IC chip design. A clock network is synthesized, and intermediate connections linking the cells are routed. In some embodiments, a runtime-determined placement and routing of the IC chip design is performed to plan a timing closure in an earlier design stage. Following this stage, a placed and routed layout of the IC chip is created. In parasitic extraction stage 160, a physical netlist is extracted from the IC chip layout. The physical netlist contains parasites such as parasitic resistors and capacitors introduced through the interconnects at the cells. In the physical verification and electrical approval stage 163, a runtime analysis and optimization is performed after relocation to the physical netlist to guarantee a runtime estimate. The runtime models in the cell library are used for delay calculation during the runtime analysis. Some embodiments of the present disclosure can be used in this stage or other stages of the chip design process 150. The layout of the IC chip is checked to ensure conformity with the netlist at the gate level and to ensure for manufacturing that it is free of electrical and lithographic problems. A stepwise fixing process can be performed to achieve a final approval of the design before submission (tape-out). The cell design process 100 and the chip design process 150 in Fig. 1 are examples. Other sequences of stages or operations, separation of stages, or additional stages or operations before, between, or after the stages shown are within the applicable scope of this disclosure. Fig. 2 is a functional block diagram of a software system 2 for creating a runtime library and performing a runtime analysis using the runtime library according to some embodiments. The software system 2 includes a library creation tool 20 and a static runtime analysis tool 25. The library creation tool 20 is configured to characterize a cell for delay calculation using input waveform generation that considers different circuit topologies that generate the same input transition characteristics. The library creation tool 20 is used, for example, in cell characterization stage 104 in cell design sequence 100 in Fig. 1. The library creation tool 20 includes a waveform acquisition module 202 and a cell characterization module 204.The waveform detection module 202 is configured to receive input transition characteristics and information about different circuit topologies of a pre-driver driving the cell in question, for example from the cell characterization module 204, and to obtain a representative input waveform for the different circuit topologies or different input waveforms for the different circuit topologies. The cell characterization module 204 is configured to receive a cell netlist 192 and one or more input waveforms with the input transition characteristics from the waveform detection module 202 and to characterize the cell with respect to the one or more input waveform(s) in order to create one or more entries in a runtime library 242 for delay calculation.The static runtime analysis tool 25 is configured to receive a physical netlist 244, obtained, for example, in the parasitic extraction stage 160 in Fig. 1, and to perform a static runtime analysis on the physical netlist using the runtime library 242. The static runtime analysis tool 25 is used, for example, in the physical verification and electrical sign-off stage 162 in the chip design process 150 in Fig. 1. The static runtime analysis tool 25 includes a runtime analysis graph generation and traversal module 252 and a delay calculation module 254. The runtime analysis graph generation and traversal module 252 is configured to formulate the physical netlist into a runtime graph and to traverse the runtime graph to perform input waveform propagation for delay calculation.The delay calculation module 254 is configured to receive the runtime library 242 from the cell characterization module 204 and a cell type and propagated input waveform to the cell from the runtime analysis graph creation and passthrough module 252, and to generate an output response of the cell as a propagated input waveform to a subsequent cell. Fig. 3 is a flowchart of a method 300 for characterizing a delay computation cell using input waveform generation, taking into account the different circuit topologies that generate the same input transition characteristics, according to some embodiments. In some embodiments, the method 300 is performed in the cell characterization stage 104 in the cell design sequence 100 in Fig. 1. In some embodiments, the method 300 is performed by the library creation tool 20 in Fig. 2. In operation 302, different input waveforms are obtained, corresponding to the different circuit topologies of a pre-driver that drives the cell, which result in the same input transition characteristics.In Operation 304, the cell is characterized using the various input waveforms to create entries in a runtime library associated with the input transition characteristics and the different circuit topologies. In Operation 306, it is checked whether there are any uncharacterized input transition characteristics in the runtime library. If so, in Operation 208, the input transition characteristics to be characterized are changed to other input transition characteristics enumerated in the runtime library, and the procedure returns to Operation 302. If not, at a connection or termination point 310, the cell's runtime library is created and is available for use. In Operation 302 in Fig. 3, various input waveforms corresponding to different circuit topologies of a pre-driver driving the cell, resulting in the same input transition characteristics, are constructed. Fig. 4 is a flowchart of a method for implementing Operation 302 in Fig. 3 according to some embodiments. In Operation 402, different netlists of the pre-driver driving the cell, configured in the different circuit topologies, are received. In Operation 404, the different input waveforms with the input transition characteristics are constructed using the different circuits of the pre-driver driving the cell. In Operation 402 of Fig. 3, different netlists of the pre-driver, which drives the cell using the different circuit topologies, are received. Fig. 5 contains schematic circuit diagrams of the different netlists 500, 520, and 540 of the pre-driver driving the cell, configured in the different circuit topologies according to some embodiments. The different netlists are netlist 500 for an average circuit topology, netlist 520 for a high-resistance (R) circuit topology, and netlist 540 for a high-fanout (FO) circuit topology. Netlist 500 for the average circuit topology includes the pre-driver 502, an FO 508 of the pre-driver 502, and an intermediate connection 506 between the pre-driver 502 and the FO 508 of the pre-driver.A cell 504 in the FO 508 is the cell to be characterized using an input waveform, a transition of a voltage Vinan to an input of the cell 504. In some embodiments, an intermediate connection segment is modeled by a resistive element with a resistance R and two capacitors, each with a capacitance C. Each of the capacitors is coupled between a respective end of the resistive element and ground. The number of intermediate connection segments contained in an intermediate connection is determined, for example, by the length of the intermediate connection. In the illustrative example of the average circuit topology in netlist 500, the intermediate connection 506 contains one intermediate connection segment and has an average R. Additionally, in the example of the average circuit topology, the FO 508 is an average FO of 3.Netlist 520 for the high-resistance (R) circuit topology and netlist 540 for the high-focal-order (FO) circuit topology are similar to netlist 500 for the average circuit topology, except for a difference in the interconnect resistance and FO, respectively. For example, in netlist 520 for the high-resistance circuit topology, an interconnect 526 that couples the FO 508 to the pre-driver 502 contains 10 interconnect segments. Therefore, the resistance of the interconnect 520 is 10Ω. In netlist 540 for the high-focal-order circuit topology, an FO 548 of the pre-driver 502 contains, for example, 60 cells. Thus, the FO 548 is 20 times the FO 508. In Operation 404 in Fig. 4, the various input waveforms with input transition characteristics are constructed using the different netlists 500, 520, and 540 of the pre-driver that drives cell 504, as shown, for example, in Fig. 5. Fig. 6 contains schematic waveform diagrams of the various input waveforms 600, 620, and 640, which have the same input transition characteristics and are constructed using the different netlists 500, 520, and 540, respectively, of the pre-driver that drives cell 504, according to some embodiments. The different input waveforms are input waveform 600 for the average circuit topology in netlist 500, input waveform 620 for the high-resistance circuit topology in netlist 530, and input waveform 640 for the high-resistance circuit topology in netlist 540.Each of the input waveforms 600, 620, and 640 is a rising transition of the voltage Vin with respect to time t at an input of cell 504 in the corresponding netlist 500, 520, or 540. In some embodiments, the rising transition of the voltage Vin for each of the input waveforms 600, 620, and 640 reaches a voltage Vlower equal to 30% of the difference between a steady-state voltage Vfinal and an initial voltage Vinitial at time tlower and reaches a voltage Vupper equal to 70% of the steady-state voltage Vfinal and the initial voltage Vinitial at time tupper. The input waveforms 600, 620, and 640 have corresponding times tlower and tupper. Therefore, the input waveforms 600, 620 and 640 have the same input transition characteristics, which in some embodiments result in an input transition time equal to tupper-tlower.In some embodiments, the input transition time of each input waveform 600, 620, and 640, generated using the corresponding netlist 500, 520, or 540, is made equal to each other by adjusting the capacitance of the corresponding intermediate connection 506, 526, or 506. However, each input waveform 600, 620, and 640 has a different tail section in which the voltage Vin rises from the voltage Vupper to the steady-state voltage Vfinal. The input waveform 620 for the high-resistance circuit topology has a longer tail section compared to the input waveform 600 for the average circuit topology. The input waveform 640 for the high-resistance circuit topology also has a longer tail section compared to the input waveform 600 for the average circuit topology.Furthermore, the tail section of the input waveform 540 has a kink due to the Miller capacitance coupled between the input and outputs of the cells in FO 548. In the example shown in Fig. 6, only rising input waveforms 600, 620, and 640 are depicted. However, a falling input waveform can be shown, which also has an input transition time between times tupper and tlower when the falling input waveform reaches a voltage Vupperb or a voltage Vlowerer, respectively, and a tail section from the voltage Vlower to a steady-state voltage Vfinal. Although input waveforms 600, 620, and 640 have the same input transition characteristics, the different tail sections of input waveforms 600, 620, and 640 cause different output responses from cell 504, which have essentially different delays with respect to their corresponding input waveforms 600, 620, and 640. When characterizing a delay model of cell 504 in the delay library, if only one of the different input waveforms 600, 620, and 640, such as input waveform 600 for the average circuit topology, is considered with respect to its input transition characteristics, the different tail sections of input waveforms 600, 620, and 640 are ignored. If, in the physical netlist generated from the parasitic extraction stage 160 in Fig.When cell 504 is configured in a circuit topology with high R or high FO, the actual propagated input waveform to cell 504 has a tail section that differs from that of the input waveform 600 used to characterize the propagation delay model of cell 504. The generated output response of cell 504 using the characterized propagation delay model therefore has a delay that differs significantly from that of the actual output response generated by a propagation delay model using the actual propagated input waveform. Thus, in order to account for a tail section of the propagated input waveform, in some embodiments, which are shown with reference to Fig. 11 and Fig. 2,13 described, the different input waveforms 600, 620 and 640 constructed in Operation 404 are used to characterize different time-of-flight models of cell 504 or a time-of-flight model of cell 504 with sensitivities to correct an output response generated using the time-of-flight model. Fig. 7 is a flowchart of another method that implements operations 302 in Fig. 3 according to some embodiments. Compared to the method described with reference to Fig. 4, which generates the input waveforms using different netlists with the various circuit topologies, the method in Fig. 7 collects waveforms from at least one chip and selects input waveforms from the collected waveforms. In operation 702, waveforms from at least one chip containing circuit topologies representative of the various circuit topologies driving the cell are collected. In operation 704, the waveforms from the at least one chip are grouped according to the input transition characteristics. In operation 706, the group of waveforms with input transition characteristics is sorted according to the tail characteristics.In operation 708, a waveform with representative tail characteristics is selected from the group of waveforms with input transition characteristics, and other waveforms with tail characteristics within the range of tail characteristics that contain the representative tail characteristics and have at least 50% occurrence of the representative tail characteristics in the at least one chip are selected as the various input waveforms. In some embodiments, operations 702, 704, and 706 are not always performed repeatedly when the process 300 in Fig. 3 backtracks to perform operation 302 for other input transition characteristics. That is, operations 702, 704, and 706 are performed before operation 302, which includes selection operation 708, and whenever the process 300 in Fig. 3 backtracks, selection operation 708 is performed for other input transition characteristics. In Operation 702 in Fig. 7, waveforms are collected from at least one chip containing circuit topologies representative of the various circuit topologies driving the cell. The term "the chip," as used here, refers to the chip design obtained, for example, from the physical verification and electrical drawing stage 162 in Fig. 1. In some embodiments, the chip is in the form of a physical netlist, and waveforms at circuit nodes in the physical netlist can be generated and probed, for example, using SPICE. Typically, the chip contains many propagation paths. Fig. 8 is a schematic representation showing waveform collection performed at an exemplary propagation path 800 in the chip according to some embodiments.The runtime path 800 begins at a lunch register 802, which sends data to a combinational logic circuit, represented, for example, as interconnected cells 810, 812, 814, and 816, and ends at a capture register 804, which captures data from the combinational logic circuit. In some embodiments, waveforms are collected at circuit nodes, for example, between register 802 and cell 810, cells 810 and 812, 812 and 814, and 814 and 816, and cell 816 and register 804, with a voltage probe 922 provided by SPICE. Part 830 of the combinational logic circuit is shown in more detail. In part 830, cell 912 and cell 814 are coupled by an intermediate connection 8302. An FO 8304 of cell 812 contains cell 814 and other cells. The voltage probe 822 is coupled to a circuit node between the intermediate connection 8302 and cell 814. In some embodiments, waveforms are collected from the critical propagation paths. For data propagation in propagation path 800 to be successful, the propagation delay between one clock period and the time at which the lunch register 802 outputs data in anticipation of a clock edge, the combinational logic circuit generates data in anticipation of the data output by the lunch register 802, and the acquisition register 804 acquires data from the combinational logic circuit must be positive. The clock period may be reduced by a clock offset. The smaller the propagation delay, the more critical the propagation path. The critical propagation path is more likely to contain one or more cells, such as cells 812 and 814, configured in circuit topologies with high resistance and / or high fanout, which manifest as a delay in the combinational logic circuit.Therefore, waveforms collected from the critical propagation paths are more representative of waveforms generated by circuit topologies with different values ​​for R and FO, such as waveforms 600, 620 and 640, shown for example in Fig. 6. Fig. 9 schematically shows waveform diagrams of waveforms obtained from operations 702, 704, and 706 in Fig. 7 according to some embodiments. Waveform diagram 902 shows waveforms collected in operation 702, which are described in detail with reference to Fig. 8. In operation 704 in Fig. 7, the waveforms from the at least one chip are grouped according to input transition characteristics. Waveform diagrams 912 and 914 show groups of waveforms grouped according to input transition characteristics. For example, the group of waveforms in waveform diagram 912 has an input transition time from voltage Vlower to voltage Vupper of 50 ps. The group of waveforms in waveform diagram 914 has an input transition time of 100 ps. In Operation 706 in Fig. 7, the group of waveforms with input transition characteristics is sorted according to the tail characteristics. Waveform diagrams 922, 294, and 926 show the group of waveforms with input transition characteristics of 50 ps, ​​sorted according to the tail characteristics. In some embodiments, the tail characteristics are a tail transition time of a waveform that transitions from a level at 70% of the difference between the steady-state voltage Vfinal and the initial voltage Vinitial to a level at 90% of the difference. The steady-state voltage Vfinal and the initial voltage Vinitial are described with reference to Fig. 6. For a rising transition, such as the waveform in waveform diagram 922, the levels at 70% and 90% of the difference between the steady-state voltage Vfinal and the initial voltage Vinitial are the voltage Vupper and a voltage Vtail, respectively.In some embodiments, the group of waveforms with input transition characteristics of 50 ps, ​​for example, is sorted in ascending order, as shown by the waveforms with tail characteristics of 40 ps, ​​60 ps and 90 ps in waveform diagrams 922, 924 and 926 respectively. In Operation 708, a waveform with representative tail characteristics is selected from the group of waveforms with input transition characteristics. In some embodiments, the mean tail characteristics are chosen as the representative tail characteristics. Furthermore, in Operation 708, other waveforms with tail characteristics within a range of tail characteristics that includes the representative tail characteristics and exhibits at least 50% occurrence of the tail characteristics in the at least one chip are also selected as input waveforms. The group of waveforms with input transition characteristics of 50 ps contains three exemplary waveforms. In other examples, more waveforms are present in a group, and a distribution of the tail characteristics of the waveforms in the group can be obtained. In addition to the mean tail characteristics, which are the 50th percentile of the distribution, percentiles such as the 25th and 75th percentiles are also selected.The range of tail characteristics bounded by the 25th percentile and the 75th percentile encompasses at least 50% of the population in the distribution. Fig. 10 is a flowchart of another method that implements Operation 302 in Fig. 3 according to some embodiments. Compared with the method described with reference to Fig. 7, which selects input waveforms with various tail characteristics from waveforms collected by at least one chip, the method in Fig. 10 constructs input waveforms by fitting linear Y-MOS equations to various tail characteristics collected by at least one chip. In Operation 1002, tail characteristics are collected from waveforms generated in at least one chip containing circuit topologies representative of the various circuit topologies of the pre-driver driving the cell.In Operation 1004, representative tail characteristics are selected from the collected tail characteristics, and other tail characteristics within a range of tail characteristics that includes the representative tail characteristics and exhibits at least 50% occurrence of tail characteristics in at least one chip are also selected. In Operation 1006, a linear Y-MOS equation is fitted to the input transition characteristics and tail characteristics of the various tail characteristics to obtain simultaneous equations. In Operation 1008, the simultaneous equations are solved to obtain a fitted linear Y-MOS equation. In Operation 1010, an input waveform is constructed using the linear Y-MOS equation. In Operation 1012, it is checked whether any selected tail characteristics are not constructed.If so, in Operation 1014 the tail characteristics to be constructed are changed to other tail characteristics within the selected tail characteristics, and the procedure returns to Operation 1006 to construct an input waveform with the tail characteristics. If not, the various input waveforms are constructed, and the procedure from Operation 302 in Fig. 10 continues with Operation 304 in Fig. 3. In Operation 1002, tail characteristics are collected from waveforms generated in at least one chip containing circuit topologies representative of the various circuit topologies of the pre-driver driving the cell. In some embodiments, the tail characteristics are a tail ratio. Fig. 11 is a schematic waveform diagram of an exemplary input waveform 1100 to illustrate a tail ratio. The input waveform 1100 is a falling transition of a voltage v with respect to time t at an input of the cell to be characterized. The voltage v is assumed to be normalized with respect to a transition region of the input waveform 1100 and to have a range of [0,1]. In some embodiments, the falling transition of the voltage v reaches a voltage V above 0.7, i.e.,, 30% of the transition range of the input waveform 1100, at time tupper; reaches a voltage Vlower equal to 0.3, i.e., 70% of the transition range of the input waveform 1100, at time tlower; and reaches a voltage Vtail equal to 0.1, i.e., 90% of the transition range of the input waveform 1100, at time ttail. A tail ratio is obtained by considering input transition characteristics obtained from a portion of the input waveform 1100 between voltages Vupper and Vlower, and supplementary input transition characteristics obtained from a portion of the input waveform 1100 between voltages Vlower and Vtail. In some embodiments, the tail ratio of the falling input waveform 800 is calculated by the following formula: where tlower-tupper are the input transition characteristics and ttail-tlower are the complementary input transition characteristics. In Fig. 11, the input waveform 1100 is a falling input waveform. In the case of a rising input waveform, the voltage v reaches a voltage Vlower equal to 0.3, i.e., 30% of the transition region of the rising input waveform, first at time tlower; reaches a voltage Vupper equal to 0.7, i.e., 70% of the transition region of the rising input waveform, subsequently at time tupper; and then reaches a voltage Vtail equal to 0.9, i.e., 90% of the rising input waveform, at time ttail. Therefore, a formula for calculating the tail ratio for a rising input waveform has the following form: As described with reference to Figures 5 and 6, input waveforms generated by a pre-driver driving the cell, configured in different circuit topologies, can have the same input transition characteristics but different tail sections. Considering the tail ratio of input waveform 1100, another input waveform with the same input transition characteristics but with different supplementary input transition characteristics due to a different tail section can be distinguished from input waveform 1100. Therefore, the various received tail ratios can be used to construct input waveforms that have the same input transition characteristics but different tail sections. A method for selecting tail ratios representing different circuit topologies is described below. Figure 12 is a schematic probability density function (pdf) of a tail ratio distribution of waveforms collected in the chip according to some embodiments. Similar to the embodiments described with reference to Figures 7 and 8, waveforms are collected from many propagation paths in the chip. These propagation paths traverse cells configured in circuit topologies with wide ranges of interconnect resistance and fanouts. Therefore, the collected waveforms have different tail ratios. The tail ratios of the collected waveforms form a tail ratio distribution. The tail ratio distribution is then transformed into a pdf that reflects the probabilities of different tail ratios occurring in the tail ratio distribution.In Operation 1004, representative tail characteristics are selected from the collected tail characteristics, and other tail characteristics within a range of tail characteristics that includes the representative tail characteristics and represents at least 50% of the occurrences of tail characteristics in which at least one chip is located are likewise selected. In some embodiments, the representative tail characteristics and other tail characteristics in Operation 1004 are selected from the pdf. For example, the mean tail ratio, the 1st percentile tail ratio, and the 99th percentile tail ratio are selected to cover the representative tail ratio as well as the more extreme tail ratios collected from the chip. Selection from other percentiles of the pdf or other methods for selecting tail ratios are within the considered scope of protection of this disclosure. In Operation 1006, a linear Y-MOS equation is fitted to the input transition characteristics and tail characteristics of various tails to obtain simultaneous equations. Fig. 13 is a schematic circuit diagram of a circuit 1300 for deriving the linear Y-MOS equation according to some embodiments. The circuit 1300 includes an NMOS 1302 and a concentrated capacitor CL. One source of the NMOS 1302 and one terminal of the concentrated capacitor CL are grounded, one drain of the NMOS 1302 and another terminal of the concentrated capacitor CL are coupled together, and one gate of the NMOS 1302 is coupled to a power supply VDD.A differential equation is obtained with respect to circuit 1300 in a state of discharge of the concentrated capacitor CL through the NMOS operating at the linear region, with the gate of NMOS 1002 fully turned on, and is shown below: where Iline is the discharge current from the concentrated capacitor CL through NMOS 1302; v is the drain-to-source voltage of NMOS 1302; a and b are coefficients of first-order and second-order terms, respectively, in the differential equation; and t is time. The linear Y-MOS equation can be derived from differential equation (3) and is shown below: To fit the linear Y-MOS equation (4) to the input transition characteristics and the tail ratio, three points (Vupper, tupper), (Vlower, tlower), and (Vtail, ttail) are identified, for example, on a falling input waveform. Then, the points corresponding to the input transition characteristics tlower-tupper are used to create one of the simultaneous equations, and the points corresponding to the tail ratio are used to create the other simultaneous equation. Therefore, two equations with two unknowns, a and b, are obtained. In Operation 1008, the simultaneous equations are solved to obtain a fitted linear Y-MOS equation. Solving these equations resolves the two unknowns a and b. The resulting linear Y-MOS equation, with the values ​​a and b solved, is the linear Y-MOS equation fitted to the input transition characteristics and the tail ratio. In Operation 1010, the fitted linear Y-MOS equation is used to construct an input waveform with the input transition characteristics and the tail ratio. For example, voltages at different times can now be obtained from the fitted linear Y-MOS equation, and an input waveform can be constructed using the voltages at these different times. The procedure for Operation 302 then proceeds back in Fig. 10 to fit the linear Y-MOS equation with respect to different tail characteristics and to construct an input waveform with the different input transition characteristics and the different tail characteristics until each of the different tail characteristics chosen in Operation 1004 is fitted with respect to it. The procedure for Operation 302 then continues with Operation 304 in Fig. 3. In Operation 304 in Fig. 3, the cell is characterized using the various input waveforms to create entries in a runtime library associated with the input transition characteristics and the different circuit topologies. Fig. 14 shows flowcharts of a method implementing Operation 304 in Fig. 3 and a corresponding method 1450 for performing waveform propagation during a runtime analysis on a physical netlist according to some embodiments. In Operation 1402, a fully characterized model associated with the input transition characteristics and with one of the various constructed input waveforms is created in the cell's runtime library. Operation 1404 checks whether a complete model has not been created for any of the various input waveforms.If so, the procedure continues with operation 1406 to change the input waveform to be generated to a different input waveform from the various input waveforms, and returns to operation 1402. If not, the procedure continues from operation 304 in Fig. 14 with operation 306 in Fig. 3, which checks whether other input transition characteristics need to be characterized. Once the cell's runtime library is created at connection point 310, procedure 1450 is performed using the runtime library. In some embodiments, procedure 1450 is performed at the physical verification and electrical acknowledgment stage 162 in Fig. 1. In some embodiments, procedure 1450 is performed by the runtime analysis tool 25 in Fig. 2. In operation 1452, a runtime analysis is performed on the physical netlist to obtain the propagated input waveform to an input of the cell. In operation 1454, input transition characteristics of the propagated input waveform are used to identify entries of different input waveforms among the input transition characteristics in the runtime library.In operation 1456, the propagated input waveform is matched with the various input waveforms in the runtime library to identify one of the entries to generate an output response from the cell. In Operation 1402, a fully characterized model, linked to the input transition characteristics and to one of the various constructed input waveforms, is created in the cell's delay library. A fully characterized model is a delay model for generating an output response of the cell, characterized using the input waveform, and is used independently of other entries in the library that are characterized using other input waveforms. In some embodiments, the delay model is a current source model. Fig. 15 is a schematic representation of a delay library 1500 of the cell according to some embodiments. In some embodiments, performing Operation 1402 creates a fully characterized model with respect to the input transition characteristics, such as the first.Input transition characteristics, and the input waveform, like a waveform of an average circuit topology, created in the runtime library 1500. Operations 1404 and 1406 continue the procedure from Operation 304, reverting to Operation 1402 to create fully characterized models for other input waveforms, such as a waveform for a circuit topology with high R and a waveform for a circuit topology with high FO, under the first input transition characteristics in runtime library 1500. Then, characterization with respect to the first input transition characteristics is complete. As described with reference to Figures 7 and 10, the different input waveforms for fully characterizing models can also be input waveforms with different tail characteristics. The procedure then continues from operation 306 in Fig. 3, starting with operation 304 in Fig. 14. For characterization with respect to the second input transition characteristics in runtime library 1500, procedure 300 returns to operation 302 to obtain various input waveforms with the second input transition characteristics, such as constructing different input waveforms for the average circuit topology, the high-R circuit topology, and the high-FO circuit topology with the second input transition characteristics. Procedure 300 then continues with operation 1402 to create fully characterized models for the various input waveforms with the second input transition characteristics. The process is repeated for other input transition characteristics until all input transition characteristics to be characterized in the runtime library have been processed.Once the cell's runtime library 1500 is created, a model can be viewed using input transition characteristics and an input waveform as a key. In Operation 1452, a time-of-flight analysis is performed on a physical netlist to obtain a propagated input waveform to an input of the cell. To perform a time-of-flight analysis on a physical netlist, the physical netlist is formulated as a time-of-flight graph. By traversing the time-of-flight graph node by node, a propagated input waveform received at an input of a node is propagated to an output of that node as a propagated input waveform to the next node. The node containing the cell, characterized using the procedure described with reference to Figures 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 to 13, is assumed to be the current node for waveform propagation.In the process of performing a runtime analysis, the propagated input waveform to the input of the cell of the current node is obtained. In Operation 1454, input transition characteristics of the propagated input waveform to the cell are used to identify entries of different input waveforms among the input transition characteristics in the time-of-flight analysis. For example, assuming that the propagated input waveform has input transition characteristics corresponding to the first input transition characteristics in time-of-flight library 1500 in Fig. 15, the entries among the first input transition characteristics in time-of-flight library 1500 in Fig. 15 are then identified. In Operation 1456, the propagated input waveform is matched with the various input waveforms in the runtime library to identify one of the entries for generating an output response for the cell. For example, if the cell is configured in a high-R circuit topology when driven by a pre-driver in the physical netlist, the generated propagated input waveform is a better match for the high-R circuit topology waveform in runtime library 1200. Consequently, the fully characterized model is identified under the high-R circuit topology waveform to generate the output response of the current node's cell. The generated output response is then used as a propagated input waveform for an input of a cell in the next node. In the embodiments described with reference to Figs. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 to 15, the cell is fully characterized with respect to the various input waveforms constructed using different pre-driver circuit topologies that drive the cell, resulting in the same input transition characteristics. By further performing waveform tuning to identify the input waveform that is closer to the propagated input waveform, not only in the input transition characteristics but also in another section, such as the tail section of the waveform, distortion in the propagated input waveform is reduced with respect to the input waveform used to characterize the cell.Therefore, the cell's output response is generated using the model characterized by the input waveform, which is more similar to the common input waveform and is more accurate. Figure 16 shows flowcharts of another method implementing Operation 304 in Figure 3, and of a corresponding method 1650 for performing waveform propagation while performing a time-of-flight analysis on a physical netlist according to some embodiments. Compared with the methods described with reference to Figure 14, the methods described with reference to Figure 16 create a fully characterized model for one of the various input waveforms and create sensitivities for some of the various input waveforms to correct an output response generated using the fully characterized model. In Operation 1602, one or more fully characterized models, associated with the input transition characteristics and with one or more input waveforms of the various input waveforms, are created in the time-of-flight library.In Operation 1604, sensitivities associated with the input transition characteristics or with the other input waveforms of the various input waveforms are created in the delay library. The procedure then continues from Operation 304 in Fig. 16 with Operation 306 in Fig. 3, which checks whether further input transition characteristics need to be characterized. In some embodiments, after the cell's runtime library has been created at connection point 310, method 1650 is performed using the runtime library. In some embodiments, method 1650 is performed at the physical verification and electrical tracing stage 162 in Fig. 1. In some embodiments, method 1450 is performed by the runtime analysis tool 25 in Fig. 2. In operation 1452, a runtime analysis is performed on the physical netlist to obtain a propagated input waveform for an input of the cell. In operation 1454, input transition characteristics of the propagated input waveform are used to identify entries of different input waveforms among the input transition characteristics in the runtime library. Operations 1452 and 1454 in method 1650 are similar to those of method 1450 in Fig. 14, and their details are omitted here.In Operation 1456, the propagated input waveform is projected onto a space of input waveforms corresponding to different circuit topologies to determine a location of the propagated input waveform in space. In Operation 1658, an output response is generated using a fully characterized model in one of the identified entries. In Operation 1660, a correction to the output response is applied using at least one sensitivity in the identified entries and the location of the propagated input waveform in space. In Operation 1602 in Fig. 16, one or more fully characterized models, associated with the input transition characteristics and with one or more input waveforms of the various input waveforms, are created in the delay library. In Operation 1604, sensitivities associated with the input transition characteristics or with other input waveforms of the various input waveforms are created. Fig. 17 is a schematic diagram for a delay library 1700 of the cell according to some embodiments. In some embodiments, in Operations 1602 and 1604, input transition characteristics, such as the first...Input transition characteristics, the various input waveforms for the different circuit topologies, such as the circuit topology with average R and FO, the circuit topology with high R and average FO, and the circuit topology with average R and high FO, are stored in the runtime library 1700, and one or more fully characterized models or sensitivities are created under the different input waveforms. In other embodiments, in operations 1602 and 1604 for input transition characteristics, such as the first input transition characteristics, the effects of some circuit topology aspects, such as resistance and fanout, on the different input waveforms are evaluated, and the evaluated results are stored in the runtime library 1700.One or more fully characterized models and sensitivities are created from the evaluated results of the various input waveforms. For simplicity, the fully characterized models and sensitivities are subsequently referred to as residing under the corresponding circuit topologies in the 1700-time-delay library. As soon as a propagated input waveform is received at the input of the cell in Operation 1452 in Fig. 16, input transition characteristics of the propagated input waveform are used to identify entries of different input waveforms among the input transition characteristics in runtime library 1700 in Operation 1454. In the following example, it is assumed that the identified entries are among the first input transition characteristics in runtime library 1700. In Operation 1656, the propagated input waveform is projected onto a space of input waveforms corresponding to different circuit topologies in order to determine a location of the propagated waveform in space. Fig. 18 is a schematic representation of a space 1800 of input waveforms corresponding to different circuit topologies, according to some embodiments. In space 1800, the input waveform corresponding to the circuit topology with average R and average FO is located at the origin. A high FO axis represents the effect of a higher FO on the input waveforms, and a high R axis represents the effect of a higher R on the input waveforms. In the example shown for illustration in Fig. 18, the high FO axis and the high R axis are orthogonal.In other examples (not shown), the axes of space are not orthogonal, and therefore an increase or decrease in the effect of FO is accompanied by an increase or decrease in the effect of R. In some embodiments, by performing operation 1656, the propagated input waveform is projected onto space 1800 at a location 1802. The high FO axis component of location 1802 reflects the effect of a higher FO on the propagated input waveform with respect to the input waveform of the average R and average FO, and the high R axis component of location 1802 reflects the effect of the higher R on the propagated input waveform with respect to the input waveform for the average R and average FO. Operation 1658 generates an output response using a fully characterized model in one of the identified entries. By performing Operation 1658, the output response is generated using the fully characterized model under the circuit topology with average R and average FO. In Operation 1660, a correction is applied to the output response using at least one sensitivity in the identified entries and the position of the propagated input waveform in space. Fig. 19 is a schematic waveform diagram of output responses 1902, 1904, and 1904 without sensitivity correction, with high resistance sensitivity correction, and further with high fanout sensitivity correction according to some embodiments. In Fig. 19, an output response is a transition of a voltage Voutin with respect to time t at an output of the cell in response to an input waveform to the input of the cell. Output response 1902 is the output response generated in Operation 1658 using the fully characterized model under the average R and average FO circuit topology in the identified entries in the runtime library 1700.In the identified entries in runtime library 1700, sensitivities for correcting the output response 1902, which is generated using the fully characterized model under the average R and average FO circuit topology with respect to the effect of a different R and FO on the propagated input waveform, accompany the fully characterized model. By applying a higher R correction to the output response 1902 using the sensitivity of a circuit topology with high R and high FO and the high R component at position 1802 of the propagated input waveform in Fig. 18, the output response 1904, corrected with respect to the higher R, is obtained.Then, by applying a correction of the higher R to the output response 1904 using the sensitivity of the circuit topology with average R and high FO and the high FO component at position 1902 of the propagated input waveform, the output response 1906, corrected with respect to the higher R and the higher FO, is obtained. Fig. 20 is a schematic representation of another runtime library 2000 of the cell according to some embodiments. Compared with the embodiments described with reference to Fig. 17, one or more fully characterized models or sensitivities under different tail characteristics are created in the runtime library 2000 in Fig. 20. In Operation 1602, for the first input transition characteristics, two fully characterized models, like the first and second fully characterized models, are created using input waveforms that have a second selected tail ratio and a fifth selected tail ratio, and stored in the runtime library 2000 under the second selected tail ratio and the fifth selected tail ratio. In Operation 1604, sensitivities for correcting an output response, created using the first selected tail ratio, are created using the second selected tail ratio and the fifth selected tail ratio.The output response correction sensitivities generated using the fully characterized model are created using input waveforms exhibiting either the first selected tail characteristic or the third selected tail characteristic, and stored in the runtime library 2000 under the first and third selected tail characteristic categories. Response correction sensitivities generated using the second fully characterized model are created and stored in the same manner. After receiving a propagated input waveform at the cell input in Operation 1452 in Fig. 16, input transition characteristics of the propagated input waveform are used to identify different tail ratios among the input transition characteristics in runtime library 2000 in Operation 1454. The identified entries among the first input transition characteristics in runtime library 2000 are subsequently used as an example. In Operation 1656, the propagated input waveform is projected onto a space of input waveforms corresponding to different circuit topologies in order to determine a location of the propagated input waveform within that space. Fig. 21 is a schematic representation of a space 2100 of input waveforms corresponding to different circuit topologies, according to some embodiments. The space 2100 is divided into a line for tail characteristics. Within the space 2100, the input waveforms with the 2nd selected tail characteristic 2104 and the 5th selected tail characteristic 2101 are shown as solid circles, and the input waveforms with the 1st selected tail characteristic 2102, the 3rd selected tail characteristic 2106, and the 4th selected tail characteristic 2108 are shown as empty circles. By performing Operation 1656, the propagated input waveform is projected onto the space 2100 at a location 2112. The common input waveform has tail characteristics that define the 3rd.The selected tail parameters are closest to 2106 and are slightly above the 3rd selected tail parameters. In operation 1658, an output response is generated using a fully characterized model in one of the identified entries. Since position 2112 of the propagated input waveform is close to the third selected tail characteristic 2106, the output response is first generated using the first fully characterized model under the second selected tail characteristic 2104. In Operation 1660, a correction is applied to the output response using at least one sensitivity in the identified entries and the position of the propagated input waveform in space. Since position 2112 is closest to the third selected tail characteristic 2106, the sensitivity corresponding to the third selected tail characteristic in runtime library 2000 and the distance between position 2112 of the propagated input waveform and the second selected tail characteristic are used to apply the correction to the output response generated using the first fully characterized model. In the embodiments described with reference to Figures 3 to 13 and 16 to 21, the cell is fully characterized with respect to some of the different input waveforms constructed using the various circuit topologies of the pre-driver driving the cell, which result in the same input transition characteristics, and is characterized for sensitivities with respect to other of the different input waveforms. By further applying a sensitivity correction to the output response, generated considering only the input transition characteristics of the propagated input waveform, based on a projected position of the propagated input waveform in the space of the different input waveforms, the effects of distortion in the propagated input waveform with respect to the input waveform used to characterize the cell are taken into account.Therefore, the cell's output response is corrected for the effects of distortion in the propagated input waveform and is more accurate. Fig. 22 is a flowchart of another method 2200 for characterizing a delay calculation cell using input waveform generation, taking into account different circuit topologies that generate the same input transition characteristics, according to some embodiments. Compared with method 300 in Fig. 3, method 2200 uses a single waveform with representative tail characteristics as the input waveform for characterizing the cell with respect to input transition characteristics. In operation 2202, an input waveform with input transition and tail characteristics is obtained, which are selected taking into account different circuit topologies of a pre-driver driving the cell, resulting in the same input transition characteristics.In operation 2204, the cell is characterized using the input waveform to create an entry in a runtime library associated with the input transition characteristics. In operation 2206, it is checked whether any input transition characteristics listed in the runtime library are uncharacterized. If so, in operation 2208, the input transition characteristics to be characterized are changed to other input transition characteristics listed in the runtime library, and the procedure returns to operation 2202. If not, the cell's runtime library is created at a termination point or a connection point 2210. Operations 2204 and 2206 are similar to operations 302 and 304 in Fig. 3, except for a representative input waveform used to characterize the cell with respect to input transition characteristics.The various embodiments for implementing operation 302 can be adapted to implement operation 2202, as described in more detail below. An embodiment for operation 2204, which differs from the embodiments for operation 304, is also provided below. Operations 2206, 2208, and 2210 are similar to operations 306, 308, and 310 in Fig. 3, and a more detailed description is omitted. Fig. 23 is a flowchart of a method for implementing operation 2202 in Fig. 22 according to some embodiments. Compared with the method described with reference to Fig. 7, the method in Fig. 23 includes operations 702, 704, and 708, which are the same as operations 702, 704, and 706 in Fig. 7, and one operation that differs from operation 708 in the method in Fig. 7. The description of the operations in Fig. 23 that are the same as those in Fig. 7 is omitted. In operation 2308, a waveform with representative tail characteristics is selected from the group of waveforms with the input transition characteristics as the input waveform. In some embodiments, similar to operation 708 in Fig. 7, the mid-tail characteristics are selected as the representative tail characteristics. The method for arranging the mid-tail characteristics has been described in detail with reference to Fig.9 described and is omitted here. Similar to the embodiments described with reference to Fig. 7, in some embodiments the operations 702, 704 and 706 in the method in Fig. 3 are not repeatedly performed whenever the method 2200 in Fig. 22 returns to perform operation 2202 for other input transition characteristics. Fig. 24 is a flowchart of another method that implements operation 2202 in Fig. 22 according to some embodiments. Compared with the method described with reference to Fig. 10, the method in Fig. 24 includes operations 2402, 2408, and 2410, which are the same as operations 1002, 1008, and 1010 in the method in Fig. 10, and operations 2404 and 2406, which differ from operations 1004 and 1006 in Fig. 10. Operation 2402, which is the same as operation 1002, is omitted. In operation 2404, representative tail characteristics are selected from the collected tail characteristics. Operation 2404 differs from operation 1004 in that individual representative tail characteristics are selected from the collected tail characteristics. The procedure for selecting representative tail characteristics for operation 2404 is similar to that for operation 1004 and is omitted here.In operation 2406, a linear Y-MOS equation is fitted to the input transition characteristics and the representative tail characteristics to obtain simultaneous equations. Operations 2408 and 2410, which are identical to operations 1008 and 1010, are omitted. Fig. 25 is a flowchart of a method 2500 for performing waveform propagation during time-of-flight analysis on a physical netlist according to some embodiments. Compared with method 1450 in Fig. 14 and method 1650 in Fig. 16, method 2500 uses only the input transition characteristics to identify a corresponding entry for generating an output response from the cell. After the cell's time-of-flight library is created at the connection point 2210, method 2500 is performed using the time-of-flight library. In some embodiments, method 2500 is performed at the physical verification and electrical tracing stage 162 in Fig. 1. In some embodiments, method 2500 is performed by the time-of-flight analysis tool 25 in Fig. 2.In Operation 2502, a runtime analysis is performed on the physical netlist to obtain a propagated input waveform for a cell input. Operation 2502 is similar to Operation 1452 in Fig. 14 and is omitted here. In Operation 2504, input transition characteristics of the propagated input waveform are used to identify an entry that is associated with the input transition characteristics in the runtime library in order to generate a cell output response. Operation 2504 is similar to Operations 1454 and 1456 in Fig. 14, except that the entry found using the input transition characteristics of the propagated input waveform is used directly to generate the cell output response, and waveform tuning is used to identify one of the entries among the input transition characteristics, which is omitted here. In the embodiments described with reference to Figures 22, 23, 24 to 25, the cell is fully characterized with respect to input waveforms using mean-tail characteristics that are representative of the tail characteristics of the various input waveforms constructed using the different circuit topologies of the pre-driver driving the cell, which result in the same input transition characteristics. By adopting the mean-tail characteristics for constructing the input waveform to characterize the cell, distortion in the propagated input waveform with respect to the input waveform used to characterize the cell is more likely to be reduced.Therefore, the output response of the cell, generated using the model characterized using the input waveform, is more likely to be similar to the distorted propagated input waveform and is more likely to be accurate. Fig. 26 is a block diagram of a hardware system 2600 for implementing the software system implementation forms described with reference to Fig. 2, and process implementation forms described with reference to Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24 to Fig. 25, according to some embodiments. The system 2600 contains at least one processor 2602, one network interface 2604, one input / output (I(O)) device 2606, one memory 2608, one main memory 2612, and one bus 2610. The bus 2612 connects the network interface 2604, the input / output (I(O)) device 2606, the memory 2608, and the main memory 2612 to the processor 2602. In some embodiments, the main memory 2612 comprises random-access memory (RAM) and / or another volatile memory device and / or read-only memory (ROM) and / or another non-volatile memory device. The main memory 2612 contains a kernel 26124 and a user space 26122, which is configured to store program instructions executed by the processor 2602 and data accessed by the program instructions. In some embodiments, the network interface 2604 is configured for remote network access to program instructions and the data accessed by the stored program instructions. The I / O device 2606 includes an input device and an output device configured to enable user interaction with the system 2600. The input device includes, for example, a keyboard, a mouse, etc. The output device includes, for example, a display, a printer, etc. The storage device 2608 is configured to store program instructions and the data accessed by the program instructions. The storage device 2608 includes, for example, a magnetic disk and an image disk. In some embodiments, when the program instructions are executed, the processor 2602 is configured as the software system 2 described with reference to Fig. 2, or configured to perform procedures described with reference to Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24 to Fig. 25. In some embodiments, the program instructions are stored in a non-transient, computer-readable recording medium, such as one or more image disk(s), hard disk(s) and non-volatile working memory device(s). In some embodiments, in a method performed by at least one processor, a cell is characterized by the at least one processor with respect to input transition characteristics, taking into account different circuit topologies of a pre-driver that drives the cell, which lead to the same input transition characteristics. In some embodiments, a system includes at least one processor and at least one memory. The at least one processor is configured to execute program instructions that configure the at least one processor as a library creation tool. The library creation tool is configured to characterize a cell with respect to input transition characteristics, taking into account different circuit topologies of a pre-driver that drives the cell, all of which result in the same input transition characteristics. The at least one memory is configured to store the program instructions. The preceding description contains exemplary operations, but these operations need not necessarily be performed in the order presented. Operations may be added, replaced, performed in a different order, and / or eliminated as needed in accordance with the nature and scope of protection of the present disclosure. Therefore, the scope of protection of the disclosure should be determined with reference to the following claims together with the full scope of protection of equivalences to which such claims entitle.

Claims

A method for designing an IC chip, comprising: characterizing by at least one processor of a cell (504) with respect to input transition characteristics, taking into account different circuit topologies of a pre-driver (502) driving the cell (504) that result in the same input transition characteristics, wherein the characterization comprises: obtaining different input waveforms with the input transition characteristics taking into account the different circuit topologies (302); and characterizing the cell using the different input waveforms to create entries in a library (304) associated with the input transition characteristics and the different circuit topologies, wherein the characterization of the cell using the different input waveforms to create entries associated with the input transition characteristics,in a library (304) comprises: for each of the different input waveforms, creating one of the entries that is used independently of the other entries in the library (150); and wherein the procedure further comprises: performing a time-of-flight analysis on a netlist such that a common input waveform with the input transition characteristics is matched to the cell with the different input waveforms in order to identify one of the entries in the library to generate an output response of the cell (1452, 1454, 1456), wherein obtaining different input waveforms with the input transition characteristics, taking into account the different circuit topologies (302), involves obtaining different input waveforms with the input transition characteristics and different first characteristics, wherein the different circuit topologies of the pre-driver driving the cell lead to the different first characteristics.and the various first characteristics are selected from the first characteristics collected from at least one chip comprising circuit topologies representative of the various circuit topologies of the pre-driver driving the cell, wherein the first characteristics are tail characteristics, the input transition characteristics include a first section of the corresponding input waveforms, and the tail characteristics include a second section of the corresponding waveform after the first section of the corresponding waveform, and wherein each of the input waveforms is a rising transition of a voltage Vin with respect to a time t at an input of the cell (504) in a corresponding netlist (500, 520, 540) of the pre-driver, wherein the rising transition of the voltage Vin for each of the input waveforms (600, 620,640) a voltage Vlower equal to 30% of a difference between a steady-state voltage Vfinal and an initial voltage Vinitial is reached at time tlower and a voltage Vupper equal to 70% of the difference between the steady-state voltage Vfinal and the initial voltage Vinitial is reached at time tupper, and wherein the input transition characteristics are an input transition time equal to tupper-tlower, or wherein each of the input waveforms is a decaying input waveform which also has an input transition time between times tupper and tlower when the decaying input waveform reaches a voltage Vupper or a voltage Vlower, and has a tail section from the voltage Vlower to a steady-state voltage Vfinal. The method of claim 1, wherein obtaining various input waveforms with input transition characteristics and various other characteristics comprises: collecting waveforms from the at least one chip comprising the circuit topologies representative of the various circuit topologies of the pre-driver driving the cell (702); grouping the waveforms from the at least one chip according to input transition characteristics (704); sorting the group of waveforms with the input transition characteristics according to first characteristics (706); and selecting a waveform with representative first characteristics from the group of waveforms with the input transition characteristics, and from other waveforms with first characteristics in a range of first characteristics comprising the representative first characteristics and containing at least 50% occurrence of first characteristics in the at least one chip, as the input waveforms with the various first characteristics (708). The method of claim 1, wherein obtaining various input waveforms with the input transition characteristics and various other characteristics comprises: collecting first characteristics of waveforms generated in the at least one chip comprising the circuit topologies representative of the various circuit topologies of the pre-driver driving the cell (1002); selecting representative first characteristics from the collected first characteristics and other first characteristics in a range of first characteristics comprising the representative first characteristics and including at least 50% occurrence of first characteristics in the at least one chip (1004); and constructing the various input waveforms by fitting an equation to the input transition characteristics and each selected first characteristic (1010). The method of claim 1, wherein obtaining different input waveforms with input transition characteristics taking into account the different circuit topologies comprises: receiving netlists (500, 520, 540) of the pre-driver driving the cell, which is configured in the different circuit topologies (402); and constructing the different input waveforms (600, 620, 640) using the different netlists of the pre-driver driving the cell (404). Method according to claim 4, wherein the different netlists comprise a first netlist (520) and a second netlist (540) of the pre-driver that drives the cell; in the first netlist (520) the pre-driver drives the cell through a longer wire (526) but has a smaller fanout (508); and in the second netlist (540) the pre-driver drives the cell through a shorter wire (506) but has a larger fanout (548). System comprising: at least one processor (1602) configured to execute program instructions, which configure the at least one processor as: a library creation tool (20) configured to characterize a cell with respect to input transition characteristics, taking into account different circuit topologies of a pre-driver driving the cell that result in the same input transition characteristics; and at least one memory (2612) configured to store the program instructions, wherein the library creation tool (20) comprises: a waveform preservation module (202) configured to preserve an input waveform with the input transition characteristics and representative first characteristics, wherein the different circuit topologies of the pre-driver driving the cell result in different first characteristics, wherein the representative first characteristics are selected from the first characteristics.which are collected by at least one chip comprising circuit topologies representative of the various circuit topologies of the pre-driver driving the cell; and a cell characterization module (204) configured to characterize the cell using the input waveform to create an entry in a library associated with the input waveform, wherein the first characteristics are tail characteristics, the input transition characteristics include a first section of the corresponding input waveforms, and the tail characteristics include a second section of the corresponding waveform following the first section of the corresponding waveform, wherein each of the input waveforms is a rising transition of a voltage Vinin with respect to a time t at an input of the cell (504) in a corresponding netlist (500, 520, 540) of the pre-driver,wherein the rising transition of the voltage Vin for each of the input waveforms (600, 620, 640) reaches a voltage Vlower equal to 30% of the difference between a steady-state voltage Vfinal and an initial voltage Vinitial at time tlower and reaches a voltage Vupper equal to 70% of the difference between the steady-state voltage Vfinal and the initial voltage Vinitial at time tupper, and wherein the input transition characteristics are an input transition time equal to tupper-tlowers, or wherein each of the input waveforms is a falling input waveform which also has an input transition time between times tupper and tlower when the falling input waveform reaches a voltage Vupper or a voltage Vlower, and has a tail section from the voltage Vupper to a steady-state voltage Vfinal. System according to claim 6, wherein the waveform preservation module (202) is configured to obtain an input waveform with the input transition characteristics and representative first characteristics by performing operations comprising: collecting waveforms from the at least one chip comprising the circuit topologies representative of the various circuit topologies of the pre-driver driving the cell; grouping the waveforms from the at least one chip according to input transition characteristics; sorting the group of waveforms with the input transition characteristics according to first characteristics; and selecting a waveform with the representative first characteristics from the group of waveforms with the input transition characteristics as the input waveform. System according to claim 6, wherein the waveform preservation module (202) is configured to obtain an input waveform with the input transition characteristics and representative first characteristics by performing operations comprising: collecting first characteristics of waveforms generated in the at least one chip comprising the circuit topologies representative of the various circuit topologies of the pre-driver driving the cell (2402); selecting the representative first characteristics from the collected first characteristics (2404); constructing the input waveform with the input transition characteristics by fitting an equation to the input transition characteristics and the representative tail characteristics (2410).

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