FPGA-based simulation method for high-voltage direct-connected energy storage system, and apparatus

Abstract

Disclosed in the present invention are an FPGA-based simulation method for a high-voltage direct-connected energy storage system, and an apparatus. A power unit of the high-voltage direct-connected energy storage system is divided into an H-bridge and an energy storage unit part, the H-bridge and a grid-side topology are placed in an FPGA for simulation, an energy storage battery branch part is placed in a CPU for simulation, and the FPGA and the CPU exchange submodule voltage and current information by means of a PCIE bus. The FPGA establishes a Thevenin model of a single high-voltage direct-connected energy storage system submodule, performs algebraic superposition by using the series relationship of submodules, and calculates a submodule capacitor voltage, a submodule terminal voltage, and a bridge arm voltage; an equivalent model and the grid-side topology run with a simulation step size of 1µs in an FPGA of a simulator; the energy storage battery branch runs in a CPU of the simulator, and the CPU supports a user-defined energy storage battery model; and the respective advantages of a real-time multi-core processor and an FPGA are fully combined, so that the high-voltage direct-connected energy storage system with any number of submodules can be precisely simulated with a simulation step size of 1µs in real time on the FPGA.

Description

Simulation method and device for high-voltage direct-hanging energy storage system based on FPGA TECHNICAL FIELD

[0001] The present application relates to the technical field of real-time simulation, in particular to a simulation method and device for a high-voltage direct-hanging energy storage system based on FPGA. BACKGROUND

[0002] With the increasing demand for energy storage technology and the requirement for grid stability and flexibility, in order to balance the difference between load and supply in the power network, improve the efficiency and reliability of the power system, the high-voltage direct-hanging energy storage system has gradually become the focus of research of various energy storage manufacturers. At present, the high-voltage direct-hanging energy storage system has mature applications in 6kv, 10kv in new energy storage, power grid side, large-scale industry and commerce, and several demonstration projects of 35kV voltage level high-voltage direct-hanging energy storage have been carried out and become the focus of research of several manufacturers.

[0003] The high-voltage direct-hanging energy storage system usually has high voltage level, large power capacity, many cascaded sub-modules, many switches, and a large volume of battery system. The testing based on the physical platform has high cost, high risk coefficient and complex engineering. It is difficult to test and debug on the physical prototype, and it is often difficult to show some abnormal operating conditions, such as voltage fluctuation and frequency deviation of the power grid. Therefore, it is necessary for the high-voltage direct-hanging energy storage controller to test through a real-time simulation device that can simulate various operating conditions of the actual system.

[0004] However, for the high-voltage direct-hanging energy storage system, the real-time simulation test mainly has the following challenges.

[0005] Firstly, the high-voltage direct-hanging energy storage system usually contains hundreds of power electronic devices, and the conventional real-time simulation device cannot accurately simulate. In order to ensure the accuracy of real-time simulation, the real-time simulation device is required to have a very small simulation step, usually several microseconds.

[0006] Secondly, there is a lot of data interaction information between the high-voltage direct-hanging energy storage system and the controller, and the traditional physical IO wiring form cannot be used to realize the interaction.

[0007] Thirdly, the traditional simulation device runs the battery model of the high-voltage direct-hanging energy storage system in the FPGA, and does not support the modification of the characteristics of the energy storage battery and the series-parallel connection.

[0008] Fourthly, the widely used device-level detailed model actually builds each sub-module of the high-voltage direct-hanging energy storage system, and can directly simulate the charging and discharging process of each sub-module capacitor. However, with the increase of simulation scale, the existence of a large number of power electronic devices causes the calculation efficiency to drop sharply, which is not suitable for fast electromagnetic transient simulation of power systems. Therefore, a simulation method and device for a high-voltage direct-hanging energy storage system based on FPGA are provided. Summary of the Invention

[0009] The purpose of this invention is to address the shortcomings of existing technologies by providing a simulation method for high-voltage direct-connected energy storage systems based on FPGA. This method splits the power unit of the high-voltage direct-connected energy storage system into H-bridge and energy storage unit parts. The H-bridge and grid-side topology are simulated in the FPGA, while the energy storage battery branch is simulated in the CPU. The FPGA and CPU exchange submodule voltage and current information via a PCIe bus. The FPGA establishes a Thevenin model of a single high-voltage direct-connected energy storage system submodule, and uses algebraic superposition based on the series relationship of the submodules to calculate the submodule capacitor voltage, submodule terminal voltage, and bridge arm voltage. The equivalent model and grid-side topology run in the FPGA simulator with a simulation step size of 1µs. The energy storage battery branch runs in the CPU simulator, which supports user-defined energy storage battery models. By fully combining the advantages of real-time multi-core processors and FPGAs, accurate real-time simulation of high-voltage direct-connected energy storage systems of arbitrary levels can be achieved on the FPGA with a simulation step size of 1µs.

[0010] To achieve the above objectives, the present invention provides the following technical solution: a simulation method for a high-voltage direct-connected energy storage system based on FPGA, comprising the following steps:

[0011] Step 1: The host computer applies the following parameters to the high-voltage direct-connected energy storage system: the number of cascaded sub-modules N, the bypass capacitor value C, and the initial capacitor voltage V. c_initial Discharge resistor R p IGBT on-resistance R on IGBT turn-off resistor R off And grid-side inductance L0, grid-side resistance R0, grid-side voltage V abc Configure information such as simulation step size ΔT;

[0012] Step 2: The high-voltage cascaded submodule is modeled on the DC side. The energy storage battery and the series inductor in front of the battery are simulated on the CPU, and the DC capacitor of the submodule is equivalent to a controllable voltage source on the CPU. The H-bridge and capacitor of the submodule are simulated on the FPGA with small steps, and the energy storage battery part is equivalent to a controllable current source on the FPGA.

[0013] Step 3: The FPGA performs Thevenin equivalent on the capacitor section of the submodule, connecting the bypass capacitor C and the discharge resistor R. p Equivalent to a resistor R ceq With voltage source V ceq Equivalent circuit model in series;

[0014] Step 4: The FPGA performs Thevenin equivalent on the cascaded submodules, and connects the H-bridge in parallel with a controllable current source I. bat The submodule is equivalent to a resistor R.smeq and voltage source V smeq in series, and pre-computed to generate R smeq , terminal voltage proportional coefficient A and battery current proportional coefficient B in different switch states;

[0015] Step 5: FPGA performs Thevenin equivalent on each phase bridge arm of the high-voltage direct-hanging energy storage, and equivalently converts the whole phase bridge arm into a resistor R EQ and voltage source V EQ in series;

[0016] Step 6: FPGA switches the equivalent circuit parameters R smeq , terminal voltage proportional coefficient A and battery current proportional coefficient B of the current sub-module according to the current on-off state of each switch tube of the sub-module, and calculates the equivalent voltage V c (t-ΔT) and battery current I bat of the last moment, and then obtains the equivalent voltage V smeq of each sub-module through accumulation, and then obtains the equivalent voltage V EQ of each phase bridge arm;

[0017] Step 7: FPGA calculates the bridge arm current I EQ according to the equivalent resistance R EQ and the equivalent voltage V sm of each bridge arm, and the parameters of the grid-side voltage and the grid-side inductance;

[0018] Step 8: FPGA calculates the capacitor current I sm and the capacitor voltage V bat of each sub-module according to the bridge arm current I c and the energy storage battery current I c ;

[0019] Step 9: CPU obtains the sub-module capacitor voltage V c uploaded by FPGA, combines the energy storage battery voltage on CPU, calculates the energy storage battery current I bat , and sends the energy storage battery current I bat to FPGA;

[0020] Step 10: FPGA uploads the information of sub-module voltage, current, bridge arm voltage and current, and the host computer can observe the running state of the high-voltage direct-hanging energy storage system in real time; the data of sub-module voltage, current and SOC are transmitted to the energy storage controller through optical fiber; the battery information in CPU can be transmitted to the BMS control system through CAN communication.

[0021] As a preferred technical solution of the present application, the configuration information in step 1 needs to be configured in the host computer, and after configuration, no additional FPGA compilation is required, so as to realize the function described by the configuration information.

[0022] The specific steps of step 1 are as follows:

[0023] Step 11: The front end of the host computer connects the device through the device IP, and configures the module cascade number N, bypass capacitor value C, capacitor initial voltage V c_initial , discharge resistance R p , IGBT on resistance R on , IGBT off resistance R off , and net side inductance L0, net side resistance R0, net side voltage V abc , simulation step ΔT parameter information of the high-voltage direct hanging energy storage system application model cascade sub-module in the host computer.

[0024] Step 12: The rear end of the host computer reads the front end configuration information and generates a configuration file.

[0025] As a preferred technical solution of the present application, the specific steps of step 3 are as follows:

[0026] Step 31: The trapezoidal integration method is used to discretize the equivalent model of the sub-module, and the bypass capacitor C is equivalent to a capacitor resistance R c series voltage source V c0eq ; wherein, the sub-module voltage V c expression is as follows:

[0027] Wherein:

[0028] I c (t) is the capacitor current; R c is the equivalent resistance of the capacitor C; ΔT is the simulation step;

[0029] Step 32: The capacitor C and the discharge resistance R p are connected in parallel, and the whole is equivalent to a resistance R ceq series voltage source V ceq equivalent model:

[0030] As a preferred technical solution of the present application, the specific steps of step 4 are as follows:

[0031] Step 41: The FPGA establishes the Thevenin equivalent model of the high-voltage direct hanging energy storage system sub-module, and regards the four switch tubes S1, S2, S3 and S4 of the sub-module as variable resistors R1, R2, R3 and R4 switching between high and low resistance values, and the resistance value is R on in the on state, and R off; the on-resistance R on ; the off-resistance R off ; the parameter configuration data;

[0032] Step 42: the H-bridge parallel energy storage unit controllable current source I bat is equivalent to a resistance R smeq in series with a voltage source V smeq ; V sm =R smeq I sm +V smeq (t-ΔT); R smeq =R A / / (R2 / / R C ) / / (R4 / / R B );

[0033] Wherein: V smeq (t-ΔT)=A*V ceq (t-ΔT)+B*I bat ;

[0034] Wherein:

[0035] R smeq is the resistance of the equivalent circuit; V smeq is the equivalent voltage source of the sub-module; I bat is the battery current calculated and issued by the CPU; V sm is the terminal voltage of the sub-module; A is the terminal voltage proportionality coefficient, and B is the battery current proportionality coefficient.

[0036] Step 43: according to the cascade module parameters and the various possible on states of the sub-module switch tubes, the initialization equivalent circuit parameters R smeq , the terminal voltage proportionality coefficient A and the capacitor voltage proportionality coefficient B of the sub-module in each state are pre-calculated and generated.

[0037] As a preferred technical solution of the present application, in step 5, the N sub-modules in the high-voltage direct hanging energy storage bridge arm are equivalent to an equivalent circuit of a bridge arm resistance R EQ in series with a voltage source V EQ , and the terminal voltages V sm of each sub-module unit are summed to obtain the bridge arm terminal voltage V MV :

[0038] Then: V MV =R EQ I sm +V EQ (t-ΔT);

[0039] Wherein:

[0040] V MV is the voltage of each phase bridge arm; R EQ is the resistance of the equivalent circuit; V EQ is the equivalent voltage source of the bridge arm; I sm is the bridge arm current.

[0041] As a preferred technical solution of the present application, in step 6, the FPGA switches and selects the corresponding initialized equivalent circuit parameters R smeq , the end voltage proportional coefficient A, and the battery current proportional coefficient B, the 4 switch conduction state combinations of each sub-module H-bridge are different, and the corresponding equivalent circuit parameters R smeq , the end voltage proportional coefficient A, and the battery current proportional coefficient B are also different;

[0042] The FPGA selects the equivalent circuit parameters and proportional coefficients at the current moment, and calculates the equivalent voltage V c (t-ΔT) of each sub-module according to the capacitor voltage V bat at the last moment and the battery current I smeq . Eq .

[0043] As a preferred technical solution of the present application, in step 8, the FPGA calculates the capacitor current I sm (t) and the capacitor voltage V bat of each sub-module according to the bridge arm current I c and the energy storage battery current I c :

[0044] Wherein: R ∑ =R1+R2+R3+R4; V c (t) = R c ·I c (t) + V c0eq (t-ΔT);

[0045] I bat is the energy storage battery current, which is calculated by the energy storage battery model in the CPU and uploaded to the FPGA; I sm is the bridge arm current; I c is the capacitor current; I c ′ is the current flowing through the capacitor and the bypass capacitor; ΔT is the simulation step; according to the electrical quantities of each sub-module at t-ΔT in the equivalent bridge arm, the capacitor voltage and current of each sub-module in the bridge arm at t are obtained by simulation calculation; the energy storage battery current I batThe sub-module capacitor voltage V uploaded by the CPU in the energy storage battery model is calculated and uploaded to the FPGA; meanwhile, the FPGA transmits the sub-module voltage V to the CPU, and the high-speed communication between the CPU and the FPGA is realized through the PCIE bus. c

[0046] As a preferred technical solution of the present application, in step 9, the CPU obtains the sub-module capacitor voltage V uploaded by the FPGA, and combines the energy storage battery voltage on the CPU to calculate the energy storage battery current I c bat bat The energy storage battery current I is sent to the FPGA; the high-speed communication between the FPGA and the CPU is realized through the PCIE bus, and the data information of the H-bridge part of the high-voltage direct-hanging energy storage battery branch and cascade is closed-loop interacted.

[0047] Meanwhile, the simulation test of the high-voltage direct-hanging energy storage system usually also includes a circuit breaker signal and a battery SOC signal, wherein the circuit breaker signal is received by the FPGA fiber from the external controller signal, and then uploaded to the CPU energy storage branch; the battery SOC is sent to the FPGA, and then transmitted to the external controller.

[0048] As a preferred technical solution of the present application, the data of the sub-module voltage, current and SOC in step 10 need to be framed, and the frame structure includes a frame synchronization package header and various data package information; one optical fiber transmits all the sub-module information of one phase, and the high-voltage direct-hanging energy storage system needs three optical fibers to be connected with the external controller through the external optical port.

[0049] An apparatus for performing a simulation method of a high-voltage direct-hanging energy storage system based on FPGA, comprising a host computer for configuring parameters, an FPGA and an optical fiber interface; the optical fiber interface is configured with an 8-way optical fiber interface, which is used for transmitting sub-module voltage, current, SOC information, and receiving PWM signals and circuit breaker signals transmitted by the external controller.

[0050] Compared with the prior art, the present application has the following advantages:

[0051] The present application proposes a simulation method and device of a high-voltage direct-hanging energy storage system based on FPGA, which splits the power unit of the high-voltage direct-hanging energy storage system into an H-bridge and an energy storage unit part; the H-bridge and the grid-side topology are simulated in the FPGA, and the energy storage battery branch part is simulated in the CPU; the FPGA and the CPU interact with each other through the PCIE bus to transmit sub-module voltage and current information, and support user-defined energy storage battery model; combining the respective advantages of the real-time multi-core processor and the FPGA, the high-voltage direct-hanging energy storage system with any number of stages can be accurately and real-timely simulated on the FPGA with a simulation step length of 1us. BRIEF DESCRIPTION OF DRAWINGS

[0052] ​​​Fig. 1 is a flow chart of the high-voltage direct-hanging energy storage modeling simulation method of the present application;

[0053] Fig. 2 is a structural schematic block diagram of the high-voltage direct-hanging energy storage simulation device of the present application;

[0054] Fig. 3 is a Thevenin equivalent model of the bypass capacitor of the sub-module of the high-voltage direct-hanging energy storage system of the present application;

[0055] Fig. 4 is a Thevenin equivalent model of the sub-module of the high-voltage direct-hanging energy storage system of the present application;

[0056] Fig. 5 is a Thevenin equivalent model of the bridge arm of the high-voltage direct-hanging energy storage system of the present application;

[0057] Fig. 6 is a waveform diagram of the real-time simulation result of the high-voltage direct-hanging energy storage system of the present application;

[0058] (a) battery DC side current; (b) cascade H-bridge capacitor voltage. DETAILED DESCRIPTION

[0059] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings, so that the advantages and features of the present application can be more easily understood by those skilled in the art, and the protection scope of the present application can be more clearly defined.

[0060] Embodiment 1: Referring to Fig. 1, the present application provides a technical solution: a high-voltage direct-hanging energy storage simulation method based on FPGA, and the specific steps are as follows:

[0061] Step 1: The host computer configures the parameter information of the module cascade number N, bypass capacitor value C, capacitor initial voltage V c_initial , discharge resistance R p , IGBT on-resistance R ob , IGBT off-resistance R off , and grid-side inductance L0, grid-side resistance R0, grid-side voltage V abc , simulation step ΔT, etc. of the cascade sub-module of the high-voltage direct-hanging energy storage system application model;

[0062] Step 11: As shown in Fig. 1, the front end of the host computer connects the device through the device IP, and configures the parameter information of the module cascade number N, bypass capacitor value C, capacitor initial voltage V c_initial , discharge resistance R p , IGBT on-resistance R on , IGBT off-resistance R off , and grid-side inductance L0, grid-side resistance R0, grid-side voltage V abc , simulation step ΔT, etc. of the cascade sub-module of the high-voltage direct-hanging energy storage system application model at the host computer;

[0063] Step 12: The rear end of the host computer reads the front end configuration information and generates a configuration file;

[0064] Step 2: Model partitioning is performed on the DC side of the high-voltage cascade sub-module, as shown in FIG. 2, wherein the energy storage battery and the series inductor before the battery are simulated on the CPU, and the DC capacitor of the sub-module is equivalent to a controllable voltage source on the CPU; the H-bridge and the capacitor of the sub-module are simulated in small steps on the FPGA, and the energy storage battery part is equivalent to a controllable current source on the FPGA;

[0065] Step 3: The FPGA performs Thevenin equivalence on the capacitor part of the sub-module, and the bypass capacitor C and the discharge resistor R p are equivalent to the equivalent circuit model of the resistor R ceq in series with the voltage source V ceq .

[0066] Step 31: The sub-module equivalent model is discretized by using the trapezoidal integration method, and the bypass capacitor C is equivalent to the capacitor resistor R c in series with the voltage source V c0eq , as shown in FIG. 3; wherein the sub-module voltage V c is expressed as follows:

[0067] Wherein:

[0068] I c (t) is the capacitor current; R c is the equivalent resistance of the capacitor C; and ΔT is the simulation step;

[0069] Step 32: As shown in FIG. 3, the capacitor C in parallel with the discharge resistor R p is equivalent to the equivalent model of the resistor R ceq in series with the voltage source V ceq .

[0070] Step 4: The FPGA performs Thevenin equivalence on the cascade sub-module, and the sub-module with the H-bridge in parallel with the controllable current source I bat is equivalent to the equivalent circuit model of the resistor R smeq in series with the voltage source V smeq , and the values of R smeq , the terminal voltage proportionality coefficient A, and the battery current proportionality coefficient B in different switch states are calculated and generated in advance;

[0071] Step 41: The FPGA establishes the Thevenin equivalent model of the high-voltage direct-hanging energy storage system sub-module, and the four switches S1, S2, S3, and S4 of the sub-module are regarded as variable resistors R1, R2, R3, and R4 switching between high and low resistance values, the resistance value being R on when turned on and R off when turned off; the on-resistance R onWith the off resistance R off is the parameter configuration data;

[0072] Step 42: As shown in Figure 4, the controllable current source I bat of the cascade submodule of the H-bridge parallel energy storage unit is equivalent to a resistance R smeq in series with a voltage source V smeq , where: V sm = R smeq I sm + V smeq (t-ΔT); R smeq =R A / / (R2 / / R C ) / / (R4 / / R B ).

[0073] Where: V smeq (t-ΔT) = A*V ceq (t-ΔT) + B*I bat .

[0074] Where:

[0075] R smeq is the resistance of the equivalent circuit; V smeq is the equivalent voltage source of the submodule; I bat is the battery current calculated and issued by the CPU; V sm is the terminal voltage of the submodule; A is the terminal voltage proportionality coefficient, and B is the battery current proportionality coefficient.

[0076] Step 43: According to the parameters of the cascade module and the various possible conduction states of the submodule switch tube, the initialization equivalent circuit parameters R smeq , terminal voltage proportionality coefficient A and capacitor voltage proportionality coefficient B of each state of the submodule are pre-calculated and generated.

[0077] Step 5: The Thevenin equivalent of the high-voltage direct-hanging energy storage is performed by the FPGA, and the whole bridge arm of each phase is equivalent to a resistance R EQ in series with a voltage source V EQ .

[0078] As shown in Figure 5, the N submodule equivalent circuits in the high-voltage direct-hanging energy storage bridge arm are equivalent to an equivalent circuit model of a bridge arm resistance R EQ in series with a voltage source V EQ , and the terminal voltage V sm of each submodule unit is summed to obtain the bridge arm terminal voltage V MV :

[0079] Then: VMV = R EQ I sm + V EQ (t-ΔT);

[0080] wherein:

[0081] V MV is the voltage of each phase leg; R EQ is the resistance of the equivalent circuit; V EQ is the equivalent voltage source of the bridge leg; I sm is the bridge leg current;

[0082] Step 6: The FPGA switches the equivalent circuit parameters R smeq , the terminal voltage proportional coefficient A and the battery current proportional coefficient B of the current corresponding sub-module according to the current on-off state of each switch tube of the sub-module, and calculates the equivalent voltage V c of each sub-module according to the capacitor voltage V bat (t-ΔT) and the battery current I smeq of the previous moment, and then obtains the equivalent voltage V EQ of each phase leg by accumulation;

[0083] Step 61: Switch the equivalent resistance R smeq and the proportional coefficients A and B of the corresponding sub-module according to the on-off state of the four switch tubes of the sub-module:

[0084] When switches S1 and S3 are on and S2 and S4 are off, switches S1 and S3 are equivalent to a small resistance R on , switches S2 and S4 are equivalent to a large resistance R off , the equivalent circuit R smeq has a resistance of R 1010 , A is 0, and B is 0;

[0085] When switches S1 and S4 are on and S2 and S3 are off, switches S1 and S4 are equivalent to a small resistance R on , switches S2 and S3 are equivalent to a large resistance R off , the equivalent circuit R smeq has a resistance of R 1001 , A is K Q , and B is S Q ;

[0086] When switches S2 and S3 are on and S1 and S4 are off, switches S2 and S3 are equivalent to a small resistance R on , switches S1 and S4 are equivalent to a large resistance R off , the equivalent circuit R smeq has a resistance of R 0110 , A is L Q , and B is TQ

[0087] When switches S2 and S4 are turned on and switches S1 and S3 are turned off, switches S2 and S4 are equivalent to small resistors R on , switches S1 and S3 are equivalent to large resistors R off , and the equivalent circuit is R smeq , the resistance value of which is R 0101 , corresponding to A being 0 and B being 0.

[0088] When switches S1, S2, S3 and S4 are all turned off, switches S1, S2, S3 and S4 are all equivalent to large resistors R off , and the equivalent circuit is R smeq , the resistance value of which is R 0000 , corresponding to A being 0 and B being 0.

[0089] The above R 1010 , R 1001 , R 0110 , R 0110 , R 0101 , K Q , L Q , S Q , and T Q are all pre-calculated values, and here, only the corresponding values need to be selected and switched according to the current on-off state of each sub-module.

[0090] Step 62: The FPGA selects the equivalent resistance R smeq and the proportional coefficients A and B at the current time, calculates the equivalent voltage V c of each cascaded sub-module according to the capacitor voltage V bat (t-ΔT) and the battery current I smeq at the previous time, and then obtains the equivalent voltage V EQ of each phase bridge arm through summation.

[0091] Step 7: The FPGA calculates the bridge arm current I EQ by integrating the equivalent resistance R EQ and the equivalent voltage V sm of each bridge arm, as well as the grid-side voltage, grid-side inductance and other grid-side parameters.

[0092] Step 8: The FPGA calculates the capacitor current I sm and the capacitor voltage V bat of each sub-module according to the bridge arm current I c and the energy storage battery current I c .

[0093] wherein R ∑ =R1+R2+R3+R4. ​V c (t) = R c · I c (t) + V c0eq (t - AT);

[0094] I bat is the energy storage battery current, which is calculated by the energy storage battery model in the CPU and uploaded to the FPGA; I sm is the bridge arm current; I c is the capacitor current; I c ' is the current flowing through the capacitor and the bypass capacitor; AT is the simulation step. According to the electrical quantities of each submodule in the equivalent bridge arm at time t-AT, the simulation calculation is performed to obtain the capacitor voltage and current of each submodule in the bridge arm at time t; the energy storage battery current I bat is calculated by the energy storage battery model in the CPU and uploaded to the FPGA; at the same time, the FPGA sends the submodule capacitor voltage V c to the CPU, and the CPU and the FPGA communicate at high speed through the PCIE bus;

[0095] Step 9: The CPU obtains the submodule capacitor voltage V c uploaded by the FPGA, combines the energy storage battery voltage on the CPU, calculates the energy storage battery current I bat , and sends the energy storage battery current I bat to the FPGA;

[0096] The CPU obtains the submodule capacitor voltage V c uploaded by the FPGA, combines the energy storage battery voltage on the CPU, calculates the energy storage battery current I bat , and sends the energy storage battery current I bat to the FPGA; the CPU and the FPGA exchange information such as submodule voltage, current, SOC, circuit breaker, etc. through the PCIE bus;

[0097] Step 10: The FPGA uploads information such as submodule voltage, current, bridge arm voltage, and current, and the upper computer can observe the running state of the high-voltage direct-hanging energy storage system in real time; the submodule voltage, current, SOC, etc. are transmitted to the energy storage controller through the optical fiber; the battery information in the CPU can be transmitted to the BMS control system through CAN communication;

[0098] The submodule voltage, current, SOC, etc. are transmitted to the energy storage controller through the optical fiber of the simulation device, wherein the submodule voltage, current, SOC, etc. need to be framed, and the frame structure includes a frame synchronization header and various data packet information. Each optical fiber transmits information of all submodules of one phase, and the high-voltage direct-hanging energy storage system needs three optical fibers to connect with the external controller through external optical ports; the battery information in the CPU can be transmitted to the BMS control system through CAN communication;

[0099] The application also provides a device of a high-voltage direct-hanging energy storage system based on FPGA, comprising:

[0100] The host computer is configured to configure parameters, including the module cascade number N of the high-voltage direct-hanging energy storage system application model cascade submodule, the bypass capacitance value C, the initial voltage V c_initial , the discharge resistance R p , the IGBT conduction resistance R on , the IGBT turn-off resistance R off , and the grid-side inductance L0, the grid-side resistance R0, the grid-side voltage V abc , and the simulation step ΔT and other parameter information.

[0101] The FPGA is configured to execute the simulation method of the application.

[0102] The optical fiber interface is configured as an 8-way optical fiber interface and is configured to send the voltage, current, SOC and other information of the submodule, receive the PWM signal and circuit breaker signal transmitted by the external controller.

[0103] Embodiment 2: Analysis of the real-time simulation result of the high-voltage direct-hanging energy storage

[0104] The performance of the high-voltage direct-hanging energy storage real-time simulator is verified by taking a 48-level high-voltage direct-hanging energy storage system as an example. The simulation model parameters are as follows: the three-phase grid voltage is 35 kV, the rated capacity is 12500 kVA, the grid frequency is 50 Hz, the high-voltage direct-hanging energy storage system level is 40, the grid-side inductance parameter is 28.8 mH, the capacitance parameter is 50000 uF, the battery capacity is 50 Ah, the rated voltage is 768 V, and the DC-side inductance is 0.85 mH.

[0105] The high-voltage direct-hanging energy storage real-time simulator provided by the application is used to simulate the system architecture and parameters described above, the high-voltage direct-hanging energy storage controller is connected to the real-time simulator, and the high-voltage direct-hanging energy storage controller and the real-time simulation device provided by the application interact with each other through optical fibers to realize the control of the high-voltage direct-hanging energy storage system.

[0106] Figure 6 includes two subgraphs, Figure 6(a) and Figure 6(b) are the battery DC-side current and the cascade H-bridge capacitor voltage sampled by the host computer of the simulator. As shown in Figures (a) and (b), through the analysis of the DC-side current and the submodule voltage waveform, it can be seen that the simulator can accurately simulate the battery current double-frequency characteristic and the ripple size and balancing effect of the submodule voltage; therefore, the real-time simulation method of the high-voltage direct-hanging energy storage system with a small step size can achieve more accurate results.

[0107] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements shall be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A simulation method of a high-voltage direct-mount energy storage system based on an FPGA, characterized in that, Specifically comprising the following steps: Step 1: The host computer configures the module cascade number N, bypass capacitor value C, capacitor initial voltage V c_initial , discharge resistance R p , IGBT on resistance R on , IGBT off resistance R off , and grid-side inductance L0, grid-side resistance R0, grid-side voltage V abc , simulation step ΔT parameter information for the high-voltage direct-hanging energy storage system application model cascade sub-module. Step 2: Model partitioning of high-voltage cascade sub-modules on the DC side, wherein the energy storage battery and the series inductor before the battery are simulated on the CPU, and the DC capacitor of the sub-module is equivalent to a controllable voltage source on the CPU; the H-bridge and the capacitor of the sub-module are simulated on the FPGA with small steps, and the energy storage battery part is equivalent to a controllable current source on the FPGA; Step 3: FPGA makes Thevenin equivalent for the capacitor part of the sub-module, equivalent the bypass capacitor C and discharge resistor R p to a resistor R ceq in series with a voltage source V ceq in the equivalent circuit model; Step 4: The FPGA performs Thevenin equivalence on the cascaded sub-modules, and the H-bridge parallel controllable current source I bat is equivalent to a resistor R smeq in series with a voltage source V smeq , and the values of R smeq , the terminal voltage proportional coefficient A, and the battery current proportional coefficient B under different switch states are calculated in advance. Step 5: FPGA performs Thevenin equivalent on each phase bridge arm of the high-voltage direct-hanging energy storage, and equivalently regards the whole phase bridge arm as a resistor R EQ with the voltage source V EQ in series; Step 6: FPGA switches the equivalent circuit parameters R of the current corresponding submodule according to the current on-off state of each switch tube of the submodule smeq , the terminal voltage proportional coefficient A and the battery current proportional coefficient B, and according to the capacitor voltage V c (t-ΔT) and the battery current I bat of the last moment, calculates the equivalent voltage V smeq of each submodule, and then obtains the equivalent voltage V EQ of each phase bridge arm through accumulation; Step 7: FPGA calculates the equivalent resistance R EQ and equivalent voltage V EQ of each leg based on the grid voltage, grid inductance parameters, and integrates to get the leg current I sm ; Step 8: FPGA calculates the capacitor current I sm and the energy storage battery current I bat of each sub-module according to the bridge arm current I c and the capacitor voltage V c ; Step 9: CPU obtains the sub-module capacitor voltage V uploaded by FPGA c , combines the energy storage battery voltage on the CPU, calculates the energy storage battery current I bat , and issues the energy storage battery current I bat to FPGA; Step 10: The FPGA transmits the voltage, current, bridge arm voltage and current of the sub-module, and the host computer can observe the running state of the high-voltage direct-hanging energy storage system in real time; the data of the sub-module voltage, current and SOC are transmitted to the energy storage controller through optical fiber; the battery information in the CPU can be transmitted to the BMS control system through CAN communication.

2. The simulation method of the high-voltage direct-attached energy storage system based on FPGA according to claim 1, characterized in that: The configuration information in step 1 needs to be configured in the host computer, and after configuration, no additional FPGA compilation is required to achieve the functions described in the configuration information; The specific steps of step 1 are as follows: Step 11: The host computer front end connects the device through the device IP, and the host computer configures the module cascade number N, bypass capacitor value C, and capacitor initial voltage V of the application model cascade submodule of the high-voltage direct-hanging energy storage system c_initial , discharge resistance R p , IGBT on-resistance R on , IGBT off-resistance R off , and net-side inductance L0, net-side resistance R0, and net-side voltage V abc , simulation step ΔT parameter information; Step 12: The host computer backend reads the front-end configuration information to generate a configuration file.

3. The simulation method of the high-voltage direct-attached energy storage system based on FPGA according to claim 1, characterized in that: The specific steps of step 3 are as follows: Step 31: Discretize the sub-module equivalent model by trapezoidal integration method, and equivalent the bypass capacitor C to a capacitor resistance R c Series voltage source V c0eq ; wherein the sub-module voltage V c The expression is as follows: wherein: I c (t) is the capacitance current; R c is the equivalent resistance of the capacitance C; ΔT is the simulation step; Step 32: Capacitor C is discharged in parallel with resistor R p The overall equivalent is resistor R ceq Series voltage source V ceq Equivalent model:

4. The simulation method of the high-voltage direct-attached energy storage system based on FPGA according to claim 1, characterized in that: The specific steps of step 4 are as follows: Step 41: Establish the Thevenin equivalent model of the high-voltage direct-connected energy storage system submodule using the FPGA. Treat the four switches S1, S2, S3, and S4 of the submodule as variable resistors R1, R2, R3, and R4 that switch between high and low resistance values. When in the on state, the resistance is R. on When turned off, it is R. off On-resistance R on With the turn-off resistor R off Configure data for parameters; Step 42: H-bridge parallel energy storage unit controllable current source I bat The sub-modules are equivalent to a resistor R smeq in series voltage source V smeq : V sm = R smeq I sm + V smeq (t - ΔT); R smeq = R A / / (R2 / / R C ) / / (R4 / / R B ); wherein: V smeq (t-ΔT) = A*V ceq (t-ΔT) + B*I bat ; wherein: R smeq is the equivalent circuit resistance; V smeq is the equivalent voltage source of the sub-module; I bat is the battery current, calculated and issued by the CPU; V sm is the terminal voltage of the sub-module; A is the terminal voltage proportional coefficient, and B is the battery current proportional coefficient; Step 43: According to the cascade module parameters and the various conduction states of the sub-module switch tubes, the initialization equivalent circuit parameters R of each state of the sub-module are pre-calculated and generated smeq , the terminal voltage proportional coefficient A and the capacitor voltage proportional coefficient B.

5. The simulation method of the high-voltage direct-attached energy storage system based on FPGA according to claim 1, characterized in that: In step 5, the N sub-module equivalent circuits in the high-voltage direct hanging energy storage bridge arm are connected in series to be equivalent to a bridge arm resistor R EQ The equivalent circuit of the series voltage source V EQ The end voltage V sm of each sub-module unit is summed to obtain the bridge arm end voltage V MV : Then: V MV = R EW I sm + V EQ (t - ΔT); wherein: V MV V is the voltage of each phase leg; R EQ R is the resistance of the equivalent circuit; V EQ V is the equivalent voltage source of the bridge leg; I sm I is the bridge leg current.

6. The simulation method of a high-voltage direct-attached energy storage system based on FPGA according to claim 1, characterized in that: In step 6, the FPGA switches and selects the corresponding initialization equivalent circuit parameters R according to the conduction state of the current submodule switch tube smeq The resistance value, the terminal voltage proportional coefficient A, and the battery current proportional coefficient B are different for different conduction state combinations of the four switch tubes of the respective submodule H-bridge, and the corresponding equivalent circuit parameters R are different smeq The resistance value, the terminal voltage proportional coefficient A, and the battery current proportional coefficient B are different for different conduction state combinations of the four switch tubes of the respective submodule H-bridge, and the corresponding equivalent circuit parameters R are different The FPGA selects the equivalent circuit parameters and proportional coefficient of the current moment, and calculates the equivalent voltage V c (t-ΔT) and the battery current I bat of each cascade sub-module, and then obtains the equivalent voltage V smeq of each phase bridge arm through summation. EQ ​ 7. The simulation method of a high-voltage direct-attached energy storage system based on FPGA according to claim 1, characterized in that: In step 8, the FPGA calculates the capacitor current I sm and the energy storage battery current I bat for each sub-module based on the bridge arm current I c (t) and the capacitor voltage V c : wherein: R ∑ = R1+ R2+ R3+ R4; V c (t) = R c ·I c (t) + V c0eq (t - ΔT); I bat is the energy storage battery current, which is calculated by the energy storage battery model in the CPU and uploaded to the FPGA;I sm is the bridge arm current;I c is the capacitor current;I c is the current flowing through the capacitor and the bypass capacitor; ΔT is the simulation step; according to the electrical quantities of each submodule in the equivalent bridge arm at time t-ΔT, the simulation calculation is performed to obtain the capacitor voltage and current of each submodule in the bridge arm at time t; the energy storage battery currentI bat is calculated by the energy storage battery model in the CPU and uploaded to the FPGA; at the same time, the FPGA sends the submodule voltage V c to the CPU, and the CPU and the FPGA communicate at high speed through the PCIE bus.

8. The simulation method of a high-voltage direct-attached energy storage system based on FPGA according to claim 1, characterized in that: In step 9, the CPU acquires the sub-module capacitor voltage V uploaded by the FPGA c , combines the energy storage battery voltage on the CPU to calculate the energy storage battery current I bat , and issues the energy storage battery current I bat to the FPGA; the FPGA and the CPU interact through the PCIE bus to close the loop of the high-voltage direct-hanging energy storage battery branch and the H-bridge part of the cascade data information. Meanwhile, the simulation test of the high-voltage direct-hanging energy storage system also includes the circuit breaker signal and the battery SOC signal, wherein the circuit breaker signal is received by the FPGA optical fiber from the external controller signal, and then transmitted to the CPU energy storage branch; the battery SOC is transmitted to the FPGA, and then transmitted to the external controller.

9. The simulation method of a high-voltage direct-attached energy storage system based on FPGA according to claim 1, characterized in that: The data of the sub-module voltage, current and SOC in step 10 need to be framed, and the frame structure includes frame synchronization header and each data packet information; each optical fiber transmits information of all sub-modules of one phase; the high-voltage direct-hanging energy storage system needs three optical fibers to connect with the external controller through the external optical port.

10. An apparatus for performing the simulation method of the FPGA-based high-voltage direct plug-in energy storage system according to any one of claims 1-9, characterized in that: It includes a host computer for configuring parameters, an FPGA and an optical fiber interface; the optical fiber interface is configured with 8 optical fiber interfaces for transmitting sub-module voltage, current and SOC information, and receiving PWM signals and circuit breaker signals transmitted by the external controller.

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