Method for forming a semiconductor device

Abstract

A method (100) for forming a semiconductor device (500), comprising: Forming a conductor (516) over a carrier substrate (502) by depositing a layer of conductive material; Forming a dielectric layer (503) over the carrier substrate (502), wherein a first portion of the dielectric layer (503) contacts a top surface of the conductor (516) and a second portion of the dielectric layer (503) contacts a side surface of the conductor (516), the first and second portions of the dielectric layer (503) being formed of the same material; Forming a substrate (508) over the dielectric layer (503); Forming (102) a first opening (514) in the substrate (508) and the first portion of the dielectric layer (503) and exposing at least a portion of a top surface (515) of the conductor (516) through the opening (514); at least one of Implanting (104) a first dopant (522) into sidewalls of the substrate (508) defining the opening (514) such that a conductor gate (526a) concentrically surrounds the opening (514); and Forming (106) an insulator (524) adjacent to sidewalls of the conductor gate (526a) such that the insulator (524) concentrically surrounds the opening (514); or Forming (106) an insulator (524) adjacent to sidewalls of the substrate (508) defining the opening (514) such that the insulator (524) concentrically surrounds the opening (514); and Implanting a first dopant (522) into the sidewalls of the substrate (508) such that a conductor gate (526a) concentrically surrounds the insulator (524); and Forming (108) a column (528) in the opening (514) such that the insulator (524) concentrically surrounds the column (528).

Description

BACKGROUNDSemiconductor devices include, among other things, transistors and capacitors, wherein transistors serve as switches and capacitors store electrical charges.The prior art relating to the subject matter of the invention can be found in US 2009 / 0 101 969 A1, U.S. Pat. No. 5,208,172 A and KR 10 2009 0 099 774.DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read with the accompanying figures. It should be appreciated that, in accordance with the usual industry practice, various devices are not drawn to scale. Indeed, the dimensions of the various devices may be arbitrarily increased or decreased for clarity of description. FIG. 1 is a flow diagram illustrating a method of forming a semiconductor device in accordance with some embodiments. FIG. 2 is a flow diagram illustrating a method of forming a semiconductor device in accordance with some embodiments. FIG. 3 is a flow diagram illustrating a method of forming a semiconductor device in accordance with some embodiments. FIG. 4 is a flow diagram illustrating a method of forming a semiconductor device in accordance with some embodiments. FIG. 5 is a view of a semiconductor device in accordance with some embodiments. FIG. 6 is a view of a semiconductor device in accordance with some embodiments. FIG. 7 is a view of a semiconductor device in accordance with some embodiments. FIG. 8 is a view of a semiconductor device in accordance with some embodiments. FIG. 9 is a view of a semiconductor device in accordance with some embodiments. FIG. 10 is a view of a semiconductor device in accordance with some embodiments. FIG. 11 is a view of a semiconductor device in accordance with some embodiments. FIG. 12 is a view of a semiconductor device in accordance with some embodiments. FIG. 13 is a view of a semiconductor device in accordance with some embodiments. FIG. 14 is a view of a semiconductor device in accordance with some embodiments. FIG. 15 is a view of a semiconductor device in accordance with some embodiments. FIG. 16 is a view of a semiconductor device in accordance with some embodiments. FIG. 17 is a view of a semiconductor device in accordance with some embodiments. FIG. 18 is a view of a semiconductor device in accordance with some embodiments. FIG. 19 is a view of a semiconductor device in accordance with some embodiments. FIG. 20 is a view of a semiconductor device in accordance with some embodiments. FIG. 21 is a view of a semiconductor device in accordance with some embodiments. FIG. 22 is a view of a semiconductor device in accordance with some embodiments. FIG. 23 is a view of a semiconductor device in accordance with some embodiments. FIG. 24 is a view of a semiconductor device in accordance with some embodiments. FIG. 25 is a view of a semiconductor device in accordance with some embodiments. FIG. 26 is a view of a semiconductor device in accordance with some embodiments. FIG. 27 is a view of a semiconductor device in accordance with some embodiments. FIG. 28 is a view of a semiconductor device in accordance with some embodiments. FIG. 29 is a view of a semiconductor device in accordance with some embodiments. FIG. 30 is a view of a semiconductor device in accordance with some embodiments. FIG. 31 is a view of a semiconductor device in accordance with some embodiments. FIG. 32 is a view of a semiconductor device in accordance with some embodiments. FIG. 33 is a view of a semiconductor device in accordance with some embodiments. FIG. 34 is a view of a semiconductor device in accordance with some embodiments. FIG. 35 is a view of a semiconductor device in accordance with some embodiments. FIG. 36 is a view of a semiconductor device in accordance with some embodiments. FIG. 37 is a view of a semiconductor device in accordance with some embodiments. FIG. 38 is a view of a semiconductor device in accordance with some embodiments. FIG. 39 is a view of a semiconductor device in accordance with some embodiments. FIG. 40 is a view of a semiconductor device in accordance with some embodiments. FIG. 41 is a view of a semiconductor device in accordance with some embodiments. FIG. 42 is a view of a semiconductor device in accordance with some embodiments. FIG. 43 is a view of a semiconductor device in accordance with some embodiments. FIG. 45 is a view of a semiconductor device in accordance with some embodiments. FIG. 46 is a view of a semiconductor device in accordance with some embodiments. FIG. 47 is a view of a semiconductor device in accordance with some embodiments. FIG. 48 is a view of a semiconductor device in accordance with some embodiments. FIG. 49 is a view of a semiconductor device in accordance with some embodiments. FIG. 50 is a view of a semiconductor device in accordance with some embodiments. FIG. 51 is a view of a semiconductor device in accordance with some embodiments. FIG. 52 is a view of a semiconductor device in accordance with some embodiments. FIG. 53 is a view of a semiconductor device in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples to implement various apparatus of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. Forming a first device over or on a second device in the following description may include, for example, embodiments in which the first and second devices are formed in direct contact, and may also include embodiments in which additional devices may be formed between the first and second devices such that the first and second devices need not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and, as such, does not force a relationship between the various embodiments and / or configurations described.Further, spatially relative terms such as "bottom," "below," "lower," "above," "upper," and the like, may be used herein for convenience of description to describe the relationship of an element or device with one or more other elements or devices as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative terms used herein may also be interpreted accordingly.One or more techniques for forming a semiconductor device and the resulting structures formed thereby are provided herein.A method 100 of forming a semiconductor device 500 according to some embodiments is shown in FIG. 1, and one or more structures formed thereby are shown in FIGS. 5-24. According to some embodiments, as shown in FIGS. 14-15, 20-21, and 23-24, the semiconductor device 500 includes a pillar 528, an insulator 524, and a conductor 526, wherein the insulator 524 concentrically surrounds the pillar 528 and the conductor 526 concentrically surrounds the pillar 528. In some embodiments, pillar 528 is configured as pillar channel 528 eand conductor 526 is configured as conductor gate 526 asuch that semiconductor device 500 includes a transistor as shown in FIGS. 14-15. In some embodiments, the pillar 528 is configured as the pillar drain 528 c, the pillar channel 528 eand a pillar source 528 b, wherein the pillar channel 528 eis disposed between the pillar drain 528 cand the pillar source 528 b, and the conductor is configured as the conductor gate 526 a, such that the semiconductor device 500 includes a transistor as shown in FIGS. 20-21. In some embodiments, pillar 528 is configured as pillar resistor 528 fand conductor 526 is configured as conductor gate 526 asuch that semiconductor device 500 includes a resistor as shown in FIGS. 23-24. Although often mentioned concentrically herein, this is not intended to be limited to only circular configurations. Rather, devices, elements, pillars, etc. that are mentioned as surrounding somewhat concentrically, surrounding somewhat concentrically, or the like, have cross-sectional dimensions, configurations, etc. that are not just circular, in accordance with some embodiments. Thus, a column, aperture, etc. has a square, rectangular, octagonal, elliptical, etc. cross-section, in accordance with some embodiments. Thus, although round, columnar, etc. dimensions are described, shown, etc., the present disclosure including the scope of the appended claims is not limited thereto. Other configurations are contemplated instead.At 102, a first opening 514 is formed in a substrate 508 as shown in FIG. 9. Prior to FIG. 9, in accordance with some embodiments, a conductor 516 overlies a carrier substrate 502, as shown in FIG. 5. In some embodiments, the conductor 516 is formed by depositing and / or growing a layer of conductive material and then the layer of conductive material is patterned, such as by etching. In some embodiments, a first dielectric layer 503 is then formed over the conductor 516, such as by growth and / or deposition, to form a first semiconductor compound 520. In some embodiments, the first dielectric layer 503 comprises silicon oxide (SiO 2) and / or silicon nitride (Si 3 N 4). In some embodiments, the conductor 516 has a thickness of between about 0.1 μm to about 4.0 μm. In some embodiments, a second semiconductor compound 521 including an adhesive oxide 506, a substrate 508, and an upper substrate 510, as shown in FIG. 6, is turned over and disposed over the first semiconductor compound 520, as shown in FIG. 7. In some embodiments, the carrier substrate 502, the substrate 508, and / or the top substrate 510 have a thickness between about 200 μm and about 700 μm. In some embodiments, the carrier substrate 502, the substrate 508, the top substrate 510, and / or other substrates mentioned herein include an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the carrier substrate 502, the substrate 508, the top substrate 510, and / or other substrates mentioned herein include silicon, silicon germanium (SiGe), and / or polysilicon. In some embodiments, the adhesion oxide 506 secures the substrate 508 to the first dielectric layer 503. In some embodiments, the adhesion oxide 506 comprises an oxide. In some embodiments, the adhesion oxide 506 has a thickness between about 10 μm and about 40 μm. In some embodiments, the top substrate 510 and a portion of the substrate 508 are removed, such as by H 2 or He, as shown in FIG. 8. In some embodiments, a horizontal or lateral crack is introduced into the substrate 508 to remove the portion of the substrate, such as where the portion of the substrate 508 being removed corresponds to a portion of the substrate 508 above the crack in a direction away from the carrier substrate 502 to the top substrate 510. In some embodiments, a first mask 518 is formed over the substrate 508 such that a portion of the substrate 508 is exposed over the conductor 516, as shown in FIG. 9. In some embodiments, the first opening 514 is formed in the substrate 508 over the conductor 516 such that at least a portion of the top surface 515 of the conductor 516 is exposed.At 104, a first dopant 522 is implanted into a sidewall of the substrate 508 defining the first opening 514 to form a conductor 526 such that the conductor 526 concentrically surrounds the first opening 514, as shown in FIG. 10, in accordance with some embodiments. In some embodiments, conductor 526 is configured as a conductor gate 526 a. In some embodiments, the conductor gate 526 aincludes polysilicon and / or doped silicon.At 106, an insulator 524 is formed adjacent the sidewalls of the conductor gate 526a such that the insulator 524 surrounds the first opening 514, as shown in FIG. 12. Prior to FIG. 12, in accordance with some embodiments, the insulator 524 is formed in the first opening 514 and over the first mask 518, as shown in FIG. 11. In some embodiments, the insulator 524 comprises a high dielectric constant material, such as an oxide. In some embodiments, the insulator 524 has a thickness between about 0.002 μm and about 2.0 μm. In some embodiments, the insulator 524 is formed by deposition. In some embodiments, the insulator 524 is removed from over the first mask 518 and the top surface 515 of the conductor 516, such as by chemical mechanical planarization (CMP) and / or dry etching, as shown in FIG. 12.At 108, a pillar 528 is formed in the first opening 514 such that the insulator 524 concentrically surrounds the pillar 528, as shown in FIGS. 14, 20, and 23, in accordance with some embodiments. In some embodiments, the pillar 528 is configured as a pillar channel 528 e, as shown in FIGS. 14-15, a pillar source 528 b, a pillar drain 528 c, and a pillar channel 528 e, where the pillar channel 528 eis between the pillar source 528 band the pillar drain 528 cas shown in FIGS. 16-21, or a pillar resistor 528 fas shown in FIGS. 22-24. Turning to FIG. 13, a first conductive material 538 is formed in the first opening 514 and over the first mask 518, such as by deposition. In some embodiments, the first conductive material 538 comprises polysilicon and / or doped silicon. In some embodiments, the pillar channel 528 eis formed such that the pillar channel 528 eis in contact with the conductor 516. In some embodiments, the excess first conductive material 538 and the first mask 518 are removed, such as by CMP, to form the pillar channel 528 e, as shown in FIG. 14. In some embodiments, the pillar channel 528 ehas a pillar width 529 of between about 0.5 μm and about 5.0 μm. Turning to FIG. 15, which shows a top view or overview of FIG. 14, in accordance with some embodiments, the top view or overview has a higher zoom plane than the side views, the conductor gate 526 acirculatory concentrically surrounds the insulator 524 and the insulator 524circulatory concentrically surrounds the pillar channel 528 e. In some embodiments, conductor 516 is connected to a current source (not shown) such that when a bias voltage is applied to conductor gate 526 a, current from the current source flows through pillar channel 528 e. In some embodiments, the pillar channel 528 eis connected to the conductor 516 and a via, transistor, and / or resistor. Turning to FIG. 16, an initial stage of formation of the pillar 528 is configured as a pillar source 528 b, a pillar drain 528 c, and a pillar channel 528 e, where the pillar channel 528 eis between the pillar source 528 band the pillar drain 528 c, in accordance with some embodiments. In some embodiments, a second material 511 is formed in the first opening 514 and over the first mask 518 such that the second material 511 is in contact with the top surface 515 of the conductor 516, in accordance with some embodiments. In some embodiments, the second material 511 comprises silicon and / or germanium. In some embodiments, a portion of the second material 511 is removed, such as by CMP and / or etching, to form a second material portion, the second material portion 511 having a height of the second material that is less than a pillar height of the pillar 528. In some embodiments, a second dopant 530 is implanted into the second material portion to form the pillar source 528 bas shown in FIG. 17. In some embodiments, the second dopant 530 comprises a p-type dopant, such as boron, and / or an n-type dopant, such as phosphorus. In some embodiments, a third material 513 is formed in the first opening 514 over the pillar source 528 band over the first mask 518, as shown in FIG. 18. In some embodiments, the second material 511 and the third material 513 are the same material. In some embodiments, the third material 513 comprises silicon and / or germanium. In some embodiments, a portion of the third material 513 is removed, such as by CMP, to form a portion of the third material 513, the portion of the third material 513 having a height of the third material that is less than a pillar height of the pillar 528. In some embodiments, a third dopant 536 is implanted into the portion of the third material 513 to form the pillar drain 528 csuch that a pillar channel 528 eis formed between the pillar source 528 band the pillar drain 528 cto form a transistor, as shown in FIG. 19. In some embodiments, the third dopant 536 comprises a p-type dopant, such as boron, and / or an n-type dopant, such as phosphorus. In some embodiments, excess material of the pillar drain 528 cand the first mask is removed, such as by CMP, as shown in FIG. 20. In some embodiments, the column 528 has a column width 529 between about 0.5 μm and about 5.0 μm. Turning to FIG. 21, which shows a top view or overview of FIG. 20, in accordance with some embodiments, the top view or overview has a higher zoom plane than the side views, the conductor gate 526 acirculatory concentrically surrounds the insulator 524 and the insulator 524circulatory concentrically surrounds the pillar drain 528 c, which overlies the pillar channel 528 eand the pillar source 528 c. In some embodiments, conductor 516 is connected to a current source (not shown) such that when a bias voltage is applied to conductor gate 526 a, current flows from the current source through pillar source 528 b, through pillar channel 528 e, and out pillar drain 528 c. In some embodiments, the pillar source 528 band / or the pillar drain 528 care connected to the conductor 516 and the pillar source 528 band / or the pillar drain 528 care connected to a via, a transistor, a capacitor, and / or a resistor. Turning to FIG. 22, which shows an initial stage of formation of the pillar 528 configured as the pillar resistor 528 f, in accordance with some embodiments. In some embodiments, a high resistance material 532, such as undoped silicon or low doped silicon, is formed in the first opening 514 and over the first mask 518, such as by deposition. In some embodiments, high resistance material 532 includes undoped silicon and / or low doped silicon. In some embodiments, the pillar resistor 528 fis formed such that the pillar resistor 528 fis in contact with the conductor 516. In some embodiments, excess high resistance material 532 and the first mask are removed, such as by CMP, to form a resistor, as shown in FIG. 23. Turning to FIG. 24, which shows a top view or overview of FIG. 23, in accordance with some embodiments, the top view or overview having a higher zoom plane than the side view, the conductor gate 526 aconcentrally surrounds the insulator 524 and the insulator 524 concentrically surrounds the pillar resistor 528 f. In some embodiments, conductor 516 is connected to a current source (not shown) such that when a bias voltage is applied to conductor gate 526 a, current from the current source flows through pillar resistor 528 f. In some embodiments, the column resistor 528 fis connected to the conductor 516 and a via, transistor, capacitor, and / or resistor.A method 200 of forming a semiconductor device 500 according to some embodiments is shown in FIG. 2, and one or more structures formed thereby at various stages of fabrication are shown in FIGS. 25-34. In some embodiments, a semiconductor device 500 includes a pillar 528, the pillar including an inner pillar portion 528 gand an outer pillar portion 528 h, an insulator 524, and a conductor 526, the insulator 524 concentrically surrounding the pillar 528, and the conductor 526 concentrically surrounding the insulator 524, as shown in FIG. 33. In some embodiments, the pillar 528 is configured as a capacitive pillar plate 528 dand the conductor 526 is configured as a capacitive conductor plate 526 d.At 202, an opening is formed in the substrate 508 as shown in FIG. 29. Prior to FIG. 29, in accordance with some embodiments, a first conductor 516 aand a second conductor 516 bare overlying a carrier substrate 502, as shown in FIG. 25. In some embodiments, the first conductor 516 aand the second conductor 516 bare formed by depositing and / or growing a layer of conductive material and then the layer of conductive material is patterned, such as by etching. In some embodiments, a first dielectric layer 503 is then formed over the first conductor 516 aand the second conductor 516 b, such as by growth and / or deposition, to form a third semiconductor compound 523. In some embodiments, the first dielectric layer 503 comprises silicon oxide (SiO 2) and / or silicon nitride (Si 3 N 4). In some embodiments, the conductor 516 aand / or the second conductor 516 bhas a thickness of between about 0.1 μm to about 4.0 μm. In some embodiments, a second semiconductor compound 521 including an adhesive oxide 506, a substrate 508, and an upper substrate 510, as shown in FIG. 26, is turned over and disposed over the third semiconductor compound 523, as shown in FIG. 27. In some embodiments, the carrier substrate 502, the substrate 508, and / or the top substrate 510 have a thickness between about 200 μm and about 700 μm. In some embodiments, the carrier substrate 502, the substrate 508, the top substrate 510, and / or other substrates mentioned herein include an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the carrier substrate 502, the substrate 508, the top substrate 510, and / or other substrates mentioned herein include silicon, silicon germanium (SiGe), and / or polysilicon. In some embodiments, the adhesion oxide 506 secures the substrate 508 to the first dielectric layer 503. In some embodiments, the adhesion oxide 506 comprises an oxide. In some embodiments, the adhesion oxide 506 has a thickness between about 10 μm and about 40 μm. In some embodiments, the top substrate 510 and a portion of the substrate 508 are removed, such as by H 2 or He, as shown in FIG. 28. In some embodiments, a horizontal or lateral crack is introduced into the substrate 508 to remove the portion of the substrate, such as where the portion of the substrate 508 being removed corresponds to a portion of the substrate 508 above the crack in a direction away from the carrier substrate 502 to the top substrate 510. In some embodiments, a first mask 518 is formed over the substrate 508 such that a portion of the substrate 508 is exposed over the first conductor 516 aand the second conductor 516 b. In some embodiments, the first opening 514 is formed in the substrate 508 over a portion of the first conductor 516 aand a portion of the second conductor 516 bso as to expose at least a portion of the top surface 515 of the first conductor 516 aand a top surface 515 of the second conductor 516 b. In some embodiments, a plurality of conductors 516 are formed in the first dielectric layer 503.At 204, an insulator 524 is formed adjacent the sidewalls of the substrate 508 defining the first opening 514 such that the insulator 524 surrounds the first opening 514, as shown in FIG. 30. Prior to FIG. 30, in accordance with some embodiments, the insulator 524 is formed in the first opening 514 and over the first mask 518, as shown in FIG. 29. In some embodiments, the insulator 524 comprises a high dielectric constant material, such as an oxide. In some embodiments, the insulator 524 has a thickness between about 0.002 μm and about 2.0 μm. In some embodiments, the insulator 524 is formed by deposition. In some embodiments, the insulator 524 is removed from over the first mask 518 and the top surface 515 of the first conductor 516 aand the top surface 515 of the second conductor 516 b, such as by chemical mechanical planarization (CMP) or dry etching, as shown in FIG. 30. In some embodiments, a first material 525 is formed in the first opening 514, such as by deposition, as shown in FIG. 31. In some embodiments, the first material 525 comprises silicon and / or germanium. In some embodiments, the first mask 518 is removed, such as by CMP, and a height of the first material 525 is decreased such that the first material is planar with the substrate 508. In some embodiments, a second mask 519 is formed over the substrate 508 and the first material 525 such that the second mask 519 does not overlay the insulator 524, as shown in FIG. 32.At 206, a first dopant 522 is implanted into a sidewall of the substrate 508 defining the first opening 514 to form a conductor 526 configured as a conductive capacitive plate 528 dsuch that the conductive capacitive plate 528 dconcentrally surrounds the insulator 524, as shown in FIG. 32, in accordance with some embodiments. In some embodiments, conductive capacitive plate 526d includes polysilicon and / or doped silicon.At 208, the pillar 528 is formed in the first opening 514, as shown in FIG. 32. In some embodiments, the column 528 is configured as a capacitive column plate 528 d. Prior to FIG. 32, in accordance with some embodiments, the inner pillar portion 528 gof the capacitive pillar plate 528 dcomprises the first material 525 as shown in FIG. 31. In some embodiments, the first dopant 522 is implanted adjacent to the insulator 524 to form an outer pillar portion 528 h. In some embodiments, the outer pillar portion 528 hconcentrally surrounds the inner pillar portion 528 g, the insulator 524 concentrically surrounds the outer pillar portion 528 h, and the conductive capacitive plate 528 dsurrounds the insulator 524, such that a capacitor is formed. In some embodiments, the outer pillar portion 528 hcomprises polysilicon and / or doped silicon. In some embodiments, the second mask 519 is removed, such as by CMP, as shown in FIG. 33. Turning to FIG. 34, which shows a top view or overview of FIG. 33, in accordance with some embodiments, the top view or overview having a higher zoom plane than the side views, conductive capacitive plate 526 dis concentrically surrounding insulator 524 and insulator 524 is concentrically surrounding capacitive pillar plate 528 d. In some embodiments, the first conductor 516 aand / or the second conductor 516 bis connected to a power source (not shown) such that when a current is applied to the conductive capacitive plate 526 d, current from the power source is stored. In some embodiments, the capacitive pillar plate 528 dis connected to the first conductor 516 aand / or the second conductor 516 b, and the conductive capacitive plate 526 dis connected to a via, a transistor, a capacitor, and / or a resistor.A method 300 of forming a semiconductor device 500 according to some embodiments is shown in FIG. 3, and one or more structures formed thereby at various stages of fabrication are shown in FIGS. 35-45.In some embodiments, a semiconductor device 500 includes a pillar 528, an insulator 524, and a first portion of a conductor 526, wherein the insulator 524 concentrically surrounds the pillar 528 and the first portion of the conductor 526 concentrically surrounds the insulator 524, as shown in FIG. 43. In some embodiments, the first portion of the conductor 526 has a height of the first portion, where the height of the first portion is less than the pillar height of the pillar 528. In some embodiments, the pillar 528 is configured as a pillar gate 528 aand the conductor 526 is configured as a pillar source 526 b, pillar drain 526 c, and pillar channel 526 esuch that the pillar source 526 band the pillar drain 526 care not continuous.At 302, a second dopant 530 is implanted into the substrate 508 to form a first portion of the conductor 526, as shown in FIG. 36. Prior to FIG. 36, in accordance with some embodiments, the carrier substrate 502, the first dielectric layer 503, the conductor 516, the adhesion layer 506, and the substrate 508 are as shown in FIG. 35, formed as described above with reference to FIGS. 5-7. In some embodiments, a first mask 518 is formed over the substrate 508 such that the first mask 518 exposes a portion of the substrate 508 over the conductor 516, as shown in FIG. 36. In some embodiments, the second dopant 530 is implanted into the exposed substrate 508. In some embodiments, the second dopant 530 comprises a p-type dopant, such as boron, and / or an n-type dopant, such as phosphorus. In some embodiments, the implant of the second dopant 530 forms a conductor source 526 band / or a conductor drain 526 c. Turning to Fig. 37, a top view or overview of Fig. 36 is shown. In some embodiments, the first mask 518 is configured such that the first mask 518 exposes a first segment 509 aof the substrate 508 and a second segment 509 bof the substrate 508. In some embodiments, the second dopant 530 is implanted such that the first segment 509 ais configured as a conductor source 526 band / or conductor drain 526 c. In some embodiments, the second segment 509 bis configured as a conductor source 526 bwhen the first segment 509 ais configured as a conductor drain 526 c. In some embodiments, the second segment 509 bis configured as the conductor drain 526 cwhen the first segment 509 ais configured as the conductor source 526 b. Turning to Fig. 38, a top view or overview of Fig. 36 is shown. In some embodiments, the first mask 518 is configured such that the first mask 518 exposes a first segment 509 aof the substrate 508, a second segment 509 bof the substrate 508, a third segment 509 cof the substrate 508, and a fourth segment 509 dof the substrate 508. In some embodiments, the second dopant 530 is implanted such that the first segment 509 aand the third segment 509 care configured as a conductor source 526 band / or a conductor drain 526 c. In some embodiments, the second segment 509 band the fourth segment 509 dare configured as conductor sources 526 bwhen the first segment 509 aand the third segment 509 care configured as conductor drains 526 c. In some embodiments, the second segment 509 band the fourth segment 509 dare configured as conductor drains 526 cwhen the first segment 509 aand the third segment 509 care configured as conductor sources 526 b.At 304, a first opening 514 is formed in the substrate 508 such that the first portion of the conductor 526 surrounds the first opening 514, as shown in FIG. 39. In some embodiments, the first opening 514 is formed by etching. In some embodiments, forming the first opening 514 removes a portion of the first mask layer 518 over the conductor 516. In some embodiments, the first opening 514 exposes at least a portion of the top surface of the conductor 516. In some embodiments, the first opening 514 is surrounded by the conductor source 526 b, the conductor drain 526 c, and the conductor channel 526 esuch that the conductor channel 526 eis between the conductor source 526 band the conductor drain 526 c.At 306, an insulator 524 is formed adjacent the sidewalls of the substrate 508 defining the first opening 514 and sidewalls of the first portion of the conductor 526 such that the insulator 524 concentrically surrounds the first opening 514, as shown in FIG. 41. Prior to FIG. 41, in accordance with some embodiments, the insulator 524 is formed in the first opening 514, over the first portion of the conductor 526, and over the first mask 518, as shown in FIG. 40. In some embodiments, the insulator 524 comprises a high dielectric constant material, such as an oxide. In some embodiments, the insulator 524 has a thickness between about 0.002 μm and about 2.0 μm. In some embodiments, the insulator 524 is formed by deposition. In some embodiments, the insulator 524 is removed from over the first mask 518 and the top surface 515 of the conductor 516, such as by CMP and / or dry etching, as shown in FIG. 41.At 308, a pillar 528 is formed in the first opening 514 such that the insulator 524 concentrically surrounds the pillar 528, as shown in FIG. 43, in accordance with some embodiments. In some embodiments, pillar 528 is configured as pillar gate 528 a, as shown in FIGS. 43-44. Turning to FIG. 43, a second conductive material 527 is formed in the first opening 514 and over the first mask 518, such as by deposition. In some embodiments, the second conductive material 527 includes polysilicon and / or metal, such as copper. In some embodiments, the excess second conductive material 527 and the first mask 518 are removed, such as by CMP, to form the pillar gate 528 a, as shown in FIG. 43. In some embodiments, the pillar gate 528 ais formed such that the pillar gate 528 ais in contact with the conductor 516. In some embodiments, the pillar gate 528 ahas a pillar width 529 between about 0.5 μm and about 5.0 μm. Turning to FIG. 44, which shows a top view or overview of FIG. 43, in accordance with some embodiments, the top view or overview having a zoom plane higher than the side views, the first conductor portion 526 is configured as the conductor source 526 b, the conductor drain 526 c, and the conductor channel 526 esuch that the conductor channel 526 eis between the conductor source 526 band the conductor drain 526 c, concentrically surrounds the insulator 524, and the insulator 524 concentrically surrounds the pillar gate 528 a. In accordance with some embodiments, FIG. 44 shows the first portion of the conductor 526 as formed in FIG. 37. Turning to FIG. 45 showing a top view or overview of FIG. 42, in accordance with some embodiments, the top view or overview has a zoom plane higher than the side view, the first conductor portion 526 concentrically surrounds the insulator 524 and the insulator 524 concentrically surrounds the pillar gate 528 a. In some embodiments, the first conductor portion 526 is configured as a first conductor source 526 b, a second conductor source 526 b, a first conductor drain 526 c, a second conductor drain 526 cand conductor channels 526 esuch that the conductor channels 526 eare between the first conductor source 526 band the first conductor drain 526 cand between the second conductor source 526 band the second conductor drain 526 c. In some embodiments, FIG. 45 shows the first portion of the conductor 526 as formed in FIG. 38. In some embodiments, conductor 516 is connected to a current source (not shown) such that when a bias voltage is applied to pillar gate 528 a, current flows through first conductor portion 526.A method 400 of forming a semiconductor device 500 according to some embodiments is shown in FIG. 4, and one or more structures formed thereby are shown in FIGS. 46- 53 at various stages of fabrication.In some embodiments, a semiconductor device 500 includes a pillar 528, an insulator 524, a first conductor portion 526, and a second conductor portion 526, wherein the insulator 524 concentrically surrounds the pillar 528, the first conductor portion 526 concentrically surrounds the pillar 528, and the second conductor portion 526 concentrically surrounds the pillar 528, as shown in FIG. 52. In some embodiments, the pillar 528 is configured as a pillar gate 528 a, the first conductor portion 526 is configured as a conductor source 526 band / or a conductor drain 526 c, and the second conductor portion 526 is configured as a conductor source 526 bwhen the first conductor portion 526 is configured as a conductor drain 526 c. In some embodiments, the second conductor portion 526 is configured as a conductor drain 526 cwhen the first conductor portion 526 is configured as a conductor source 526 bas shown in FIG. 52.At 402, a third dopant (not shown) is implanted into the substrate 508 to form the second conductor portion 526 configured as a conductor drain 526c, as shown in FIG. 47. Prior to FIG. 47, in accordance with some embodiments, the carrier substrate 502, the first dielectric layer 503, the conductor 516, the adhesion layer 506, and the substrate 508 are shown in FIG. 46 and are formed as described above with reference to FIGS. 5-7, in accordance with some embodiments. In some embodiments, the first mask 518 is formed over the substrate 508 such that the first mask 518 exposes a portion of the substrate 508 over the conductor 516, as shown in FIG. 47. In some embodiments, the third dopant is implanted into the exposed substrate 508. In some embodiments, the third dopant comprises a p-type dopant, such as boron, or an n-type dopant, such as phosphorus. In some embodiments, the third dopant implant forms a conductor source 526 b, not shown, and / or a conductor drain 526 c, as shown in FIG. 48. In some embodiments, the third implant is a deep implant, such as an implant having a high energy, such as an energy between about 100 keV and about 500 keV. In some embodiments, the second conductor portion 526 configured as a pillar drain 526 cis of a second portion height 511.At 404, a second dopant 530 is implanted into the substrate 508 to form the first conductor portion 526 configured as a conductor source 526 bas shown in FIG. 47. In some embodiments, the second dopant 530 is implanted into the substrate 508 over the second portion of the conductor 526. In some embodiments, the second dopant 530 comprises a p-type dopant, such as boron, and / or an n-type dopant, such as phosphorus. In some embodiments, the implementation of the second dopant 530 forms a conductor source 526 bas shown in FIG. 47 and / or a conductor drain 526 cthat is not shown. In some embodiments, the second dopant 530 is a shallow implant, such as a low energy implant, such as an energy between about 10 keV and about 50 keV. In some embodiments, the first portion of the conductor configured as a pillar source 526 bhas a first portion height 521.At 406, a first opening 514 is formed in the substrate 508 such that the first portion of the conductor 526 surrounds the first opening 514 and the second portion of the conductor 526 surrounds the first opening 514, as shown in FIG. 48. In some embodiments, the first opening 514 is formed by etching. In some embodiments, forming the first opening 514 removes a portion of the first mask layer 518 over the conductor 516. In some embodiments, the first opening 514 exposes at least a portion of the top surface of the conductor 516. In some embodiments, the first opening 514 is concentrically surrounded by the first portion of the conductor 526 configured as a conductor source 526 b. In some embodiments, the first opening 514 is concentrically surrounded by the second portion of the conductor 526 configured as the conductor drain 526 c. In some embodiments, the first opening is concentrically surrounded by a conductor channel 526 esuch that the conductor channel 526 eis between the conductor source 526 band the conductor drain 526 c.At 408, an insulator 524 is formed adjacent sidewalls of the substrate 508, sidewalls of a first portion of the conductor 526 configured as a conductor source 526 b, and sidewalls of a second portion of the conductor 526 configured as a conductor drain 526 csuch that the insulator 524 concentrically surrounds the first opening 514, and the first portion of the conductor and the second portion of the conductor concentrically surround the insulator 524, as shown in FIG. 50. Prior to FIG. 50, in accordance with some embodiments, the insulator 524 is formed in the first opening 514, over the conductor drain 526 c, the conductor source 526 band the first mask 518, as shown in FIG. 49. In some embodiments, the insulator 524 comprises a high dielectric constant material, such as an oxide. In some embodiments, the insulator 524 has a thickness between about 0.002 μm and about 2.0 μm. In some embodiments, the insulator 524 is formed by deposition. In some embodiments, the insulator 524 is removed from over the first mask 518 and the top surface 515 of the conductor 516, such as by chemical mechanical planarization (CMP) and / or dry etching, as shown in FIG. 50.At 410, a pillar 528 is formed in the first opening 514 such that the insulator 524 concentrically surrounds the pillar 528, as shown in FIG. 52, in accordance with some embodiments. In some embodiments, pillar 528 is configured as a pillar gate 528 a, as shown in FIGS. 52- 53. Prior to FIGS. 52-53, in accordance with some embodiments, a second conductive material 525 is formed in the first opening 514 and over the first mask 518, such as by deposition, as shown in FIG. 51. In some embodiments, the second conductive material 525 comprises polysilicon and / or metal, such as copper. In some embodiments, excess second conductive material 525 and first mask 518 are removed, such as by CMP, to form pillar gate 528 a, as shown in FIG. 52. In some embodiments, the pillar gate 528 ais formed such that the pillar gate 528 ais in contact with the conductor 516. In some embodiments, the pillar gate 528a has a pillar width 529 between about 0.5 μm and about 5.0 μm. In some embodiments, the pillar gate 528 ahas a pillar height 531, where the pillar height 531 is greater than a sum of the height of the first portion 521 and the height of the second portion 311. Turning to FIG. 53, which shows a top view or overview of FIG. 52, in accordance with some embodiments, where the top view or overview has a higher zoom plane than the side views, the conductor source 526 bsurrounds the conductor drain 526 cin a concentric manner, and the insulator 524 surrounds the pillar gate 528 ain a concentric manner. In some embodiments, conductor 516 is connected to a current source (not shown) such that when a bias voltage is applied to pillar gate 528 a, current flows from pillar source 526 bto pillar drain 526 cthrough pillar channel 526 e.The foregoing describes features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objects and / or to realize the same advantages of the embodiments introduced herein.Various acts of embodiments are provided herein. The order in which some or all of the operations are described should not be understood as necessarily depending on the order. Alternative orderings will become apparent knowing this description. Furthermore, it should be understood that not all operations need necessarily be present in each embodiment provided herein. It should also be appreciated that in some embodiments not all operations are necessary.It will be appreciated that layers, devices, elements, etc. shown herein are shown with certain dimensions relative to each other, such as structural dimensions or orientations, for example for ease and convenience of understanding, and that in some embodiments, their actual dimensions may vary substantially from those shown herein. In addition, there are a variety of techniques for forming the layers, devices, elements, etc. mentioned herein, such as etching techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques such as magnetron or ion beam sputtering, growth techniques such as thermal growth, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), CVD in plasma (PECVD), or atomic layer deposition (ALD), as examples.Further, "exemplary" is used herein to serve as an example, embodiment, illustration, etc., and is not necessarily advantageous. As used in this application, "or" is intended to mean inclusive "or" rather than exclusive "or.". In addition, "a" as used in this application and the appended claims will generally be understood to mean "one or more" unless otherwise indicated or clearly understood from the context to be the singular form. In addition, at least one of A and B and / or the like is generally intended to mean A or B or both A and B. Moreover, to the extent that "comprises," "comprises," "has," "with," or variants thereof are used, such terms are intended to be inclusive, similar to the term "comprises.". Moreover, unless otherwise stated, "first," "second," or the like, are not intended to indicate a temporal aspect, a spatial aspect, an order, etc. Rather, such terms are used only as identifiers, names, etc. for devices, elements, features, etc. A first element and a second element generally correspond to, for example, element A and element B, or two different or two identical elements, or the same element.

Claims

A method (100) of forming a semiconductor device (500), comprising: forming a conductor (516) over a carrier substrate (502) by depositing a layer of conductive material; forming a dielectric layer (503) over the carrier substrate (502), wherein a first portion of the dielectric layer (503) contacts a top surface of the conductor (516) and a second portion of the dielectric layer (503) contacts a side surface of the conductor (516), wherein the first and second portions of the dielectric layer (503) are formed of the same material; forming a substrate (508) over the dielectric layer (503); forming (102) a first opening (514) in the substrate (508) and the first portion of the dielectric layer (503) and exposing at least a portion of a top surface (515) of the conductor (516) through the opening (514); at least one of implanting (104) a first dopant (522) into sidewalls of the substrate (508) defining the opening (514) such that a conductor gate (526a) concentrically surrounds the opening (514); and forming (106) an insulator (524) adjacent sidewalls of the conductor gate (526a) such that the insulator (524) concentrically surrounds the opening (514); or forming (106) an insulator (524) adjacent sidewalls of the substrate (508) defining the opening (514) such that the insulator (524) concentrically surrounds the opening (514); and implanting a first dopant (522) into the sidewalls of the substrate (508) such that a conductor gate (526a) concentrically surrounds the insulator (524); and forming (108) a pillar (528) in the opening (514) such that the insulator (524) concentrically surrounds the pillar (528).The method (100) of claim 1, wherein forming a pillar (528) comprises: filling the opening (514) with a first material, wherein the first material is a conductive material (538).The method (100) of claim 1, wherein forming a pillar (528) comprises: filling the opening (514) with a material (528f) comprising undoped silicon or low doped silicon.The method (100) of claim 1, wherein forming a pillar (528) comprises: filling a bottom portion of the opening (514) with a second material; implanting a second dopant into the second material; filling a remaining portion of the opening (514) with a third material; implanting a third dopant into a top portion of the third material.The method (100) of claim 4, wherein the second material (511) and the third material (513) comprise silicon or germanium.The method of any one of claims 1 to 5, wherein the carrier substrate (502) and / or the substrate (508) has a thickness of about 200 μm to about 700 μm.The method of any of claims 1 to 6, wherein the carrier substrate (502) and / or the substrate (508) comprises an epitaxial layer, a silicon-on-insulator structure, a wafer, or a chip formed from a wafer.The method of any one of claims 1 to 7, wherein the carrier substrate (502) and / or the substrate (508) comprises at least one of silicon, silicon germanium, or polysilicon.The method of any of claims 1 to 8, further comprising: forming an adhesion oxide (506) to attach the substrate (508) to the first dielectric layer (503).The method of claim 9, wherein the adhesion oxide (506) has a thickness of about 10 μm to about 40 μm.The method of any of claims 1 to 10, wherein the conductor gate (526a) comprises polysilicon and / or doped silicon.The method of any of claims 1 to 11, wherein the insulator (524) comprises an oxide.The method of any one of claims 1 to 12, wherein the insulator (524) has a thickness of about 0.002 μm to about 2.0 μm.

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