Semiconductor device

Abstract

Semiconductor device comprising: an n-drift layer (1); a p-base layer (2) in a channel region on the n-drift layer (1); an n-emitter layer (3) on the p-base layer (2); a gate trench electrode (5) which penetrates the p-base layer (2) and the n-emitter layer (3) and is in contact with the p-base layer (2) and the n-emitter layer (3) via a gate insulating film (6); a p-anode layer (7) in a region outside the channel region on the n-drift layer (1), wherein the impurity concentration of the p-anode layer (7) is lower than the impurity concentration of the p-base layer (2); an emitter electrode (9) connected to the n-emitter layer (3) and the p-anode layer (7); a p-collector layer (11) below the n-drift layer (1); an n-cathode layer (12) below the n-drift layer (1); a collector electrode (13) connected to the p-collector layer (11) and the n-cathode layer (12); an n-buffer layer (14) surrounding the p-collector layer (11); and a p-separation layer (15) surrounding the n-cathode layer (12), wherein the n-buffer layer (14) comprises a high-resistance n-buffer layer interface (16) that separates the p-collector layer (11) and the p-separator layer (15), and the p-separator layer (15) has a high-resistance p-separator layer interface (17) that separates the n-cathode layer (12) and the n-buffer layer (14), wherein a total impurity concentration and an impurity concentration on surfaces of the n-buffer layer interface (16) and the p-separation layer interface (17) are reduced, a diffusion resistance and a contact resistance of the n-buffer layer interface (16) and the p-separation layer interface (17) are increased, and a lateral width of the n-buffer layer interface (16) and the p-separation layer interface (17) is narrow; the p-base layer (2) and the n-emitter layer (3) are arranged in a region separate from the p-anode layer (7) and the n-emitter layer (3) is not arranged above the n-cathode layer (12).

Description

[0001] The present invention relates to a reverse-conducting insulated gate bipolar transistor (RC-IGBT) that combines the characteristics of an IGBT and a diode into one structure, and more particularly to a semiconductor device that can reduce snapback.

[0002] Generally, power devices must meet various requirements, such as withstanding voltage, ensuring a safe operating range to prevent element destruction during operation, and the like. One of the most important requirements is low loss. Low loss in power devices has effects such as reducing the size and weight of the device, and, more broadly, contributes to environmental protection through reducing energy consumption. Furthermore, realizing these properties at the lowest possible cost is required. As a measure to solve this problem, a reverse conducting IGBT is proposed, which combines the characteristics of an IGBT and a diode into one structure.

[0003] The reverse conducting IGBT is illustrated, for example, on pages 133 to 136 of ISPSD2004. In a normal IGBT, only a p + -collector layer is formed on a rear surface, but in the reverse conducting IGBT, a p + -collector layer and a + A cathode layer is formed on a rear surface. Ideally, the reverse conducting IGBT can achieve the two effects of an IGBT and a diode in one structure.

[0004] However, this reverse conducting IGBT has some technical problems. One of them is snapback during conduction. To maintain a low forward voltage, it is necessary to have a pn junction consisting of the p-collector layer and an n-type - -drift layer is formed, is forward biased and a positive hole is drawn from the p + -collector layer is injected. Due to the presence of the n +-cathode layer, however, an electron current flowing from an emitter electrode flows to the n + The cathode layer is exposed to a problem that until this junction is turned on, snapback occurs, while no conductivity modulation occurs, and the turn-on voltage becomes high. A similar problem also occurs during FWD operation with current flowing in the opposite direction. If the gate voltage becomes positive and an N-channel MOSFET channel enters an enhanced state, the electron current flows to the channel side, and a similar snapback phenomenon occurs, leading to an increase in losses.

[0005] In response to these problems, a structure is shown on pages 283 to 286 of ISPSD2009 in which a locally wide p +-collector layer is formed and an IGBT operating section is formed first. In addition, on pages 161 to 164 of ISPSD2007, a structure is shown in which an n + The cathode layer is surrounded by a p-type separation layer, and an oxide film is embedded in a boundary with a back electrode. Both have an effect of suppressing snapback in an operating direction of an IGBT. However, the former structure has a problem of increasing a chip area, and the latter structure has a problem of increasing resistance heat of the back electrode, and the like.

[0006] Another problem with reverse conducting IGBTs is an increase in recovery current during FWD operation. In reverse conducting IGBTs, there is a trade-off between some of the characteristics of IGBT operation and FWD operation. Thus, it is difficult to reduce the recovery current when considering the balance. To solve this problem, there are methods of significantly reducing the concentration of a p-type base layer, macro-arranging the IGBT / FWD, local lifetime control, and the like (see, for example, JP 2005-101514 A, JP 2005-317751 A, JP 2007-134625 A, and JP 2008-053648 A). However, there are trade-off problems such as reduced resistance, deterioration of area efficiency, and the like, and sufficient improvement has not been achieved.

[0007] In the conventional reverse conducting IGBT, there was a problem of an increase in a forward voltage due to snapback during IGBT / FWD operation and an increase in quiescent current loss.

[0008] CN 103 383 958 A describes a semiconductor device in the form of an IGBT. A p-type base layer is arranged on an n-type drift layer. It extends from a channel region of the field-effect transistor contained in the IGBT to a region outside the channel region.

[0009] DE 10 2012 100 349 A1 discloses a semiconductor component comprising a semiconductor body with a base region and a first electrode arranged on a horizontal main surface of the semiconductor body. The semiconductor body further includes an IGBT cell with a body region forming a first pn junction with the base region, and a diode cell with an anode region forming a second pn junction with the base region. A source region in ohmic contact with the first electrode and an anti-latch-up region in ohmic contact with the first electrode are formed, in a vertical cross-section, only in the IGBT cell. The anti-latch-up region has a higher maximum doping concentration than the body region. Furthermore, a corresponding reverse-conducting IGBT is specified.

[0010] In view of the problems described above, it is an object of the present invention to provide a semiconductor device that can reduce snapback.

[0011] This object is achieved by the teaching of the independent claims. Particularly preferred embodiments of the invention are defined in the subclaims.

[0012] In the reverse conducting IGBT according to the present invention, an n-type buffer layer surrounds a p-type collector layer. A p-type separation layer surrounds an n-type cathode layer. The n-type buffer layer separates the p-type collector layer and the p-type separation layer. The p-type separation layer separates the n-type cathode layer and the n-type buffer layer. Therefore, the present invention makes it possible to reduce snapback.

[0013] The above and other objects, features, and advantages of the invention will become more apparent from the following description of the present invention taken in conjunction with the accompanying drawings, in which: Fig. 1 is a sectional view of a semiconductor device according to Embodiment 1 of the present invention; Fig. 2 a diagram showing an impurity concentration distribution along line AA' in Fig. 1 shows; Fig. 3 a diagram showing the impurity concentration distribution along line BB' in Fig. 1 shows; Fig. 4 is a plan view of a semiconductor device according to Embodiment 1 of the present invention; Fig. 5 to 13 are sectional views illustrating a manufacturing process of the semiconductor device according to Embodiment 1 in the present invention; Fig. 14 is a diagram showing a difference in the turn-off waveform of the IGBT between the case when the p + -collector layer is arranged directly under the p-anode layer, and the case when the n + -cathode layer is arranged directly below the p-anode layer; Fig. 15 is a diagram showing a difference in the turn-off waveform of the IGBT according to a size relationship between the width Wp of the p + -collector layer and the width Wn of the n + -cathode layer; Fig. 16 is a plan view of a variant 1 of the semiconductor device according to Embodiment 1 of the present invention; Fig. 17 is a plan view of a variant 2 of the semiconductor device according to Embodiment 1 of the present invention; Fig. 18 is a sectional view of a semiconductor device according to Embodiment 2 of the present invention; Fig. 19 is a sectional view of a semiconductor device according to Embodiment 3 of the present invention; Fig. 20 is a sectional view of a semiconductor device according to Embodiment 4 of the present invention; Fig. 21 is a plan view of a semiconductor device according to Embodiment 4 of the present invention; Fig. 22 is a sectional view of a semiconductor device according to Embodiment 5 of the present invention; Fig. 23 is a sectional view of a semiconductor device according to Embodiment 6 of the present invention; Fig. 24 is a sectional view of a semiconductor device according to Embodiment 7 of the present invention; Fig. 25 is a plan view of a semiconductor device according to Embodiment 7 of the present invention; Fig. 26 is a sectional view of a semiconductor device according to Embodiment 8 of the present invention; Fig. 27 is a sectional view of a variant of a semiconductor device according to Embodiment 8 of the present invention; Fig. 28 is a sectional view of a semiconductor device according to Embodiment 9 of the present invention; Fig. 29 is a plan view of a semiconductor device according to Embodiment 9 of the present invention; and Fig. 30 is a sectional view of a semiconductor device according to Embodiment 10 of the present invention.

[0014] Referring to the drawings, various embodiments of semiconductor devices according to the present invention will now be described. Like components are designated by like reference numerals, and their repeated description will be omitted. Example 1

[0015] Fig. 1 is a sectional view of a semiconductor device according to Embodiment 1 of the present invention. A p-base layer 2 is provided in a channel region on an n-drift layer 1. On the p-base layer 2, an n + -Emitter layer 3 and a p + -Contact layer 4 is provided. A gate trench electrode 5 made of polysilicon penetrates the p-base layer 2 and the n + -Emitter layer 3 and is in contact with these layers through a gate insulating film 6.

[0016] In a region other than this channel region, a p-anode layer 7 is provided on the n-drift layer 1. An impurity concentration (= doping concentration) of the p-anode layer 7 is lower than the impurity concentration of the p-base layer 2. In the p-anode layer 7, the p + -Contact layer 4 not formed.

[0017] An n-type carrier storage layer 8 is provided between the n-type drift layer 1 and the p-type base layer 2. The n-type carrier storage layer 8 is also provided under the p-type anode layer 7. An emitter electrode 9 is connected to the n-type + -Emitter layer 3, the p + -Contact layer 4 and the p-anode layer 7. The gate trench electrode 5 and the emitter electrode 9 are separated by an interlayer insulating film 10.

[0018] Under the n-drift layer 1 are a p + -collector layer 11 and a n + -cathode layer 12 is provided. A collector electrode 13 is connected to the p + -collector layer 11 and the n + -cathode layer 12. An n + -Buffer layer 14 surrounds the p + -collector layer 11, and a p-separation layer 15 surrounds the n + -Cathode layer 12. The n + -buffer layer 14 has a high resistance n-buffer layer boundary section 16 which connects the p +-collector layer 11 from the p + -separation layer 15. The p-separation layer 15 has a high resistance p-separation boundary section 17, which separates the n + -Cathode layer 12 from the n + -buffer layer 14 separates.

[0019] A floating region 18 is provided on the n-drift layer 1 between the channel region and the p-anode layer 7, which is not connected to the emitter electrode 9. A dummy gate trench electrode 19 and a dummy gate insulating film 20, which are connected to the emitter electrode 9 and are made of polysilicon, separate a channel region and the p-anode layer 7 from the floating region 18. The p-anode layer 7 is surrounded by the dummy gate trench electrode 19 and the dummy gate insulating film 20.

[0020] Directly below the p-anode layer 7 is the n +-cathode layer 12, which is required for FWD operation. A ratio of a width of the p-collector layer 11, which functions as a collector during IGBT operation, to a cell width is greater than a ratio of the width of the n + -Cathode layer 12, which acts as a cathode during FWD operation, to the cell width (ie Wp / (Wn+Wp) > Wn / (Wn+Wp)).

[0021] An N-channel MOSFET consists of the n-drift layer 1, the n-carrier storage layer 8, the p-base layer 2, the n + Emitter layer 3, gate insulating film 6, and gate trench electrode 5. A FWD is formed from the p-type anode layer 7 and the n-type carrier storage layer 8. The MOSFET and the FWD are connected in parallel to the n-type drift layer 1.

[0022] Next, a configuration for increasing the resistance of the n-buffer layer interface 16 and the p-isolation layer interface 17 will be described. Specifically, the total concentration and the surface concentration of the two are reduced, a diffusion resistance and a contact resistance are increased, and a width Wsn of the n-buffer layer interface 16 and a width Wsp of the p-isolation layer interface 17 are narrowed.

[0023] Fig. Figure 2 is a diagram showing an impurity concentration distribution along line AA' in Fig. 1 shows. Fig. Figure 3 is a diagram showing the impurity concentration distribution along a line BB' in Fig. 1 shows. An impurity peak concentration of the n-buffer layer interface 16 and the p-separation layer interface 17 are at a position deeper than a diffusion depth of the p + -collector layer 11 or the n +-cathode layer 12 is formed. That is, in a region between the p + -collector layer 11 and the n + -cathode layer 12 is the impurity concentration at the surfaces of the n + The concentration of the n-buffer layer 14 and the p-isolation layer 15 in contact with the collector electrode 13 is lower than the peak concentration of these two. Therefore, the impurity concentration of the n-buffer layer junction 16 and the p-isolation layer junction 17 becomes lower as they approach the collector electrode 13 on the back surface, reducing the surface concentration of the two and increasing the resistance.

[0024] In addition, the n-buffer layer boundary section 16 utilizes a lateral diffusion region of the n +-buffer layer 14, and the p-type separation layer boundary section 17 utilizes the lateral diffusion region of the p-type separation layer 15 to keep the concentration low. Therefore, the width Wsn and the width Wsp are preferably set to a lateral diffusion width. If a depth of the p + -collector layer 11 is set to a minimum of about 0.3 µm, the depth of the n + -buffer layer 14 should be approximately 0.7 to 1.5 µm. Since a diffusion width in a lateral direction has a lower rate than the diffusion width in a vertical direction, if its value is assumed to be a general value of 0.75, the width of the n-buffer layer boundary section 16 must be approximately 0.5 to 1.1 µm. Assuming this also applies to the relationship between the n + -cathode layer 12 and the p-separation layer 15, a distance between the p + -collector layer 11 and the n + -Cathode layer 12 preferably about 1.0 to 2.2 µm.

[0025] Alternatively, the width Wsn and the width Wsp are preferably set to minimum widths determined by a performance of a photolithography device used in a manufacturing process. In the photolithography device used in semiconductor manufacturing, an overlay misalignment can be kept to 2 µm or less even without using a conventional device. For the above reason, the distance between the p + -collector layer 11 and the n + -Cathode layer 12 preferably 2 µm or less or possibly 1.0 µm or less.

[0026] Fig. 4 is a plan view of a semiconductor device according to Embodiment 1 of the present invention. A sectional view taken along line CC' in Fig. 4 corresponds to Fig. 1. A surface structure of the semiconductor device is designed in a stripe type. The n +-Emitter layer 3 and the p + -Contact layer 4 is connected to the emitter electrode 9 through a contact hole 21. The p-anode layer 7 is connected to the emitter electrode 9 through a contact hole 22.

[0027] The following describes the operation of the semiconductor device according to this embodiment. During a quiescent operation in a forward direction of the IGBT, the MOSFET is turned on. Therefore, an electron flows from the emitter electrode 9 into the n-drift layer 1. Subsequently, the electron current flows into the n + -buffer layer 14 and flows through the n-buffer layer boundary section 16 into the collector electrode 13. Here, the n-buffer layer boundary section 16 is set to a high resistance and is the one in the p + -collector layer 11 and the n +-buffer layer 14 is forward biased with an extremely low current. Then a positive hole flows from the p + -collector layer 11 through the n + -buffer layer 14 into the n-drift layer 1, conductivity modulation takes place, and the steady state is reached. In the off state, the MOSFET is off, and an excess carrier is absorbed by the p-base layer 2, the p + -Contact layer 4 and the p-anode layer 7 to the emitter electrode 9.

[0028] During FWD operation, operation starts in a state where the potential of the emitter electrode 9 is higher than the potential of the collector electrode 13. The operation at this time varies depending on the gate potential, but a generally used case is described here where the gate voltage is positive. The gate trench electrode 5 is positive, and the MOSFET is turned on.

[0029] When the FWD enters an on state, the electron current flows from the n + -cathode layer 12 into the n-type drift layer 1, but in the conventional structure, the electron current does not flow to the diode first, but into the MOSFET, so that snapback operation occurs. In this embodiment, however, the p-type anode layer 7 is provided through the non-emitter-grounded floating region, and the high-resistance n-type drift layer 1 is arranged directly below the floating region. Thus, even a small amount of electrons flowing into the channel region simply turns on the pn junction formed between the p-type anode layer 7 and the n-type carrier storage layer 8, and the positive hole flows in from the emitter electrode 9. This causes conductivity modulation, and the steady state with a low voltage between the terminals is achieved.

[0030] When turning off, the operation starts when the potential of the emitter electrode 9 becomes lower than the potential of the collector electrode 13. As a base operation, the current decreases, while the pn junction between the p-base layer 2 and the p + -Contact layer 4 or the p-anode layer 7 is forward biased. After that, the polarity is reversed, the current increases, and a forward bias of the pn junction near the junction is removed, and the current increase stops. The excess carrier in the n-drift layer 1 is output, and the operation is completed (recovery operation).

[0031] A manufacturing method of the semiconductor device according to this embodiment will be described below. Fig. 5 to 13 are sectional views showing a manufacturing process of the semiconductor device according to Embodiment 1 of the present invention.

[0032] First, as in Fig. As illustrated in Figure 5, the surface structure of the semiconductor device is formed by a photolithography process, an injection process, a diffusion / film formation process, and the like. Since this can be done by ordinary manufacturing processes, the details will not be explained here.

[0033] Then, as in Fig. 6, a wafer is grounded and thinned from a back surface direction. After that, as shown in Fig. 7, a protective mask 23 for forming the n + -Buffer layer 14 and the p + -collector layer 11 is formed on the rear surface by means of photolithography. Here, areas for forming the n + -buffer layer 14 and the p-separation layer 15 by about 2 µm.

[0034] Then, as in Fig. 8, n-type impurities are injected at a position relatively deep from the back surface to form an n-type buffer layer forming region 24. It is designed so that a concentration peak becomes deeper than a diffusion depth of the p-type + -Collector layer 11 after a subsequent heat treatment.

[0035] Then, as in Fig. 9, p-type impurities are injected from the back surface at a position that is flat, so as to form a p + -collector layer forming region 25. After that, the protective mask 23 is removed. Subsequently, as shown in Fig. 10, a protective mask 26 for forming the p-separation layer 15 and the n + -cathode layer 12 is formed by a similar photolithography process. Here, areas for forming the n + -buffer layer 14 and the p-separation layer 15 by about 2 µm.

[0036] Then, as in Fig. 11, the p-type impurities are injected from the back surface at a position which is relatively deep to form a p-type separation layer forming region 27. It is designed so that the concentration peak becomes deeper than the diffusion depth of the n + -Cathode layer 12 after the subsequent heat treatment. Subsequently, as shown in Fig. 12, the n-type impurities are injected from the back surface at a position that is flat, so as to form an n + -cathode layer forming region 28.

[0037] Then, as in Fig. 13, by removing an injection mask and applying the heat treatment the n + -Buffer layer 14 and the p + -collector layer 11 and the n +-cathode layer 12 and the p-type separation layer 15 are formed. Subsequently, the semiconductor device according to this embodiment can be formed by forming a film of the collector electrode 13 on the back surface using a conventional semiconductor technique.

[0038] In this embodiment, the p + -collector layer 11 surrounding n-buffer layer 14, which the n + The p-type separation layer 15 surrounding the cathode layer 12, the high-resistance n-type buffer layer junction 16, and the p-type separation layer junction 17 are provided between them. As a result, snapback during IGBT / FWD operation is reduced, and quiescent current loss can be reduced.

[0039] In addition, the p-anode layer 7 is formed with a low concentration at a position away from the channel region including the n +The emitter layer 3 is arranged through the floating region. In the on-state and at a positive gate voltage, since the potential of the p-base layer 2 is close to the emitter potential, positive holes cannot flow easily. Thus, the current flows to the p-anode layer 7, and many carriers accumulate there. Therefore, in the recovery state, many of the carriers are output through the p-anode layer 7. Since the p-anode layer 7 is formed with a low concentration, the forward bias of the pn junction is quickly removed, and the off-state is reached without an increase in a recovery current (Irr). Therefore, the recovery current can be reduced. In addition, since the n-carrier storage layer 8 under the p-anode layer 7 acts in a direction of suppressing the injection of positive holes, the recovery current can be suppressed more effectively.

[0040] Fig. 14 is a diagram showing a difference in a turnoff waveform of the IGBT between the case when the p + -collector layer is arranged directly under the p-anode layer, and in the case when the n + -cathode layer is arranged. If the n + -cathode layer 12 is not arranged directly under the p-anode layer 7, a voltage rises until the displacement, since a displacement to the FWD is not carried out until the p-separation layer 15 and the n + -cathode layer 12 are forward biased. On the other hand, as in this embodiment, by arranging at least a part of the p-separation layer 15 and the n acting as a cathode +A current can be effectively supplied to the cathode layer 12 directly beneath the p-anode layer 7, which acts as an anode during FWD operation, and an overvoltage can be reduced. Furthermore, since the pn junction on the rear surface can be turned on more easily during FWD operation, a junction voltage Vf can be reduced and a loss can be reduced.

[0041] Fig. 15 is a diagram showing a difference in the turnoff waveform of the IGBT according to a size relationship between the width Wp of the p + -collector layer and the width Wn of the n + -cathode layer. If the ratio of the width of the p acting as a collector during IGBT operation + -collector layer 11 to cell width (Wp / (Wp+Wn)) is greater than the ratio of the width of the n acting as cathode during FWD operation + -cathode layer 12 to the cell width (Wn / (Wp+Wn)), ie if the width Wp of the p+ -collector layer 11 greater than the width Wn of the n + -cathode layer 12, an overvoltage when turning off the switching element interacting with the FWD can be reduced, and a switching loss can be reduced, as well as a quiescent current loss during IGBT operation. In this way, a reduction of Vce (sat) of the IGBT and snapback suppression can be realized by increasing Wp, and the p-type separation layer 15 and the n + -Cathode layer 12 can be easily forward biased by reducing Wn.

[0042] By combining the structures of this embodiment, snapback can be avoided even when the pitch on both the front and back surfaces is made smaller compared to the repeat width of the conventional short anode structure. As a result, the IGBT / FWD operates uniformly in the same area, improving area efficiency and reducing costs.

[0043] Furthermore, by connecting the dummy gate trench electrode 19 surrounding the p-anode layer 7 to the emitter electrode 9, the gate capacitance can be reduced and the size of a drive circuit when the gate terminal is driven can be made smaller. The electrode surrounding the p-anode layer 7 is formed by the dummy gate trench electrode 19, but it can also be formed by the gate trench electrode 5, and then the effect of reducing snapback and reducing recovery current can also be achieved.

[0044] Fig. 16 is a plan view of a variant 1 of the semiconductor device according to Embodiment 1 of the present invention. A sectional view taken along line DD' in Fig. 16 corresponds to Fig. 1. A the n + -A channel region containing an emitter layer 3 is arranged at a vertex of a regular hexagon and a p-anode layer 7 is arranged at its center. Fig. 17 is a plan view of a variant 2 of the semiconductor device according to Embodiment 1 of the present invention. A sectional view taken along line EE' in Fig. 17 corresponds to Fig. 1. A gate trench electrode 5 is arranged in a network state, the p-anode layer 7 is arranged at its center, and a channel region portion having the n + Emitter layer 3 is arranged on an outer periphery. Wiring connected to the channel region portion is omitted from the figure. In the case of these planar structures, effects similar to this embodiment can also be achieved. Example 2

[0045] Fig. 18 is a sectional view of a semiconductor device according to Embodiment 2 of the present invention. The n-buffer layer 14 is provided between the n-drift layer 1 and the p-collector layer 11, and the p-separation layer 15 is provided between the n-drift layer 1 and the n- + -cathode layer 12. An embedded oxide film 29 separates the p + -collector layer 11 and the p-separation layer 15 from each other and separates the n + -cathode layer 12 and the n-buffer layer 14 from each other.

[0046] When embedding the oxide film 29, a mask is first formed using a conventional photolithography technique, and oxygen is injected at a predetermined location using an impurity injection technique. After the mask is removed, the embedded oxide film 29 is formed by applying a heat treatment. The other structures can be formed using a manufacturing method similar to Embodiment 1.

[0047] The following describes the operation of the semiconductor device according to this embodiment. The explanation for the operation similar to Embodiment 1 is omitted.

[0048] When an IGBT is turned on, an electron current flows from the emitter electrode 9 to the back surface. Since the n + -Buffer layer 14 and the n +-cathode layer 12 are electrically separated by the embedded oxide film 29, the current does not flow into the n + -cathode layer 12, but flows from the n + -Buffer layer 14 into the p + -collector layer 11. As a result, positive holes flow from the p + -Collector layer 11, conductivity modulation occurs, and the on state is realized. In this embodiment, there is no snapback during IGBT operation, and there is no increase in loss caused by snapback.

[0049] At the FWD, the positive holes flowing in from the anode layer 7 flow, since the p-collector layer 11 and the p + -separation layer 15 are insulated by the embedded oxide film 29, not to the p-collector layer 11, but into the n +-Cathode layer 12. As a result, the diode begins conductivity modulation operation. Since no snapback behavior is observed during operation in this direction, there is no loss caused by snapback.

[0050] In addition, since an oxide film is not formed at the boundary between the collector electrode 13 and a Si layer as in the conventional example, the shape becomes flat. As a result, thermal resistance at the back surface can be kept low, and thus problems such as reduced resistance of a short circuit caused by a local temperature rise and the like can be avoided. Example 3

[0051] Fig. 19 is a sectional view of a semiconductor device according to Embodiment 3 of the present invention. There is no n-type carrier storage layer 8 in this embodiment. By omitting the n-type carrier storage layer 8, injection of positive holes can be increased, and snapback during FWD operation can be particularly reduced. Particularly, if a repetition interval of the surface pattern is short, the effect of realizing a reduction in snapback and a simultaneous reduction in the recovery current is high. Example 4

[0052] Fig. 20 is a sectional view of a semiconductor device according to Embodiment 4 of the present invention. In Embodiment 1, the n-type carrier storage layer 8 is provided directly under the p-type anode layer 7, but in this embodiment, the low-concentration p-type anode layer 7 extends to the bottom portion of the dummy gate trench electrode 19.

[0053] By omitting the n-type carrier storage layer 8, the injection of positive holes can be increased and, in particular, snapback during FWD operation can be reduced. Furthermore, by forming the deep, low-concentration p-type anode layer 7, snapback can be further reduced and recovery loss can also be reduced. This embodiment is effective for a structure with a short surface pattern repetition interval, similar to Embodiment 3.

[0054] Ideally, the deep, low-concentration p-type anode layer 7 is formed, but if there is a process of introducing a deep, high-concentration p-type impurity layer in the manufacturing process, the p-type anode layer 7 can be formed simultaneously with the high-concentration p-type impurity layer. As a result, the structure of this embodiment can be realized without expanding the manufacturing process.

[0055] Fig. 21 is a plan view of a semiconductor device according to Embodiment 4 of the present invention. By calculating a ratio such that a total impurity concentration becomes the design concentration of the p-type anode layer 7 and disposing a plurality of high-concentration p-type impurity layers 30 in a distributed manner, the effective p-type anode layer 7 can be formed. Example 5

[0056] Fig. 22 is a sectional view of a semiconductor device according to Embodiment 5 of the present invention. The impurity concentration of the p-type anode layer 7 and the p-type base layer 2 is the same. Thus, the p-type anode layer 7 can be formed simultaneously with the p-type base layer 2. Thus, the effect similar to Embodiment 1 can be achieved without increasing the manufacturing cost. Example 6

[0057] Fig. 23 is a sectional view of a semiconductor device according to Embodiment 6 of the present invention. Compared with Embodiment 1, the width of the p-anode layer 7 is made smaller. As a result, injection efficiency of positive holes flowing in from the p-anode layer 7 is reduced, and recovery current can be lowered. This is effective if overall loss reduction can be realized by lowering the recovery current. The manufacturing process is the same as in Embodiment 1. In addition, the recovery current can be further reduced by simultaneously applying the feature of Embodiment 5. Example 7

[0058] Fig. Fig. 24 is a sectional view of a semiconductor device according to Embodiment 7 of the present invention. Compared to Embodiment 1, an emitter connection resistor 31 is connected between the emitter electrode 9 and the n +-Emitter layer 3 switched.

[0059] When the FWD operation mode is performed in Embodiment 1, since the MOSFET is turned off if the positive voltage is applied to the gate trench electrode 5, the electron current does not flow to the pn junction formed by the p-anode layer 7 and the n-carrier storage layer 8, but first flows into the MOSFET. On the other hand, in this embodiment, a DC resistor is connected to the MOSFET, and a voltage drop occurs due to the flow of the electron current, and thus the current can easily flow to the pn junction of the p-anode layer 7 and the n-carrier storage layer 8. Therefore, by more effectively generating conductivity modulation, snapback can be reduced / suppressed, thereby reducing losses during FWD operation.

[0060] Fig. 25 is a plan view of a semiconductor device according to Embodiment 7 of the present invention. A first contact hole 32 connects the n +-emitter layer 3 and the emitter electrode 9, and a second contact hole 33 connects the p-base layer 2 and the emitter electrode 9. The first contact hole 32 and the second contact hole 33 are separated from each other. As a result, the voltage drop generated in the first contact hole 32 becomes larger than in the case where the contact holes are integrally formed, and the emitter connection resistance 31 can be realized. In addition, by making the area of ​​the first contact hole 32 smaller than the area of ​​the second contact hole 33, the contact resistance becomes higher, and the effect of this embodiment can be achieved more easily. Since this embodiment can be formed with the flux similar to that of Embodiment 1 by changing the mask of the contact hole, a detailed description of the manufacturing process will be omitted.

[0061] The surface concentration of the n +-Emitter layer can be made lower than the peak concentration. As a result, since the impurity concentration of the n + -Emitter layer 3 becomes lower the closer it comes to the emitter electrode 9, the emitter connection resistance 31 can be realized. Example 8

[0062] Fig. 26 is a sectional view of a semiconductor device according to Embodiment 8 of the present invention. Compared with Embodiment 1, a floating region between the channel region where the N-channel MOSFET is formed and a region where the p-anode layer 7 is formed is made wider. As a result, snapback occurring in the forward characteristics during FWD operation can be effectively reduced. In addition, by decreasing the area ratio of the p-anode layer 7, the recovery current is reduced and a loss can be reduced. In this embodiment, one p-anode layer 7 is provided for two channel regions, and by providing one p-anode layer 7 for a plurality of channel regions, a free design can be realized, so that the characteristics of the IGBT and the diode become the desired characteristics.

[0063] Fig. Fig. 27 is a sectional view of a variant of a semiconductor device according to Embodiment 8 of the present invention. The floating region is made wider than in the device of Fig. 26. As a result, an enhanced effect can be achieved. Example 9

[0064] Fig. Fig. 28 is a sectional view of a semiconductor device according to Embodiment 9 of the present invention. In an active region, a cell having the characteristics of Embodiment 1 is repeatedly arranged. In a terminal region, a p + -Drain layer 34 with a depth greater than the depth of the gate trench electrode 5 is provided. The p + -sink layer 34 is connected to the emitter electrode 9. At the p + -Drain layer 34, a polysilicon electrode 35 and an aluminum electrode 36 are formed sequentially through the interlayer insulating film 10.

[0065] An emitter connection resistor 37 is connected between the p + -sink layer 34 and the emitter electrode 9. Directly below the p + -sink layer 34, the p-collector layer 11 and the n-buffer layer 14 are provided, and the n + -Cathode layer 12 and the p-separation layer 15 are not provided.

[0066] An operation of the semiconductor device according to this embodiment will now be described. In the FWD operation mode, the emitter electrode 9 functions as an anode side of the diode. The p-type impurity regions connected to the emitter electrode 9 are the p + -Contact layer 4, the p-base layer 2, the p-anode layer 7 and the p + -Sink layer 34.

[0067] The p +The sink layer 34 is used to diffusionally hold a surge voltage like a guard ring and must be set at a relatively high concentration, and thus a large amount of positive holes flows out of the emitter electrode 9 and increases the recovery current. Therefore, in this embodiment, the n + -Cathode layer 12 not directly under this p + -drain layer 34 is provided, but the p-collector layer 11 is provided, and thus electrons are not supplied from the collector electrode 13 directly below it. Since the FWD operation itself of the p + As a result, a loss / reduction due to an increase in the recovery current can be suppressed. In this embodiment, the p-collector layer 11 and the n-buffer layer 14 are directly below the p- + -sink layer 34 is provided, but by providing at least the p +-Collector layer 11 the effect can be achieved.

[0068] In addition, the emitter connection resistor 37 is connected between the emitter electrode 9 and the p + -sink layer 34. By providing a resistor in a current path performing the FWD operation as above, a bias voltage of the pn junction of the p + -sink layer 34 and the n-drift layer 1 in the forward direction during FWD operation, and the p + The number of positive holes flowing into the sink layer 34 decreases. Therefore, the conductivity modulation in this region becomes smaller, and the increase in the recovery current can be suppressed.

[0069] Fig. 29 is a plan view of a semiconductor device according to Embodiment 9 of the present invention. By forming an emitter electrode 9 with the p +By forming the contact hole 38 connecting the emitter and drain layers 34 in a point state, the emitter connection resistor 37 is realized. Since this method can be realized only by changing a mask of a light print in the process of forming the contact hole 38, an increase in manufacturing costs can be prevented. Example 10

[0070] Fig. 30 is a sectional view of a semiconductor device according to an embodiment 10 of the present invention. In the active region, a cell having the features of embodiment 1 is repeatedly arranged. In the connection region, the p + -drain layer 34 with a depth deeper than that of the gate trench electrode 5. An embedded oxide film 39 is provided between the n-drift layer 1 and the collector electrode 13 directly below the p + -Sink layer 34 is provided.

[0071] A main path of inflow from the p +The sink layer 34 is blocked by the embedded oxide film 39 during FWD operation, and there is no current flowing in from directly below it, including the recovery current, etc., thus making the recovery current small and reducing loss. Furthermore, since irregularity of the back surface electrode can be reduced, radiation characteristics are improved, and problems such as a reduced resistance of a short circuit caused by a local temperature rise and the like can be avoided.

[0072] In Embodiments 9 and 10, the cell structure has the feature of Embodiment 1, but Embodiments 1 to 8 can also be applied. Furthermore, it can also be applied to a structure in which a polarity of the p-type line / n-type line is reversed. Furthermore, even if the cell structure is not an IGBT, it can be applied to a structure with a body diode such as a FWD as in a power MOSFET, whereby snapback and the recovery current during FWD operation can be reduced. In addition, all of the embodiments can be combined with each other.

[0073] The semiconductor device also applies to wide-band semiconductors with a band gap larger than silicon. Wide-band semiconductors include silicon carbide, gallium nitride material, or diamond.

[0074] The semiconductor device made of such a wide bandgap semiconductor has high withstand voltage performance and high allowable current density, and therefore, the size can be reduced. Furthermore, by using this downsized semiconductor device, the size of a semiconductor module including this semiconductor device can also be reduced. Furthermore, since the thermal resistance of the semiconductor device is high, the size of a cooling fin of a heat sink can be reduced, and a water cooling section can be replaced with an air cooling section, thus further reducing the size of the semiconductor module. Furthermore, since the semiconductor device has low power loss and high efficiency, the performance of the semiconductor module can be improved.

Claims

[1] A semiconductor device comprising: an n-drift layer (1); a p-base layer (2) in a channel region on the n-drift layer (1); an n-emitter layer (3) on the p-base layer (2); a gate trench electrode (5) which penetrates the p-base layer (2) and the n-emitter layer (3) and is in contact with the p-base layer (2) and the n-emitter layer (3) through a gate insulating film (6); a p-anode layer (7) in a region other than the channel region on the n-drift layer (1), wherein an impurity concentration of the p-anode layer (7) is lower than the impurity concentration of the p-base layer (2); an emitter electrode (9) connected to the n-emitter layer (3) and the p-anode layer (7); a p-collector layer (11) under the n-drift layer (1); an n-cathode layer (12) under the n-drift layer (1); a collector electrode (13) connected to the p-collector layer (11) and the n-cathode layer (12); an n-buffer layer (14) surrounding the p-collector layer (11); and a p-separation layer (15) surrounding the n-cathode layer (12), wherein the n-buffer layer (14) comprises a high-resistance n-buffer layer boundary portion (16) separating the p-collector layer (11) and the p-separation layer (15), and the p-separation layer (15) has a high-resistance p-separation layer boundary portion (17) separating the n-cathode layer (12) and the n-buffer layer (14), wherein a total impurity concentration and an impurity concentration at surfaces of the n-buffer layer boundary portion (16) and the p-isolation layer boundary portion (17) are reduced, a diffusion resistance and a contact resistance of the n-buffer layer boundary portion (16) and the p-isolation layer boundary portion (17) are increased, and a lateral width of the n-buffer layer boundary portion (16) and the p-isolation layer boundary portion (17) is narrow; the p-base layer (2) and the n-emitter layer (3) are arranged in a region separate from the p-anode layer (7) and the n-emitter layer (3) is not arranged above the n-cathode layer (12). [2] A semiconductor device according to claim 1, wherein, in a region between the p-collector layer (11) and the n-cathode layer (12), the impurity concentration at surfaces of the n-buffer layer (14) and the p-separation layer (15) in contact with the collector electrode (13) is lower than a peak concentration in the n-buffer layer (14) and the p-separation layer (15). [3] A semiconductor device according to claim 1 or 2, wherein a distance between the p-collector layer (11) and the n-cathode layer (12) is 2 µm or less. [4] A semiconductor device according to any one of claims 1 to 3, wherein a width of the p-collector layer (11) is larger than a width of the n-cathode layer (12). [5] A semiconductor device according to any one of claims 1 to 4, further comprising a floating region (18) provided between the channel region and the p-anode layer (7) on the n-drift layer (1) and not connected to the emitter electrode (9); and a dummy gate trench electrode (19) or the gate trench electrode (5) which separates the floating region (18) from the channel region and the p-anode layer (7), wherein the dummy gate trench electrode (19) is connected to the emitter electrode (9). [6] A semiconductor device according to claim 5, further comprising an n-type carrier storage layer (8) under the p-type anode layer (7). [7] A semiconductor device according to any one of claims 1 to 3, further comprising a floating region (18) provided between the channel region and the p-anode layer (7) on the n-drift layer (1) and not connected to the emitter electrode (9); and a dummy gate trench electrode (19) or the gate trench electrode (5) which separates the floating region (18) from the channel region and the p-anode layer (7), wherein the dummy gate trench electrode (19) is connected to the emitter electrode (9) and wherein the p-anode layer (7) extends to a bottom portion of the dummy gate trench electrode (19). [8] A semiconductor device according to any one of claims 1 to 7, further comprising an emitter junction resistor (31, 37) connected between the emitter electrode (9) and the n-type emitter layer (3). [9] A semiconductor device according to claim 8, further comprising a first contact hole (32) connecting the n-type emitter layer (3) to the emitter electrode (9), and a second contact hole (33) connecting the p-type base layer (2) to the emitter electrode (9), wherein the first contact hole (32) and the second contact hole (33) are separated from each other. [10] A semiconductor device according to claim 8, wherein a surface concentration of the n-emitter layer (3) is lower than a peak concentration of the n-emitter layer (3). [11] A semiconductor device according to any one of claims 1 to 10, wherein at least a part of the n-cathode layer (12) is disposed directly under the p-anode layer (7). [12] A semiconductor device according to any one of claims 1 to 11, comprising a plurality of channel regions, wherein the p-anode layer (7) is provided for a plurality of the plurality of channel regions. [13] A semiconductor device according to any one of claims 1 to 12, further comprising a p-well layer (34) in a terminal region and connected to the emitter electrode (9), wherein the n-cathode layer (12) is not provided directly under the p-well layer (34). [14] A semiconductor device according to any one of claims 1 to 12, further comprising a p-well layer (34) in a terminal region and connected to the emitter electrode (9), and an embedded oxide film (29, 39) provided between the n-drift layer (1) and the collector electrode (13) directly under the p-well layer (34). [15] A semiconductor device according to claim 13 or 14, further comprising an emitter junction resistor (31, 37) connected between the emitter electrode (9) and the p-well layer (34).

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