PRIORITY-BASED CONTEXT PREP EFFECT

Abstract

Methods and devices can prioritize the processing of high-priority and low-priority contexts transmitted to a processing unit via separate ports. According to one embodiment, transmitting a context to the low-priority port causes it to be prioritized over contexts already being processed, whereas transmitting a context to the high-priority port causes contexts already being processed to be interrupted.

Description

BACKGROUND OF THE INVENTION

[0001] A computer hardware architecture generally processes a workload in a specific, predefined sequence. However, preemptions may exist within this sequence. Such preemptions can result in significant latency, slowing down the system. This latency effect can be particularly noticeable in processor-intensive activities such as graphics processing, especially three-dimensional (3D) rendering.

[0002] US 5,592,678 A discloses a multitasking data processing apparatus comprising means for executing processes and a display adapter for executing functions supporting a display, the display adapter comprising a first port means for receiving requests to execute selected functions with a first execution priority from the means for executing processes, a second port means for simultaneously receiving requests to execute selected functions with a second execution priority lower than the first execution priority from the means for executing processes, and means connected to the first and second port means for executing selected functions according to the execution priority.Furthermore, in a multitasking data processing device comprising means for executing processes and a display adapter for executing functions that support a display, a method for executing processes comprises the steps of receiving requests to execute selected functions from the means for executing processes in a first port means, the requests having a first execution priority, concurrently receiving requests to execute selected functions from the means for executing processes in a second port means, the requests having a second execution priority lower than the first execution priority, and executing the selected functions according to the execution priority.

[0003] US 2013 / 0173861 A1 discloses parallel computing environments in which threads executing in adjacent processors can access the same data set. These can be designed and configured to share one or more cache memory levels. Before a processor forwards a data request to a higher cache memory level following a cache miss, the processor can determine whether a neighboring processor has stored the data in a local cache memory. If so, the processor can forward the request to the neighboring processor to retrieve the data. Because access to the cache memories is shared between the two processors, the effective memory size is increased. This can advantageously reduce cache misses for each level of shared cache memory without increasing the individual size of the caches on the processor chip.

[0004] US 2011 / 0131374 A1 discloses: Described embodiments enable the transfer of data from one location to another location in a memory of a media controller. A transmit data path and a receive data path of the media controller are linked with generic direct memory access (GDMA). The transmit data path includes a transmit buffer (TX), and the receive data path includes a receive buffer (RX). The GDMA is programmed with a total transmission count and a transmission mode. The GDMA processes the moving data based on the total transmission count and the transmission mode by converting one or more pieces of the moving data in the TX buffer into a predefined frame structure defined with status entries, translating the frames of the moving data between the TX data path and the RX data path, and synchronizing the moving data between the TX buffer and the RX buffer with the status entries.

[0005] At a sufficiently high level of a computer system, an application can submit a workload to a driver, which in turn can submit a corresponding context (also called a "task") to hardware. On a given computer system, there may be multiple contexts in progress—the workload—that use the computer hardware. The operating system can manage these multiple contexts by allocating a hardware time slot to each context, leveraging the time-sharing capabilities of the computer and its operating system. The speed with which these contexts are handled defines, at least in part, the efficiency of the computer system.

[0006] One approach to increasing efficiency has been to allow certain contexts to be prioritized over lower-priority contexts. This can occur during the execution of low-priority context workloads, such as when the operating system (OS) detects the movement of a mouse or other pointing device, which creates graphical user interface (GUI) contexts, which are generally given higher priority for processing at the microprocessor level than other contexts. GUI workloads can be given higher priority because they directly and immediately impact the end-user experience.

[0007] Although computers can be used to handle many different types of contexts, among the most computationally demanding are those that involve rendering 3D graphics. Modern games and other video-intensive programs can place a high value on graphics, and end users can easily judge the quality of those graphics themselves. A system that can render images efficiently and quickly may be more desirable than one that is slow and inefficient. SUMMARY OF THE INVENTION

[0008] The invention is intended to improve the efficiency and speed of context processing in a computer system. The invention is defined by the subject matter of the independent patent claims. Advantageous embodiments of the invention are the subject matter of the dependent patent claims and are explained below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The various advantages of the embodiments will become apparent to those skilled in the art from studying the following description and the appended claims as well as from the following drawings, in which: Fig. 1 is a block diagram of an example graphics processing architecture according to an embodiment; Fig. 2 is a block diagram of an example pipeline according to an embodiment; Fig. 3 is a block diagram of an example of prioritized context flow according to one embodiment; Fig. 4 is a flowchart of an example method for handling high priority and low priority context transfers according to one embodiment; Fig. 5 is a flowchart of another example of a method for handling high priority and low priority context transfers according to one embodiment; Fig. 6 is a block diagram of an example logic architecture according to an embodiment; Fig. 7 is a block diagram of a system according to one embodiment; and Fig. 8 is a block diagram of an example small form factor system according to one embodiment. DESCRIPTION OF EMBODIMENTS

[0010] The embodiments described herein include a high-priority port, which may be implemented in hardware as a hardware front-end command streamer. These embodiments allow high-priority contexts to temporarily interrupt lower-priority contexts rather than being preempted over them, as explained in more detail below. Embodiments may include dedicated on-chip memory built into the graphics chip of the 3D pipeline to save and restore the state and workload of an interrupted low-priority context. Embodiments may also include a low-priority port for handling low-priority contexts that may nevertheless take precedence over some ongoing workflow.

[0011] Embodiments presented here can consider three levels of workflow contexts, which are listed here in order of priority from lowest to highest: a. Basic workflow (also referred to here as low priority context workload, or LPCW (Low Priority Context Workload)); b. Low-priority contexts that take precedence over the base workflow; and c. High-priority contexts that take precedence over a. and b.

[0012] Fig. 1 shows a block diagram of an example graphics processing unit (GPU) 101 that may be used in example embodiments. The illustrated GPU 101 includes a command streamer 111 ("CS", also referred to in the literature as the hardware front end). Data from the command streamer 111 may be fed to a media pipeline 113. The command streamer 111 may also be connected to a 3D fixed function pipeline 115. The illustrated command streamer 111 manages the use of the 3D and media pipelines 115, 113 by switching between the pipelines and forwarding command streams to the active pipeline. The 3D pipeline 115 may provide specialized primitive processing functions, while the media pipeline 113 may provide more general functionality.For 3D rendering, the 3D pipeline 115 is fed by vertex buffers 117, while the media pipeline 113 can be fed by a separate set of memory objects 119. Intermediate results from the 3D and media pipelines 115, 113, as well as commands from the command generator 111, are fed to a graphics subsystem 121, which is directly connected to the pipelines and to the command generator 111.

[0013] The illustrated graphics subsystem 121 includes a unified return buffer (URB) 123 connected to an array of graphics processing cores 125. The unified return buffer 123 may contain memory shared by different functions to enable threads of execution to return data that is later received by other functions or threads. The array of cores 125 processes the values ​​from the 3D and media pipelines 115, 113 to ultimately generate target surfaces 127. The array of cores may have access to sampler functions 129, mathematical functions 131, inter-thread communications 133, color calculators (CC) 135, and a render cache 137 for temporarily storing fully rendered surfaces.A set of source surfaces 139 can be applied to the graphics subsystem 121, and after all of these functions 129, 131, 135, 137, 139 have been applied by the array of cores, a set of target surfaces can be created. For general computation purposes, the illustrated command generator 111 is used to perform operations depending on the specific implementation by the array of cores 125.

[0014] 3D rendering processes often involve particularly intensive cycle time utilization, placing significant demands on developers, who must strive to optimize both speed and throughput efficiency. Although the embodiments presented here are specific to the requirements of 3D contexts, the embodiments have broad applicability to other workload situations where speed and throughput must be optimized.

[0015] Fig. Figure 2 shows a more detailed view of the 3D pipeline 115. It can be seen that the pipeline 115 includes a number of stages for handling basic primitive image processing functions for processing 3D images. The illustrated pipeline 115 includes a graphics hardware front-end (HWFE) 115a, an input assembler 115b, pre-rasterization shaders 115c, a rasterizer 115d, a pixel shader 115e, and an output merger 115f. Other hardware implementations may include additional or fewer stages. Each of these stages may be coupled to a dedicated on-chip memory 116 for storing state and work items of temporarily suspended low-priority context. Such easy access to these objects in memory can reduce latency, as explained in more detail below.

[0016] The block diagram in Fig. 3 shows an example of a context flow according to one embodiment. In this example, an operating system (OS) 306 executes various applications, as shown in the Fig. 3: a mapping application 302, a browser 304, and a graphical user interface (GUI) 308. The OS 306 may include a kernel mode driver (KMD) 310, which supports, among other things, a low priority queue 311 and a high priority queue 312. The latter may receive contexts from a touch device 314 (e.g., a mouse or trackpad) via a graphics microcontroller 316. Other hardware may also be used and other software may be executed; the objects depicted here are examples of commonly used hardware and software, which typically create a number of contexts with different priorities.

[0017] In Fig. 3, the low priority queue 311 contains those contexts which, although designated as "low priority," may nevertheless take precedence over other, less time-sensitive contexts that make up the bulk of the overall low priority context workload. In other words, although the queue 311 is referred to in this application as a "low priority queue," its contexts may nevertheless be of higher priority than other contexts to which it may be preceded. Contexts that have an even higher priority than those in the low priority queue 311 may be directed to the high priority queue 312. The high priority queue 312 may receive contexts from various sources, although these may be Fig. 3 as touch commands generated at the touch device 314 via the graphics microcontroller 316. Both the low priority queue 311 and the high priority queue 312 can be implemented either in software or in hardware.

[0018] The contexts in the illustrated queues 311 and 312 are assigned to one of two ports by a software scheduler 318, which may handle hundreds, thousands, or more contexts at any given time. The first of these ports is the low-priority context delivery port 320, which receives low-priority contexts from the low-priority queue 311. A high-priority context delivery port 322 receives high-priority contexts from the high-priority queue 312. In one embodiment, these two ports 320, 322 are both implemented in hardware. Delivery to these ports may then be forwarded to a hardware scheduler 328.

[0019] The illustrated hardware scheduler 328 arbitrates between low-priority contexts that have been delivered to the low-priority context delivery port 320, high-priority contexts that have been delivered to the high-priority context delivery port 322, and those low-priority contexts that may be temporarily interrupted, as explained in more detail below. The hardware scheduler 328 can determine which of these should be made the active context 330 and forwarded for execution on the pipeline 332. In making this determination, its selection priority is to first select a high-priority context, then any low-priority context that has been interrupted, and then other low-priority contexts. The illustrated hardware scheduler 328 forwards the state and workload details, such as memory areas, memory objects 119, and vertex buffers 117 ( Fig. 1), which are used to process the active context 330 passing through the pipeline when the context workload is forwarded to pipeline 332 for processing. The pipeline 332 may include 3D and / or media pipelines, such as the 3D and media pipelines 115, 113 ( Fig. 1), as previously discussed with reference to an embodiment of the invention. The hardware scheduler 328 may also be responsible for temporarily interrupting the active context 330 when a higher priority context is waiting to be processed, which in turn halts the pipeline 332. Such an interrupt may occur when a high priority context has been sent to the high priority context delivery port 322. This causes any low priority context being processed to be halted at an appropriate logical boundary, and its state and outstanding workload and work items are copied to memory.

[0020] When a relatively low-priority context is interrupted, its state is saved. In this example, "state" can refer to the hardware configuration, including that of each stage of the pipeline required to process a particular workload / context, and can further include additional software instructions. (For example, whether the context consists of triangles or rectangles, as well as the primitive hardware operations that need to be performed on them.) Any partially processed context, i.e., outstanding, unfinished work, can also be saved. In the present example, storage for the state and partially processed work for interrupted low-priority contexts is provided as dedicated on-chip memory 333.Providing this mechanism locally on the same chip as the GPU or CPU can provide significantly faster access times (by several orders of magnitude) compared to using main memory, resulting in faster subsequent processing of low-priority contexts that have been interrupted.

[0021] In response to an interruption of a low-priority context due to the arrival of a high-priority context, the illustrated pipeline 332 signals the hardware scheduler 328 that the pipeline has interrupted a low-priority context and is in a state where it can accept a high-priority context. The illustrated hardware scheduler 328 moves the interrupted low-priority context from an active context state 330 to an interrupted low-priority (LP) context state 334, and processing of the high-priority context can begin. The hardware can also store that the low-priority context has been interrupted and that it can be resubmitted for execution later, after the execution of the joined high-priority context completes and before any other low-priority context begins.

[0022] In the case of preemption by a low-priority context where no high-priority context is involved, as soon as a low-priority context is preempted by another low-priority context, the software scheduler 318 is updated and aware that the low-priority context has been preempted and removed from the pipeline. Furthermore, some information concerning the state of the preempted low-priority context may be saved in memory, such as software instructions, for use when processing of the preempted low-priority context continues in the pipeline. This memory may be main memory, bulk memory, or double data rate (DDR) memory, such as may be allocated for storing graphics contexts.The software scheduler 318 may store the identifier of the low priority context that has been preceded by another so that it can be retransmitted or discarded at a later time.

[0023] It will now Fig. 4, which shows a flowchart of an example of a method 400 for providing preemption of high-priority contexts over low-priority contexts. The method 400 may be implemented in executable software as a set of logic instructions stored on a machine- or computer-readable storage medium of memory, such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic, such as programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed functionality logic hardware using circuit technology such as application specific integrated circuits (ASICs), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof.

[0024] Referring first to the left half of the flowchart, we first consider the case where no high-priority contexts need to be processed. In the simplest case, a computer may be in the middle of processing a 3D rendering workflow. This may mean, for example, that an image is to be generated from thousands of triangular elements, which a 3D image pipeline with the Fig. 2, filling the pipeline with this context. This context can be ordinary low-priority context workload. Execution begins in block 404 shown, since in this simple case there can be no low-priority context states to be restored from memory in block 403. If no preemptions or interrupts are to be considered in block 406, execution can be completed in block 408. In the spirit of good management and design, the completed, now-executing context can be saved in block 410 for further use at another location in memory. This memory can be main memory or DDR memory on the GPU, or any other memory suitable for storing a completed context.Additionally, in 410, the software scheduler may be informed that the context has been completed, and the process ends in 412.

[0025] Often, the case may be that, amidst the stream of contexts that make up the overall workflow, there are some that must be given a first degree of priority. Examples of such contexts are diverse. For example, in a media context, an embodiment may involve showing a movie or clip while a general-purpose graphics processing unit (GPGPU) workload may be operating in the background, performing mathematically intensive calculations such as N-body gravity simulations. In this example, media is then given priority over the GPGPU workload. In other embodiments, the opposite may be true.

[0026] Although a given context may be referred to herein as a "low priority context" with respect to high priority contexts, it may nevertheless be of higher priority than other contexts in the workflow. Such relative precedence may not always be due to the automatic priority of one use (e.g., mouse movement) over another (e.g., mathematical calculations). For example, in another embodiment, an algorithm may be implemented in the operating system and executed by the software scheduler 318 ( Fig. 3), which aims to provide all contexts with a balanced share of hardware access, resulting in preemptions that do not necessarily follow the paradigm of giving priority to GPU contexts over other contexts.

[0027] Next, consider the case where a low-priority context that has priority over the general workflow is to be processed. The low-priority context may be submitted to the low-priority context submission port by block 432 at the starting block 434. As noted above, so-designated contexts may have priority over the base workflow, and they may have priority over another, previously submitted low-priority context that is currently being processed. Thus, at block 436, the method may instruct that preference be given to any contexts in the pipeline that are not high-priority contexts, including a previously submitted low-priority context that is currently being processed.Preemption here means pausing the workflow flowing to the 3D pipeline and flushing out the contexts already in the pipeline (i.e. allowing processing to complete at such stations as those defined in . Fig. 2). This process of flushing the pipeline may not be instantaneous—it may require thousands of clock cycles, depending on the depth of the pipeline and the amount of work stored in the internal cache of its stations. For example, in graphics processing that uses triangles as primitives for rendering 3D objects, each station in a pipeline may have a cache containing thousands of triangles. The process of flushing the pipeline may result in the completion of work on these triangles in the pipeline, thus introducing significant latency while waiting for the pipeline to become free in the illustrated block 438.

[0028] Once the pipeline has become free, in block 440, the software scheduler may receive a state update from the hardware scheduler indicating that the new low-priority context has been accepted. In block 442, the low-priority context begins the process of executing in the pipeline in block 402, which marks the end of the commit phase in block 444. Execution begins in block 403 with a retrieval from memory of any available state data previously stored in memory, and in block 404 shown, the hardware may begin executing the workload. While the workload is executing, in block 406, the pipeline monitors the system for any new preemptions or interruptions due to low-priority or high-priority context commits.During execution in block 406, it may occur that another low-priority context arrives via block 451 to be preempted, or that a high-priority context has triggered an interrupt in the context. If no further preemptions or interruptions occur, the context is closed in block 408 and may be saved in memory as before in block 410 for possible future reuse before the method ends in block 412.

[0029] On the other hand, an incoming low-priority context or a high-priority context may be detected in block 406, in which case the low-priority context is not completed in block 408, but is either interrupted or preempted by another one. In block 414, if no interrupt is indicated, another one is preempted by the low-priority context in block 415. A further test for interruption is performed in block 420, and if not, preemption remains in effect. In block 422, the state of the low-priority context is saved to memory, and the hardware scheduler can inform the software scheduler that a low-priority context has been preempted by another one.

[0030] A high-priority context port in block 446 is provided for the transmission of contexts classified as high-priority contexts. In this example, high-priority contexts may be generated by a mouse, trackpad touch, and other GUI commands for which timely execution is particularly important. In other embodiments, other operations may result in other contexts that may be classified as having high priority. In this embodiment, the high-priority context transmission port in block 446 is implemented in hardware, although in other embodiments it may be implemented in software.

[0031] The high-priority contexts are detected by the software scheduler or another part of the operating system. If detected, rather than preempting any low-priority contexts in the pipeline, which would incur the penalty of a relatively high latency for flushing the pipeline, an interrupt is triggered from all contexts in the pipeline at the illustrated block 450, and an indication of this can be sent to block 406 via block 451. Instead of flushing the pipeline, each context in the pipeline is allowed to pause at the next logical point that can be reached, such as upon completion of any in-flight operations or transactions in progress at the station where it is located.For example, if the context consists of graphics processing of thousands of triangles at each station in the pipeline, the processing of each individual triangle in progress at a station may be allowed to complete, but afterward, the pipeline for that context is interrupted, and the state of the context and the pending / intermediate data in the pipeline are copied to memory / on-chip storage. Referring to flowchart 400, context may be saved at various locations in memory, including block 410, block 422, block 426, and block 450. The latency caused by interrupting a pipeline may be significantly smaller than flushing it.

[0032] Once the interrupt is terminated in block 452 or the execution of the previous context has already ended, the software scheduler may be informed in block 454 that a high-priority context has been accepted. Execution of the high-priority context may then begin in block 456. In block 460, any previously stored state information concerning the high-priority context, which may optionally have been stored in memory, may be read to restore this state of the high-priority context, and execution of the high-priority context begins. Execution completes in block 462. In block 464, the state of the completed high-priority context may be saved in memory for future use, and the software scheduler may be informed that the high-priority context has completed.In block 466, processing of any outstanding, interrupted low priority context may continue, or the overall process may end in 468.

[0033] Referring again to the left-hand side of method 400, further aspects of high-priority context processing are now considered. An interrupt indication (the flag of a high-priority context) arrives in block 406, and it is acknowledged in block 414. Next, in block 424, any active low-priority context (which may be any context that is not of high priority) is temporarily interrupted. In block 426, the state of the interrupted low-priority context and any intermediate data already generated by it are saved to memory, such as on-chip memory. The software scheduler is also notified that the low-priority context has been interrupted.Block 426 may receive an indication from block 466 that work on the interrupted low priority context may be resumed, in which case block 430 informs the software scheduler that work on the interrupted context may be resumed, which it does starting with block 402.

[0034] It will now Fig. 5; another example of a method for providing preference for high-priority contexts over low-priority contexts is illustrated by a flowchart 500. First, consider the case where a high-priority context is transmitted to the high-priority port at block 504. If there are no low-priority contexts in processing to consider at block 506, the high-priority context is sent to the pipeline and executed at block 512. Conversely, if a low-priority context is already present in the pipeline, that low-priority context is interrupted at block 508, and its state and unfinished work are saved to memory (which may be dedicated on-chip memory) at block 510. In addition, any completed context processing may be stored in main or DDR graphics memory.

[0035] After completing the high-priority context in block 512, the system is queried in block 514 for any interrupted low-priority contexts. If none exist, the system is further queried in block 518 to determine if any additional low-priority contexts remain to be processed. If none exist, the workflow ends. If there are any additional low-priority contexts to be processed, this occurs in block 520, and then, once this is completed, this workflow ends.

[0036] If it is determined in block 514 that there is still an interrupted low priority context to be processed, its state and any partially completed work are restored from memory in block 516 and processed in the pipeline in block 517, after which control transfers to block 518 and flow continues as above.

[0037] At block 532, a low priority context may be delivered to the low priority port. As can be seen for this case from flowchart 500, at conditional block 534 it is determined whether a high priority context has been delivered to the high priority port. If so, control transfers to block 506 to perform processing as above. If not, at block 536 it is further determined whether any older low priority contexts exist in the pipeline. If none exist, the low priority context is delivered to the pipeline and executed to completion at 538, and the workload is terminated at 540. Conversely, if another low priority context is already in the pipeline, at block 542 the newer low priority context is preempted and executed at block 544.After its completion, the older, lower priority context, which was preferred over the other one, is loaded and executed again in block 546.

[0038] An example of a logic architecture 600 according to one embodiment is shown in Fig. 6. The logic architecture 600 includes a graphics pipeline 602, a low-priority context port 604, and a high-priority context port 606. A high-priority context detection module 614 may detect the transmission of high-priority contexts to the high-priority port 606. If such a context is detected at a time when a low-priority context is the active context in the pipeline 602, the low-priority context interrupt module 616 may interrupt the low-priority context, and its state and any partially completed work may be saved to on-chip memory 620 by the interrupted context save module 618.After the high priority context has been processed, the state and any partially completed work of the interrupted context are restored by the interrupted context recovery module 622 from the on-chip memory 620 in the pipeline, and work on the interrupted low priority context continues.

[0039] It is possible that there are no high-priority contexts to be processed. In this case, the low-priority context detection module 626 detects the transmission of low-priority contexts to the low-priority port 604. If such a context is detected at a time when another low-priority context is the active context in the pipeline 602, the low-priority context preemption module 628 preempts the low-priority context, and certain aspects of its state, as well as any completed work, may be saved by the preempted context save module 630 to memory 632, which may be main memory or DDR memory.After the low priority context has been processed, the state information that may have been saved and the low priority context over which the other was preferred are restored to the pipeline by the preempted context restoration module 622, and work on the low priority context over which the other was preferred continues.

[0040] Fig. 7 shows one embodiment of a system 700. In various embodiments, the system 700 may be a media system, although the system 700 is not limited to this context. For example, the system 700 may be integrated with a personal computer (PC), a notebook computer, an ultra-laptop computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a mobile phone, a combination mobile phone / PDA, a television, a smart device (e.g., a smartphone, smart tablet, or smart TV), a mobile internet device (MID), a messaging device, a data communications device, etc. Thus, the system 700 may be used to render images as described herein.

[0041] In various embodiments, system 700 includes a platform 702 connected to a display 720. Platform 702 may receive video bitstream content from a content device such as content service device(s) 730 or content delivery device(s) 740, or other similar content sources. A navigation controller 750, including one or more navigation features, may be used to interact with, for example, platform 702 and / or display 720. Each of these components is described in more detail below.

[0042] In various embodiments, platform 702 may include any combination of a chipset 705, processor 710, memory 712, storage 714, graphics subsystem 715, applications 716, and / or a radio device 718. Chipset 705 may provide two-way communication between processor 710, memory 712, storage 714, graphics subsystem 715, applications 716, and / or radio device 718. For example, chipset 705 may include a storage adapter (not shown) capable of providing two-way communication with storage 714.

[0043] Processor 710 may be implemented as a complex instruction set computer (CISC) or reduced instruction set computer (RISC) processor, an x86 instruction set compatible processor, a multi-core processor, or any other microprocessor or central processing unit (CPU). In various embodiments, processor 710 may be dual-core processor(s), dual-core mobile processor(s), and so on.

[0044] The memory 712 may be implemented as a volatile memory device, such as, but not limited to, random access memory (RAM), dynamic random access memory (DRAM), or static RAM (SRAM).

[0045] Data storage 714 may be implemented as a non-volatile storage device, such as, but not limited to, a magnetic disk drive, an optical disk drive, a tape drive, an internal storage device, an attached storage device, flash memory, a battery-backed SDRAM (synchronous DRAM), and / or a network-accessible storage device. In various embodiments, data storage 714 may include technology to increase enhanced storage performance protection for valuable digital media, for example, when including multiple hard disk drives.

[0046] The graphics subsystem 715 may perform processing of images, such as still or video images, for display. The graphics subsystem 715 may, for example, be a graphics processing unit (GPU) or a visual processing unit (VPU). The graphics subsystem 715 may therefore include the previously discussed GPU 101 ( Fig. 1). Additionally, processor 710 may be configured to operate as a CPU via instructions received from memory 712, data storage 714, or another suitable source. An analog or digital interface may be used to communicatively couple graphics subsystem 715 and display 720. For example, the interface may be any of a high-definition multimedia interface, DisplayPort, wireless HDMI, and / or wireless HD-compatible technologies. Graphics subsystem 715 may be integrated with processor 710 or chipset 705. Graphics subsystem 715 may be a standalone card communicatively coupled to chipset 705.

[0047] The graphics and / or video processing methods described herein may be implemented in various hardware architectures. For example, graphics and / or video functionality may be integrated into a chipset. Alternatively, a discrete graphics and / or video processor may be used. As yet another embodiment, the graphics and / or video functions may be implemented by a general-purpose processor, including a multi-core processor. In yet another embodiment, the functions may be implemented in a consumer electronics device.

[0048] The radio device 718 may include one or more radio devices capable of transmitting and receiving signals using various suitable wireless communication technologies. Such technologies may include communications over one or more wireless networks. Example wireless networks include (but are not limited to) wireless local area networks (WLANs), wireless personal area networks (WPANs), wireless metropolitan area networks (WMANs), cellular mobile networks, and satellite networks. When communicating over such networks, the radio device 718 may operate in accordance with one or more applicable standards of any version.

[0049] In various embodiments, display 720 may include any monitor or television-type display. For example, display 720 may include a computer display screen, a touchscreen display, a video monitor, a television-like device, and / or a television. Display 720 may be digital and / or analog. In various embodiments, display 720 may be a holographic display. Additionally, display 720 may be a transparent surface capable of receiving a visual projection. Such projections may convey various forms of information, images, and / or objects. For example, such projections may be a visual overlay for a mobile augmented reality (MAR) application.Controlled by one or more software applications 716, the platform 702 may display a user interface 722 on the display 720.

[0050] In various embodiments, content service device(s) 730 may be hosted by any national, international, and / or independent service so that platform 702 may access them, for example, over the Internet. Content service device(s) 730 may be connected to platform 702 and / or display 720. Platform 702 and / or content service device(s) 730 may be connected to a network 760 to transfer media information between them and network 760 (e.g., send to or receive from it). Content delivery device(s) 740 may be connected to platform 702 and / or display 720.

[0051] In various embodiments, content service device(s) 730 may include a cable TV box, a personal computer, a network, a telephone, internet-enabled devices, or a device capable of delivering digital information and / or digital content, and any other similar device capable of unidirectionally or bidirectionally communicating content between content providers and the platform 702 and / or the display 720 via the network 760 or directly. It is understood that content may be communicated unidirectionally and / or bidirectionally to and from any of the components in the system 700 and a content provider via the network 760. Examples of content may include any media information, such as video, music, medical or gaming information, and so on.

[0052] The content service device(s) 730 receive(s) content, such as cable television programs, that include media information, digital information, and / or other content. Examples of content providers may include any provider of television, radio, or internet content via cable or satellite. These examples are not intended to limit the embodiments.

[0053] In various embodiments, platform 702 may receive control signals from a navigation controller 750 having one or more navigation features. The navigation features of controller 750 may be used, for example, to interact with user interface 722. In various embodiments, navigation controller 750 may be a pointing device, which may be a computer hardware component (particularly, a user interface device) that allows a user to input spatial (e.g., continuous or multidimensional) data into a computer. Many systems, such as graphical user interfaces (GUIs), televisions, and monitors, allow the user to control and input data into the computer or television using physical gestures.

[0054] Movements of the navigation features of controller 750 may be reproduced on a display (e.g., display 720) by movements of a pointer, cursor, focus ring, or other visual indicators displayed on the display. For example, under the control of software applications 716, the navigation features located on navigation controller 750 may be mapped to virtual navigation features displayed, for example, on user interface 722. In various embodiments, controller 750 may not be a separate component, but rather is integrated into platform 702 and / or display 720. However, embodiments are not limited to the elements or context illustrated or described herein.

[0055] In various embodiments, drivers (not shown) may include technology that allows users, for example, to instantly turn platform 702 on and off like a television with the touch of a button after initial boot, if enabled. Program logic may enable platform 702 to stream content to media adapters or other content service device(s) 730 or content delivery device(s) 740 when the platform is turned off. Additionally, chipset 705 may include, for example, hardware and / or software support for 5.1 surround sound audio and / or high-resolution 7.1 surround sound audio (multi-channel audio). The drivers may include a graphics driver for integrated graphics platforms. In various embodiments, the graphics driver may include a PCI (Peripheral Component Interconnect) Express graphics card.

[0056] In various embodiments, one or more of the components illustrated in system 700 may be integrated. For example, platform 702 and content service device(s) 730 may be integrated, or platform 702 and content delivery device(s) 740 may be integrated, or platform 702, content service device(s) 730, and content delivery device(s) 740 may be integrated, for example. In various embodiments, platform 702 and display 720 may be an integrated unit. For example, display 720 and content service device(s) 730 may be integrated, or display 720 and content delivery device(s) 740 may be integrated. These examples are not intended to limit the embodiments.

[0057] In various embodiments, system 700 may be implemented as a wireless system, a wired system, or a combination of both. When implemented as a wireless system, system 700 may include components and interfaces suitable for communication over wireless shared media, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic, and so on. An example of wireless shared media may include portions of a wireless spectrum, such as an RF spectrum, and so on.When implemented as a wired system, the system 700 may include components and interfaces suitable for communication over wired communication media, such as input / output (I / O) adapters, physical connectors for connecting the I / O adapter to a corresponding wired communication medium, a network interface card (NIC), a disk storage controller, a video controller, an audio controller, and so on. Examples of wired communication media may include a wire, a cable, metal lines, a printed circuit board (PCB), a backplane, a switch fabric, a semiconductor material, a twisted-pair cable, a coaxial cable, fiber optic cables, and so on.

[0058] Platform 702 may establish one or more logical or physical channels for transmitting information. The information may include media information and control information. Media information may refer to any data representing content intended for a user. Examples of content may include, for example, data from a conversation, a video conference, video streaming, an electronic message ("email"), a voice message ("voicemail"), alphanumeric symbols, graphics, images, video, text, and so on. Data from a conversation may include, for example, voice information, quiet periods, background noise, comfort noise, tones, and so on. Control information may refer to any data representing commands, instructions, or control words intended for an automated system.For example, control information may be used to route media information through a system or to instruct a node to process the media information in a predetermined manner. However, embodiments are not limited to the elements or context described in [the context]. Fig. 7 are shown or described.

[0059] As described above, the system 700 may be implemented in various physical styles or form factors. Fig. Figure 8 illustrates embodiments of a small form factor device 800 in which system 700 may be implemented. In various embodiments, device 800 may be implemented, for example, as a mobile computing device with wireless capabilities. A mobile computing device may be any device with a processing system and a mobile power source or supply, such as one or more batteries.

[0060] As described above, examples of a mobile computing device may include a personal computer (PC), a notebook computer, an ultra-laptop computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a mobile phone, a combination mobile phone / PDA, a television, a smart device (e.g., smartphone, smart tablet, or smart TV), a mobile internet device (MID), a messaging device, a data communication device, and so on.

[0061] Examples of a mobile computing device may also include computers configured to be worn by a person, such as a wrist computer, a finger computer, a ring computer, an eyeglass computer, a belt clip computer, a wristband computer, a shoe computer, a clothing computer, and other wearable computers. In various embodiments, a mobile computing device may be implemented, for example, as a smartphone capable of executing computer applications as well as voice communications and / or data communications. Although some embodiments may be described, by way of example, with reference to a mobile computing device implemented as a smartphone, it should be understood that other embodiments may be implemented using other wireless mobile computing devices.The embodiments are not limited in this regard.

[0062] As in Fig.8, device 800 may include a housing 802, a display 804, an input / output (I / O) device 806, and an antenna 808. Device 800 may also include navigation features 812. Display 804 may include any suitable display device for displaying information suitable for a mobile computing device. I / O device 806 may include any suitable I / O device for inputting information to a mobile computing device. Examples of I / O device 806 may include an alphanumeric keyboard, a numeric keypad, a touchpad, input keys, buttons, switches, toggle switches, microphones, speakers, voice recognition devices, and software, among others. Information may also be input to device 800 through a microphone. Such information may be digitized by a voice recognition device.The embodiments are not limited in this regard.

[0063] Example 1 may include a system comprising a processor, a pipeline, a first port for receiving contexts having a first priority, a second port for receiving a context having a second priority higher than the first priority, a second priority context detection module for detecting receipt of the second priority context at the second port, and an interrupt module for interrupting a context in the pipeline after the second priority context detection module detects receipt of the second priority context at the second port.

[0064] Example 2 may include the system of Example 1, further comprising on-chip memory for storing a state of at least one of the contexts, wherein the on-chip memory and the processor are on a common chip.

[0065] Example 3 may include the system of Example 2, further comprising a recovery module to recover a broken context after the second priority context is completed.

[0066] Example 4 may include the system of Example 3, wherein at least one of the modules is implemented in software.

[0067] Example 5 may include the system of Example 1, wherein the interrupt module is implemented in hardware.

[0068] Example 6 may include the system of Example 1 or 2, further comprising a preemption module to, after a context has been delivered to the first port, preempt that context over a context in the pipeline.

[0069] Example 7 may include the system of any of the preceding examples, further comprising a preemption recovery module operable to recover a context that has been preempted over another.

[0070] Example 8 may include the system of any of Examples 1, 2, 4, or 5, further comprising an interrupt recovery module that may restore a context that has been temporarily interrupted.

[0071] Example 9 may include the system of any of the preceding examples, further comprising a three-dimensional (3D) graphics processor.

[0072] Example 10 may include a method comprising transmitting a first context to a first port designated for contexts having a first priority, transmitting the first context to a pipeline, transmitting a second context to a second port designated for contexts having a second priority, and interrupting the first context before its processing in the pipeline is complete.

[0073] Example 11 may include the method of Example 10, further comprising detecting transmission of the context to the second port.

[0074] Example 12 may include the method of Example 10, further comprising copying state and unfinished work of the first context to on-chip memory and thereafter communicating the second context to the pipeline.

[0075] Example 13 may include the method of Example 12, further comprising continuing to process the first context after processing the second context is complete.

[0076] Example 14 may include the method of any of Examples 10-13, further comprising, after a context has been communicated to the first port, preferring the context over a context in the pipeline.

[0077] Example 15 may include at least one computer-readable storage medium comprising a set of instructions that, when executed by a computing device, cause the computing device to transmit a first context to a first port designated for contexts having a first priority, transmit the first context to a pipeline, transmit a second context to a second port designated for contexts having a second priority, and interrupt the first context before its processing in the pipeline is complete.

[0078] Example 16 may include the at least one computer-readable storage medium of Example 15, wherein the instructions, when executed, cause the computing device to detect the transmission of a context to the second port.

[0079] Example 17 may include the at least one computer-readable storage medium of Example 15, wherein the instructions, when executed, cause a computing device to copy the state and unfinished work of the first context to on-chip memory and thereafter communicate the second context to the pipeline.

[0080] Example 18 may include the at least one computer-readable storage medium of any of Examples 15-17, wherein the instructions, when executed, cause a computing device to continue processing the first context after processing the second context is complete.

[0081] Example 19 may include the at least one computer-readable storage medium of any of Examples 15-17, wherein the instructions, when executed, cause a computing device, after a context has been communicated to the first port, to prefer that context to a context in the pipeline.

[0082] Example 20 may include an apparatus comprising a first port for receiving contexts of a first priority, a second port for receiving contexts of a second priority, a pipeline for processing contexts, a context detection module for detecting delivery of contexts to the ports, a scheduler module for sending contexts to the pipeline, and an interrupt module for interrupting pipeline processing of contexts received at the first port in favor of contexts received at the second port.

[0083] Example 21 may include the apparatus of Example 20, further comprising an on-chip memory for storing the state of at least one of the contexts.

[0084] Example 22 may include the apparatus of Example 20, further comprising a recovery module to restore a context in the pipeline.

[0085] Example 23 may include the apparatus of any of Examples 20 or 21, further comprising memory for storing state information related to contexts.

[0086] Example 24 may include the apparatus of Example 20, further comprising a graphics processing unit.

[0087] Example 25 may include the apparatus of any of Examples 20-22, further comprising a suspended context recovery module to resume processing of a suspended context after completing processing of a context communicated to the second port.

[0088] Example 26 may include an apparatus comprising a pipeline, a first port for transmitting contexts of a first priority, a second port for transmitting contexts of a second priority, means for detecting transmission of a context to the second port, and means for interrupting a context in the pipeline after detecting transmission of a context to the second port.

[0089] Example 27 may include the apparatus of Example 26, wherein the means for interrupting the context is implemented in software.

[0090] Example 28 may include the apparatus of Example 26, wherein the means for interrupting the context is implemented in hardware.

[0091] Example 29 may include the apparatus of Example 26, further comprising an on-chip memory in which the state of a context is stored at a first priority.

[0092] Example 30 may include the apparatus of examples 26 or 29, further comprising memory in which to store the state of a context having a second priority.

[0093] Example 31 may include the apparatus of Example 26, further comprising memory to store the state of a context communicated to one of the ports and a module to resume processing of an interrupted context.

[0094] Example 32 may include the apparatus of any of Examples 26-29, further comprising means for, after a context has been communicated to the first port, preferring the context to a context in the pipeline.

[0095] Example 33 may include the apparatus of Example 32, further comprising means for restoring a context over which another has been preferred.

[0096] Example 34 may include the apparatus of Example 26, further comprising means for restoring a context that has been interrupted.

[0097] Example 35 may include the apparatus of Example 26, further comprising a plurality of pipelines.

[0098] Example 36 may include a method for prioritizing tasks to be processed by a processor, comprising: providing first and second ports corresponding to tasks of a lower and higher degree of processing priority, respectively; forwarding lower priority tasks submitted to the first port to a pipeline; preempting any lower priority task currently executing in the pipeline by flushing the pipeline of any such lower priority tasks that may be in it when a task is submitted to the first port and submitting a task in its place that was submitted to the first port; and interrupting any lower priority tasks that may be in the pipeline when a task is submitted to the second port and submitting a task submitted to the second port in its place.

[0099] Example 37 may include the method of Example 36, wherein the task transmitted to the second port comprises graphics.

[0100] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so on), integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, chipsets, and so on.Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (APIs), instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and / or software elements may vary according to any number of factors, such as desired computational speed, power levels, thermal tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds, and other design and performance constraints.

[0101] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing various logic within the processor, which, when read by a machine, cause the machine to create logic to perform the techniques described herein. Such representations, called "IP cores," may be stored on a tangible, machine-readable medium and delivered to various customers or manufacturing facilities for loading into the manufacturing machines that actually manufacture the logic or processor.

[0102] Embodiments are applicable for use with all types of semiconductor chips for integrated circuits (ICs). Examples of such IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, and the like. Additionally, in some of the drawings, signal conductor lines are represented by lines. Some of these may be thicker to represent multiple individual signal paths, have a number designation to indicate a count of the individual signal paths, and / or have arrows at one or more ends to indicate the primary direction of information flow. However, this should not be construed as limiting. Rather, such additional details may be used in conjunction with one or more example embodiments to facilitate understanding of a circuit.The illustrated signal lines, whether or not carrying additional information, may actually comprise one or more signals capable of being transmitted in multiple directions and may be implemented using any suitable type of signaling scheme, such as digital or analog lines implemented with differential pairs, fiber optic lines, and / or single-ended lines.

[0103] Examples of sizes / models / values / ranges may have been provided, although the embodiments are not limited to them. As manufacturing techniques (e.g., photolithography) become more sophisticated over time, it is expected that smaller devices could be manufactured. Furthermore, well-known power / ground connections to IC chips and other components may not be shown in the figures for simplicity of illustration and discussion, as well as to avoid obscuring the understanding of certain aspects of the embodiments.Furthermore, arrangements may be illustrated in block diagram form to avoid obscuring the clarity of embodiments, and also in view of the fact that specific features relating to the implementation of such arrangements of block diagrams will be highly dependent on the platform in which the embodiment is to be implemented, i.e., such specific features should be within the knowledge of a person skilled in the art. Where specific details (e.g., circuits) are set forth to describe example embodiments, it should be apparent to those skilled in the art that embodiments may be practiced without, or with modifications to, these specific details. Therefore, the description is to be considered illustrative and not restrictive.

[0104] For example, some embodiments may be implemented using a machine-readable or tangible computer-readable medium or product that can store an instruction or set of instructions that, when executed by a machine, can cause the machine to perform a method and / or operations according to the embodiments. Such a machine may, for example, include any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and / or software.The machine-readable medium or product may, for example, be any suitable type of memory unit, memory device, memory product, memory medium, data storage device, data storage product, data storage medium and / or data storage unit, for example memory, removable or non-removable media, erasable or non-erasable media, writable or rewritable media, digital or analog media, hard disks, floppy disks, CD-ROMs (Compact Disk Read-Only Memories), CD-Rs (Compact Disks Recordable), CD-RWs (Compact Disks Rewritable), optical disks, magnetic media, magneto-optical media, removable memory cards or disks, various types of DVDs (Digital Versatile Disks), tapes, cassettes or the like.The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language.

[0105] Unless expressly stated otherwise, it is understood that terms such as "processing," "computing," "calculating," "determining," or the like refer to the action and / or processes of a computer or computing system, or similar electronic data processing device, that manipulates data represented as physical quantities (e.g., electronic) within the registers and / or memories of the computing system and / or converts it into other data similarly represented as physical quantities within the memories, registers, or other such information storage, transmission, or display devices of the computing system. The embodiments are not limited in this context.

[0106] The term "coupled" or "connected" may be used herein to denote any type of direct or indirect relationship between the components in question, and may refer to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Furthermore, the terms "first," "second," etc., are used herein only for convenience and have no particular temporal or chronological significance unless otherwise noted.

Claims

[1] System (101), which includes: a processor (125); a pipeline (115, 332, 602); a first port (320, 604) for receiving a low priority context; a second port (322, 606) for receiving a context with a high priority; a high priority context detection module (614, 626) for detecting receipt of the high priority context at the second port (322, 606); and an interrupt module (616) for interrupting a low priority context in the pipeline (115, 332, 602) after the high priority context detection module (614, 626) detects receipt of the high priority context at the second port (322, 606); an on-chip memory (116, 333, 620) for storing a state of the low-priority context, wherein the on-chip memory (116, 333, 620) and the processor (125) are located on a common chip; and a recovery module (622) for recovering an interrupted low priority context after the high priority context is completed. [2] The system (101) of claim 1, wherein at least one of the modules is implemented in software. [3] The system (101) of claim 1 or 2, wherein the interrupt module (616) is implemented in hardware. [4] The system (101) of any one of claims 1 to 3, further comprising a preemption module (628) for, after the low priority context has been transmitted to the first port (320, 604), preempting it over a context in the pipeline (115, 332, 602). [5] The system (101) of claim 4, further comprising a preemption recovery module (634) for restoring the context that has been preempted by another. [6] The system (101) of any one of claims 1 to 5, wherein the processor is a 3D graphics processor. [7] Procedure which includes: transmitting a low priority context to a first port (320, 604) designated for low priority contexts; transmitting the context with a low priority to a pipeline (115, 332, 602); transmitting a high priority context to a second port (322, 606) designated for high priority contexts; and interrupting the context with a low priority before its processing in the pipeline (115, 332, 602) is completed; Copying a state and unfinished work of the low priority context into an on-chip memory (116, 333, 620) and then transmitting the high priority context to the pipeline (115, 332, 602); and Continue processing the low-priority context after processing the second context is complete. [8] The method of claim 7, further comprising detecting transmission of the context with a high priority to the second port (322, 606). [9] The method of claim 7 or 8, further comprising, after a low priority context has been transmitted to the first port (320, 604), preferring it to a context in the pipeline (115, 332, 602). [10] At least one computer-readable storage medium comprising a set of instructions that, when executed by a data processing device, cause the data processing device to: transmits a low priority context to a first port (320, 604) designated for low priority contexts; transmits the context to a pipeline (115, 332, 602) with a low priority; transmits a high priority context to a second port (322, 606) designated for high priority contexts; interrupts the context with a low priority before its processing in the pipeline (115, 332, 602) is completed; copies a state and unfinished work of the context with a low priority into an on-chip memory (116, 333, 620) and then transmits the context with a high priority to the pipeline (115, 332, 602); and continues processing the low-priority context after processing the high-priority context has been completed. [11] At least one computer-readable storage medium according to claim 10, wherein the instructions, when executed, cause a data processing device to recognize the transmission of the context with a high priority to the second port (322, 606). [12] At least one computer-readable storage medium according to claim 10 or 11, wherein the instructions, when executed, cause a data processing device, after a low priority context has been communicated to the first port (320, 604), to prefer that context to a context in the pipeline (115, 332, 602). [13] Device comprising: a first port (320, 604) for receiving low priority contexts; a second port (322, 606) for receiving high priority contexts; a pipeline (115, 332, 602) for processing low priority and high priority contexts; a context detection module (614, 626) for detecting the transmission of contexts to the ports; a scheduler module (328) for sending contexts to the pipeline (115, 332, 602); and an interrupt module (616) for interrupting the pipeline processing of low priority contexts received at the first port (320, 604) in favor of high priority contexts received at the second port (322, 606); an on-chip memory for storing a state of at least one of the low priority contexts; and a suspended context recovery module (622) for resuming processing of a suspended context having a low priority after completing processing of a high priority context transmitted to the second port (322, 606). [14] The apparatus of claim 13, further comprising memory for storing state information relating to contexts. [15] The apparatus of claim 13, further comprising a graphics processing unit.

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