Automatic commutation comparison value determination for BLDC motors using sign determination of the EMF

Abstract

The invention relates to a method and a device for controlling the commutation time for the control of a BLDC motor. In this case, a corrected voltage signal (U korrU ) is generated from the EMF at a motor terminal (U). A fourth integrator (Int 2U ) integrated in a commutation interval in which this motor connection (U) is not supplied with current by the control block (St), this corrected voltage signal (U korrU ) to an integrated sign signal (S 2U ). A first integrator (Int 1U ) integrates the corrected voltage signal (U korrU ) to a threshold signal (S 1U ). A comparator (CMP 2U ) compares the threshold signal (S 1U ) with a default value (V U) and forms a commutation signal (A1). Depending on the commutation signal (A1), the commutation time of an assigned output of a control block (St) connected to the assigned motor terminal (U, V, W) is changed. A second summer (SU 2U ) adds the default value (V U ) with the associated integrated sign signal (S 2U ) to the reload value (S 3U ). The reload values ​​(S 3U ) is stored in a sample and hold circuit (SaH U ) triggered with the edge of the commutation signal (A1) and stored as a default value (V U ) is used for the said comparator. The generation of the new default value (V U ) depends on the current memory value of the sample and hold circuit (SaH U ).

Description

Introduction

[0001] The invention relates to a method for controlling the stator coils of a brushless motor with excitation based on a permanent magnet located in the rotor. Such a motor typically comprises a rotor, which itself contains a permanent magnet with at least two magnetic poles. The even number of magnetic poles should be distributed symmetrically around the motor's axis of rotation, which is only approximately the case in reality. The rotor is rotatably mounted in a magnetic field generated by stator coils outside the rotor. The magnetic field generated by the stator coils also generally exhibits only approximate rotational symmetry around the rotor axis. This magnetic field is generated by the superposition of the fields of the several different stator coils, which are typically grouped symmetrically around the axis of rotation of said rotor, which is also only approximately achieved in reality.When suitably controlled, these stator coils generate a rotating magnetic field with a magnetic field-related rotation axis, which in turn only approximately corresponds to the mechanical rotation axis of the rotor. The rotor then follows this rotating magnetic field with its magnetic poles due to its permanent magnetization. Block commutation can be used to control the stator coils of such electric motors with rotors with a magnetic field excited by one or more permanent magnets, the aforementioned BLDC motors. To generate a progressive magnetic field, at least three stator coils are required. The control of the at least three stator coils is achieved by at least three associated half-bridges, each containing an upper and a lower power switch, preferably each with a power transistor.This control of the power transistors is as synchronous as possible to the angular position of the rotor relative to the position of the stator coils in order to maximize efficiency. According to the state of the art, the rotor position can be detected using sensors or based on the electromotive force induced in the motor's stator coils. For more information, see . Fig. 1, which shows such a system according to the state of the art. The stator coils of such a motor (M) preferably have three motor terminals, designated here as U, V, and W. Here, U is the first motor terminal, V the second motor terminal, and W the third motor terminal. A control block (St) applies the supply voltages in predetermined commutation intervals (Φ1 to Φ6, Fig. 2) to the respective motor terminals (U, V, W) or leaves the motor terminals (U, V, W) in some of the specified commutation intervals (Φ1 to Φ6, Fig. 2) even de-energised, whereby at the relevant motor terminals (U, V, W) in the relevant commutation intervals (Φ1 to Φ6, Fig. 2) the electromotive force (EMF) causes a measurable voltage waveform. As already described, each half-bridge has an upper switch for connecting the respective motor terminal (U, V, W) to a positive supply voltage and a lower switch for connecting the respective motor terminal (U, V, W) to a negative supply voltage. This allows a voltage that is not present in Fig. The control shown in Figure 1, which is typically located within the control block (St), connects the respective motor terminal (U, V, W) to the upper or lower supply voltage. The upper and lower switches can now be switched independently of each other. Only three of the four possible switching states of the upper and lower switches of a single half-bridge are permitted at any one time. • In a first state, the upper switch is closed, connecting the relevant motor terminal to the positive supply voltage. • In a second state, the lower switch is closed, which connects the relevant motor terminal to the lower supply voltage. • In a third permitted connection, both switches are open, meaning the associated motor connection (U, V, W) is not energized. The corresponding half-bridge of the control block (St) is passive. • The simultaneous closing of both switches is locked as a fourth, non-permissible switching state in order to prevent cross currents through the upper and lower switches in the form of a short circuit.

[0002] Due to the control method, block commutation, one of the three half-bridges for controlling the respective motor terminals is always in the passive state, which corresponds to the third state described, in which the respective motor terminal is not actively energized. During this third state, the EMF curve becomes visible at the respective motor terminal (U, V, W) as a phase voltage against a reference potential, for example, ground. With block commutation, this third state always occurs at one of the three motor terminals (U, V, W) during each of the six cyclically repeated commutation intervals (Φ1 to Φ6, Fig. 2). The first state in block commutation is also always present at one of the three motor terminals (U, V, W) during each of the six cyclically repeated commutation intervals (Φ1 to Φ6, Fig. 2). The second state is also always present at one of the three motor terminals (U, V, W) during each of the six cyclically repeated commutation intervals (Φ1 to Φ6, Fig. 2). The phase voltage at the motor terminal (U,V,W) which is in a commutation interval (Φ1 to Φ6, Fig. 2) is currently in the third high-impedance state on the part of the driving half-bridge, can, as is known from the prior art, be used to determine the position of the rotor. Fig. 2 shows the corresponding voltages at the three motor terminals (U, V, W) in the six cyclically repeated commutation intervals (Φ1 to Φ6, Fig. 2).

[0003] The following table shows the states (states 1-3) of the half-bridges in the different commutation intervals (Φ1 to Φ6, Fig. 2) in this example from the state of the art. U V W Φ1 1 3 2 Φ2 1 2 3 Φ3 3 2 1 Φ4 2 3 1 Φ5 2 1 3 Φ6 3 1 2

[0004] Thus, in the state of the art, the EMF can be measured by six different measurement configurations • be measured in the first commutation interval (Φ1) at the second motor terminal (V) and • be measured in the second commutation interval (Φ2) at the third motor terminal (W) and • be measured in the third commutation interval (Φ3) at the first motor terminal (U) and • be measured in the fourth commutation interval (Φ4) at the second motor terminal (V) and • be measured in the fifth commutation interval (Φ5) at the third motor terminal (W) and • be measured in the sixth commutation interval (Φ6) at the first motor terminal (U).

[0005] During this measurement, the so-called zero crossing of the EMF is often used, where it changes its sign relative to a reference potential. The internal time base for commutation is controlled so that this zero crossing occurs exactly in the middle of the commutation interval at the motor terminal (U, V, W) that is currently in the third state.

[0006] It should be briefly mentioned here that the voltage at the motor terminal (U, V, W) is also called phase voltage.

[0007] Alternatively, in the third state, the EMF curve itself, i.e. the voltage curve at the motor terminal (U, V, W), can be used to determine the commutation time. Since the speed of the rotor only influences the amplitude of the EMF, which is otherwise a function of the magnetic flux curve over the angular position, the integral of the EMF over time from the zero crossing to the following commutation time represents a motor constant. Conversely, by specifying an upper limit for the integral, a commutation time with a fixed angular distance from the zero crossing can be specified directly, i.e., without the detour via a time base.

[0008] This measurement of the EMF is carried out by an EMF evaluation device (EMKA), which is Fig. 1. This measures in the six commutation intervals (Φ1 to Φ6, Fig. 2) according to the respective current commutation interval (Φ1 to Φ6, Fig. 2) corresponding measurement configuration and generates a separate commutation signal (A1, A2, A3) for each of the motor terminals (U, V, W). The commutation signals (A1, A2, A3) are Fig. 2. The rotor position is also plotted as a parameter on the X-axis.

[0009] With each edge change on a commutation signal (A1, A2, A3), a control logic within the control block (St) changes its state. Alternatively, it is possible to Fig. 2 the commutation interval (Φ1 to Φ6) is derived from the commutation signals (A1, A2, A3) using static logic. For example, the first phase can be represented as an AND operation of the negated first commutation signal (A1) with the negated second commutation signal (A2) and the third commutation signal (A3). The other phases can be determined analogously. However, it has been shown that preferably between the commutation intervals (Φ1 to Φ6) a short-term and asynchronous interval after each commutation interval (Φ i with 0 <i<7) ein diesem Kommutierungsintervall (Φ i with 0 <i<7) zugehöriges Kommutierungszwischenintervall (Φ i ' with 0 <i<7) eingefügt wird, in dem die Schalter der Halbbrücken, die ihren Schaltungszustand ändern, abgeschaltet sind, um Querströme sicher auszuschließen. Insofern ist es sinnvoll, wenn die Gesamtzahl der wirklich durchlaufenen Zustände eines endlichen Automaten im Steuerblock (St) zwölf statt sechs beträgt.

[0010] Fig. 3 shows an exemplary sub-device from the prior art for determining the first commutation signal (A1) for commutation at the first motor terminal (U). This is part of the EMF evaluation device (EMKA). The following description will focus primarily on this first branch. However, it will be easy for a person skilled in the art to transfer what has been written to the two corresponding branches for the second motor terminal (V) with the associated second commutation signal (A2) and for the third motor terminal (W) with the associated third commutation signal (A3), which are arranged in parallel. In a first stage, a virtual star point signal (SpS) is generated from the three voltages of the three motor terminals (U, V, W) by means of a star connection comprising three voltage dividers (SpT1, SpT2, SpT3).This represents the mean value of the voltages at the three motor terminals (U, V, W) and is therefore subtracted from the voltage at the first motor terminal (U) by means of a second summer (SU. 2U ) is subtracted. The corrected voltage signal (U korr ) of the first motor terminal (U) is the difference between the phase voltage U and the mean value of the three phase voltages and is calculated in a first integrator (Int 1U ) is integrated. If necessary, the integrator can also be designed as a filter. The first threshold signal (S 1U ). A comparator, more precisely a first comparator (CMP 1U ), compares this first threshold signal (S 1U ) with a first default value (V refU ) for the commutation and generates therefrom the first commutation signal (A1), which is used as described in the said control block (St) for the angular commutation of the first half-bridge, which supplies current to the first motor terminal (U).

[0011] For example, a system for optimal commutation is known from DE 100 54 594 A1. Fig. 3 of DE 100 54 594 A1 shows three regulatory branches, which essentially correspond to Fig. 3 of this disclosure. The first default value (V refU ), the second default value (V refV ) and the third default value (V refW ), which may coincide, are not shown, but are implicitly recognizable to the person skilled in the art by the designation "comparator." As described above, these must be correctly parameterized in advance for the method of DE 100 54 594 A1, which is why the method of DE 100 54 594 A1 does not solve the described problem.

[0012] From US 2008 / 0 252 240 A1 a device is known which determines an optimized commutation time by evaluating the EMF. Fig. 5 of US 2008 / 0 252 240 A1 shows the time course of a phase voltage (reference symbol Vu of US 2008 / 0 252 240 A1) in the upper part. This phase voltage (reference symbol Vu of US 2008 / 0 252 240 A1) always shows the EMF (reference symbol Vu' of US 2008 / 0 252 240 A1) when the associated driver is high-impedance. In the lower part of the Fig. 3 of US 2008 / 0 252 240 A1, the current flow to the other two phases is shown temporally, with the current flowing to the phase in question always occurring when the signal (reference symbol Spwm in US 2008 / 0 252 240 A1) is at its lowest value. If the phase in question is high-impedance, the other two phases are energized, and the EMF can be measured at the phase in question.

[0013] The EMF can therefore only be measured at the phase voltage under consideration (reference symbol Vu of US 2008 / 0 252 240 A1) when the other two phases are energized.

[0014] In a device or method according to US 2008 / 0 252 240 A1, the zero crossing of the EMF is searched for in order to determine the optimal commutation time. If the commutation time does not occur during a high-impedance period of the driver, this determination of the commutation time is achieved by linear interpolation from a first point in time with a suitable time delay. The disclosure of US 2008 / 0 252 240 A1 describes the determination of this time delay.

[0015] If the zero crossing is in the non-energized time period, at which the phase voltage (reference symbol Vu of US 2008 / 0 252 240 A1) is not on the EMF line (reference symbol Vu' of US 2008 / 0 252 240 A1 in Fig. 3 of US 2008 / 0 252 240 A1), the zero crossing can only be estimated. This situation shows Fig. 5 of US 2008 / 0 252 240 A1. This is done in the technique of US 2008 / 0 252 240 A1 as follows: According to US 2008 / 0 252 240 A1, a measurement of the phase voltage of interest (reference symbol Vu of US 2008 / 0 252 240 A1) is always taken at observable times. This creates a step-shaped signal (reference symbol Sdiff of US 2008 / 0 252 240 A1 in Fig. 5 of US 2008 / 0252 240 A1). At the same time, the temporal gradient of the phase voltage (reference symbol Vu of US 2008 / 0252 240 A1) is recorded at these measurement times based on two previous measurements, and a sawtooth curve (reference symbol Sramp of US 2008 / 0252 240 A1) is generated with this gradient. This allows the zero crossing to be linearly interpolated into the period during which the EMF at the phase connection of interest cannot be measured because it is energized by simply adding these signals (reference symbols Sdiff and Sramp of US 2008 / 0252 240 A1) with the correct sign.

[0016] This method directly evaluates the zero crossing of the EMF and determines the zero crossing through time-linear interpolation. This has the following disadvantages. 1. The method of US 2008 / 0 252 240 A1 is susceptible to interference because disturbances in the EMF, i.e., the phase voltage of interest (reference symbol Vu in US 2008 / 0252 240 A1), lead to inaccuracies in the calculation of the zero crossing. This makes the method of US 2008 / 0 252 240 A1 particularly susceptible to interference, such as EMC, especially at low speeds with low EMF. 2. The actual commutation time must be determined by adding a linearly interpolated time period. Linearity is based on the formation of the first time derivative in the form of the sawtooth signal (reference symbol Sramp in US 2008 / 0 252 240 A1). This linear interpolation assumes a non-accelerated motor. Thus, the method of US 2008 / 0 252 240 A1 only works at low accelerations. A control system such as that of US 2008 / 0 252 240 A1 is therefore unsuitable for handling high load dynamics.

[0017] Fig. Figure 4 shows the voltage at the first motor terminal (U) during optimal commutation for a low, medium, and high angular velocity. The first threshold signal (S) assigned to the first motor terminal (U) 1U ), which according to the previous description and the Fig. 3, increases essentially quadratically until it is equal to the first preset value (V refU ) for commutation. The first commutation signal (A1) (not shown) then switches, and the half-bridge assigned to the first motor terminal (U) is commutated. It is completely irrelevant whether the angular velocity is high or low.

[0018] Fig. Figure 5 shows the voltage at the first motor terminal (U) for early commutation, late commutation, and optimal commutation. The first threshold signal (S) assigned to the first motor terminal (U) is 1U) increases again essentially quadratically until it is equal to the first preset value (V refU ) for commutation. The first commutation signal (A1) (not shown) then switches and the half-bridge assigned to the first motor terminal (U) is commutated. This occurs in the left part of the figure. Fig. 5 too early, in the middle part of the figure too late, and in the right part of the figure at an optimal time. It should be clear that a zero crossing position in the middle of the respective commutation interval is optimal.

[0019] In addition to the branch described so far within the EMF evaluation (EMKA) for the first motor connection (U), there is typically a second branch for the second motor connection (V) with associated individual elements (SU 2V , INT 1V , CMP 1V ) and signals (V korr , S 1V , V refV) and a third branch for the third motor connection (W) with associated individual elements (SU 2W , INT 1W , CMP 1W ) and signals (W korr , S 1W , V refW ).

[0020] In order to achieve commutation to the same angular position of the rotor in different motors, the respective default values ​​(V refU , V refV , V refW ) must be adjusted accordingly. However, since the course of the magnetic flux in relation to the angular position of the rotor is usually unknown and cannot be determined from the motor data sheet, the respective default values ​​(V refU , V refV , V refW ) must first be determined experimentally. The respective default values ​​(V refU , V refV , V refW) during operation until commutation is carried out at the desired time. Typically, however, the default values ​​are the same (V refU =V refV =V refW =V ref ).

[0021] It is clear to the person skilled in the art that the device previously described in space multiplexing can also be used in time multiplexing, meaning that only one branch in the EMF evaluation (EMKA) needs to be implemented if the values ​​of a motor connection (U, V, W) in the commutation intervals (Φ1 to Φ6, Fig. 2), in which the corresponding half-bridge is in states one or two, can be temporarily stored and the values ​​can be loaded into the corresponding branch assigned to the motor terminal (U, V, W) which is used in the commutation intervals (Φ1 to Φ6, Fig. 2) has an associated half-bridge located in the respective commutation interval (Φ1 to Φ6, Fig. 2) is currently in the third state. Therefore, it makes sense for parts of the device to be implemented using a microcontroller, signal processor, or other computer. In this respect, the various elements described above can also be combined into one or a few elements. Object of the invention

[0022] The object of the invention is to enable automatic determination of the respective default values ​​for the respective motor terminals (U, V, W), thus eliminating the need for characterizing the individual, specific BLDC motors during production. The deficiencies identified in the prior art are to be avoided. This particularly concerns avoiding manual parameterization as in a method according to DE 10 054 594 A1 and speed dependency, as in a method according to US 2008 / 0 252 240 A1.

[0023] This object is achieved by a method according to claim 1 and a device according to claim 6. Description of the invention

[0024] The inventive fully automatic determination of the default value V ref In contrast to the method of US 2008 / 0 252 240 A1, the method is carried out by integrating the EMF. From the prior art, it is known to those skilled in the art that this is a flux-based method, which is independent of the speed and thus also independent of the acceleration, which represents a decisive advantage over the method of US 2008 / 0 252 240 A1. This determination of the specified value V ref This can occur during active operation or when the rotor is set in rotation by an external force. In contrast to US 2008 / 0 252 240 A1, a constant speed is therefore not necessary. Typically, a common default value (Vref ) for all three motor connections (U, V, W). The determination of motor connection-specific default values ​​(V refU , V RefV , V refW ) is expressly possible for the purpose of an even more precise correction of the motor asymmetries.

[0025] The device according to the invention therefore comprises means for automatically adapting the specified value of the integration to the respective motor, which distinguishes the invention from the prior art. The aim here is that the zero crossing of the EMF ultimately lies in the middle of the commutation interval (Φ1 to Φ6) without manual adjustment through automatic adaptation of the specified value of the integration. It is irrelevant whether commutation is actually carried out, such as during active operation of the motor, or not, such as during an externally induced rotation of the rotor. If the zero crossing lies in the middle of the commutation interval (Φ1 to Φ6), the EMF at the non-energized motor terminal (U, V, W) has a negative sign during the first half of the commutation interval (Φ1 to Φ6) and a positive sign during the second half of the commutation interval (Φ1 to Φ6).For example, if these signs are summed using a fixed clock cycle, i.e., integrated discretely, the sum value at the ideal commutation time is zero. Otherwise, a deviation with a negative or positive sign occurs. A negative sign indicates a zero crossing that is too early, corresponding to late commutation, and a positive sign indicates a zero crossing that is too late, corresponding to early commutation. Analog integration is, of course, also possible.

[0026] By adding the residual value to the reference value of the integration, a new value is created, which is then used as the reference value. This moves the zero crossing toward the center of the commutation interval (Φ1 to Φ6). Small fluctuations and measurement errors can be avoided by using a hysteresis function or another filter. Description of the characters Fig. 1 shows a schematic circuit of a control device from the prior art and was already described in the introduction as belonging to the prior art. Fig. Figure 2 shows the three exemplary commutation signals (A1, A2, A3) and the corresponding voltage curves at the motor terminals (U, V, W) in a schematic manner for several commutation intervals (Φ1 to Φ6) and was already described in the introduction as belonging to the state of the art. Fig. 3 shows an exemplary branch within the EMF evaluation (EMKA) for the first motor connection (U) for generating the first commutation signal (A1) assigned to the first motor connection (U) and was already described in the introduction as belonging to the state of the art. Fig. 4 shows the quadratic increase of the first threshold signal (S 1U) and the voltage at the first motor terminal (U) when the corresponding half-bridge of the control block (St) is in the high-impedance third state, for different angular velocities and was already described in the introduction as belonging to the state of the art. Fig. 5 shows the voltage at the first motor terminal (U) when the associated half-bridge of the control block (St) is in the high-impedance third state, for different values ​​of the first preset value according to the invention (V u ) and the voltage curve of the first threshold signal (S 1U ) and was already described in the introduction as belonging to the state of the art. Fig. 6 shows an exemplary branch according to the invention within the EMF evaluation (EMKA) for the first motor connection (U) for generating the first commutation signal (A1) assigned to the first motor connection (U). Fig. Figure 7 shows, firstly, the voltage at the first motor terminal (U) when the associated half-bridge of the control block (St) is in the high-impedance third state, for different values ​​of the first preset value according to the invention (V u ) and secondly the voltage curve of the first threshold signal (S 1U ) and thirdly the voltage curve of the first integrated sign signal (S 2U ) for these cases. Fig. 8 shows an exemplary branch according to the invention within the EMF evaluation (EMKA) for the second motor connection (V) for generating the first commutation signal (A2) assigned to the second motor connection (V). Fig. 9 shows an exemplary branch according to the invention within the EMF evaluation (EMKA) for the third motor connection (W) for generating the first commutation signal (A3) assigned to the third motor connection (W). Fig. 10 shows the system according to the invention according to Fig. 1 with three branches according to the invention according to the Fig. 6, Fig. 8 and Fig. 9. Fig. 11 corresponds to the Fig. 6 However, the limitation is effected in a different way. Fig. 12 corresponds to the Fig. 8 However, the limitation may be made in a manner other than that provided for in Fig. 11 is carried out. Fig. 13 corresponds to the Fig. 9 However, the limitation may be expressed in a manner other than that provided for in Fig. 11 and Fig. 12 takes place. Fig. 14 corresponds to the Fig. 6 where, however, no sign extraction occurs. Fig. 15 corresponds to the Fig. 8 However, no sign extraction is performed. Fig. 16 corresponds to the Fig. 9 However, no sign extraction is performed. Fig. 17 corresponds to the Fig. 6 where a switch can now prevent the control and freeze the default value. Fig. 18 corresponds to the Fig. 8 where a switch can now prevent the control and freeze the default value. Fig. 19 corresponds to the Fig. 9 where a switch can now prevent the control and freeze the default value. Fig. 20 shows the process for pre-parameterization in the production of a system according to the invention and for reloading the values ​​during operation.

[0027] The invention is explained in more detail below with reference to the figures, which do not correspond to the prior art. The scope of this disclosure is determined solely by the claims.

[0028] Fig. Figure 6 shows an exemplary sub-device according to the invention for determining the first commutation signal (A1) for commutation at the first motor terminal (U). This is a first branch (ZW1) of the EMF evaluation (EMKA) of the Fig. 1 and Fig. 10. In this respect, the Fig. 3 is replaced by this new sub-device according to the invention in at least one branch of the EMF evaluation (EMKA), which typically contains such a branch for each motor terminal (U, V, W). In a first stage of the sub-device according to the invention, a virtual star-point signal (SpS) is generated from the three voltages of the three motor terminals (U, V, W) using the already known and unchanged star connection of three voltage dividers (SpT1, SpT2, SpT3). This virtual star-point voltage (SpS) is again, as before, subtracted from the voltage at the first motor terminal (U) by means of the known second summer (SU 2U) is subtracted. The corrected voltage signal (U korr ) of the first motor connection (U) is in a first integrator (Int 1U ) is integrated again. In a special embodiment of the invention, the integrator can also be designed as a filter. Preferably, the first integrator (Int 1U ) only positive values ​​of the corrected voltage signal (U korr ) of the first motor terminal (U) in the commutation intervals (Φ1 to Φ6) in which the corresponding half-bridge of the first motor terminal (U) is high-impedance. In the example described here, these are the third commutation interval (Φ3) and the sixth commutation interval (Φ6). The first integrator (Int 1U) is typically reset immediately before or at the beginning of such a commutation interval (Φ3, Φ6), for example by the control block (St) or another controller. In order to only use the positive values ​​of the corrected voltage signal (U korr ) of the first motor connection (U) there are two possibilities: Firstly, it is possible with the help of a first limiter (B U ) only positive signal components of the corrected voltage signal (U korr ) of the first motor connection (U) to the first integrator (Int1U) and otherwise to the first integrator (Int 1U ) by the first limiter (B U ) to return a zero value. (This is in Fig. 6.) On the other hand, it is possible to use a first sign signal (Sig U ), which is the sign of the corrected voltage signal (U korr) of the first motor terminal (U) and a first commutation interval signal (P U ) a first integrator control signal (IntCtr U ). This controls the first integrator (Int 1U ) in such a way that it sets the first integrator to zero for the first time in the third commutation interval (Φ3) when the corrected voltage signal (U korr ) of the first motor terminal (U) is positive and an integration of the corrected voltage signal (U korr ) of the first motor terminal (U) by the first integrator (Int 1U ) is initiated when the corrected voltage signal (U korr ) of the first motor terminal (U) is negative and secondly, in the sixth commutation interval (Φ6), the first integrator is set to zero when the corrected voltage signal (U korr) of the first motor terminal (U) is negative and an integration of the corrected voltage signal multiplied by +1 (U korr ) of the first motor terminal (U) by the first integrator (Int 1U ) is initiated when the corrected voltage signal (U korr ) of the first motor terminal (U) is positive. (This is shown in Figure 11 as a variant of Figure 6.)

[0029] Tests have shown that the use of the first limiter (B U ) is particularly preferable.

[0030] The first threshold signal (S 1U ) as the output of the first integrator (Int 1U ), which is already known from the prior art. A comparator, more precisely a fourth comparator according to the invention (CMP 2U ), compares this first threshold signal (S 1U ) but not, as in the state of the art, with the said first default value (V refU) for the commutation, which had to be determined experimentally, but with a first default value according to the invention (V U ), which is determined by the sub-device itself, which represents the core of the invention. This will be discussed in more detail later. The fourth comparator (CMP 2U ) now generates the first commutation signal (A1), which is used as described in the said control block (St) for the timely commutation of the first half-bridge, which supplies current to the first motor terminal (U). Here, the fourth comparator (CMP 2U ) preferably exhibits a hysteresis in a special embodiment of the invention.

[0031] In contrast to the prior art, the sub-device according to the invention has a first sign unit (Sgn U ) which determines the sign of the corrected voltage signal (U korr ). This determined sign is determined by the first sign unit (Sgn U) as the first sign signal (Sig U ) is output. A fourth integrator (Int 2U ) when the first half-bridge is in the third state and during the third and sixth commutation interval (Φ3, Φ6) this sign is maintained. The integration is reset to zero at the beginning of the commutation interval (Φ3, Φ6). The value of the integration can be adjusted by a first constant factor (F U ) to adjust the transient response by a fourth integrator (Int 2U ) contained in the multiplier. This results in the first integrated sign signal (S 2U ). To this first integrated sign signal (S 2U ) the current first default value according to the invention (V U ) by a third summer (SU 3U ) for the first motor connection (U). This results in the first recharge value (S 3U) for the first default value (V U ) for the commutation of the first motor terminal (U) at the next commutation. This is controlled by a first sample-and-hold circuit (SaH U ) is secured when the first commutation signal (A1) has an edge.

[0032] Preferably, the rising and falling edges of the first commutation signal (A1) are evaluated. Alternatively, the fourth integrator (Int 2U ) in the third commutation interval (Φ3) the first integrated sign signal (S 2U ) with a positive multiplication factor of 1 and in the sixth commutation interval (Φ6) the first integrated sign signal (S 2U ) with a negative multiplication factor of -1. The value of the integration can be multiplied by a first constant factor (F U ) to adjust the transient response by a fourth integrator (Int 2U) contained in the multiplier. At the same time, the first integrator (Int 1U ) in the third commutation interval (Φ3) the first threshold signal (S 1U ) with a positive multiplication factor of 1 and in the sixth commutation interval (Φ6) the first threshold signal (S 1U ) with a negative multiplication factor of -1. In this case, the rising edge of the first commutation signal (A1) is always evaluated. Another possibility is that the output of the fourth integrator (Int 2U ) has an absolute value generator, so that the fourth integrator (Int 2U) only outputs the absolute value with a positive sign. Even then, the positive edge of the first commutation signal (A1) is preferably evaluated at the transition from the sixth commutation interval (Φ6) to the first commutation interval (Φ1) or at the transition from the third commutation interval (Φ3) to the fourth commutation interval (Φ4).

[0033] The output of the first sample and hold circuit (SaH U ) represents the current first default value according to the invention (V U ) which is determined by the fourth comparator (CMP 2U ) is used to form the first commutation signal (A1). The first recharge value (S 3U ) for the new inventive first default value (V U ) for the commutation of the first motor connection (U) at the next commutation on one side and the first default value according to the invention (V U ) on the other hand differ by the first temporary change value (ΔVU ).

[0034] Fig. Figure 7 shows, firstly, the voltage at the first motor terminal (U) when the associated half-bridge of the control block (St) is in the high-impedance third state, for different values ​​of the first preset value according to the invention (V U ) and secondly the voltage curve of the first threshold signal (S 1U ) and thirdly the voltage curve of the first integrated sign signal (S 2U ) for these cases.

[0035] The left shows a commutation that is too early. In this case, the first preset value according to the invention (V U ) is too small. The first temporary change value (ΔV U ) is positive and is set to the first default value (V U ) are added together. The first reload value thus determined (S 3U) is then transferred to the first sample and hold circuit (SaH U ) and thus from that point onwards as the new first default value (V U ), whereby this first default value (V U ), which makes this sub-device state-of-the-art with experimentally pre-determined first default values ​​(V refU ) differs.

[0036] In the middle, a commutation that is too late is shown. In this case, the first preset value according to the invention (V U ) is too large. The first temporary change value (ΔV U ) is negative and is set to the first default value (V U ) are added together. The first reload value thus determined (S 3U ) is then fed back into the first sample and hold circuit (SaH U) and thus from that point onwards as the new first default value (V U ), whereby this first default value (V U ) is also tracked in this case, which also in this case makes this sub-device of the state of the art with experimentally pre-determined first default values ​​(V refU ) differs.

[0037] If the first integrated sign signal (S 2U ) is zero at the end of the third or sixth commutation interval (Φ3, Φ6), the zero crossing of the EMF is located, as desired, in the middle of the third or sixth commutation interval (Φ3, Φ6).

[0038] Fig. Figure 8 shows an exemplary sub-device according to the invention for determining the second commutation signal (A2) for the commutation at the second motor connection (V). This is a second branch (ZW2) of the EMF evaluation (EMKA) of the Fig. 1 and Fig. 10. In this respect, the Fig. 3 is replaced by this new sub-device according to the invention in at least the second branch (ZW2) of the EMF evaluation (EMKA), which typically contains such a branch for each motor terminal (U, V, W). In a first stage of the sub-device according to the invention, a virtual star-point signal (SpS) is generated from the three voltages of the three motor terminals (U, V, W) using the already known and unchanged star connection of three voltage dividers (SpT1, SpT2, SpT3). This circuit part can be used jointly with the first branch (ZW1). This virtual star-point voltage (SpS) is again, as before, subtracted from the voltage at the second motor terminal (V) by means of the known associated second summer (SU 2V ) is subtracted. The corrected voltage signal (V korr ) of the second motor terminal (V) is in a first integrator (Int 1V) is reintegrated. In a special version of the invention, the integrator can also be designed as a filter.

[0039] Preferably, the second integrator (Int 1V ) only positive values ​​of the corrected voltage signal (V korr ) of the second motor terminal (V) in the commutation intervals (Φ1 to Φ6) in which the corresponding half-bridge of the second motor terminal (V) is high-impedance. In the example described here, these are the first commutation interval (Φ1) and the fourth commutation interval (Φ4). The second integrator (Int 1V ) is typically reset immediately before or at the beginning of such a commutation interval (Φ1, Φ4), for example by the control block (St) or another controller. In order to only use the positive values ​​of the corrected voltage signal (V korr ) of the second motor connection (V), there are again two possibilities: Firstly, it is possible with the help of a second limiter (B V ) only positive signal components of the corrected voltage signal (V korr ) of the second motor connection (V) to the second integrator (Int 1V ) and otherwise to the second integrator (Int 1V ) by the second limiter (B V ) to return a zero value. (This is in Fig. 8.)

[0040] On the other hand, it is possible to use a second sign signal (Sig V ), which is the sign of the corrected voltage signal (V korr ) of the second motor terminal (V) and a second commutation interval signal (P V ) a second integrator control signal (IntCtr V ). This controls the second integrator (Int 1V ) in such a way that it first in the first commutation interval (Φ1) the second integrator (Int 1V) to zero when the corrected voltage signal (V korr ) of the second motor terminal (V) is positive and an integration of the corrected voltage signal (V korr ) of the second motor terminal (V) by the second integrator (Int 1V ) is initiated when the corrected voltage signal (V korr ) of the second motor terminal (V) is negative and

[0041] secondly, in the fourth commutation interval (Φ4), the second integrator is set to zero when the corrected voltage signal (V korr ) of the second motor terminal (V) is negative and an integration of the corrected voltage signal (V korr ) of the second motor terminal (V) by the second integrator (Int 1V ) is initiated when the corrected voltage signal (V korr ) of the second motor terminal (V) is positive. (This is shown in Figure 12 as a variant of Figure 8.)

[0042] Tests have shown that the use of the second limiter (B V ) is particularly preferable.

[0043] The second threshold signal (S 1V ) as the output of the second integrator (Int 1V ), which is already known from the prior art. A comparator, more precisely a fifth comparator according to the invention (CMP 2V ), compares this second threshold signal (S 1V ) but not, as in the prior art, with the said second default value (V refV ) for the commutation, which had to be determined experimentally, but with a second default value according to the invention (V V ), which is now determined by the sub-device itself, which again represents the core of the invention. The fifth comparator (CMP 2V) now generates the second commutation signal (A2), which is used as described in the said control block (St) for the timely commutation of the second half-bridge, which supplies current to the second motor terminal (V). Here, the fifth comparator (CMP 2V ) preferably in a special embodiment of the invention again exhibits a hysteresis.

[0044] In contrast to the prior art, the sub-device according to the invention has a second sign unit (Sgn V ) which determines the sign of the corrected voltage signal (V korr ). This determined sign is then used by the second sign unit (Sgn V ) as a second sign signal (Sig V ) is output. A fifth integrator (Int 2V) when the second half-bridge is in the third state and during the first and fourth commutation intervals (Φ1, Φ4) ​​this sign is maintained. The integration is reset to zero at the beginning of the commutation interval (Φ1, Φ4). The value of the integration can be adjusted by a second constant factor (F V ) to adjust the transient response by means of a fifth integrator (Int 2V ) contained in the multiplier. This results in the second integrated sign signal (S 2V ). To this second integrated sign signal (S 2V ) the current second default value according to the invention (V V ) by a third summer (SU 3V ) for the second motor connection (V). This results in the second recharge value (S 3V ) for the second default value (V V) for the commutation of the second motor terminal (V) at the next commutation. This is controlled by a second sample-and-hold circuit (SaH V ) is secured when the second commutation signal (A2) has an edge. The rising and falling edges of the second commutation signal (A2) are evaluated. Alternatively, the fifth integrator (Int 2V ) in the first commutation interval (Φ1) the second integrated sign signal (S 2V ) with a positive multiplication factor of 1 and in the fourth commutation interval (Φ4) the second integrated sign signal (S 2V ) with a negative multiplication factor of -1. The value of the integration can be multiplied by a second constant factor (F V ) to adjust the transient response by means of a fifth integrator (Int 2V) contained in the multiplier. At the same time, the second integrator (Int 1V ) in the first commutation interval (Φ1) the second threshold signal (S 1V ) with a positive multiplication factor of 1 and in the fourth commutation interval (Φ4) the second threshold signal (S 1V ) with a negative multiplication factor of -1. In this case, the rising edge of the second commutation signal (A2) is always evaluated. Another possibility is that the output of the fifth integrator (Int 2V ) has an absolute value generator, so that the fifth integrator (Int 2V) only outputs the absolute value with a positive sign. Even then, the positive edge of the second commutation signal (A2) is preferably evaluated during the transition from the first commutation interval (Φ1) to the second commutation interval (Φ2) or during the transition from the fourth commutation interval (Φ4) to the fifth commutation interval (Φ5).

[0045] The output of the second sample and hold circuit (SaH V ) represents the current second default value according to the invention (V V ) which is determined by the fifth comparator (CMP 2V ) is used to form the second commutation signal (A2). The second recharge value (S 3V ) for the new second default value according to the invention (V V ) for the commutation of the second motor connection (V) at the next commutation on one side and the second default value according to the invention (V V) on the other hand differ by the second temporary change value (ΔV V ).

[0046] Fig. Figure 9 shows an exemplary sub-device according to the invention for determining the third commutation signal (A3) for the commutation at the third motor connection (W). This is a third branch (ZW3) of the EMF evaluation (EMKA) of the Fig. 1 and Fig. 10. In this respect, the Fig. 3 is replaced by this new sub-device according to the invention in at least the third branch (ZW3) of the EMF evaluation (EMKA), which typically contains such a branch for each motor terminal (U, V, W). In a first stage of the sub-device according to the invention, a virtual star-point signal (SpS) is generated from the three voltages of the three motor terminals (U, V, W) using the already known and unchanged star connection of three voltage dividers (SpT1, SpT2, SpT3). This circuit part can be used jointly with the first branch (ZW1). This virtual star-point voltage (SpS) is again, as before, subtracted from the voltage at the third motor terminal (W) by means of the known associated second summer (SU 2W ) is subtracted. The corrected voltage signal (W korr ) of the third motor terminal (W) is in a first integrator (Int 1W) is reintegrated. In a special version of the invention, the integrator can also be designed as a filter.

[0047] Preferably, the third integrator (Int 1W ) only positive values ​​of the corrected voltage signal (W korr ) of the third motor terminal (W) in the commutation intervals (Φ1 to Φ6) in which the corresponding half-bridge of the third motor terminal (W) is high-impedance. In the example described here, these are the fifth commutation interval (Φ5) and the second commutation interval (Φ2). The third integrator (Int 1W ) is typically reset immediately before or at the beginning of such a commutation interval (Φ5, Φ2), for example by the control block (St) or another controller. In order to only use the positive values ​​of the corrected voltage signal (W korr ) of the third motor connection (W), there are again two possibilities: Firstly, it is possible with the help of a third limiter (B W ) only positive signal components of the corrected voltage signal (W korr ) of the second motor connection (W) to the third integrator (Int 1W ) and otherwise to the third integrator (Int 1W ) by the third limiter (B W ) to return a zero value. (This is in Fig. 9.) On the other hand, it is possible to use a third sign signal (Sig W ), which is the sign of the corrected voltage signal (W korr ) of the third motor terminal (W) and a third commutation interval signal (P W ) a third integrator control signal (IntCtr W ). This controls the third integrator (Int 1W ) in such a way that it first in the fifth commutation interval (Φ5) the third integrator (Int 1W) to zero when the corrected voltage signal (W korr ) of the third motor terminal (W) is positive and an integration of the corrected voltage signal (W korr ) of the third motor terminal (W) by the third integrator (Int 1w ) is initiated when the corrected voltage signal (W korr ) of the third motor terminal (W) is negative and secondly, in the second commutation interval (Φ2), the third integrator is set to zero when the corrected voltage signal (W korr ) of the third motor terminal (W) is negative and an integration of the corrected voltage signal (W korr ) of the third motor terminal (W) by the third integrator (Int 1W ) is initiated when the corrected voltage signal (W korr ) of the third motor terminal (W) is positive. (This is shown in Figure 13 as a variant of Figure 9.)

[0048] Tests have shown that the use of the third limiter (B W ) is particularly preferable.

[0049] The third threshold signal (S 1W ) as the output of the third integrator (Int 1W ), which is already known from the prior art. A comparator, more precisely a sixth comparator according to the invention (CMP 2W ), compares this third threshold signal (S 1W ) but not, as in the state of the art, with the said third default value (V refV ) for the commutation, which had to be determined experimentally, but with a third default value according to the invention (V W ), which is now determined by the sub-device itself, which again represents the core of the invention. The sixth comparator (CMP 2W) now generates the third commutation signal (A3), which is used as described in the aforementioned control block (St) for the timely commutation of the third half-bridge, which supplies current to the third motor terminal (W). Here, the sixth comparator (CMP 23 ) preferably in a special embodiment of the invention again exhibits a hysteresis.

[0050] In contrast to the prior art, the sub-device according to the invention, the third branch (ZW3), has a third sign unit (Sgn W ) which determines the sign of the corrected voltage signal (W korr ). This determined sign is determined by the third sign unit (Sgn W ) as the third sign signal (Sig W ) is output. A sixth integrator (Int 2W) when the third half-bridge is in the third state and during the second and fifth commutation intervals (Φ2, Φ5) this sign is maintained. The integration is reset to zero at the beginning of the commutation interval (Φ2, Φ5). The value of the integration can be adjusted by a third constant factor (F V ) to adjust the transient response by means of an integrator in the sixth (Int 2V ) contained in the multiplier. This results in the third integrated sign signal (S 2W ). To this third integrated sign signal (S 2W ) the current third default value according to the invention (V W ) by a third summer (SU 3W ) for the third motor connection (W). This results in the third recharge value (S 3W ) for the third default value (V W) for the commutation of the third motor terminal (W) at the next commutation. This is controlled by a third sample-and-hold circuit (SaH W ) is secured when the third commutation signal (A3) has an edge.

[0051] Preferably, the rising and falling edge of the third commutation signal (A1) is evaluated. Alternatively, the sixth integrator (Int 2W ) in the fifth commutation interval (Φ5) the third integrated sign signal (S 2W ) with a positive multiplication factor of 1 and in the second commutation interval (Φ2) the third integrated sign signal (S 2W ) with a negative multiplication factor of -1. The value of the integration can be multiplied by a third constant factor (F V ) to adjust the transient response by means of an integrator in the sixth (Int 2V) contained in the multiplier. At the same time, the third integrator (Int 1W ) in the fifth commutation interval (Φ5) the third threshold signal (S 1W ) with a positive multiplication factor of 1 and in the second commutation interval (Φ2) the third threshold signal (S 1W ) with a negative multiplication factor of -1. In this case, the rising edge of the third commutation signal (A3) is always evaluated at the transition from the second commutation interval (Φ2) to the third commutation interval (Φ3) or at the transition from the fifth commutation interval (Φ5) to the sixth commutation interval (Φ6). Another possibility is that the output of the sixth integrator (Int 2W ) has an absolute value generator, so that the sixth integrator (Int 2W) only outputs the absolute value with a positive sign. Even then, the positive edge of the third commutation signal (A3) is preferentially evaluated.

[0052] The output of the third sample and hold circuit (SaH W ) represents the current third default value according to the invention (V W ) which is determined by the sixth comparator (CMP 2W ) is used to form the third commutation signal (A3). The third recharge value (S 3W ) for the new third default value according to the invention (V W ) for the commutation of the third motor terminal (W) at the next commutation on one side and the third default value according to the invention (V W ) on the other hand differ by the third temporary change value (ΔV W ).

[0053] Fig. 10 shows Fig. 1 with the three branches (ZW1, ZW2, ZW3). The control block (St) or another controller activates the integration in the integrators of the branch whose corresponding half-bridge at the corresponding motor terminal (U, V, W) is currently in the high-impedance phase in the respective commutation interval (Φ1 to Φ6). As previously explained, the states of the commutation signals (A1, A2, A3) reflect the current commutation interval (Φ1 to Φ6) in the form of a binary logic vector.

[0054] The Fig. 11 to 13 have already been mentioned above.

[0055] Fig. 14 shows a variant of the Fig. 6 where the corrected voltage signal (U korr ) of the first motor connection (U) directly as an input signal for the fourth integrator (Int 2U ) serves.

[0056] Fig. 15 shows a variant of the Fig. 8 where the corrected voltage signal (V korr) of the second motor terminal (V) directly as an input signal for the fifth integrator (Int 2V ) serves.

[0057] Fig. 16 shows a variant of the Fig. 9 where the corrected voltage signal (W korr ) of the third motor terminal (W) directly as an input signal for the sixth integrator (Int 2W ) serves.

[0058] Fig. Figure 17 shows a further preferred embodiment of the invention using the example of the first branch (ZW1). If the method described above for automatically determining the first default value (V U ) once a stable first default value according to the invention (V U ), it no longer changes. This means that the lower branch of the control of the first setpoint value according to the invention (V U ) consisting of the first sign unit (Sgn U ), the fourth integrator (Int 2U ) and the third summer (SU2U ), which is assigned to the first motor terminal (U), is no longer required. Therefore, in a special embodiment of the invention, it is possible, e.g. after the automatic adjustment has been carried out, to set the clock of the associated first sample-and-hold circuit (SaH U ) so that its output signal, the first inventive preset value (V U ), remains at the achieved, as stable as possible value. For this purpose, Fig. 17 an additional first switch (SW U ) into the connection between the first commutation signal (A1) and the trigger input of the first sample-and-hold circuit (SaH U ) is inserted. With this first switch (SW U ), it is then possible to switch between the two states "automatic parameterization" and "normal engine operation." Automatic parameterization occurs, for example, after the system is switched on when the engine is first started or upon request.

[0059] For this purpose, the system according to the invention has a system controller (SSt), which typically comprises a finite state machine as a sequence controller and / or a microprocessor with memory and which, by means of one or more analog-to-digital converters and possibly further sample-and-hold circuits, generates the precharge value (V0) for the respectively assigned sample-and-hold circuits (SaH U , SaH V , SaH W ). This precharge value (V0) can also be in the form of three separate precharge values ​​(V U , V V , V W ) are generated specifically for the respective branch (ZW1, ZW2, ZW3). In addition, the system control (SSt) evaluates the status of the respective inventive default value (V U , V V , V W ), in this case the first inventive default value (V U). This can be achieved, for example, by digital-to-analog conversion and evaluation of the digitized signal curve of the respective inventive default value (V U , V V , V W ), in this case the first inventive default value (V U ), happen. If the first preset value according to the invention (V U ) between two or more than two engine revolutions by less than 25%, better less than 12%, better less than 6%, better less than 2%, better less than 1%, the system control (SSt) opens the first switch (SW U ).

[0060] However, after switching off the supply voltage, the system would maintain the first inventive default value (V U ) and would have to carry out the parameterization again the next time it is switched on.

[0061] It is therefore useful if the first inventive default value (V U) is saved in a non-volatile, preferably digital memory, preferably within the system control (SSt) and is used as the first preload value (V 0U ) is used as a replacement for the preload value (V0) when the system is restarted. The non-volatile memory takes over the first preload value according to the invention (V U ) when opening the first switch (SW U ) and can, for example, in the case of a non-volatile memory, also be able to use this determined first precharge value according to the invention (V U ) about switching off the supply as the first precharge value (V 0U ) out.

[0062] This then enables, for example, the one-time automatic parameterization of the device according to the invention in conjunction with a specific motor at the end of a production line. Each time the system is restarted, the first precharge value (V) determined in this way, for example, at the end of production, is then used. 0U) is read directly from the non-volatile memory and the system can start directly without another automatic calibration.

[0063] Fig. Figure 18 illustrates this further preferred embodiment of the invention using the example of the second branch (ZW2). If the method described above for automatically determining the second preset value (V V ) again a stable second default value according to the invention (V V ), this also no longer changes. This means that the lower branch of the control of the second setpoint value according to the invention (V V ) consisting of the second sign unit (Sgn V ), the fifth integrator (Int 2V ) and the third summer (SU 2V), which is assigned to the second motor connection (V), is no longer required. Therefore, in a special embodiment of the invention, it is possible again, e.g. after the automatic adjustment, to set the clock of the associated second sample-and-hold circuit (SaH U ) so that its output signal, the second inventive preset value (V V ), remains at the achieved, as stable as possible value. For this purpose, Fig. 18 an additional second switch (SW U ) into the connection between the second commutation signal (A2) and the trigger input of the second sample-and-hold circuit (SaH U ) is inserted. With this second switch (SW V), it is then possible to switch between the two states "automatic parameterization" and "normal engine operation." Automatic parameterization occurs, for example, after the system is switched on when the engine is first started or upon request, typically analogous to the first branch (ZW1).

[0064] Typically, the system control (SSt) evaluates the state of the second inventive default value (V V ). This can be achieved, for example, by digital-to-analog conversion and evaluation of the thus digitized signal curve of the second inventive default value (V V ). If the second preset value (V U ) between two or more than two engine revolutions by less than 25%, better less than 12%, better less than 6%, better less than 2%, better less than 1%, the system control (SSt) opens the second switch (SW V ).

[0065] However, after switching off the supply voltage, the system would also use the second inventive default value (V V ) and would have to carry out the parameterization again the next time it is switched on.

[0066] It is therefore useful if the second inventive default value (V V ) is saved in a non-volatile, preferably digital memory, preferably within the system control (SSt) and is used as a second preload value (V 0V ) is used as a replacement for the preload value (V0) when the system is restarted. The non-volatile memory takes over the second preload value according to the invention (V V ) when opening the second switch (SW V ) and can, for example, in the case of a non-volatile memory, also be able to use this determined second precharge value according to the invention (V V ) about switching off the supply as a second precharge value (V 0V ) out.

[0067] This then enables, for example, the one-time automatic parameterization of the device according to the invention in conjunction with a specific motor at the end of a production line. Each time the system is restarted, the second precharge value (V) determined in this way, for example, at the end of production, is then used. 0V ) is read directly from the non-volatile memory and the system can start directly without another automatic calibration.

[0068] Fig. Figure 19 illustrates this further preferred embodiment of the invention using the example of the third branch (ZW3). If the method described above for automatically determining the third preset value according to the invention (V W ) again a stable third default value according to the invention (V W ), this also no longer changes. This means that the lower branch of the control of the third preset value according to the invention (VW ) consisting of the third sign unit (Sgn W ), the sixth integrator (Int 2W ) and the third summer (SU 2W ), which is assigned to the third motor connection (W), is also no longer required. Therefore, in this particular embodiment of the invention, it is also possible, e.g. after the automatic adjustment has been carried out, to adjust the clock of the associated third sample-and-hold circuit (SaH W ) here as well, so that its output signal, the third inventive preset value (V W ), remains at the achieved, as stable as possible value. For this purpose, Fig. 19 an additional third switch (SW W ) into the connection between the third commutation signal (A3) and the trigger input of the third sample-and-hold circuit (SaH W ) is inserted. With this third switch (SW W), it is then possible to switch between the two states "automatic parameterization" and "normal engine operation." Automatic parameterization occurs, for example, after the system is switched on when the engine is first started or upon request, similar to the first branch (ZW1) and / or the second branch (ZW2).

[0069] Again, the system control (SSt) typically evaluates the state of the third inventive default value (V W ). This can be achieved, for example, by digital-to-analog conversion and evaluation of the thus digitized signal curve of the third inventive default value (V W ). If the third preset value (V W ) between two or more than two engine revolutions by less than 25%, better less than 12%, better less than 6%, better less than 2%, better less than 1%, the system control (SSt) opens the third switch (SW W ).

[0070] However, after switching off the supply voltage, the system would use the third inventive default value (V W ) as well as the other two inventive default values ​​(V U , V V ) and would have to carry out the parameterization again the next time it is switched on.

[0071] It is therefore useful if the third inventive default value (V W ) is saved in a non-volatile, preferably digital memory, preferably within the system control (SSt) and is used as a third preload value (V 0W ) is used as a replacement for the preload value (V0) when the system is restarted. The non-volatile memory takes over the third preload value according to the invention (V W ) when opening the second switch (SW V ) and can, for example, in the case of a non-volatile memory, also be able to use this determined third precharge value according to the invention (V W) about switching off the supply as a third precharge value (V 0W ) out.

[0072] This then enables, for example, the one-time automatic parameterization of the device according to the invention in conjunction with a specific motor at the end of a production line. Each time the system is restarted, the third precharge value (V) determined in this way, for example at the end of production, is then used. 0W ) is read directly from the non-volatile memory and the system can start directly without another automatic calibration.

[0073] It should be noted that it is also possible to simulate the system with only one lower control branch, for example consisting of the first sign unit (Sgn U ), the fourth integrator (Int 2U ) and the third summer (SU 2U ) for the first motor connection (U) or consisting of the second sign unit (Sgn V), the fifth integrator (Int 2V ) and the third summer (SU 2V ) for the second motor connection (V) or consisting of the third sign unit (Sgn W ), the sixth integrator (Int 2W ) and the third summer (SU 2W ) for the third motor connection (W) and the determined preset value (V U ,V V , V W ) directly for the other motor terminals (U, V, W) as substitute default values ​​according to the invention (V U , V V , V W ) to share.

[0074] Fig.Figure 20 shows the process for using a device according to the invention. The system controller (SSt) or the control block (St), which can explicitly assume the function of the system controller (SSt) if necessary, determines that the system has not been supplied with power in the meantime, thus has probably been switched on. This is the process start, the first process step (1).

[0075] Next, in the second process step (2), the system control (SSt) determines whether a valid parameterization exists. For the sake of explanation, we will initially assume that this is not the case.

[0076] In this case, the system switches to a third process step (3) to precharge the sample and hold circuits (SaH U , SaH V , SaH W) with the preload value (V0), which is typically stored in the program of a microprocessor within the system control (SSt). This provides the entire system with meaningful starting values ​​in order to be able to adjust itself. Typically, the switches (SW U , SW V , SW W ) closed.

[0077] The system is now able to use the inventive default values ​​(V U , V V , V W ) itself. This is done in the next fourth process step (4), in which these inventive default values ​​(V U , V V , V W ) and thus determined. If the quality of the obtained, inventive target values ​​(V U , V V , V W ) is sufficient, which is typically the case when their fluctuations are small enough, the system control (SSt) switches to the next, fifth process step (5).

[0078] In the fifth process step (5), the system control (SSt) saves the values ​​thus determined of the inventive default values ​​(V U , V V , V W ) in a memory. This is preferably a digital non-volatile memory, which is why the system controller (SSt) preferably has one or more digital-to-analog converters to convert these values ​​of the inventive default values ​​(V U , V V , V W ) to be able to digitize.

[0079] In a subsequent sixth process step (6), the respective switches (SW U , SW V , S W) is opened. This preferably occurs with a time delay relative to the edges of the respective associated commutation signal (A1, A2, A3). Particularly preferably, this occurs synchronously with one of the other two commutation signals, as this eliminates a hazard between the respective commutation signal and the opening of the respective switch. The system then preferably switches to a waiting loop (11).

[0080] This waiting loop (11) can be exited in three ways. First, after a specified period of time, the system controller (SSt) can request a new parameterization, or a control command from outside the system initiates such a parameterization. In this case, the system controller typically returns to the third process step (3).

[0081] Secondly, if certain error conditions exist, a restart of the system can be forced with the start parameters already determined once and at the same time without a new parameterization by switching to the seventh process step (7) and with a new parameterization by switching to the eighth process step (8).

[0082] This second branch splits off in the second process step (2), in which the system control (SSt) determines whether a valid parameterization exists. It is now assumed that this is the case.

[0083] In this case, the system control (SSt) loads the sample and hold circuits (SaH U , SaH V , SaH W ) with the determined preload values ​​(V 0U , V 0V , V 0W ). At the beginning of the following eighth process step (8), the system control (SSt) closes the switches (SW U, SW V , SW W ).

[0084] The system is now again able to achieve the inventive default values ​​(V U , V V , V W ) more precisely for the current operating period on the basis of a previous operation. This is done, if necessary, in the next eighth process step (8), in which these inventive default values ​​(V U , V V , V W ) are adjusted again and thus determined. If the quality of the obtained inventive target values ​​(V U , V V , V W ) is sufficient, which is typically the case when their fluctuations are small enough, the system control (SSt) switches to the next, ninth process step (9).

[0085] In the ninth process step (9), the system control (SSt) saves the newly determined values ​​of the inventive default values ​​(V U , V V , V W) in a memory. This is preferably the aforementioned digital non-volatile memory.

[0086] In a subsequent tenth process step (10), the respective switches (SW U , SW V , SW W ) is opened. This preferably occurs, as described, with a time delay from the edges of the corresponding commutation signal (A1, A2, A3). The system then preferably switches to the waiting loop (11).

[0087] Instead of re-parameterization, the system control (SSt) can also preferably jump directly from the seventh process step (7) to the tenth process step (10). Advantages of the invention

[0088] The invention avoids the need for experimental determination of the reference value for commutation by integrating the EMF. The method is thus capable of adapting itself to different motors. This also enables automated adjustment of the parameter during the manufacture of products based on it. For example, series variations in the motor to be used can be compensated for. Even the realization of different products that differ only in the motor used is possible without additional adjustment effort.

[0089] The invention can be used to control BLDC motors using block commutation in sensorless operation based on the evaluation of the magnetic flux. When using the magnetic flux as an integral of the EMF, in contrast to commutation based on zero crossings, the adjustment between the angular position and the internal time base is eliminated. The time base is therefore no longer necessary. Instead, commutation occurs directly based on the EMF curve without any further calculation steps. The method thus offers greater stability and a better response to dynamic changes in the angular velocity of the rotor. However, it requires manual adjustment to the motor used in each case. The invention described here eliminates this disadvantage by performing the adjustment automatically. List of reference symbols 1 first process step 2 second process step 3 third process step 4 fourth process step 5 fifth process step 6 sixth process step 7 seventh process step 8 eighth process step 9 ninth process step 10 tenth process step 11 eleventh process step A1 First commutation signal for the control block (St). The first commutation signal is generated by the EMF evaluation (EMKA). The first commutation signal determines the time of the next voltage commutation by the control block (St). The voltage commutation affects the half-bridge of the control block, whose upper and lower switches are connected to the first motor terminal (U). The signal is assigned to the first motor terminal (U). A2 Second commutation signal for the control block (St). The second commutation signal is generated by the EMF evaluation (EMKA). The second commutation signal determines the time of the next voltage commutation by the control block (St). The voltage commutation affects the half-bridge of the control block, whose upper and lower switches are connected to the second motor terminal (V). The signal is assigned to the second motor terminal (V). A3 Third commutation signal for the control block (St). The third commutation signal is generated by the EMF evaluation (EMKA). The third commutation signal determines the time of the next voltage commutation by the control block (St). The voltage commutation affects the half-bridge of the control block, whose upper and lower switches are connected to the third motor terminal (W). The signal is assigned to the third motor terminal (V). B Ufirst limiter. The first limiter generates the limited corrected voltage signal (U' korr ) of the first motor terminal (U) from the corrected voltage signal (U korr ) of the first motor terminal (U). In doing so, it sets the limited corrected voltage signal (U' korr ) of the first motor terminal (U) to zero when the corrected voltage signal (U korr ) of the first motor terminal (U) is negative. This limitation can also be inverted if the sign of all components of the system is selected appropriately. It is therefore essential that the limiter only detects one polarity of the corrected voltage signal (U korr ) of the first motor terminal (U) and maps the other polarity to zero. This device part is assigned to the first motor terminal (U). B V second limiter. The second limiter generates the limited corrected voltage signal (V' korr) of the second motor terminal (V) from the corrected voltage signal (V korr ) of the second motor terminal (V). It sets the limited corrected voltage signal (V' korr ) of the second motor terminal (V) to zero when the corrected voltage signal (V korr ) of the second motor terminal (V) is negative. This limitation can also be inverted if the sign of all components of the system is selected appropriately. It is therefore essential that the second limiter only detects one polarity of the corrected voltage signal (V korr ) of the second motor terminal (V) and maps the other polarity to zero. This part of the device is assigned to the second motor terminal (V). B W third limiter. The third limiter generates the limited corrected voltage signal (W' korr ) of the third motor terminal (W) from the corrected voltage signal (W korr) of the third motor terminal (W). It sets the limited corrected voltage signal (W' korr ) of the third motor terminal (W) to zero when the corrected voltage signal (W korr ) of the third motor terminal (W) is negative. This limitation can also be inverted if the sign of all components of the system is selected appropriately. It is therefore essential that the third limiter only detects one polarity of the corrected voltage signal (W korr ) of the third motor terminal (W) and maps the other polarity to zero. This device part is assigned to the third motor terminal (W). CMP 1U The first comparator compares the first threshold signal (S 1U ) with the default value (V ref) for commutation and generates therefrom a first commutation signal (A1) that controls the commutation of the half-bridge of the control block (St), which is connected to the first motor terminal (U). This device part is assigned to the first motor terminal (U). CMP 1V The second comparator compares the second threshold signal (S 1V ) with the default value (V ref ) for commutation and generates therefrom a second commutation signal (A2) that controls the commutation of the half-bridge of the control block (St), which is connected to the second motor terminal (V). This device part is assigned to the second motor terminal (V). CMP 1W The third comparator compares the third threshold signal (S 1W ) with the default value (V ref) for commutation and generates a third commutation signal (A3) therefrom, which controls the commutation of the half-bridge of the control block (St), which is connected to the third motor terminal (W). This device part is assigned to the third motor terminal (W). CMP 2U The fourth additional comparator according to the invention compares the first threshold signal (S 1U ) with the first preset value (V U ) for the commutation and generates therefrom as a first output signal (A1) a first commutation signal (A1) that controls the commutation. In the case according to the invention, its first output signal, also called the first commutation signal (A1), triggers the first sample-and-hold circuit (SaH U ). This device part is assigned to the first motor connection (U). CMP 2V The fifth additional comparator according to the invention compares the second threshold signal (S 1V ) with the second default value (VV ) for the commutation and generates therefrom a second commutation signal (A2) as a second output signal (A2), which controls the commutation. In the case according to the invention, its second output signal, also called second commutation signal (A2), triggers the second sample-and-hold circuit (SaH V ). This device part is assigned to the second motor connection (V). CMP 2W The sixth additional comparator according to the invention compares the third threshold signal (S 1W ) with the third preset value (V W ) for the commutation and generates therefrom a third commutation signal (A3) as a third output signal (A3), which controls the commutation. In the case according to the invention, its third output signal, also called the third commutation signal (A3), triggers the third sample-and-hold circuit (SaH W ). This device part is assigned to the third motor connection (W). F Ufirst constant factor (F U ) for adjusting the transient response of the first branch (ZW1) by means of a fourth integrator (Int 2U ) contained in the multiplier. The factor is assigned to the first motor connection (U). F V second constant factor (F V ) for adjusting the transient response of the second branch (ZW2) by means of a fifth integrator (Int 2V ) contained in the multiplier. The factor is assigned to the second motor terminal (U). F W third constant factor (F W ) for adjusting the transient response of the third branch (ZW3) by means of a sixth integrator (Int 2w ) contained multiplier. The factor is assigned to the third motor connection (W). ΔV U first temporary change value for the change of the first default value according to the invention (V U) for the commutation of the first motor terminal (U) at the next commutation. The first reload value (S 3U ) for the new inventive first default value (V U ) for the commutation of the first motor connection (U) at the next commutation on one side and the first default value according to the invention (V U ) on the other hand differ by this first temporary change value (ΔV U ). The value is assigned to the first motor connection (U). ΔV V second temporary change value for the change of the second default value according to the invention (V V ) for the commutation of the second motor terminal (V) at the next commutation. The second recharge value (S 3V ) for the new second default value according to the invention (V V ) for the commutation of the second motor connection (U) at the next commutation on one side and the second default value according to the invention (VV ) on the other hand differ by this second temporary change value (ΔV V ). The value is assigned to the second motor terminal (V). ΔV W third temporary change value for the change of the third default value according to the invention (V W ) for the commutation of the third motor terminal (U) at the next commutation. The third recharge value (S 3W ) for the new third default value according to the invention (V W ) for the commutation of the third motor terminal (W) at the next commutation on one side and the third default value according to the invention (V W ) on the other hand differ by this third temporary change value (ΔV W ). The value is assigned to the third motor terminal (W). EMKA EMF evaluation. The EMF evaluation generates the commutation signals (A1, A2, A3) for controlling the commutation time of the half-bridges of the control circuit (St). The commutation signals (A1, A2, A3) are generated depending on the voltages at the motor terminals (U, V, W) and the commutation intervals (Φ1 to Φ6). The first commutation signal (A1) is generated in the third commutation interval (Φ3) and / or the sixth commutation interval (Φ6) depending on the connection voltage at the first motor terminal (U). The second commutation signal (A2) is generated in the first commutation interval (Φ1) and / or the fourth commutation interval (Φ4) depending on the connection voltage at the second motor terminal (V). The third commutation signal (A3) is generated in the second commutation interval (Φ2) and / or in the fifth commutation interval (Φ5) depending on the connection voltage at the third motor connection (V). Int 1U first integrator. In the state of the art, the first integrator forms the corrected voltage signal (U korr ) of the first motor terminal (U) or by integrating the limited corrected voltage signal (U' korr ) of the first motor terminal (U) an associated first threshold signal (S 1U ). This device part is assigned to the first motor connection (U). Int 1V second integrator. In the state of the art, the second integrator forms the corrected voltage signal (V korr ) of the second motor terminal (V) or by integrating the limited corrected voltage signal (V' korr ) of the second motor terminal (V) an associated second threshold signal (S 1V ). This device part is assigned to the second motor connection (V). Int 1Wthird integrator. In the state of the art, the third integrator forms the corrected voltage signal (W korr ) of the third motor terminal (W) or by integrating the limited corrected voltage signal (W' korr ) of the third motor terminal (W) an associated third threshold signal (S 1W ). This device part is assigned to the third motor connection (W). Int 2U fourth integrator. The fourth integrator according to the invention forms by integrating the first sign signal (Sig U ) an associated first integrated sign signal (S 2U ). This part of the device is assigned to the first motor terminal (U). The output of the fourth integrator is typically multiplied by -1 to obtain the first integrated sign signal (S 2U ) before output. The value of the integration can be adjusted by a first constant factor (F U) to adjust the transient response by a fourth integrator (Int 2U ) contained in the multiplier. This part of the device is assigned to the first motor terminal (U). Int 2V fifth integrator. The fifth integrator according to the invention forms by integrating the second sign signal (Sig V ) an associated second integrated sign signal (S 2V ). This part of the device is assigned to the second motor terminal (V). The output of the fifth integrator is typically multiplied by -1 to obtain the second integrated sign signal (S 2V ) before output. The value of the integration can be multiplied by a second constant factor (F V ) to adjust the transient response by means of a fifth integrator (Int 2V ) contained in the multiplier. This part of the device is assigned to the second motor terminal (V). Int 2Wsixth integrator. The sixth integrator according to the invention forms by integrating the third sign signal (Sig W ) an associated third integrated sign signal (S 2W ). This device part is assigned to the third motor terminal (W). The output of the sixth integrator is typically multiplied by -1 to produce the third integrated sign signal (S 2W ) before output. The value of the integration can be adjusted by a third constant factor (F W ) to adjust the transient response by means of an integrator in the sixth (Int 2W ) included in the multiplier. This part of the device is assigned to the third motor terminal (W). IntCtr U first integrator control signal for the first integrator (Int 1U ). The first integrator control signal is derived from the first sign signal (Sig U ) by the first integrator control signal generating unit (XU ) depending on a first commutation interval signal (P U ) and the first sign signal (Sig U ). This device part is assigned to the first motor connection (U). IntCtrV second integrator control signal for the second integrator (Int 1V ). The second integrator control signal is derived from the second sign signal (Sig V ) by the second integrator control signal generating unit (X V ) depending on a second commutation interval signal (P V ) and the second sign signal (Sig V ). This device part is assigned to the second motor connection (V). IntCtr W third integrator control signal for the third integrator (Int 1W ). The third integrator control signal is derived from the third sign signal (Sig W ) by the third integrator control signal generating unit (X W) depending on a third commutation interval signal (P W ) and the third sign signal (Sig W ). This device part is assigned to the third motor connection (W). M exemplary BLDC motor Φ1 first commutation interval. In this commutation interval, the upper switch of the half-bridge within the control circuit, which is connected to the first motor terminal (U) on one side and the upper supply voltage on the other side, is closed. At the same time, the lower switch of the half-bridge within the control circuit, which is connected to the third motor terminal (W) on one side and the lower supply voltage on the other side, is closed. In addition, both switches of the half-bridge within the control circuit that are connected to the second motor terminal (V) are open. Therefore, the electromotive force (EMF) can be measured as a phase voltage at the second motor terminal (V) in this commutation interval. Φ2 second commutation interval. In this commutation interval, the upper switch of the half-bridge within the control circuit, which is connected to the first motor terminal (U) on one side and the upper supply voltage on the other side, is closed. At the same time, the lower switch of the half-bridge within the control circuit, which is connected to the second motor terminal (V) on one side and the lower supply voltage on the other side, is closed. In addition, both switches of the half-bridge within the control circuit that are connected to the third motor terminal (W) are open. Therefore, the electromotive force (EMF) at the third motor terminal (W) is measurable as a phase voltage in this commutation interval. Φ3 third commutation interval. In this commutation interval, the upper switch of the half-bridge within the control circuit, which is connected to the third motor terminal (W) on one side and the upper supply voltage on the other side, is closed. At the same time, the lower switch of the half-bridge within the control circuit, which is connected to the second motor terminal (W) on one side and the lower supply voltage on the other side, is closed. In addition, both switches of the half-bridge within the control circuit that are connected to the first motor terminal (U) are open. Therefore, the electromotive force (EMF) at the first motor terminal (U) is measurable as a phase voltage in this commutation interval. Φ4 fourth commutation interval. In this commutation interval, the upper switch of the half-bridge within the control circuit, which is connected to the third motor terminal (W) on one side and the upper supply voltage on the other side, is closed. At the same time, the lower switch of the half-bridge within the control circuit, which is connected to the first motor terminal (U) on one side and the lower supply voltage on the other side, is closed. In addition, both switches of the half-bridge within the control circuit that are connected to the second motor terminal (V) are open. Therefore, the electromotive force (EMF) is measurable as a phase voltage at the second motor terminal (V) in this commutation interval. Φ5 fifth commutation interval. In this commutation interval, the upper switch of the half-bridge within the control circuit, which is connected to the second motor terminal (V) on one side and the upper supply voltage on the other side, is closed. At the same time, the lower switch of the half-bridge within the control circuit, which is connected to the first motor terminal (U) on one side and the lower supply voltage on the other side, is closed. In addition, both switches of the half-bridge within the control circuit that are connected to the third motor terminal (W) are open. Therefore, the electromotive force (EMF) at the third motor terminal (W) is measurable as a phase voltage in this commutation interval. Φ6 sixth commutation interval. In this commutation interval, the upper switch of the half-bridge within the control circuit, which is connected to the second motor terminal (V) on one side and the upper supply voltage on the other side, is closed. At the same time, the lower switch of the half-bridge within the control circuit, which is connected to the third motor terminal (W) on one side and the lower supply voltage on the other side, is closed. In addition, both switches of the half-bridge within the control circuit that are connected to the first motor terminal (U) are open. Therefore, the electromotive force (EMF) can be measured as a phase voltage at the first motor terminal (U) in this commutation interval. P U first commutation interval signal. The first commutation interval signal signals the first integrator control signal generation unit (XU ), which generates the first integrator control signal (IntCtr U ) indicates which commutation interval (Φ1 to Φ6) the system is in. The first commutation interval signal is typically generated by the control block (St) or another sub-device of the system according to the invention, for example, based on the commutation signals (A1, A2, A3). It can also be a bus of these commutation signals. The signal is assigned to the first motor terminal (U). P V second commutation interval signal. The second commutation interval signal signals the second integrator control signal generation unit (X V ), which supplies the second integrator control signal (IntCtr V) indicates which commutation interval (Φ1 to Φ6) the system is in. The second commutation interval signal is typically generated by the control block (St) or another sub-device of the system according to the invention, for example, based on the commutation signals (A1, A2, A3). It can also be a bus of these commutation signals. The signal is assigned to the second motor terminal (V). P W third commutation interval signal. The third commutation interval signal signals the third integrator control signal generation unit (X W ), which provides the third integrator control signal (IntCtr W) indicates which commutation interval (Φ1 to Φ6) the system is in. The third commutation interval signal is typically generated by the control block (St) or another sub-device of the system according to the invention, for example, based on the commutation signals (A1, A2, A3). It can also be a bus of these commutation signals. The signal is assigned to the third motor terminal (W). S 1U first threshold signal. The first threshold signal is calculated by integrating the corrected voltage signal (U korr ) of the first motor connection (U) in the first integrator (Int 1U ). The signal is assigned to the first motor terminal (U). S 1V second threshold signal. The second threshold signal is obtained by integrating the corrected voltage signal (V korr ) of the second motor terminal (V) in the second integrator (Int 1V). The signal is assigned to the second motor terminal (V). S 1W third threshold signal. The third threshold signal is obtained by integrating the corrected voltage signal (W korr ) of the third motor terminal (W) in the third integrator (Int 1W ). The signal is assigned to the third motor terminal (W). S 2U first integrated sign signal. The first integrated sign signal according to the invention is obtained by integrating the first sign signal (Sig U ) of the first motor connection (U) in the fourth integrator (Int 2U ). The signal is assigned to the first motor terminal (U). S 2V second integrated sign signal. The second integrated sign signal according to the invention is obtained by integrating the second sign signal (Sig U ) of the second motor terminal (V) in the fifth integrator (Int 2V). The signal is assigned to the second motor terminal (V). S 2W third integrated sign signal. The third integrated sign signal according to the invention is obtained by integrating the third sign signal (Sig W ) of the third motor terminal (W) in the sixth integrator (Int 2W ). The signal is assigned to the third motor terminal (W). S 3U first reload value for the new inventive first default value (V U ) for the commutation of the first motor terminal (U) at the next commutation. The first reload value is transferred to the first sample-and-hold circuit (SaH U ) is loaded. The signal is assigned to the first motor terminal (U). S 3V second reload value for the new second default value according to the invention (V V) for the commutation of the second motor terminal (V) at the next commutation. The second recharge value is fed into the second sample-and-hold circuit (SaH V ) is loaded. The signal is assigned to the second motor terminal (V). S 3W third reload value for the new third default value according to the invention (V W ) for the commutation of the third motor terminal (W) at the next commutation. The third reload value is transferred to the third sample-and-hold circuit (SaH W ) is loaded. The signal is assigned to the third motor terminal (W). SaH U first sample-and-hold circuit. The first sample-and-hold circuit loads the current first reload value (S 3U ) for the new inventive first default value (V U ) for the commutation of the first motor connection (U) and outputs this as the first default value (V U) for the commutation of the first motor connection (U). The commutation time is determined by an edge of a first commutation signal (A1). The edge can be falling and / or rising depending on the implementation. The first commutation signal (A1) is a control signal for the control block (St). Preferably, it is the output signal (A1) of the fourth comparator (Cmp 2U ). This device part is assigned to the first motor connection (U). SaH V second sample-and-hold circuit. The second sample-and-hold circuit loads the current second reload value (S 3V ) for the new second default value according to the invention (V V ) for the commutation of the second motor connection (V) and outputs this as the second default value (V V) for the commutation of the second motor connection (V). The commutation time is determined by an edge of a second commutation signal (A2). The edge can be falling and / or rising depending on the implementation. The second commutation signal (A2) is a control signal for the control block (St). Preferably, it is the output signal (A1) of the fifth comparator (Cmp 2V ). This device part is assigned to the second motor connection (V). SaH W third sample-and-hold circuit. The third sample-and-hold circuit loads the current third reload value (S 3W ) for the new third default value according to the invention (V W ) for the commutation of the third motor connection (W) and outputs this as the third default value (V W) for the commutation of the third motor connection (W). The commutation time is determined by an edge of a third commutation signal (A3). The edge can be falling and / or rising depending on the implementation. The third commutation signal (A3) is a control signal for the control block (St). Preferably, it is the output signal (A3) of the sixth comparator (Cmp 2W ). This device part is assigned to the third motor connection (W). Sgn U first sign unit. The first sign unit according to the invention determines the sign of the corrected voltage signal (U korr ) of the first motor terminal (U). It outputs the first sign signal (Sig U ). This device part is assigned to the first motor connection (U). Sgn Vsecond sign unit. The second sign unit according to the invention determines the sign of the corrected voltage signal (V korr ) of the second motor terminal (V). It outputs the second sign signal (Sig V ). This part of the device is assigned to the second motor connection (V). Sgn W third sign unit. The third sign unit according to the invention determines the sign of the corrected voltage signal (W korr ) of the third motor terminal (W). It outputs the third sign signal (Sig W ). This device part is assigned to the third motor connection (W). Sign U first sign signal. The first sign signal represents the sign of the corrected voltage signal (U korr ) of the first motor connection (U). The signal is assigned to the first motor connection (U). Sign Vsecond sign signal. The second sign signal represents the sign of the corrected voltage signal (V korr ) of the second motor terminal (V). The signal is assigned to the second motor terminal (V). Sign W third sign signal. The third sign signal represents the sign of the corrected voltage signal (W korr ) of the third motor terminal (W). The signal is assigned to the third motor terminal (U). SdT marking of the figure in question as state of the art PLC virtual star point signal. The virtual star point signal is preferably the sum of the first, second and third reduced terminal signals (U r , V r , W r ) and is formed in the first summer (SU1). The signal is assigned to all motor terminals (U, V, W). SpT1 first voltage divider. The first voltage divider reduces the voltage at the first motor terminal (U) by a factor of 1 / 3 to the reduced first terminal signal (U r ). This part of the device is assigned to all motor connections (U, V, W). SpT2 second voltage divider. The second voltage divider reduces the voltage at the second motor terminal (U) by a factor of 1 / 3 to the reduced second terminal signal (V r ). This part of the device is assigned to all motor connections (U, V, W). SpT3 third voltage divider. The third voltage divider reduces the voltage at the third motor terminal (W) by a factor of 1 / 3 to the reduced third terminal signal (W r ). This part of the device is assigned to all motor connections (U, V, W). SSt System Control This is typically a finite state machine as a sequence control and / or a microprocessor with memory. The system control typically includes one or more analog-to-digital converters and, if necessary, additional sample-and-hold circuits that provide the precharge value (V0) for the sample-and-hold circuits (SaH U , SaH V , SaH W ). This precharge value (V0) can also be provided in the form of three separate precharge values ​​(V 0U , V 0V , V 0W ) are generated specifically for the respective branch (ZW1, ZW2, ZW3). In addition, the system control (SSt) evaluates the status of the respective inventive default value (V U , V V , V W ). This can be achieved, for example, by digital-to-analog conversion and evaluation of the digitized signal curve of the respective inventive default value (V U , V V , V W). If the respective inventive default value (V U , V V , V W ) between two or more than two engine revolutions by less than 25%, better less than 12%, better less than 6%, better less than 2%, better less than 1%, the system control (SSt) opens the respective switch (SW U , SW V , SW W ). However, after switching off the supply voltage, the system would maintain the respective inventive default value (V U , V V , V W ) and would have to carry out a new parameterization the next time it is switched on. It is therefore advisable if the respective inventive default value (V U , V V , V W ) is saved in a non-volatile, preferably digital memory, preferably within the system control (SSt) and is stored as a respective assigned specific preload value (V 0U , V 0V , V 0W) is used as a replacement for the general preload value (V0) when the system is restarted. The non-volatile memory takes over the respective assigned preload value (V U , V V , V W ) when opening the respective switch (SW U , SW V , SW W ) and can, for example, in the case of a non-volatile memory, also be able to determine the respective precharge value (V U , V V , V W ) about switching off the supply as the respective specific pre-charge value (V 0U , V 0V , V 0W ). This part of the device is typically assigned to all motor terminals (U, V, W). St Control block. The control block generates the signals for the three motor terminals (U, V, W) from the commutation signals A1, A2, A3. This control circuit for block commutation typically has three half-bridges (not shown). The output of a first half-bridge is connected to the first motor terminal (U). The output of a second half-bridge is connected to the second motor terminal (V). The output of a third half-bridge is connected to the third motor terminal (W). Each of the half-bridges typically has an upper switch that can connect the output of the respective half-bridge to an upper supply voltage and a lower switch that can connect the output of the respective half-bridge to a lower supply voltage.A locking circuit within the block commutation control circuit prevents simultaneous connection of the upper and lower supply voltages to the respective output of a half-bridge. Furthermore, the block commutation control circuit has a logic that can assume at least six states. These six states correspond to the six commutation intervals (Φ1 to Φ6). The control circuit changes state with a predetermined edge of a commutation signal (A1, A2, A3), which can be falling and / or rising. This can result in asynchronicity of the commutation signals (A1, A2, A3). SU1 first adder. The first adder forms the first, second and third reduced terminal signal (U r , V r , W r ) a virtual starpoint signal (VSP). This device part is typically assigned to all motor terminals (U, V, W). SU2U second summer for the first motor connection (U). The second summer for the first motor connection (U) subtracts the virtual star point signal (SpS) from the voltage signal of the first motor connection (U) and thereby forms the corrected voltage signal (U korr ) of the first motor connection (U). This device part is assigned to the first motor connection (U). SU 2V second summer for the second motor connection (V). The second summer for the second motor connection (V) subtracts the virtual star point signal (SpS) from the voltage signal of the second motor connection (V) and thereby forms the corrected voltage signal (V korr ) of the second motor connection (V). This device part is assigned to the second motor connection (V). SU 2Wsecond summer for the third motor connection (W). The second summer for the third motor connection (V) subtracts the virtual star point signal (SpS) from the voltage signal of the third motor connection (W) and thereby forms the corrected voltage signal (W korr ) of the third motor connection (W). This device part is assigned to the third motor connection (W). SU 3U third summer for the first motor connection (U). The third summer for the first motor connection (U) adds the first integrated sign signal (S 2U ) and the first default value according to the invention (V U ) for the commutation of the first motor connection (U) to the first recharge value (S 3U ) for the new inventive first default value (V U ) for the commutation of the first motor terminal (U) during the next commutation. This device part is assigned to the first motor terminal (U). SU 3Vthird summer for the second motor connection (V). The third summer for the second motor connection (V) adds the second integrated sign signal (S 2V ) and the second default value according to the invention (V V ) for the commutation of the second motor connection (V) to the second recharge value (S 3V ) for the new second default value according to the invention (V V ) for the commutation of the second motor terminal (V) during the next commutation. This device part is assigned to the second motor terminal (V). SU 3W third summer for the third motor connection (W). The third summer for the third motor connection (W) adds the third integrated sign signal (S 2W ) and the third default value according to the invention (V W ) for the commutation of the third motor connection (W) to the third recharge value (S 3W ) for the new third default value according to the invention (V W) for the commutation of the third motor terminal (W) during the next commutation. This device part is assigned to the third motor terminal (W). SW U first switch. The first switch separates the first commutation signal (A1) from the trigger input of the first sample-and-hold circuit (SaH U ). Preferably, it sets the trigger input of the first sample-and-hold circuit (SaH U ) to a defined potential such that it no longer accepts any further values ​​depending on the first commutation signal (A1). This device part is assigned to the first motor terminal (U). SW V second switch. The second switch separates the second commutation signal (A2) from the trigger input of the second sample-and-hold circuit (SaH V ). Preferably, it sets the trigger input of the second sample-and-hold circuit (SaH V) to a defined potential such that it no longer accepts any further values ​​depending on the second commutation signal (A2). This device part is assigned to the second motor terminal (V). SW W Third switch. The third switch separates the third commutation signal (A3) from the trigger input of the third sample-and-hold circuit (SaH W ). Preferably, it sets the trigger input of the third sample-and-hold circuit (SaH W ) to a defined potential such that it no longer accepts any further values ​​depending on the third commutation signal (A3). This device part is assigned to the third motor terminal (W). U first motor connection of the example BLDC motor U rReduced first terminal signal. The voltage level is preferably 1 / 3 lower than the voltage at the first motor terminal (U). The signal is assigned to the first motor terminal (U). U korr corrected voltage signal (U korr ) of the first motor terminal (U). The corrected voltage signal (U korr ) of the first motor connection (U) is added to the corresponding second summator (SU 2U ) is generated by subtracting the virtual starpoint signal (SpS) from the voltage signal of the first motor terminal (U). The signal is assigned to the first motor terminal (U). U' korr limited corrected voltage signal (U' korr ) of the first motor connection (U). The signal is assigned to the first motor connection (U). V second motor connection of the exemplary BLDC motor V0 Precharge value for the sample and hold circuits (SaH U , SaH V , SaH W). This is the initialization value for the first, second and third preset values ​​(V U , V V , V W ). In order for the very first commutation to succeed, an initial value for the first, second and third default value (V U , V V , V W ) with which the respective commutation signal (A1, A2, A3) can be generated at the beginning as the starting value for the control. This initial value can be set quite roughly and only ensures that the process can start at all. The value itself is not entirely motor-independent, but can be selected so that it can be used unchanged for a very wide range of motors. The signal is typically assigned to all motor terminals (U, V, W). V 0U First precharge value. The signal is assigned to the first motor terminal (U). V 0VSecond precharge value. The signal is assigned to the second motor terminal (V). V 0W Third precharge value. The signal is assigned to the third motor terminal (W). V r Reduced second terminal signal. The voltage level is preferably 1 / 3 lower than the voltage at the second motor terminal (V). The signal is assigned to the second motor terminal (V). V refU The first default value for commutation is experimentally optimized according to the state of the art. The signal is assigned to the first motor terminal (U). V refV Second default value for commutation, experimentally optimized according to the state of the art. The signal is assigned to the second motor terminal (V). V refW The third preset value for commutation is experimentally optimized according to the state of the art. The signal is assigned to the third motor terminal (W). V UDetermined first default value for the commutation of the first motor connection (U). The signal is assigned to the first motor connection (U). V V Determined second default value for the commutation of the second motor connection (V). The signal is assigned to the second motor connection (V). V W Determined third preset value for the commutation of the third motor connection (W). The signal is assigned to the third motor connection (W). V korr corrected voltage signal (V korr ) of the second motor terminal (V). The corrected voltage signal (V korr ) of the second motor terminal (V) is added to the associated second summator (SU 2V ) is generated by subtracting the virtual starpoint signal (SpS) from the voltage signal of the second motor terminal (V). The signal is assigned to the second motor terminal (V). V' korr limited corrected voltage signal (V' korr) of the second motor terminal (V). The signal is assigned to the second motor terminal (V). W third motor connection of the exemplary BLDC motor W r Reduced third terminal signal. The voltage level is preferably 1 / 3 lower than the voltage at the third motor terminal (W). The signal is assigned to the third motor terminal (W). W korr corrected voltage signal (W korr ) of the third motor terminal (W). The corrected voltage signal (W korr ) of the third motor terminal (W) is added to the corresponding second summing element (SU 2W ) is generated by subtracting the virtual starpoint signal (SpS) from the voltage signal of the third motor terminal (W). The signal is assigned to the third motor terminal (W). W' korr limited corrected voltage signal (W' korr ) of the third motor terminal (W). The signal is assigned to the third motor terminal (W). X U first integrator control signal generating unit. The first integrator control signal generating unit generates, based on the first commutation interval signal (P U ) and the first sign signal (Sig U ) the first integrator control signal (IntCtr U ). This device part is assigned to the first motor connection (U). X V second integrator control signal generating unit. The second integrator control signal generating unit generates, based on the second commutation interval signal (P V ) and the second sign signal (Sig V ) the second integrator control signal (IntCtr V ). This device part is assigned to the second motor connection (V). X W third integrator control signal generation unit. The third integrator control signal generation unit generates, based on the third commutation interval signal (P W) and the third sign signal (Sig W ) the third integrator control signal (IntCtr W ). This device part is assigned to the third motor connection (W). ZW1: First branch within the EMF evaluation (EMKA) for generating the first commutation signal (A1) from the EMF at the first motor terminal (U) during the third commutation interval (Φ3) and during the sixth commutation interval (Φ6). This device part is assigned to the first motor terminal (U). ZW2: second branch within the EMF evaluation (EMKA) for generating the second commutation signal (A2) from the EMF at the second motor terminal (V) during the first commutation interval (Φ1) and during the fourth commutation interval (Φ4). This device part is assigned to the second motor terminal (V). ZW3: Third branch within the EMF evaluation (EMKA) for generating the third commutation signal (A3) from the EMF at the third motor terminal (W) during the second commutation interval (Φ2) and during the fifth commutation interval (Φ5). This device part is assigned to the third motor terminal (W).

Claims

[1] Procedure for determining the first target value to be determined (V U ) for controlling the commutation time for controlling the stator coils of a BLDC motor via at least one first motor connection (U), characterized by , a. generating an assigned, corrected voltage signal (U korrU ) b. continuous and / or sampling-summing integration and / or filtering of this corrected voltage signal (U korrU ) by a subsequent fourth integrator (Int 2U ) for generating an associated first integrated sign signal (S 2U ), c. optional multiplying the associated first integrated sign signal (S 2U) at a point in the signal path before its output by the fourth integrator (Int 2U ) but at least before a third summator (SU 3U ) for the first motor connection (U) with a first constant factor (F U ) in particular by one or more sub-devices of the fourth integrator (Int 2U ), d. continuous and / or sampling-summing integration and / or filtering of an assigned, corrected voltage signal (U korrU ) by a subsequent first integrator (Int 1U ) for generating an associated first threshold signal (S 1U ), e. Comparison of the assigned first threshold signal (S 1U ) with a determined first default value (V U) by an associated additional fourth comparator (CMP 2U ), f. Formation of an associated first commutation signal (A1), depending on the comparison result of the associated additional fourth comparator (CMP 2U ), g. Changing the commutation time of the assigned output of the control block (St) connected to the assigned first motor terminal (U) as a function of the assigned first commutation signal (A1), h. Addition of the assigned determined first default value (V U ) with the associated first integrated sign signal (S 2U ) by an associated second summer (SU 2U ) for the first motor connection (U), i. Formation of an assigned first reload value (S 3U ) depending on the result of the addition of the assigned determined first default value (V U) with the associated first integrated sign signal (S 2U ) by an associated second summer (SU 2U , SU 2V , SU 2W ) for the first motor connection (U), j. Saving the assigned first reload value (S 3U ) in an associated memory for this value, in particular in an associated first sample-and-hold circuit (SaH U ), at least temporarily in dependence on the associated first commutation signal (A1), k. Generation of the assigned first default value (V U ) depending on the current memory value of the assigned first reload value (S3 U ) in the assigned memory for the assigned first reload value (S3 U ), in particular in the associated first sample-and-hold circuit (SaH U ). [2] Method according to the preceding claim, comprising the steps a. Connecting the associated first commutation signal (A1), in particular by means of an associated first switch (SW U ), in such a way that the storage of the assigned first reload value (S 3U ) in an associated memory for this value, in particular an associated first sample-and-hold circuit (SaH U ), depending on the associated first commutation signal (A1), b. Saving the assigned first preset value (V U ) in an associated non-volatile memory for this associated first default value (V U ), in particular in a memory in a system control (SSt), c. Separating the associated first commutation signal (A1), in particular by opening an associated first switch (SW U ), from the allocated memory for the allocated first reload value (S 3U) in such a way that the storing of the stored assigned first default value (V U ) based on the assigned first recharge value (S 3U ) or the assigned first precharge value (V 0U ) or another precharge value (V0) in this associated memory during this separation is NOT dependent on the associated first commutation signal (A1). [3] Method according to one or more of the two preceding claims, comprising the steps a. Disconnecting the associated first commutation signal (A1), in particular by opening an associated first switch (SW U ), from the allocated memory for the allocated first reload value (S 3U ) in such a way that the storing of the stored assigned first default value (V U ) based on the assigned first recharge value (S 3U ) or the assigned first precharge value (V 0U) or another precharge value (V0) in this associated memory during this separation is NOT dependent on the associated first commutation signal (A1), a. Output of the assigned first default value (V) previously stored in an assigned non-volatile memory, in particular in a system control (SSt). U ) as the new assigned first precharge value (V 0U ) for future commutation intervals (Φ1 to Φ6), b. Saving the assigned first precharge value (V 0U ) instead of the assigned first reload value (S3 U ) in the assigned memory for the assigned first reload value (S 3U ), in particular in the associated first sample-and-hold circuit (SaH U ), for at least one commutation interval (Φ1 to Φ6), c. optionally connecting the associated first commutation signal (A1), in particular by means of the associated first switch (SWU ), in such a way that the storage of the assigned first reload value (S 3U ) in an associated memory for this value, in particular an associated first sample-and-hold circuit (SaH U ), depending on the associated first commutation signal (A1). [4] Method according to one or more of the three preceding claims, comprising the steps a. Disconnecting the associated first commutation signal (A1), in particular by opening an associated first switch (SW U ), from the allocated memory for the allocated first reload value (S 3U ) in such a way that the storing of the stored assigned first default value (V U ) based on the assigned first recharge value (S3 U ) or the assigned precharge value (V 0U) or another precharge value (V0) in this associated memory during this separation is NOT dependent on the associated first commutation signal (A1), b. Output of the default value (V0) previously stored or otherwise made available in an assigned non-volatile memory, in particular in a system control (SSt), as the newly assigned first preload value (V 0U ) for future commutation intervals (Φ1 to Φ6), c. Saving the assigned first precharge value (V 0U ) instead of the assigned first reload value (S 3U ) in the assigned memory for the assigned first reload value (S3 U ), in particular in the associated first sample-and-hold circuit (SaH U ), for at least one commutation interval (Φ1 to Φ6), d. Connecting the associated first commutation signal (A1), in particular by means of the associated first switch (SWU ), in such a way that the storage of the assigned first reload value (S 3U ) in an associated memory for this value, in particular an associated first sample-and-hold circuit (SaH U ), depending on the associated first commutation signal (A1). [5] Method according to one or more of the four preceding claims, additionally characterized in that a. that the continuous and / or sampling-summing integration and / or the filtering of an assigned, corrected voltage signal (U korrU ) by a subsequent first integrator (Int 1U ) for generating an associated first threshold signal (S 1U) in such a way that only one polarity of the respective corrected voltage signal (U korrU ) the value of the respective assigned first threshold signal (S 1U ) influenced. [6] Device for determining a first preset value (V U ) and for controlling the commutation time for controlling the stator coils of a BLDC motor via at least one first motor connection (U), characterized by , a. an associated fourth integrator (Int 2U ) for the continuous or continuously sampling integration and / or filtering of an associated, corrected voltage signal (U korrU ) during a commutation interval (Φ3, Φ6), in which this first motor terminal (U) is not supplied with current by a control block (St), for generating an associated first integrated sign signal (S 2U ) and b. an associated, subsequent first integrator (Int 1U ) for the continuous and / or sampling-summing integration and / or filtering of an assigned, corrected voltage signal (U korrU ) for generating an associated first threshold signal (S 1U ), and c. an associated fourth comparator (CMP 2U ) for comparing the associated first threshold signal (S 1U ) with a determined first default value (V U ),and d. a device for forming an associated first commutation signal (A1), depending on the comparison result of the associated fourth comparator (CMP 2U), wherein the commutation time of an associated output of a control block (St) connected to the associated first motor terminal (U) depends on the associated first commutation signal (A1), and e. an associated second summer (SU 2U ) for the first motor connection (U) for adding the assigned determined first preset value (V U ) with the associated first integrated sign signal (S 2U ) and f. a device for forming an associated first recharge value (S 3U ) depending on the result of the addition of the assigned determined first default value (V U ) with the associated first integrated sign signal (S 2U ) by an associated second summer (SU 2U ) for the first motor connection (U) and g. an associated memory for this value, in particular an associated first sample and hold circuit (SaHU ), to save the assigned first reload value (S 3U ) at least temporarily in dependence on the associated first commutation signal (A1) and h. a device for generating the associated determined first default value (V U ) depending on the current memory value of the assigned first reload value (S 3U ) in the assigned memory for the assigned first reload value (S3 U ), in particular in the associated first sample-and-hold circuit (SaH U ). [7] Device according to the preceding claim, characterized additionally by a. a first sign unit (Sgn) assigned to the first motor terminal (U) U ) used to generate an associated first sign signal (Sig U) during a commutation interval (Φ3, Φ6), in which this first motor terminal (U) is not supplied with current by a control block (St), continuously or continuously scanning the sign of an associated, corrected voltage signal (U korrU ) and b. where the associated fourth integrator (Int 2U ) instead of the assigned, corrected voltage signal (U korrU ) for generating an associated first integrated sign signal (S 2U ) the associated first sign signal (Sig U ) integrates and / or filters. [8] Device according to one or more of the two preceding claims, characterized additionally by a. an associated first switch (SW U), for connecting the associated first commutation signal (A1) in such a way that the storage of the associated first recharge value (S 3U ) in an associated memory for this value, in particular an associated first sample-and-hold circuit (SaH U ), depending on the associated first commutation signal (A1), when the first switch (SW U ) is in a first state, in particular closed, and that the storage of the associated first recharge value (S 3U ) in an associated memory for this value, in particular an associated first sample-and-hold circuit (SaH U ), does NOT depend on the assigned first commutation signal (A1) if the first switch (SW U ) is in a second state, in particular open. [9] Device according to one or more of the three preceding claims, characterized additionally by a. an assigned, in particular non-volatile, memory for the assigned first default value (V U ), which can in particular be a memory in a system control (SSt). [10] Device according to one or more of the four preceding claims, additionally characterized by a. that by using the allocated memory for the allocated first reload value (S 3U ) next to the assigned first reload value (S 3U ) at least one further value can be stored as a substitute, wherein this further value is an assigned first preload value (V 0U ) and / or another precharge value (V0). [11] Device according to one or more of the five preceding claims, characterized in that a. that the output of the associated fourth comparator (CMP 2U ) has a hysteresis. [12] Device according to one or more of the six preceding claims, characterized in that a. that the device is a sub-device (X U , B U ,) which ensures that the continuous and / or sampling-summing integration and / or the filtering of an associated, corrected voltage signal (U korrU ) by a subsequent first integrator (Int 1U ) for generating an associated first threshold signal (S 1U ) in such a way that only one polarity of the respective corrected voltage signal (U korrU ) the value of the respective assigned first threshold signal (S 1U ) influenced.

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