Chip protective casing and arrangement with a chip protective casing

Abstract

Chip protective encapsulation comprising: a first dielectric layer (50) comprising at least one organic component having a decomposition temperature of at least 180 °C; a semiconductor chip (52) embedded in the first dielectric layer (50), wherein the semiconductor chip (52) has a first surface and a thickness t1; a second dielectric layer (64) arranged on a first surface of the first dielectric layer (50), wherein the second dielectric layer (64) has two sublayers (65, 66); a first conductive layer arranged on the first surface of the semiconductor chip (52) and electrically coupled to the semiconductor chip (52), wherein the first conductive layer has a thickness t2, where t2 ≥ t1 / 3, and wherein the first conductive layer (92) forms a first contact pad;a third dielectric layer (64) arranged on a second surface of the first dielectric layer (50), the second surface being opposite the first surface of the first dielectric layer (50); and a second conductive layer arranged on a second surface of the semiconductor chip (52) and electrically coupled to the semiconductor chip (52), wherein the second surface faces the first surface of the semiconductor chip (52), wherein the second conductive layer has a thickness t3, where t3 ≥ t1 / 3, and wherein the second conductive layer forms a second contact pad, wherein the semiconductor chip (52) is arranged in an opening (51) of the first dielectric layer (50), wherein a gap (59) is formed between side faces (60) of the opening (51) and side faces (61) of the semiconductor chip (52), and wherein the second and third dielectric layers (64) extend into the gap (59).

Description

BackgroundAn electronic component may include one or more semiconductor devices in a chip package. The chip package contains internal electrical connections from the semiconductor device to a substrate or lead frame containing / external contacts. The external contacts are used to mount the electronic component on a redistribution board such as a printed circuit board. The chip package may include a package covering the semiconductor device and the internal electrical connections. The housing may comprise a plastic material such as epoxy and may be manufactured by a molding process such as injection molding.Instead of mounting a package containing one or more semiconductor devices on an outer surface of a printed circuit board (PCB), the semiconductor device may be embedded in the printed circuit board itself. A circuit board may comprise one or more dielectric layers, such as fiberglass cloth, impregnated with a polymer, such as epoxy, and one or more patterned conductive layers, such as copper foil, providing a conductive redistribution structure. A semiconductor device may be embedded in the circuit board by laminating one or more layers of the circuit board to opposite sides of the semiconductor device. The electrical connections between the semiconductor device and the redistribution structure of the circuit board may be provided by inserting vias through the dielectric layers of the circuit board to expose a contact region of the semiconductor device and by inserting conductive material into the via.CN 102270622 A describes an arrangement having a semiconductor chip which is embedded in a printed circuit board and which is contacted by metal layers which are arranged on an upper side and a lower side of the printed circuit board.US 2014 / 0327071 A1 describes a method in which a semiconductor chip is embedded in an encapsulation layer, such as an epoxy resin layer, for example, and in which regions of the semiconductor chip are subsequently removed starting from one of its surfaces selectively with respect to the encapsulation layer.CN 101039552 A describes an arrangement having a semiconductor chip embedded in a core layer which has a plurality of insulating layers.US 2015 / 0259194 A1 describes an arrangement having two printed circuit boards, in each of which a semiconductor chip is embedded and which are arranged one above the other and are electrically connected to one another via contacts.Reliable embedding of semiconductor components in a printed circuit board is desirable.OverviewAn embodiment of the invention relates to a chip protective cladding according to claim 1. A further embodiment relates to an arrangement according to claim 18 with such a chip protective cladding.Brief Description of the DrawingsThe elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined as long as they are not mutually exclusive. Embodiments are depicted in the drawings and are illustrated in detail in the following description. FIG. 1 shows a chip protection package according to an example for explanation. FIG. 2 shows a chip protective cladding according to a further example for explanation. FIG. 3 ashows a perspective top view of a core layer of a chip protection cladding. FIG. 3 b shows a cross-sectional view of the core layer of the chip protection cladding. FIG. 4 ashows a perspective top view of a semiconductor chip inserted into an opening in the core layer of the chip protective cladding. FIG. 4 b illustrates a cross-sectional view of the semiconductor chip into which the opening of the core layer of the chip protective cladding is inserted. FIG. 5 ashows a perspective top view of a dielectric layer applied to the semiconductor chip and the core layer. FIG. 5 bshows a perspective bottom view of the dielectric layer applied to the semiconductor chip and the core layer. FIG. 5 cshows a cross-sectional view of the dielectric layer applied to the semiconductor chip and the core layer. FIG. 6 ashows a perspective top view of a first conductive layer applied to the semiconductor chip. FIG. 6 bshows a perspective bottom view of the first conductive layer applied to the semiconductor chip. FIG. 6 cshows a cross-sectional view of the first conductive layer applied to the semiconductor chip. FIG. 7 ashows a perspective top view of a second conductive layer applied to the semiconductor chip and the dielectric layer. FIG. 7 b illustrates a bottom perspective view of the second conductive layer deposited on the semiconductor chip and the dielectric layer. FIG. 7 cshows a cross-sectional view of the second conductive layer applied to the semiconductor chip and the dielectric layer. FIG. 7 d shows a partial cross-sectional view of FIG. 7 c illustrating thicknesses of the semiconductor chip, the dielectric layers and the conductive layers. FIG. 8 ashows a perspective top view of a singulated chip protection package. FIG. 8 b shows a bottom perspective view of a singulated chip protection wrap. FIG. 9 shows a cross-sectional view of a chip protection package according to an embodiment. FIG. 10 shows a cross-sectional view of a chip protection package embedded in a circuit board according to an embodiment.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "leading", "following", etc. is used with reference to the orientation of the figure(s) being / are described. Because components of the embodiments may be positioned in a number of different orientations, directional terminology is used for purposes of illustration and is in no way limiting.Embodiments will be explained below. In this case, identical structural features are denoted by identical or similar reference symbols in the figures. In the context of the present description, "lateral" or "lateral direction" shall be understood to mean a direction or extension that is generally parallel to the lateral extension of a semiconductor material or a semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is to be understood to mean a direction that is generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.As used in this specification, the terms "coupled" and / or "electrically coupled" are not intended to mean that the elements must be directly coupled to one another-intermediate elements may be provided between the "coupled" or "electrically coupled" elements.As used in this specification, when an element such as a layer, region or substrate is referred to as extending "on" or "on" another element, an element may be directly on the other element or may extend directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as extending "directly on" or "directly on" another element, there are no intervening elements present. As used in this specification, an element, when referred to as being "connected" or "coupled" to another element, may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.FIG. 1 shows a chip protective cladding 20 according to an example for explanation. The chip protection package 20 includes a first dielectric layer 21, a semiconductor chip 22, a second dielectric layer 23, and a conductive layer 24. The second dielectric layer 23 is disposed on a first surface 25 of the first dielectric layer 21, and the conductive layer 24 is disposed on and electrically coupled to the semiconductor chip 22.The semiconductor chip 22 has a thickness t 1 and the conductive layer 24 has a thickness t 2. The ratio of the thickness of the conductive layer t 2 to the thickness of the semiconductor chip t 1 may be at least one third, or in an alternative nomenclature t 2 ≥ t 1 / 3.The conductive layer 24 is also disposed on the second dielectric layer 23 and may have a thickness of at least 5 μm in regions positioned on the second dielectric layer 21. The conductive layer 24 may include a metal such as copper or an alloy.The semiconductor chip 22 may have a thickness t 1 that is in the range of 40 μm to 100 μm. Semiconductor chips of such thickness may benefit from the additional mechanical support provided by the first dielectric layer 21, the second dielectric layer 23, and the conductive layer 24 of the chip protective cladding during handling, for example during transport and / or during embedding within a higher level printed circuit board. During embedding in a circuit board, the device to be embedded may be exposed to heat and pressure if circuit board fabrication techniques are used. The chip protection package 20 provides protection for the semiconductor chip 22 during this process.The conductive layer 24 may have a thickness in the range of 15 μm to 70 μm above at least a portion of the semiconductor chip, provided that t 2 ≥ t 1 / 3. This conductive layer thickness is relatively large and can be used to provide a robust electrical connection to the semiconductor chip 22 during subsequent handling, such as the electrical connection between the conductive layer 24 and the redistribution structure of a higher level circuit board in which the chip protection wrap 20 is embedded.The ratio of the side surface of the semiconductor chip 22 to the side surface of the chip protective cladding 20 may be within the range of 1:1.05 to 1:1.25.The side surface of the semiconductor chips 22 and the chip protective cladding 20 is the area of their respective larger surface. For example, if the semiconductor chip 22 has a length l s, a width b s and a thickness t 1 it has a side surface a s= ( l s x b s). If the chip protective cladding 20 has a length l e, a width b e and a thickness t e it has a side surface a e= ( l e x b e) such that 105% ≤ a e / a s ≤ 125%.The side surface a e of the chip protective cladding 20 is between 5% and 25% larger than the side surface a s of the semiconductor chip 22, so that the enlargement of the side surface of the chip protective cladding 20 compared to the semiconductor chip 22 is limited to between 5% larger and 25% larger than that of the semiconductor chip 22. This is useful for reducing the space required by the chip protective cladding 20 when embedded in a higher level circuit board. The smaller side surface and thickness of the chip protection wrap 20 compared to a fully packaged semiconductor chip, such as a semiconductor chip in a chip package conforming to the JEDEC (Joint Electron Device Engineering Council) standard, may be used to reduce space and volume requirements within an application while providing protection of the semiconductor chip 22 during handling and during the embedding process.The semiconductor chip 22 may include power device such as a power transistor device. The semiconductor chip 22 may include a vertical device, i.e. a device having a vertical drift path including at least one electrode on two opposing main surfaces. The vertical device may be a vertical power transistor device such as a MOSFET (metal oxide semiconductor field effect transistor) or IGBT (insulated gate bipolar transistor) or a diode.The semiconductor chip 22 may include, for example, a silicon-based or a group III nitride-based semiconductor device.The chip protection wrap 20 may provide a type of prepackaging the semiconductor chip 22, which facilitates embedding the semiconductor chip 22 within a circuit board. For example, the first dielectric layer 21 and the second dielectric layer 23 provide edge protection for the semiconductor chip 22, so that handling by a pick-and-place machine is simplified.The first dielectric layer 21 in which the semiconductor chip 22 is embedded may provide a core layer or a support layer in contact with at least the side surfaces 26 of the semiconductor chip 22. The back surface 27 of the semiconductor chip 22 may be disposed within the material of the first dielectric layer 21 and covered by the material. The first dielectric layer 21 may include at least one organic component that includes a decomposition temperature of at least 180° C. or at least 220° C. By having a decomposition temperature of at least 180° C., the first dielectric layer 21 remains mechanically and chemically stable during subsequent processing, for example during application of the second dielectric layer 23 and the conductive layer 24 to the first dielectric layer 21. The first dielectric layer 21 and the second dielectric layer 23 may include a polymer. The second dielectric layer 23 is arranged on the first surface 25 of the first dielectric layer 21 and may extend from the first dielectric layer 21 onto the semiconductor chip 22. The second dielectric layer 23 may be used to attach the semiconductor chip 22 within the dielectric core layer 21, or may be used in combination with the first dielectric layer 21 to protect the semiconductor chip 22 from external mechanical, chemical or environmental causes. The second dielectric layer 23 may include a photo-structurable polymer composition, thus allowing the second dielectric layer 23 to be patterned using photo-imaging techniques.At least the outermost surface of the second dielectric layer 23 may include an epoxy-based composite material. The epoxy-based composite material may include an epoxy-based resin matrix and a filler such as fibers or particles to increase the mechanical strength of the epoxy resin. An epoxy-based composite may be used at the outermost surface to increase adhesion between the second dielectric layer 23 and the overlying conductive layer 24.The second dielectric layer 23 may be patterned to provide recesses 28 in which regions 29 of the semiconductor chip 22 are exposed. An electrode of the semiconductor chip 22 or a contact pad coupled to an electrode positioned within or on the semiconductor body of the semiconductor chip 22 may form the base of a recess 28.Conductive material or portions of the conductive layer 24 may be inserted into the recesses 28 and disposed on portions of the second dielectric layer 23 to electrically couple the semiconductor chip 22 to the conductive layer 24 disposed on top of the second dielectric layer 23. The semiconductor chip 22 may be fully encapsulated by a combination of the first dielectric layer 21, the second dielectric layer 23, and the conductive layer 24 providing a protection structure for the semiconductor chip 22.The second dielectric layer 23 may have a thickness of 5 μm to 20 μm. The conductive layer 24 may have a thickness of 5 μm to 70 μm on regions positioned on the second dielectric layer. The second dielectric layer 23 and the conductive layer 24 provide an increased thickness of the dielectric material and conductive material, respectively, above the semiconductor material of the semiconductor chip 22. As a result, the surface of the semiconductor chip 22 is provided with additional protection compared to the bare semiconductor chip 22.The second dielectric layer 23 in combination with the conductive layer 24 increases the thickness of the conductive material disposed on top of the semiconductor chip 22. The thickness of the conductive layer 24 in regions disposed on the semiconductor chip 22 may be greater than the thickness of the conductive layer 24 in regions disposed on the second dielectric layer 23, because a portion of the conductive layer 24 is disposed in a recess 28 of the second dielectric layer 23 having a base formed by the semiconductor chip 22. Above the semiconductor chip 22, the conductive layer 24 may have a thickness corresponding to the sum of the thickness of the second dielectric layer 23 and the thickness of the conductive layer 24 in regions near the semiconductor chip 22. This increased thickness may be used to facilitate the electrical connection between the conductive layer 24 and the redistribution structure of the circuit board.The conductive layer 24 may have a thickness of about 5 μm to 70 μm or 10 μm to 50 μm in regions on the second dielectric layer 23. in regions on the semiconductor chip 22, the conductive layer 34 may have a total thickness of 10 μm to 90 μm or 15 μm to 70 μm if the second dielectric layer has a thickness of 5 μm to 20 μm. The thickness of the metallization provided on the semiconductor chip may be 5 μm or less. As a result, if a portion of the conductive layer 24 provides a base of a via inserted into the layer of the circuit board laminated to the conductive layer 24, a portion of the conductive material of the conductive layer 24 remains even if a portion of the conductive material 24 is removed by inserting the via and any subsequent cleaning operations. This remaining portion of the conductive layer 24 may be more easily and easily coupled to the conductive material inserted into the via to electrically couple the semiconductor chip 22 to the circuit board within the chip protection enclosure 20.The first dielectric layer 21, the second dielectric layer 23 and the conductive layer 24 may have a lateral extension that is larger than the lateral extension of the semiconductor chip 22. the chip protection enclosure 20 provides a so-called fan-out arrangement such that peripheral surfaces of the conductive layer 24 are laterally arranged adjacent to the semiconductor chip 22 and may have a larger size or distance than the contact pad or pads directly arranged on the semiconductor chip 22.The dimensions of the chip protection wrap 20 may also be selected to provide one or more predetermined thicknesses for the wrap 20. For example, it may be desirable for the cladding to have a total thickness corresponding to a thickness of a prepreg layer of a printed circuit board. However, depending on the type of device provided by the semiconductor chip 22, the semiconductor chip 22 may have different thicknesses. Therefore, semiconductor chips of different thickness may be provided within a cladding 20 having a standard thickness corresponding to that of the prepreg layer of a printed circuit board. As a result, semiconductor chips with differing thicknesses can be more easily embedded within a common layer of the circuit board, as they are provided in the form of a cladding 20 having a standardized thickness corresponding to the thickness of the prepreg layer.The casing 20 can be provided with a / r predetermined casing contour or casing base surface. Two or more predetermined casing contours and / or casing bases may be provided to form a set of casing standards. The envelope contour may have a predetermined lateral size and shape. The enclosure base surface may have a predetermined number, size, and distribution of contact pads. This may be used to facilitate embedding different semiconductor chips within a circuit board if the semiconductor chip is provided in a chip protection enclosure 20 having a / n predetermined / n enclosure contour and / or enclosure footprint.The chip protection package 20 may also facilitate testing the semiconductor chip 22 before the chip protection package including the semiconductor chip 22 is embedded within a circuit board, as the chip protection package 20 may include contact pads with a larger side surface than the contact pads of the semiconductor metallization.The first dielectric layer 21 contains an organic component having a decomposition temperature of at least 180° C., or at least 220° C. The decomposition temperature may be within the range of 180° C. and 300° C., and more specifically, may be within the range of 220° C. to 300° C.An organic component is a carbon-containing component that is predominantly covalently bonded. The decomposition temperature is the temperature at which the organic component starts to chemically decompose. As a result, the organic component can be considered to be chemically stable at temperatures below the decomposition temperature.The first dielectric layer 21 may include a curable dielectric material that is substantially fully cured before the second dielectric layer 23 is deposited. For example, the first dielectric layer may include a thermosetting polymer such as an epoxy resin that is substantially fully cured prior to application of the second dielectric layer 23.The first dielectric layer 21 may contain a photostructureable polymer composition. The first dielectric layer 21 may be a photostructureable polymer composition that is sufficiently cured so that the first dielectric layer 21 does not undergo a substantial curing process upon exposure to light. As a result, the first dielectric layer 21 remains chemically and mechanically stable during the deposition and photopatterning of the second dielectric layer 23. The first dielectric layer 21 may comprise a photopatternable polyimide composition. The second dielectric layer 23 may also comprise a photopatternable polymer composition containing polyimide.A photostructureable polymer composition comprises a polymer that changes its structure when exposed to light, for example light in the ultraviolet or visible region of the electromagnetic spectrum. A photostructureable polymer composition may be referred to as photosensitive. The structural change results in curing of the photostructureable polymer composition when exposed to this light as a result of cross-linking between polymer chains or polymerization of the photostructureable polymer composition. Dielectric layers comprising a photostructureable polymer composition may contain, in the uncured state, a mixture of monomers, oligomers and photoinitiators, which, after light exposure, are brought into a form of a cured polymeric material. The dielectric layers containing a photopatternable polymer composition undergo photoinduced polymerization to at least partially cure or cure the dielectric layer.Some dielectric layers having a photostructureable polymer composition, such as dielectric layers containing an epoxy resin, may be subjected to thermal treatment for curing in addition to a partial curing treatment carried out by light exposure. Some dielectric layers, such as dielectric layers comprising acrylate-based polymers, may be substantially fully cured using photo-induced polymerization only.The first dielectric layer 21 may be prefabricated with one or more openings for the semiconductor chips and may be considered as a core. The core may also act as a spacer that is the same or similar in thickness to the thickness of the chip.The first dielectric layer 21 may be in a partially cured state at this stage in the manufacturing process, so that some cross-linking between the first dielectric layer 21 and the second dielectric layer 23 may be achieved. Methods for producing an uncured or partially cured layer include resins that have high viscosity or are solid at room temperature, B-staging (thermal) or polyimide material with a photoreactive amide type (or other type) included, and a polyimide system that has not been brought to a fully cured state.When the opening extends through the entire thickness of the first dielectric layer 21, the first dielectric layer 21 may be mounted on a carrier, such as a thermal release or UV release tape, to allow the chips to be placed and held in the openings.With the semiconductor die 22 in the openings and supported on the carrier, the first layer of photo patternable polymer polyimide is deposited on the first surface of the package and dried to form the first dielectric layer 23. The material is exposed and developed and then the assembly is removed from the carrier tape.If the opening extends through the entire thickness of the first dielectric layer 21, this process may be repeated on the opposite side. The entire assembly is thermally cured and may or may not be cured until complete reaction. If the cure is not complete, some polymerization may occur with the following organic layers, which may aid adhesion.The chip protection package 20 may include a third dielectric layer disposed on the second dielectric layer 23. The third dielectric layer is disposed between the second dielectric layer 23 and the conductive layer 24.In examples that include two or more dielectric layers disposed on the semiconductor chip 22 and the first dielectric layer 21, different compositions may be used to provide each of the dielectric layers with different properties. For example, the second dielectric layer 23 directly disposed on the first dielectric layer 21 and the semiconductor chip 22 may have a composition selected to provide moisture protection for the semiconductor chip 22. For example, the second dielectric layer 23 may include a photo patternable polyimide. The third dielectric layer may be positioned on the second dielectric layer 23, and may include a polymer such as an epoxy resin that provides better adhesion to a conductive layer such as copper than the material of the second dielectric layer 23.The second dielectric layer and the third dielectric layer may comprise a photostructureable polymer or a photostructureable polymer composition. The photostructureable polymer may be the same or different in the second dielectric layer and the third dielectric layer. If both deposited dielectric layers comprise a photo-structurable polymer, a single patterning step may be used to provide the recesses 28 exposing portions of the semiconductor die 22 and / or the conductive step 24 disposed on the first surface of the first dielectric layer 21.The composition of the first dielectric layer 21 may also be chosen to provide specific properties. For example, the first dielectric layer 21 may include a composite material including a filler and a matrix. The filler may be a glass fibre network and the matrix may comprise an epoxy resin. If it is desired that the first dielectric layer 21 has good mechanical integrity, a composite material may be used.The filler may be used to adjust the flow properties of the layer before curing or curing, to adjust the coefficient of thermal expansion (CTE), or the heat resistance of the substrate. The filler may also increase the mechanical strength of the composite. The filler may be in the form of a plurality of fibers, such as glass fibers or carbon fibers, which may be crosslinked and impregnated with a dielectric material such as a polymer. The filler is not limited to fibers, but may have other shapes. For example, the filler may include a plurality of particles having a substantially spherical shape.The first dielectric layer 21 may be provided by a layer of so-called prepreg including crosslinked glass fibers impregnated with partially cured or B-stage resin or crosslinked glass fibers impregnated with fully cured resin. The resin may be an epoxy resin. The first dielectric layer 21 may include FR4.The chip protective package 20 is an electronic component that provides prepackage or protective intermediate package for one or more semiconductor chips. The chip protective wrap 20 has characteristics suitable for reliably embedding the chip protective wrap 20 in a printed circuit board, in particular for embedding the chip protective wrap 20 in a printed circuit board or the use of manufacturing techniques typical of the production of printed circuit boards.The conductive layer 24 may have a non-contactable surface. The noncontactable surface can be a surface on which no low-resistance contact with a further metal is formed. For example, the outermost surface of the conductive layer 24 may have a roughness sufficient to prevent the formation of a low impedance contact with another metal. This roughness can be provided to provide a good mechanical bond to the adjacent layer of the printed circuit board, for example a layer of prepreg. The outermost surface of the conductive layer 24 may be mechanically roughened or oxidized to produce a non-contactable surface that may also have an increased surface roughness.An electrically non-conductive protective layer may be provided on the conductive layer 24. This additional electrically non-conductive protective layer may be provided to prevent oxidation or corrosion of the underlying conductive layer 24 during storage. The additional non-conductive protective layer may be removed to form contact regions either before the chip protective cladding 20 is embedded in the circuit board or after the chip protective cladding 20 is embedded in the circuit board. For example, the additional protective layer may be removed during the formation of vias through outer layers of the circuit board to expose portions of the conductive layer 24 at the base of the vias.The ratio of the side surface of the semiconductor chip 22 to the side surface of the chip protective cladding 20 may be within the range of 1:1.05 to 1:1.5. The side surface is the area of the main surface or the largest two-dimensional surface of the semiconductor chip 22 and the chip protective cladding 20.The semiconductor chip may have a side surface in the range of 0.5 mm 2 to 150 mm 2. The side surface of the semiconductor chip may depend on the device and the field of application. For example, a transistor device for use for consumer electronics may have a side surface in the range of 1 mm 2 to 10 mm 2 or 1 mm 2 to 5 mm 2, for example 1 mm 2. A transistor device for use in automotive electronics may have a thickness in the range of 7 mm 2 to 150 mm 2, for example 144 mm 2. The side surface of the chip protective cladding may be in the range of 0.525 mm 2 to 187.5 mm 2, 1,05 mm 2 to 12.5 mm 2 or 1.05 mm 2 to 7.25 mm 2 or. 7.35 mm 2 and 187.5 mm 2 are preferred.The semiconductor chip has a thickness t 1. The thickness t 1 is the thickness of the semiconductor body excluding any metallization disposed on the surface.The ratio between the thickness t 2 of the conductive layer 24 disposed on a surface of the semiconductor chip 22 and the thickness t 1 of the semiconductor chip 22 is t 2 ≤ t 1 / 3. The upper limit of the ratio between the thickness t 2 of the conductive layer 24 disposed on a surface of the semiconductor chip 22 and the thickness t 1 of the semiconductor chip 22 may be 1.5 t 1 such that t 1 / 3 ≤ t 2 ≤ 1.5 t 1.The thickness t 1 may be in the range of 40 μm to 100 μm, 40 μm to 80 μm, or 50 μm to 60 μm. For vertical devices such as vertical transistor devices, it may be desirable to reduce the thickness of the semiconductor body in order to reduce or adjust the RDSonof the device. Thinner semiconductor chips may be more difficult to handle and may be more susceptible to damage, for example during embedding in a printed circuit board. The chip protection package according to some of the examples described herein may be used to increase the robustness of these thin semiconductor chips during handling and, for example, embedding in a circuit board.The semiconductor chip may include a chip metallization disposed on the semiconductor body. This metallization may have a thickness of 3 μm to 20 μm or 3 μm to 10 μm. The conductive material of the chip protection cladding is applied to the semiconductor and may increase the thickness of the metallization by at least 10 μm. The total metal thickness t 2 may be in the range of 15 μm to 70 μm or 20 μm to 50 μm. If the semiconductor chip comprises a vertical device such as a vertical diode or a vertical transistor device, each of the opposing surfaces of the semiconductor chip comprises a metallization. The total metal thickness on each of the two opposing surfaces may be in the range of 15 μm to 70 μm or 20 μm to 50 μm.A vertical transistor device may have two electrodes on a first surface, for example a gate electrode and a current electrode, and a further electrode, for example a second current electrode, on a second surface opposite the first surface. For a MOSFET device, a gate electrode and a source electrode may be disposed on the first surface and a drain electrode may be disposed on the second surface. The drain electrode may extend over almost the entire second surface. The source electrode may extend over most of the first surface, the gate electrode having a smaller side surface. The second dielectric layer may extend onto the first surface to include two discrete recesses, one defining a central portion of the gate electrode and a second recess defining a central portion of the source electrode. The third dielectric layer may extend onto the second surface and may surround a central portion of the drain electrode.The chip protection cladding may further include a seed layer disposed on side surfaces and a base of at least one discrete recess extending through the second dielectric layer. The seed layer may also extend onto the outermost surfaces of the second dielectric layer. The seed layer is conductive and may comprise a metal or an alloy, for example copper, and may be deposited using electroless plating. One or more conductive layers may be deposited on the seed layer using electroless plating or electroplating. Electroplating methods tend to have a faster deposition rate than electroless plating methods.Electroless plating is also referred to as chemical or autocatalytic plating and is a non-electroplating method that includes simultaneous reactions in an aqueous solution that occur without the use of external electrical current so that a layer is deposited on a substrate in contact with the solution. Electroplating differs from electroless plating in that an external electric power source is used.The chip protection cladding 20 may be manufactured by embedding a semiconductor chip 22 in the first dielectric layer 21, applying the second dielectric layer 23 on the first surface 25 of the first dielectric layer 21, forming at least one recess 28 in the second dielectric layer 23, thereby arranging at least one recess 28 on the semiconductor chip 22, and incorporating a conductive material into the recess 28. When the second dielectric layer 23 contains a photopatternable polymer composition, the method further includes at least partially curing the second dielectric layer by applying electromagnetic radiation. In some embodiments, the electromagnetic radiation may be UV light.The second dielectric layer 23 may include a polymer composition having a portion cured by application of electromagnetic radiation and a portion cured, i.e., thermally cured, by application of heat. These photostructureable polymer compositions may be partially cured and / or structured by applying electromagnetic radiation and subsequently subjected to a thermal curing in order to completely or substantially completely cure the second dielectric layer.Before applying the conductive material, a third dielectric layer may be applied to the second dielectric layer 23. The third dielectric layer may comprise a photopatternable polymer such as an epoxy resin. Here, the third dielectric layer may be patterned simultaneously with the second dielectric layer 23 to provide the at least one recess 28.Polyimide, when cured, is highly chemically resistant. To prepare a polyimide layer for subsequent adhesion or metallization steps, an additional layer of material that can be chemically activated without damaging the polyimide passivation may be deposited. A material such as photostructureable epoxy would be very suitable for this application. The surface of this material may be prepared to aid metallization and to aid surface adhesion properties. The material can be applied simultaneously to both surfaces and can be exposed, developed and cured in a manner similar to passivation.The conductive material may be introduced into the recess 28 to have a surface substantially coplanar with the outer surface of the dielectric layer. In this case, a further conductive layer may be applied, which extends over the surface of the second dielectric layer 23 and the conductive material. This further conductive layer may be patterned to provide discrete areas coupled to one or more contact pads on the semiconductor chip 22. The conductive material and the further conductive layer may be provided by a single conductive layer extending into the recess or recesses and over the main surface of the dielectric layer.If a seed layer is deposited, it may be deposited as a continuous layer extending between the discrete conductive areas of the patterned conductive layer 24. The seed layer may be removed in these areas, for example, by applying a resist to protect the contact pads and wet etching.The first dielectric layer 21 may be a prefabricated material such as a core layer of a circuit board material or a B-stage prepreg layer. Here, openings may be formed in the first dielectric layer 21 in which the semiconductor chip 22 is placed. The opening may extend through the thickness of the first dielectric layer 21. Here, a temporary base for the opening may be provided by placing a liner on the second main surface of the first dielectric layer 21. The semiconductor chip 22 may be placed on the pad within the opening, and the second dielectric layer 23 may be deposited to extend from the first dielectric layer 21 to the semiconductor chip 22 via a gap between side surfaces of the opening and the side surfaces of the semiconductor chip 22, thereby fixing the semiconductor chip 22 in the first dielectric layer 21. The liner may then be removed and another dielectric layer may be deposited on the second main surface of the first dielectric layer 21 to attach the semiconductor chip 22 within the opening.The second dielectric layer 23 and the conductive layer 24 may be disposed on a single main surface 25 of the first dielectric layer 21. The second dielectric layer 23 and the conductive layer 24 may also be disposed on the opposite second main surface of the first dielectric layer 21.The semiconductor chip 22 may include a lateral device and may have contact pads on only a single main surface. The semiconductor chip 22 may include a device having a vertical drift distance and in contact with the two opposing surfaces of the semiconductor chip 22. Examples of devices having a vertical drift path are a diode and a vertical transistor device.The thickness of the semiconductor chip 22 may be substantially equal to the thickness of the first dielectric layer 21 such that the first main surface of the semiconductor chip 22 is substantially coplanar with the first main surface 25 of the first dielectric layer 21 and the second main surface of the semiconductor chip 22 is substantially coplanar with the second main surface of the first dielectric layer 21. In these examples, at least one additional dielectric layer and at least one conductive layer are disposed on both the first main surface and the second main surface of the first dielectric layer. In these examples, the chip protective cladding has contact pads on both opposing major surfaces of the chip protective cladding.FIG. 2 shows a chip protective cladding 30 according to another example for explanation. The chip protection package 30 includes a semiconductor chip 31 having one or more contact pads 32 on a first main surface 33 and one or more contact pads 34 on a second main surface 35 opposite the first main surface 33. The semiconductor chip 31 may include a vertical semiconductor device such as a diode or a transistor having a vertical drift path. The semiconductor chip 31 is arranged in a first dielectric layer 36. The first dielectric layer may include a polymer such as polyimide. The first dielectric layer 36 may include a composite material including a filler and a matrix, such as a fiberglass mesh filler impregnated with epoxy resin forming the matrix. As an example, the first dielectric layer 36 may include FR4.The side surfaces 37 of the semiconductor chip 31 may be in direct contact with the material forming the first dielectric layer 36. In other embodiments, the semiconductor chip 31 is placed in an opening provided in a pre-formed dielectric layer 36 such that there is a small gap between the side surfaces 37 of the semiconductor chip 31 and the material of the first dielectric layer 36.The height of the semiconductor die 31 may be substantially equal to the thickness of the first dielectric layer 36 such that an outermost surface 38 of the first contact pad 32 is substantially coplanar with a first main surface 39 of the first dielectric layer 36 and an outermost surface 40 of the second contact pad 34 is substantially coplanar with a second main surface 41 of the first dielectric layer 36. However, the ratio between the thickness of the semiconductor chip 31 and the first dielectric layer 36 may vary. For example, the thickness of the semiconductor body of the semiconductor chip 31 may be substantially equal to the thickness of the first dielectric layer 36, such that the first main surface 33 of the semiconductor chip 31 is substantially coplanar with the first main surface 39 of the first dielectric layer 36 and the second main surface 35 of the semiconductor chip 31 is substantially coplanar with the second main surface 41 of the first dielectric layer 36.The chip protection cladding 30 comprises two dielectric layers 42, 43 arranged on both the first main surface 39 and the second main surface 41 of the first dielectric layer 36. The second dielectric layer 42 is arranged directly on the first main surface 39 of the first dielectric layer 36 and the first main surface 38 of the semiconductor chip 31. The first dielectric layer 42 may have a composition selected to form a good passivation for the underlying material of the first dielectric layer 36 and the semiconductor chip 31. The third dielectric layer 43 is disposed on the second dielectric layer 42 and may contain material having good adhesion promoting properties to metals.The lateral extension of the second dielectric layer 42 and the third dielectric layer 43 may be substantially the same. The second dielectric layer 42 and the third dielectric layer 43 may extend on the surfaces of the semiconductor chip 31 and may partially overlap the peripheral regions of the contact pads 32, 34. This arrangement of the second dielectric layer 42 and the third dielectric layer 43 may be used to attach the semiconductor chip 31 in an opening in the first dielectric layer 36 or to assist in attaching the semiconductor chip 31 within the first dielectric layer 36.The second dielectric layer 42 may have a thickness of 5 μm to 20 μm on each main surface 39, 41 of the first dielectric layer 36. The third dielectric layer may have a thickness of 10 μm to 70 μm on each main surface 39, 41 of the first electrical layer 36.The chip protection package 30 further includes a conductive layer 44 disposed on the third dielectric layer 43 on the first main surface 33 of the first dielectric layer 36. The conductive layer 44 is also disposed in a recess 45 in the second dielectric layer 42 and the third dielectric layer 43 having a base formed by a central portion of the first contact pad 32. Similarly, on the opposite side of the first dielectric layer 36, a conductive layer 46 is disposed in a recess 47 in the second dielectric layer 42 and the third dielectric layer 43 having a base formed by a central portion of the second contact pad 34.The conductive layers 44, 46 have a lateral extent that is greater than the lateral extent of the respective contact pads 32, 34. The conductive layers 44, 46 are arranged on the respective contact pads 32, 34 and on the third dielectric layer 43 in regions adjacent to the contact pad 32, 34. As a result, the dielectric layers 36, 42, 43 provide a support structure for a conductive fanout type redistribution structure for the chip protective cladding 30.In the example illustrated in FIG. 2, the chip protective enclosure 30 further includes an electrically non-conductive layer 48 covering the outermost surfaces of the conductive layers 44, 46. The electrically non-conductive layer 48 may provide corrosion protection for the underlying material of the conductive layers 44, 46.The second dielectric layer 42 and the third dielectric layer 43 may comprise a photopatternable polymer composition such that the recesses 45, 47 may be formed by photoimage techniques. The recesses 45, 47 may be formed through both dielectric layers 42, 43 using a single resist and cure process. Both the second dielectric layer 42 and the third dielectric layer 43 can contain photostructured polyimide, for example. The second dielectric layer 42 may include a photo-structurable polyimide and the third dielectric layer 43 may include a photo-structurable epoxy resin. The conductive layers 44, 46 may include copper. The outermost electrically non-conductive layer 48 may include an organic material such as polyimide, an epoxy, or parylene.The chip protective enclosure 30 may have external dimensions and an external outline suitable for embedding within a circuit board. For example, the overall height of the chip protective cladding 30 may correspond to the thickness of a standard core layer used in circuit board fabrication. The thickness of the one or more deposited dielectric layers 42, 43 and / or the first dielectric layer 36 and / or the conductive layer 44 may be adjusted depending on the thickness of the semiconductor chip 31 such that the chip protection cladding 30 has a predetermined thickness.The placement of the first dielectric layer 36, the second dielectric layer 42, and the third dielectric layer 43 around the side surfaces 37 and edges of the semiconductor chip 31 provides mechanical protection for the semiconductor chip 31 during handling processes such as pick-up and placement that can be used to position the chip protection enclosure 30 within layers of the circuit board. The second dielectric layer 42, the third dielectric layer 43, and the conductive layer 44 also provide protection for the semiconductor chip 31 during a lamination process during which the chip protection encapsulant 30 is embedded in a dielectric layer of the circuit board.The conductive layers 44, 46 increase the thickness of the metal disposed directly above the semiconductor chip 31. The conductive layers 44, 46 also provide a thicker metal layer than the thickness of the contact pads 32, 34 disposed on the semiconductor chip 31. For example, each of the conductive layers 44, 46 may have a thickness of at least 5 μm, for example 10 μm to 70 μm, in regions positioned on the third dielectric layer 43. The conductive layers 44, 46 may be used to electrically couple the chip protective cladding 30, and therefore the semiconductor chip 31, to the conductive redistribution structure of the circuit board using circuit board fabrication techniques such as drilling vias and plating vias. The thickness of the conductive layers 44, 46 may be employed to enable using methods such as deep drilling in which a portion of the conductive layer at the drill bit is removed by the drilling process and a subsequent cleaning process. By increasing the thickness of the conductive layers 44, 46, the remaining portion of the layer at the base of the via has a clean surface, such that good electrical contact can be made with the conductive material inserted into the via to form the conductive via 44.The fabrication of the chip protective cladding will now be described in conjunction with Figs. 3 to 8. The fabrication processes are typically performed on a plate having a large number of envelope locations, for example hundreds or thousands of envelope locations. For purposes of illustration, a panel having four enclosure positions is shown in top and bottom perspective views in Figures 3-8, and the cross-sectional views represent a single component position.FIG. 3 ashows a perspective top view and FIG. 3 bshows a cross-sectional view of a core layer 50 of a chip protective cladding. The core layer 50 contains cross-linked glass fibers impregnated with an epoxy resin and provides a first dielectric layer for the chip protective cladding. The core layer 50 may include, for example, FR4. The core layer 50 includes a plurality of openings 51, each of which extends through the thickness of the core layer 50 and each has a lateral size and shape for receiving a semiconductor chip.FIG. 4 ashows a perspective top view and FIG. 4 bshows a cross-sectional view of a semiconductor chip 52 inserted into an opening 51 of the core layer 50. The semiconductor chip 52 may include a transistor device. The semiconductor chip 52 has a metallization structure on two opposing major surfaces and a total height corresponding to the thickness of the core layer 50, such that the top surface 53 of the top surface metallization 54 is substantially coplanar with a bottom surface 55 of the core layer 50 and a bottom surface 56 of the bottom surface metallization 57 is substantially coplanar with a bottom surface 58 of the core layer 50.The semiconductor chip 52 has lateral dimensions slightly smaller than the lateral dimensions of the opening 51, such that a gap 59 is present between the side surfaces 60 of the core layer 50 defining the opening 51 and the side surfaces 61 of the semiconductor chip 52. This gap 59 allows the semiconductor chip 52 to be placed in the opening 51 formed in a prefabricated core layer 50, for example by pick-and-place methods. The opening 51 includes a base 62 provided by a / n temporary / n backing or carrier 63 applied to the underside 58 of the core layer 50. The carrier 63 is used to temporarily store and position the semiconductor chip 52 within the opening 51.FIG. 5 ashows a perspective top view, FIG. 5 bshows a perspective bottom view and FIG. 5 cshows a cross-sectional view of a dielectric layer 64 applied to the semiconductor chip 52 and the core layer 50. The dielectric layer 64 is disposed on both the top 55 and bottom 58 surfaces of the core layer 50. In this particular example, the dielectric layer 64 includes two sub-layers 65, 66. The first sublayer 65 is arranged directly on the top side 55 and the bottom side 58 of the core layer 50, and the second sublayer 66 is arranged on the first sublayer 65 on both sides of the core layer 50. One or both of the dielectric layer sub-layers 65, 66 may be deposited using, for example, a printing technique.The first sublayer 65 and the second sublayer 66 may have different compositions, which may be selected to adapt properties of each of the sublayers. The first sub-layer 65 may include a photoimageable ("photoimageable") polyimide and is used as a passivation layer. The second sub-layer 66 contains a photoimageable epoxy used to promote adhesion to an overlying metal layer.The dielectric layer 64 extends from the top 55 of the core layer 50 via the gap 59 between the side surfaces 60 of the opening 51 and the side surfaces 61 of the semiconductor chip 52 onto the top 53 of the top metallization 54 of the semiconductor chip 52. Similarly, on the opposite side, the dielectric layer 64 extends from the bottom 58 of the core layer 50 via the gap 59 onto the bottom 56 of the bottom metallization 57 of the semiconductor chip 52.The dielectric layer 64 may enter the gap 59 and be in direct contact with the side surfaces 61 of the semiconductor die 52 and side surfaces 60 of the opening to assist in securing the position of the semiconductor die 52 within the opening 51. If the core layer 50 is thicker, an additional element may be disposed between the side surfaces 61 of the semiconductor die 52 and the side surfaces 60 of the opening 51 to assist in securing the semiconductor die 52 within the opening 51.In the example illustrated in FIGS. 3 to 8, the semiconductor chip 52 includes a vertical transistor device including a gate pad 67 and a source pad 68 on the top side and a drain pad 69 on the bottom side. The dielectric layer 64 includes discrete recesses 70 formed above the gate pad 67, the source pad 68, and the drain pad 69.FIG. 6 ashows a perspective top view, FIG. 6 bshows a perspective bottom view and FIG. 6 cshows a cross-sectional view of a first conductive layer 71 applied to the semiconductor chip 52. Specifically, the first conductive layer 71 is introduced into the recesses 70 positioned in the dielectric layer 64 such that portions of the conductive layer 71 are electrically coupled to the gate pad 67, the source pad 68, and the drain pad 69. The outer surface 72 of the first conductive layer 71 is substantially coplanar with the outer surfaces 73, 74 of the dielectric layer 64 to form discrete conductive areas electrically isolated from each other by portions of the dielectric layer 64. The conductive material 71 may include a metal such as copper or an alloy.The conductive material 71 positioned in the recesses 70 may be used to increase the thickness of the metal positioned on the semiconductor chip 52. This increased metal thickness is useful to improve the robustness and current carrying capacity of the semiconductor device.The first conductive layer 71 may be deposited by electroless plating. In some examples, a seed layer is first deposited covering the outer surfaces 73, 74 of the dielectric layer 64, side surfaces defining the recesses 70, and the exposed surfaces of the gate pad 67, the source pad 68, and the drain pad 69. Since the seed layer provides a continuous conductive path, it may be used as an electrode to which the first conductive layer 71 may be deposited using electroplating methods.FIG. 7 ashows a perspective top view, FIG. 7 bshows a perspective bottom view and FIG. 7 cshows a cross-sectional view of a second conductive layer 75 applied to the semiconductor chip 52, the first conductive layer 71 and the dielectric layer 64. The second conductive layer 75 extends over the dielectric layer 64 in regions above the core layer 50 and has a lateral extension that is greater than the lateral extension of the first conductive layer 71 and the lateral extension of the gate pad 67, the source pad 68 and the drain pad 69.The second conductive layer 75 may be subsequently patterned to define the contact pads on the outermost surfaces of the chip protection wrap. As a result, the combination of the core layer 50 and the dielectric layer 64 provides a support structure for enlarging the side surface area of the contact pads of the semiconductor chip 52. The core layer 50 may then be singulated, for example by sawing, to produce a plurality of chip protection envelopes 76.FIG. 7 dillustrates a partial cross-sectional view illustrating thicknesses. The semiconductor chip 52 has a thickness t 1. The source pad 68 has a thickness t 4 the first conductive layer 71 has a thickness t 5 and the second conductive layer 75 has a thickness t 8. The total thickness of the conductive material on the top surface of the semiconductor chip 52 is therefore the sum of t 4, t 5 and t 8. The total thickness may be at least one third of the thickness t 1 of the semiconductor chip 52, such that (t 4+ t 5+ t 8) ≥ t 1 / 3. The sum of the thickness of the source pad 68 and the first conductive layer 71 may be about half of the total thickness, so that (t 4+ t 5) ≥ t 1 / 6.Similarly, on the back side of the semiconductor chip 22, the drain pad 69 has a thickness t 6 the first conductive layer 71 has a thickness t 7 and the second conductive layer 75 has a thickness t 9. The total thickness of the conductive material on the back side of the semiconductor chip 52 is therefore the sum of t 6, t 7 and t 9. The total thickness may be at least one third of the thickness of the semiconductor chip 52, such that (t 6+ t 7+ t 9) ≥ t 1 / 3. The sum of the thickness of the drain pad 69 and the first conductive layer 71 may be about half of the total thickness, so that (t 6+ t 7) ≥ t 1 / 6. The gate pad 67 may have a thickness smaller than the thickness of the source pad 8 and the drain pad 69.The thickness t 1 of the semiconductor chip may be in the range of 40 μm to 100 μm, 40 μm to 80 μm, or 50 μm to 60 μm.The chip metallization of the source pad 68 and the drain pad 69, which are arranged on the same semiconductor body, may have a thickness of t 4 and t 6 respectively, within the range of 3 μm to 20 μm or 3 μm to 10 μm.The conductive material deposited on the semiconductor chip 52 may increase the thickness t 5 or t 7 of the metallization by at least 10 μm.The thickness t 8 and t 9 of the conductive layer 75 in regions disposed on the dielectric layer are each within the range of 5 μm to 70 μm or 10 μm to 50 μm.The total metal thickness t 2, t 3 of the conductive material disposed above the semiconductor chip 52 may be in the range of 15 μm to 70 μm or 20 μm to 50 μm.The thickness of the conductive layers t 4, t 5 and t 8 on the top side of the semiconductor chip 52 may be the same as or different from the thickness of the conductive layers t 6, t 7 and t 9 on the back side of the semiconductor chip 52. Any difference in thickness may result from electroplating process in which deposition on surfaces facing an electrode of the galvanic cell or located in closer proximity to an electrode of the galvanic cell may be performed more quickly, resulting in a greater thickness than deposition on surfaces facing away from an electrode of the galvanic cell or located at a greater distance from an electrode of the galvanic cell.FIG. 8 ashows a perspective top view and FIG. 8 bshows a perspective bottom view of a singulated chip protection enclosure 76. The chip protection wrap 76 includes a gate contact pad 77, which may be disposed in the corner of the top surface 79, and a source contact pad 78 extending over most of the top surface 79 of the chip protection wrap 76. The chip protective wrap 76 also includes a drain contact pad 80 that extends over most of the bottom surface 81 of the chip protective wrap 76. The contact pads 77, 78 and 80 project beyond the outer sides 73, 74 of the dielectric layer 64.FIG. 9 illustrates a cross-sectional view of a chip protection package 90 according to an embodiment. The chip protective cladding 90 includes a core layer 50, a semiconductor chip 52 positioned in an opening 51 in the core layer 50, and a dielectric layer 64 disposed on the core layer 50 and the semiconductor chip 52 as in the chip protective cladding 76 shown in FIGS. 7 and 8.The chip protection wrap 90 includes a seed layer 91 that extends over the surfaces 73, 74 of the dielectric layer 64, side surfaces of the recesses 70, and exposed portions of the gate pad 67, the source pad 68, and the drain pad 69 of the semiconductor chip 51. The chip protective cladding 90 includes a single conductive layer 92 that extends into the recesses 70 of the dielectric layer 64 and on regions of the outermost surfaces 73, 74 of the dielectric layer 64. The seed layer 91 and the conductive layer 92 are patterned or patterned to provide a separate gate pad 77 and source pad 78 on the top side 79 and a drain pad 80 on the bottom side 81.The chip protection cladding 90 has been further processed to create a roughened surface 93 on the conductive layer 92. This roughened outermost surface 93 is noncontactable and serves to promote mechanical anchoring between the chip protective cladding 90 and other dielectric layers of the circuit board applied to the chip protective cladding 90 to embed the chip protective cladding 90 within the circuit board.An example of a process flow for manufacturing chip protection packages is as follows:adhering a core layer having a plurality of openings to a carrier tape;placing semiconductor chips in the openings;applying a first passivation, for example polyimide, to a first surface of the assembly;drying the first passivation;exposing and developing the first passivation;releasing the core layer from the carrier tape;applying a second passivation to a second surface of the package;drying the second passivation;exposing and developing the second passivation;curing or partially curing the first and second passivation;applying an organic material such as epoxy to both sides of the assembly substantially simultaneously;drying the organic material;exposing and developing the organic material;curing the organic material;preparing the semiconductor chip metallization and the organic material for coating;applying a seed layer to both surfaces substantially simultaneously by electroless plating;applying a coating resist to both surfaces substantially simultaneously;exposing and developing the coating resist;electrolytic plating both surfaces simultaneously to deposit a conductive layer of metal such as copper;etching unwanted material to create an outer redistribution structure that includes pads;Singulating the wrappers from the assembly, and testing and packaging the wrappers.FIG. 10 illustrates the chip protective enclosure 90 embedded in a circuit board. The chip protective cladding 90 may be mounted in an opening 96 of a core layer 97 of a circuit board. A first dielectric layer 94 is disposed on the bottom surface 81, and a second dielectric layer 95 is disposed on the top surface 79 of the chip protective cladding 90. Additional conductive layers and dielectric layers may be added on one or more of both sides of this structure depending on the number of layers required in the multilayer printed circuit board. The dielectric layers 94, 95, 97 are laminated together using pressure and heat. The roughened surface 93 of the conductive layer 92 of the chip protective cladding 90 may be used to increase the mechanical adhesion between the chip protective cladding 90 and the adjacent dielectric layers 94, 95 during the lamination process and after the lamination process. The structure of the chip protection wrap 90 protects the semiconductor chip 52 during this lamination process.To provide electrical coupling to the chip protective cladding 90, which is now embedded in the circuit board, vias 98, 99 may be inserted through the dielectric layers 94, 95, for example, by laser drilling or mechanical drilling. The vias 98, 99 may be positioned to be above the core layer 50 of the chip protection cladding 90 and adjacent to the semiconductor chip 52. Due to the increased thickness of the conductive layer 92 in areas adjacent the semiconductor die 52, some of the material having the roughened surface 93 may be removed during the drilling process and subsequent chemical cleaning to provide a clean surface. The prepared surface may be used to create an improved electrical connection between the conductive material 100 inserted into the vias 98, 99 and the underlying portion of the conductive layer 92. The conductive material 100 electrically couples the chip protection package to the conductive redistribution structure 101 of the circuit board 102. The redistribution structure may include a patterned copper foil disposed on or between dielectric layers.The thickness of the chip protective cladding 90 may be selected to correspond to the thickness of the core layer 97 of the circuit board. In other examples, the thickness of the semiconductor die 52 may vary within the core layer 50 such that the combination of the thickness of the core layer 50, the chip protective cladding 90, the dielectric layer 64, and the conductive layer 92 is used to compensate for variations in the thickness of the semiconductor die 52 such that the outer dimensions of the chip protective cladding conform to a predetermined standard thickness.In the examples described in connection with the figures, each chip protection wrap contains a single chip. However, the chip protection package is not limited to including a single semiconductor chip, and may include two or more semiconductor chips. The two or more semiconductor chips may be electrically coupled to each other to provide a / n desired / n circuit or part of a circuit. For example, the cladding may include two transistor devices coupled in a half bridge configuration. These examples may also be referred to as a system in the enclosure. The circuit or sub-circuit and / or the individual semiconductor chips may be tested prior to lamination into a higher level printed circuit board.Some of the aspects described herein are summarized below using numbered examples.Example 1. chip protective cladding, comprising: a first dielectric layer comprising at least one organic component having a decomposition temperature of at least 180°C; a semiconductor chip embedded in the first dielectric layer, the semiconductor chip having a first surface and a thickness t 1 ; a second dielectric layer disposed on a first surface of the first dielectric layer, the second dielectric layer comprising a photopatternable polymer composition; and a conductive layer disposed on the first surface of the semiconductor chip and electrically coupled to the semiconductor chip, the conductive layer having a thickness t 2 where t 2 ≥ t 1 / 3.Example 2. the package of example 1, wherein the second dielectric layer extends from the first dielectric layer onto the semiconductor chip.Example 3. the cladding of Examples 1 or 2, wherein the outermost surface of the second dielectric layer comprises an epoxy-based composite.Example 4. the package of any of Examples 1 to 3, wherein the conductive layer extends from the semiconductor chip to the second dielectric layer.Example 5. the package of any of Examples 1 to 4, wherein a first electrode of the semiconductor chip forms a base of a discrete recess extending through the second dielectric layer, and the conductive layer is disposed in the discrete recess.Example 6. the package of any of Examples 1 to 5, further comprising: a third dielectric layer disposed on a second surface of the first dielectric layer, the second surface opposing the first surface of the first dielectric layer, the third dielectric layer comprising a photostructureable polymer composition; and another conductive layer disposed on a second surface of the semiconductor chip and electrically coupled to the semiconductor chip, the another conductive layer having a thickness t 3 where t 3 ≥ t 1 / 3.Example 7. the package of example 6, wherein the third dielectric layer extends onto the second surface of the semiconductor chip.Example 8: The package of example 6 or 7, wherein the further conductive layer extends onto the third dielectric layer.Example 9 The package of any of examples 6 to 8, wherein a second electrode of the semiconductor chip forms a base of a recess extending through the third dielectric layer and the further conductive layer is disposed in the discrete recess.Example 10. the package of any of Examples 1 to 9, wherein the semiconductor chip comprises a vertical transistor device.Example 11 The cover of any one of Examples 1 to 10, wherein 40 μm ≤ t 1 ≤ 100 μm and 15 μm ≤ t 2 ≤ 70 μm.Example 12 The package of any of Examples 1 to 11, wherein the second dielectric layer comprises two or more sub-layers of different composition.Example 13 The shell of Example 12, wherein a second sublayer has a chemical affinity to copper that is greater than a chemical affinity a first sublayer has to copper.Example 14. The cover of Example 12 or 13, wherein the first sublayer comprises a photostructureable polyimide and the second sublayer comprises a photostructureable epoxy-based composite.Example 15. The case of any one of Examples 1 to 14, wherein the conductive layer has a non-contact surface.Example 16. The case of any of Examples 1 to 15, wherein the conductive layer is covered by an electrically insulating layer.Example 17. a method comprising: embedding a semiconductor chip in a first dielectric layer, the semiconductor chip having a thickness t 1 and the first dielectric layer comprising at least one organic component having a decomposition temperature of at least 180°C; applying a second dielectric layer to a first surface of the first dielectric layer and a first surface of the semiconductor chip, the second dielectric layer comprising a photostructured polymer composition; creating at least one recess in the second dielectric layer, the at least one recess comprising a base formed by a first electrode of the semiconductor chip, the first electrode having a thickness t 4; introducing a conductive material into the recesses, wherein the conductive material has a thickness t 5 wherein (t 4+ t 5) ≥ t 1 / 6.Example 18. The method of Example 17, further comprising applying a conductive layer to the conductive material and to the second dielectric layer.Example 19: The method of Example 18, wherein the conductive layer has a thickness t 8 where (t 4+ t 5+ t 8) ≥ t 1 / 3.Example 20 The method of Example 18, further comprising applying an electrically non-conductive coating to the conductive layer.Example 21: The method of any one of Examples 17 to 20, further comprising roughening the surface of the conductive layer.Example 22. The method of any of Examples 17 to 21, wherein applying the conductive material comprises applying a seed layer to side surfaces of the recess and to the second dielectric layer by electroless plating and applying a conductive layer to the seed layer by electroplating.Example 23. The method of any of Examples 17 to 22, wherein the second dielectric layer is deposited by printing.Example 24. The method of any of Examples 17 to 23, further comprising: applying a third dielectric layer to a second surface of the first dielectric layer and a second surface of the semiconductor chip, the third dielectric layer comprising a photo-structurable polymer composition; creating at least one recess in the third dielectric layer, the at least one recess comprising a base formed by a second electrode of the semiconductor chip, the second electrode having a thickness t 6 and incorporating a conductive material into the at least one recess, the conductive material having a thickness t 7 wherein (t 6+ t 7) ≥ t 1 / 6.Example 25. chip protection package comprising: means for embedding a semiconductor chip; means for passivating at least portions of a surface of the semiconductor chip; means for promoting adhesion to a conductive layer, and means for electrically coupling the semiconductor chip to the conductive layer.Example 26: a package, comprising: a support layer comprising a polymer; a transistor device embedded in the support layer; a passivation layer disposed on the support layer and at least portions of the transistor device, the passivation layer comprising a polymer, and a conductive layer disposed on the passivation layer and electrically coupled to the transistor device, wherein a ratio of a side surface of the transistor device to a side surface of the chip protection package is 1:1.05 to 1:5.Example 27. the case of example 26, wherein the passivation layer is disposed on a first surface of the support layer, a second surface of the support layer, portions of a first surface of the transistor device, and portions of a second surface of the transistor device, and a further conductive layer is disposed on the second surface of the transistor device and the second surface of the passivation layer, wherein the further conductive layer is electrically coupled to the transistor device.Example 28: The package of example 26 or 27, wherein the transistor device has a thickness t1, the conductive layer has a thickness t2on the first surface of the transistor device, and the further conductive layer has a thickness t 3 on the second surface of the transistor device, wherein t 1 / 3 ≤ t 2 ≤ 1.5 t 1 and t 1 / 3 ≤ t 3 ≤ 1.5 t 1.Example 29. the chip protective wrap of any of Examples 26-28, further comprising an adhesion promoting layer disposed on the passivation layer, wherein the adhesion promoting layer has a chemical affinity for copper that is greater than a chemical affinity the passivation layer has for copper, wherein the conductive layer is disposed on the adhesion promoting layer.Example 30. the chip protective wrap of Example 29, wherein the passivation layer comprises a polyimide and the adhesion promoting layer comprises an epoxy-based composite.Spatially relative terms such as "below," "below," "lower," "over," "upper," and the like, are used to facilitate the description to explain the positioning of an element relative to a second element. These terms are used to include different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as "first", "second", and the like are also used to describe various elements, regions, portions, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the specification.As used herein, the terms "comprise," "include," "include," "comprise," and the like are open ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a / e / r" and "the / s" are intended to include both the plural and the singular, unless the context clearly indicates otherwise. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

Claims

A chip protective cladding, comprising: a first dielectric layer (50) comprising at least one organic component having a decomposition temperature of at least 180°C; a semiconductor chip (52) embedded in the first dielectric layer (50), the semiconductor chip (52) having a first surface and a thickness t 1 ; a second dielectric layer (64) disposed on a first surface of the first dielectric layer (50), the second dielectric layer (64) comprising two sub-layers (65, 66); a first conductive layer disposed on the first surface of the semiconductor chip (52) and electrically coupled to the semiconductor chip (52), the first conductive layer having a thickness t 2 where t 2 ≥ t 1 / 3 and the first conductive layer (92) forming a first contact pad; a third dielectric layer (64) disposed on a second surface of the first dielectric layer (50), the second surface opposing the first surface of the first dielectric layer (50); a second conductive layer disposed on a second surface of the semiconductor chip (52) and electrically coupled to the semiconductor chip (52), the second surface being opposite the first surface of the semiconductor chip (52), the second conductive layer having a thickness t 3 where t 3 ≥ t 1 / 3 and the second conductive layer forming a second contact pad, the semiconductor chip (52) being disposed in an opening (51) of the first dielectric layer (50), a gap (59) being formed between side surfaces (60) of the opening (51) and side surfaces (61) of the semiconductor chip (52), and the second and third dielectric layers (64) extending into the gap (59).The chip protective cladding of claim 1, wherein the first conductive layer comprises a source pad (68), a seed layer (91), and a single conductive layer (92).The chip protective cladding of claim 2, wherein the seed layer (91) is disposed between the source pad (68) and the single conductive layer (92) and between portions of the first dielectric layer (64) and the single conductive layer (92).The chip protection package of claim 1 or 2, wherein the second conductive layer comprises a drain pad (69), a seed layer (91), and a single conductive layer (92).The chip protection package of claim 2, wherein the seed layer (91) is disposed between the drain pad (69) and the single conductive layer (92) and between portions of the first dielectric layer (64) and the single conductive layer (92).The chip protective cladding of any of claims 2 to 5, wherein the single conductive layer (92) of the first and second conductive layers has a roughened surface (93).The chip protective cladding of any of claims 1 to 6, wherein the second sublayer (66) has a chemical affinity to copper that is greater than a chemical affinity the first sublayer (65) has to copper.The chip protective cladding of any of claims 1 to 7, wherein the first sublayer (65) comprises a photostructureable polyimide and the second sublayer (65) comprises a photostructureable epoxy-based composite.The chip protective cladding of any of claims 1 to 8, wherein the second dielectric layer (64) extends from the first dielectric layer (50) onto the semiconductor chip (52).The chip protective cladding of any of claims 1 to 9, wherein the first conductive layer extends from the semiconductor chip (52) to the second dielectric layer (64).The chip protective cladding of any of claims 2 to 10, wherein the source pad (68) forms a base of a discrete recess extending through the second dielectric layer (64), and the first conductive layer is disposed in the discrete recess.The chip protective cladding of any of claims 1 to 11, wherein the third dielectric layer extends onto the second surface of the semiconductor chip.The chip protective cladding of any of claims 1 to 12, wherein the second conductive layer extends onto the third dielectric layer (64).The chip protective cladding of any of claims 1 to 13, wherein the drain pad (69) of the semiconductor chip forms a base of a recess extending through the third dielectric layer (64), and the second conductive layer is disposed in the discrete recess.The chip protection package of any of claims 1 to 14, wherein the semiconductor chip (52) comprises a vertical transistor device.The chip protective cladding according to any one of claims 1 to 15, wherein 40 μm ≤ t 1 ≤ 100 μm and 15 μm ≤ t 2 ≤ 70 μm.The chip protective cladding of any of claims 1 to 16, wherein the first and second conductive layers each have a non-contact surface.An assembly comprising: a circuit board (97); a chip protective enclosure according to any of claims 1 to 17 disposed in a recess of the circuit board (97); a first dielectric layer (95) disposed on a first side of the circuit board (97) and a first side of the chip protective enclosure; and a second dielectric layer (94) disposed on a second side of the circuit board (97) and a second side of the chip protective enclosure.

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