Electrode configurations for increasing the electrothermal insulation of phase-change storage elements and associated techniques

Abstract

Device comprising the following: multiple phase-change memory elements, wherein individual phase-change memory elements from the multiple phase-change memory elements contain the following: a phase-change material layer; a first electrode layer arranged on the phase-change material layer and in direct contact with the phase-change material layer; a second electrode layer arranged on top of and in direct contact with the first electrode layer; and a bit line that is located on the second electrode layer and in direct contact with the second electrode layer; wherein the individual phase-change memory elements are separated from the multiple phase-change memory elements by electrically insulating columns; and material of the second electrode layer is arranged between the bit line and the electrically insulating columns.

Description

Area

[0001] Embodiments of the present invention relate generally to the field of integrated circuits, and more particularly to electrode configurations for increasing the electrothermal isolation of phase change memory elements and related techniques. background

[0002] Phase-change memory (PCM) technology, such as multi-stack crosspoint PCM, is a promising alternative to other non-volatile memory (NVM) technologies. There is a continuous drive to increase the electrothermal isolation of phase-change memory elements to optimize PCM operation, for example, by providing programming current in the form of a threshold voltage (V T )-to-current(I) characteristic, V T -I- characteristic curve, contains.

[0003] Multi-stack crosspoint PCMs are known from the documents US 2009 / 0 261 315 A1, US 2009 / 0 303 780 A1, US 2011 / 0 297 911 A1, US 2013 / 0 277 640 A1, US 2014 / 0 117 303 A1 and US 2014 / 0 158 964 A1.

[0004] The objective is to improve the electrothermal insulation of multi-stack cross-point PCMs.

[0005] The object is achieved by the device according to patent claim 1, the method according to patent claim 7 and the system according to patent claim 15. Further embodiments emerge from the subclaims. Brief description of the drawings

[0006] Embodiments will be readily understood from the following detailed description when taken in conjunction with the accompanying drawings. To simplify this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings. Fig. 1 schematically illustrates a top view of an example chip in wafer form and in singulated form in accordance with some embodiments. Fig. 2 schematically illustrates a cross-sectional side view of an integrated circuit (IC) package in accordance with some embodiments. Fig. 3A-B, Fig. 4A-B, Fig. 5A-B, Fig. 6A-B, Fig. 7A-B, Fig. 8A-B, Fig. 9A-B and Fig. 10A-B schematically illustrate cross-sectional side views of a phase change memory (PCM) device during various stages of fabrication in accordance with some embodiments. Fig. 3C, Fig. 4C, Fig. 5C, Fig. 6C, Fig. 7C, Fig. 8C and Fig. 9C schematically illustrate a top view of a phase change memory (PCM) device during various stages of fabrication in accordance with some embodiments. Fig. 11 is a flow diagram of a method of manufacturing a PCM device in accordance with some embodiments. Fig. 12 schematically illustrates an example system including a PCM device in accordance with various embodiments described herein. Detailed description

[0007] Embodiments of the present invention describe electrode configurations for increasing the electrothermal isolation of phase-change memory elements and related techniques. In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, wherein like reference characters designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense.

[0008] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0009] The description may use the phrases "in one embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The term "coupled" may refer to a direct connection, an indirect connection, or an indirect communication.

[0010] As used herein, the reference "module" may refer to, be a part of, or include an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, a state machine, and / or other suitable components that provide the described functionality.

[0011] Fig. 1 schematically illustrates a top view of an example chip 102 in wafer form 10 and in singulated form 100 in accordance with some embodiments. In some embodiments, chip 102 may be one of a plurality of chips (e.g., chips 102, 102a, 102b) of a wafer 11 made of semiconductor material such as silicon or another suitable material. The plurality of chips may be formed on a surface of wafer 11. Each of these chips may be a repeating unit of a semiconductor product including a phase-change memory (PCM) device as described herein. For example, chip 102 may include circuitry 103 of a PCM device in accordance with some embodiments. According to various embodiments, circuitry 103 may include one or more PCM elements (e.g., cells) that may be configured in an array.The PCM elements may, for example, include a phase-change material such as a chalcogenide glass that can be switched between crystalline and amorphous states with the application of heat produced by an electric current. The state (e.g., crystalline / amorphous) of the phase-change material may correspond to a logical value (e.g., 1 or 0) of the PCM elements. Circuitry 103 may, in some embodiments, be part of a PCM and switching (PCMS) device. That is, the PCM elements may include a switch, such as an Ovonic Threshold Switch (OTS), configured for use in selection / programming operations of the PCM elements.

[0012] Circuitry 103 may further include one or more bitlines and one or more wordlines coupled to the PCM elements. The bitlines and wordlines may, in some embodiments, be configured such that each of the PCM elements is located at an intersection of each individual bitline and wordline. A voltage or bias may be applied to a target PCM element from the PCM elements using the wordlines and bitlines to select the target cell for a read or write operation. Bitline drivers may be coupled to the bitlines, and wordline drivers may be coupled to the wordlines to assist in decoding / selecting the PCM elements. Capacitors and resistors may be coupled to the bitlines and wordlines. Circuitry 103 may, in some embodiments, include other suitable devices and configurations.For example, the circuitry 103 may include one or more modules configured to perform reading, programming, verification, and / or analysis operations.

[0013] In some embodiments, the circuitry 103 may be formed using PCM manufacturing techniques and / or other suitable semiconductor manufacturing techniques. It is noted that the circuitry 103 in Fig. 1 is only depicted schematically and may represent a wide variety of suitable logic or memory in the form of circuitry, for example one or more state machines containing circuitry and / or instructions in memory (e.g. firmware or software) configured to perform actions such as reading, programming, verification and / or analysis operations.

[0014] After a manufacturing process completes the semiconductor product, wafer 11 may undergo a singulation process in which each of the chips (e.g., chips 102, 102a, 102b) is separated from one another to provide discrete "components" of the semiconductor product. Wafer 11 may be any of several sizes. In some embodiments, wafer 11 has a diameter ranging from about 25.4 mm to about 450 mm. Wafer 11 may include other sizes and / or other shapes in other embodiments. According to various embodiments, circuitry 103 may be disposed on a semiconductor substrate in wafer form 10 or singulated form 100. In some embodiments, chip 102 may include logic or memory, or combinations thereof.

[0015] Fig. 2 schematically illustrates a cross-sectional side view of an integrated circuit (IC) package 200 in accordance with some embodiments. In some embodiments, the IC package 200 may include one or more chips (hereinafter "chip 102") electrically and / or physically coupled to a package substrate 121. The chip 102 may include circuitry (e.g., the circuitry 103 of Fig. 1) such as a PCM device as described herein. In some embodiments, the package substrate 121 may be coupled to a circuit board 122, as shown.

[0016] Chip 102 may represent a discrete product fabricated from a semiconductor material (e.g., silicon) using semiconductor manufacturing techniques such as thin-film deposition, lithography, etching, and the like used in connection with forming PCM devices. In some embodiments, chip 102 may be, include, or be part of a processor, memory, a system-on-chip (SoC), or an ASIC. In some embodiments, an electrically insulating material such as a molding compound or underfill material (not shown) may encapsulate at least a portion of chip 102 and / or chip-level interconnect structures 106.

[0017] The chip 102 may be attached to the package substrate 121 according to a wide variety of suitable configurations, including, for example, being directly coupled to the package substrate 121 in a flip-chip configuration, as shown. In the flip-chip configuration, an active side S1 of the chip 102, containing active circuitry, is attached to a surface of the package substrate 121 using chip-level interconnect structures 106 such as contact bumps, pillars, and other suitable structures that may also electrically couple the chip 102 to the package substrate 121. The active side S1 of the chip 102 may contain circuitry such as PCM elements. An inactive side S2 may be arranged opposite the active side S1, as can be seen.In other embodiments, chip 102 may be arranged on another chip coupled to package substrate 121 in any of many suitable stacked-chip configurations. For example, a processor chip may be coupled to package substrate 101 in a flip-chip configuration, and chip 102 may be mounted on the processor chip in a flip-chip configuration and electrically coupled to the package substrate using through silicon vias (TSVs) formed across the processor chip. In still other embodiments, chip 102 may be embedded in package substrate 121 or coupled to a chip embedded in package substrate 121. Other chips may be coupled to package substrate 121 in a side-by-side configuration with chip 102 in other embodiments.

[0018] In some embodiments, the chip-level interconnection structures 106 may be configured to route electrical signals between the chip 102 and the package substrate 121. The electrical signals may include, for example, input / output (I / O) signals and / or power / ground signals used in connection with the operation of the chip. The chip-level interconnection structures 106 may be coupled to corresponding chip contacts arranged on the active side S1 of the chip 102 and corresponding package contacts arranged on the package substrate 121. The chip contacts and / or package contacts may include, for example, contact pads, vias, trenches, traces, and / or other suitable contact structures.

[0019] In some embodiments, the package substrate 121 is an epoxy-based laminate substrate having a core and / or buildup layers, such as an Ajinomoto buildup film (ABF) substrate. The package substrate 121 may comprise other suitable types of substrates in other embodiments, including, for example, substrates formed from glass, ceramic, or semiconductor materials.

[0020] The package substrate 121 may include electrical routing features configured to route electrical signals toward and away from the chip 102. The electrical routing features may include, for example, package contacts (e.g., contact pads 110) disposed on one or more surfaces of the package substrate 121 and / or internal routing features (not shown), such as trenches, vias, or other interconnection structures, to route electrical signals through the package substrate 121.

[0021] The circuit board 122 may be a printed circuit board (PCB) constructed from an electrically insulating material such as an epoxy resin laminate. For example, the circuit board 122 may include electrically insulating layers made of materials such as polytetrafluoroethylene, phenolic cotton paper, materials such as Flame Retardant 4, FR-4, FR-1 cotton paper, and epoxy resin materials such as CEM-1 or CEM-3, or textile glass materials laminated together using an epoxy resin pre-impregnated material. Interconnection structures (not shown) such as traces, trenches, and vias may be formed through the electrically insulating layers to route the electrical signals of the chip 102 through the circuit board 122. The circuit board 122 may, in other embodiments, be made of other suitable materials. In some embodiments, the circuit board 122 is a motherboard (e.g.,Motherboard 1202 from . Fig. 12).

[0022] Package-level interconnections, such as solder bumps 112, may be coupled to contact pads 110 on the package substrate 121 and / or the circuit board 122 to form corresponding solder connections configured to further route the electrical signals between the package substrate 121 and the circuit board 122. The contact pads 110 may be made of any suitable electrically conductive material, such as metal, including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), and combinations thereof. The package-level interconnections may include other structures and / or configurations, including, for example, land grid array (LGA) structures and the like.

[0023] The IC package 200 may, in other embodiments, include a wide variety of other suitable configurations, including, for example, suitable flip-chip and / or wire-bond configurations, interposers, multi-chip packaging configurations, system-in-package (SiP) and / or package-on-package (PoP) configurations. Other suitable techniques for routing electrical signals between the chip 102 and other components of the IC package 200 may be used in some embodiments.

[0024] Fig. 3A-B, Fig. 4A-B, Fig. 5A-B, Fig. 6A-B, Fig. 7A-B, Fig. 8A-B, Fig. 9A-B and Fig. 10A-B schematically illustrate cross-sectional side views of a phase change memory (PCM) device during various stages of fabrication in accordance with some embodiments. Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A and Fig. 10A depict a cross-sectional side of the PCM device 300 from the same first perspective, and Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B and Fig. 10B depict a cross-sectional side of the PCM device 300 from the same second perspective, which is perpendicular to the first perspective. Fig. 3C, Fig. 4C, Fig. 5C, Fig. 6C, Fig. 7C, Fig. 8C and Fig. 9C schematically illustrate a top view of the phase change memory (PCM) device 300 during various stages of fabrication in accordance with some embodiments. Fig. 3A-C represent the PCM device 300 during the same stage of manufacturing, Fig. 4A-C represent the PCM device 300 during the same stage of manufacturing, Fig. 5A-C represent the PCM device 300 during the same stage of manufacturing, and so on. The labels P'-P'', BL'-BL'', and WL'-WL'' are provided to facilitate understanding of the relative orientation between the different perspectives (e.g., Fig. 3A-C). For example, Fig. 3A-9A represent a cross section along WL'-WL'', Fig. 3B-9B may represent a cross section along BL'-BL'', and Fig. 3C-9C may represent a cross section along P'-P''.

[0025] Referring to Fig. 3A-C depicts a PCM device 300 after depositing an electrically conductive material, such as wordline metal 304, on a substrate 301 to form a wordline layer and depositing materials to form a stack of layers on wordline metal 304. One or more interposed layers and / or structures (hereinafter, "circuitry 302") may be disposed between substrate 301 and wordline metal 304. For example, circuitry 302 may include complementary metal-oxide-semiconductor (CMOS) devices and / or metallizations formed on substrate 301 between wordline metal 304 and substrate 301. Substrate 301 may, in some embodiments, be a semiconductor substrate, such as silicon. Substrate 301 is not shown in the remaining figures to avoid obscuring other aspects.The wordline metal 304 may, for example, include tungsten. Other suitable materials for the substrate 301 and the wordline metal 304 may be used in other embodiments.

[0026] The stack of layers may include a bottom electrode layer 306 disposed on the wordline metal 304, a device select layer (SD layer) 308 disposed on the bottom electrode layer 306, a middle electrode layer 310 disposed on the SD layer 308, a phase change material (PM) layer 312 disposed on the middle electrode layer 310, and a first top electrode layer (TE1) 314 disposed on the PM layer 312, as can be seen. Each layer of the stack of layers may be deposited according to any suitable technique.

[0027] According to various embodiments, the lower electrode layer 306 may be formed of one or more conductive and / or semiconductive materials such as carbon (C), carbon nitride (C x N y), n-doped polysilicon and p-doped polysilicon; metals containing Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta and W, conductive metal nitrides containing TiN, TaN, WN and TaCN; conductive metal silicides containing tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides, conductive metal silicide nitrides containing TiSiN and WSiN; conductive metal carbide nitrides containing TiCN and WCN and conductive metal oxides containing RuO2. The SD layer 308 may comprise a PN diode, a MIEC (Mixed Ionic Electronic Conduction) device, or an OTS (Ovonic Threshold Switch) based on chalcogenide alloys having compositions including any of the chalcogenide alloy systems described for the memory element (e.g., the PM layer 312), and may additionally further comprise an element that suppresses crystallization.The middle electrode layer 310 may be formed of one or more conductive and / or semiconductive materials such as carbon (C), carbon nitride (C. x N y); n-doped polysilicon and p-doped polysilicon; metals including Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides, and titanium silicides; conductive metal silicide nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN; and conductive metal oxides including RuO2. The PM layer 312 may be made of a phase change material, such as a chalcogenide glass, which can be switched between crystalline and amorphous states with the application of heat produced by an electric current, such as a B. an alloy containing at least two of the elements germanium, antimony, tellurium, silicon, indium, selenium, sulfur, nitrogen and carbon.The first upper electrode layer 314 may be made of an electrically conductive material such as a metal or semimetal (e.g., semiconducting material) having a resistance in a range of 1 milliohm·centimeter (mOhm·cm) to 100 mOhm·cm, such as carbon (C), carbon nitride (C. x N y), n-doped polysilicon and p-doped polysilicon, metals including Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W, conductive metal nitrides including TiN, TaN, WN, and TaCN, conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides, and titanium silicides, conductive metal silicide nitrides including TiSiN and WSiN, conductive metal carbide nitrides including TiCN and WCN, and conductive metal oxides including RuO2. Layers 306, 308, 310, 312, and 314 may, in other embodiments, be made of other suitable materials having other suitable properties.

[0028] In some embodiments, the first top electrode layer 314 may have a thickness in the range of 5 nanometers (nm) to 15 nm. In one embodiment, the first top electrode layer 314 may have a thickness of about 15 nm or less. In processes that form only the first top electrode layer 314, it may be difficult to increase the first top electrode layer 314 beyond 15 nm due to the height of the sub-stack to be etched at the wordline definition, coupled with mechanical weakness of the phase-change material and a desire to reliably separate adjacent wordlines. The first top electrode layer 314 may have other suitable thicknesses in some embodiments.

[0029] Referring to Fig. 4A-C depicts the PCM device 300 after wordline definition. Wordline definition may be achieved, for example, by using a patterning process such as lithography and / or etching processes to selectively remove portions of the stack of layers to provide the lines 316 of the stack of layers on the underlying circuitry 302 with trenches 315 between the lines 316, as can be seen. The trenches 315 may separate PCM elements from each other. Fig. 4B, the word line metal 304 is structured such that the word line extends in a direction into and out of the plane of the drawing. In Fig. 4C, the word line metal 304 is disposed below the first upper electrode layer 314 and extends in a left-to-right direction across the plane of the drawing.

[0030] Referring to Fig. 5A-C depicts the PCM device 300 after deposition of dielectric material to fill a region between the lines 316. For example, in the depicted embodiment, a dielectric underlayer 318 may be conformally deposited on surfaces of the stack of layers (e.g., on the lines 316), on the wordline metal, and on the circuitry 302, as can be seen. A dielectric fill material 320 may be deposited to fill the region between the lines 316 using any suitable technique. In some embodiments, the dielectric underlayer 318 may be made of silicon nitride (Si3N4 or generally Si x N y, where x and y represent any suitable relative amount), and the dielectric fill material 320 may be made of silicon oxide (SiO2). The dielectric base 318 and the dielectric fill material 320 may be made of other suitable materials in other embodiments.

[0031] Referring to Fig. 6A-C depicts the PCM device 300 after recessing the dielectric material (e.g., the dielectric fill material 320 and the dielectric underlayer 318) to expose the first top electrode layer 314. In some embodiments, a planarization process such as chemical mechanical polishing (CMP) may be used to recess the dielectric material. Other suitable techniques for recessing the dielectric material may be used in other embodiments.

[0032] Referring to Fig. 7A-C depicts the PCM device 300 after depositing a second top electrode layer (TE2 layer) 322 on the first top electrode layer 314 and depositing a bitline metal 324 on the second top electrode layer 322 to form a bitline layer. In some embodiments, the second top electrode layer 322 may be deposited on portions of the dielectric underlayer 318 and the dielectric fill material 320, as shown in Fig. 7B. According to various embodiments, the second top electrode layer 322 may be deposited using, for example, physical vapor deposition (PVD) or chemical vapor deposition, among other suitable techniques. The second top electrode layer 322 may be formed of an electrically conductive material, such as a metal or semimetal, having a resistance ranging from 1 milliohm-centimeter (mOhm-cm) to 100 mOhm-cm. In some embodiments, the second top electrode layer 322 may include one or more conductive and semiconductive materials, such as carbon (C), carbon nitride (C x N y), n-doped polysilicon and p-doped polysilicon; metals including Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides, and titanium silicides; conductive metal silicide nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN; and conductive metal oxides including RuO2. The second top electrode layer 322 may be suitably integrated into the manufacturing process flow (e.g., etched, cleaned, and sealed) and may exhibit good adhesion to the first top electrode layer 314 and / or the bitline metal 324. In some embodiments, the second top electrode layer 322 may have the same chemical composition as the first top electrode layer 314.In other embodiments, the second top electrode layer 322 may have a different chemical composition than the first top electrode layer 314. In other embodiments, the second top electrode layer 322 may be made of other suitable materials and / or may have other suitable properties.

[0033] In some embodiments, the second top electrode layer 322 may have a thickness in the range of 5 nanometers (nm) to 40 nm. In one embodiment, the second top electrode layer 322 may have a thickness of about 15 nm. In other embodiments, the second top electrode layer 322 may be made of other suitable materials, may be deposited by other suitable techniques, and / or may have a other suitable thickness. The bitline metal 324 may be made of any suitable metal, including, for example, tungsten, and may be deposited using any suitable technique.

[0034] Referring to Fig. 8A-C depicts the PCM device 300 after bitline definition. Bitline definition may be achieved using a patterning process such as lithography and / or etching processes to remove portions of the bitline metal 314, the second top electrode 322, and the stack of layers 306, 308, 310, 312, 314 to expose individual PCM elements 416 from an array of PCM elements on the underlying circuitry 320, as can be seen. Fig. 8A, the bit line metal 314 extends in a direction into and out of the plane of the drawing. In Fig. 8B, the bit line metal 324 is patterned such that the bit line extends in a left-to-right direction across the plane of the drawing perpendicular to the word lines.

[0035] In some embodiments, the second top electrode layer 322 may be disposed on and in direct contact with the first top electrode layer 314, as can be seen. The bitline metal 324 may be disposed on and in direct contact with the second top electrode layer 322. In some embodiments, individual PM elements 416 including the stack of layers (e.g., PM layer 312) may be separated by electrically insulating pillars 420. In the depicted embodiment, the electrically insulating pillars 420 include the dielectric materials 318, 320. As shown in Fig. 8B, material of the second top electrode layer 322 is disposed between the bitline metal 324 and the electrically insulating pillars 420. For example, in the vertical direction (e.g., a direction parallel to a height of the individual PCM element 416), material of the second top electrode layer 322 is disposed directly between the electrically insulating pillars 420 and the bitline metal 324. Material of the first top electrode layer 314 may be disposed directly between (e.g., in a horizontal direction perpendicular to the vertical direction) adjacent pillars of the electrically insulating pillars 420, as can be seen. The material of the first top electrode layer 314 may not be disposed directly between the electrically insulating pillars 420 and the bitline metal 324 in some embodiments.

[0036] Forming the second top electrode layer 322 on the first top electrode layer 314 may increase the overall thickness (e.g., beyond ~15 nm) of the top electrode of the individual PCM elements 416. Techniques and configurations described herein may address challenges associated with increasing the top electrode thickness beyond 15 nm due to the height of the sub-stack to be etched during wordline definition, along with the mechanical weakness of the phase-change material itself and an ability to reliably separate adjacent wordlines. Previously, these challenges may have limited the optimization of the phase-change material operation with respect to programming current and / or the shape of the VI-I characteristic curve.The presently described manufacturing techniques and PCM configurations may provide a thicker top electrode to overcome such limitations to enable further optimization of the operation. For example, a height of the sub-stack to be etched during wordline definition may not be increased. In this way, the mechanical stability of the stack may not be compromised, which may avoid short circuits during wordline definition. In some embodiments, the total thickness of the top electrode (e.g., the thickness of TE1+TE2) may be more than doubled compared to a process forming only TE1. For example, in some embodiments, the total thickness of TE1+TE2 may be approximately 25-40 nm. In some embodiments, the second top electrode layer 322 may provide a reliable continuous etch barrier during bitline definition (e.g.,Etching the bitline metal 324), which may enable the use of a thicker bitline metal 324, which may reduce the bitline resistance for better current delivery throughout the array.

[0037] Referring to Fig. 9A-C depict the PCM device 300 after bit line sealing and filling. As shown in Fig. As shown in Figures 9A-B, a dielectric underlayer 918 may be conformally deposited on the individual PCM elements 416 and on the wordline metal 304. A dielectric fill material 920 may be deposited on the dielectric underlayer 918 to fill a region between the individual PCM elements 416. In some embodiments, the dielectric underlayer 918 and the dielectric fill material 920 may be consistent with the embodiment described in connection with the dielectric underlayer 318 and the dielectric fill material 320, respectively. In other embodiments, the dielectric underlayer 918 and the dielectric fill material 910 may be comprised of suitable dielectric materials other than the materials used for the dielectric underlayer 318 and the dielectric fill material 320.

[0038] Fig. 10A-B illustrate schematic cross-sectional side views of a phase change memory (PCM) device 1000 during manufacture in accordance with some embodiments. For example, the Fig. 10A-B the same stage of production as Fig. 9A-C, that is, after bit line sealing and filling, but for a different area of ​​the PCM device 1000. Fig. 9A-B and Fig. 10A-B may schematically represent cross-sections of a final product according to various embodiments, such as a storage device ready to be sold to a customer.

[0039] The PCM device 1000 may represent a decoding area. The decoding area may share the same level with the individual PCM elements 416 of Fig. 9A together. For example, the PCM device 1000 includes a bit line metal 324 disposed on a second upper electrode layer 322. The bit line metal 324 and the second upper electrode layer 322 of Fig. 10A-B may be on the same level as the bit line metal 324 and the second top electrode layer 322 of Fig. 9A-B. The individual PCM elements 416 of Fig. 9A can be in the plane of the drawing or out of the plane of the drawing relative to the PCM device 1000, which in Fig. 10A is shown.

[0040] The PCM device 1000 may include a bitline via 340 and a wordline via 342 coupled as shown. The bitline via 340 and the wordline via 342 may each represent one of a plurality of vias formed in a decoding region that are in the same plane as the individual PCM elements 416 of Fig. 9A. In some embodiments, the second top electrode layer 322 may be disposed directly between the bitline metal 324 and the bitline via 340, as shown. In some embodiments, the second top electrode layer 322 may be disposed on the dielectric fill material 320, as shown. The dielectric fill material 320 may, in some embodiments, represent multiple layers of dielectric material.

[0041] Barrier pads 337 and 338 may be formed to encapsulate the electrically conductive material of the respective bitline via 340 and wordline via. In some embodiments, the wordline via 342 and the bitline via 340 may each be made of tungsten (W), and the barrier pads 337, 338 may be made of titanium nitride (TiN) or tantalum nitride (TaN). The wordline via 342, the bitline via 340, and the barrier pads 337, 338 may be made of other suitable materials in other embodiments.

[0042] Forming the second top electrode layer 322 as described herein may result in the second top electrode layer 322 being present between the bitline metal 324 and underlying vias (e.g., bitline via 340 and wordline via 342). A thickness of the second top electrode layer 322 may be adjusted to create an adjustable ballast between decoders and cells on the bitline side. In the event that the thickness and / or resistance of the second top electrode layer 322 creates a series resistance that is too high, a loose mask may be introduced to remove the second top electrode layer 322 from the decoding region, possibly by over-etching the vias at the end of the bitline metal etch.If complete symmetry of the carbon morphology is desired for symmetric cell operation, the thickness of the bottom electrode may be adjusted (e.g., by overetching during bitline definition). In some embodiments, the resistance of the second top electrode layer 322 may be less than 20 mOhm·cm and have a thickness less than or equal to about 15 nm to reduce the influence of increasing resistance in the bitline path. For example, for a via area equal to ~30×50 nm, 2 a second top electrode layer 322 having a resistance and thickness as described, adding resistance in the bit line path that is lower than 2 kiloohms (KOhm).

[0043] Fig. 11 is a flow diagram of a method 1100 for manufacturing a PCM device (e.g., PCM device 300 of Fig. 3A-9C) in accordance with some embodiments. The method 1100 may be used with embodiments associated with Fig. 1-10B, and vice versa.

[0044] At 1102, the method 1100 may include providing a substrate (e.g., the substrate 301 of Fig. 3A-B). The substrate may, for example, contain a semiconductor substrate such as a silicon wafer or chip.

[0045] At 1104, the method 1100 may include forming a plurality of phase change memory (PCM) elements on the substrate, wherein individual PCM elements (e.g., individual PCM elements 416 of Fig. 8A-B) from the plurality of PCM elements a phase change material (e.g., the PM layer 312 of Fig. 3A-9C), a first upper electrode layer (e.g., the first upper electrode layer 314 of Fig. 3A-9C) disposed on the phase change layer and in direct contact with the phase change layer, and a second upper electrode layer (e.g., the second upper electrode layer 322 of Fig. 7A-9C) disposed on the first upper electrode layer and in direct contact with the first upper electrode layer.

[0046] According to various embodiments, forming the plurality of PCM elements on the substrate may include forming a stack of layers. For example, the stack of layers may be formed by depositing a wordline layer (e.g., the wordline metal 304 of Fig. 3A-B) on the substrate, applying a lower electrode layer (e.g., the lower electrode layer 306 of Fig. 3A-B) on the word line layer, applying a device selection layer (e.g., the device selection layer 308 of Fig. 3A-B) on the lower electrode layer, applying a middle electrode layer (e.g., the middle electrode layer 310 of Fig. 3A-B) on the device selection layer, applying a phase change material layer (e.g., the phase change material layer 312 of Fig. 3A-B) on the middle electrode layer and applying a first upper electrode layer (e.g., the first upper electrode layer 314 of Fig. 3A-B) are formed on the phase change material layer.

[0047] The stack of layers can be patterned to provide the individual PCM elements. Patterning can include, for example, lithography and / or etching processes. For example, word line definition as used in conjunction with Fig. 4A-C, and / or bit line definition as described in connection with Fig. 8A-C may be executed to provide the individual PCM elements.

[0048] In some embodiments, dielectric material may be deposited to fill a space between the individual PCM elements. For example, a dielectric underlayer (e.g., dielectric underlayer 318) may be conformally deposited on the stack of layers of the individual PCM elements, and a dielectric fill material (e.g., dielectric fill material 320) may be deposited to fill a remaining space between the individual PCM elements.

[0049] In some embodiments, techniques associated with Fig. 5A-C, to apply dielectric material. The dielectric material may be recessed to expose the first upper electrode layer, for example, using techniques used in connection with Fig. 6A-6C. In some embodiments, the second upper electrode layer may be deposited on the first upper electrode layer, for example, using techniques described in connection with Fig. 7A-C. A bit line layer may be deposited on the second upper electrode layer, for example, using techniques associated with Fig. 7A-C.

[0050] Various operations are described as multiple discrete operations in sequence in a manner that is very helpful for understanding the claimed subject matter. However, the order of description should not be interpreted to imply that these operations are necessarily order-dependent. In particular, these operations need not be performed in the order of presentation. Described operations may be performed in a different order than the described embodiment. Various additional operations may be performed, and / or described operations may be omitted in additional embodiments.

[0051] Embodiments of the present disclosure may be implemented in a system using any suitable hardware and / or software to configure it as desired. Fig. 12 schematically illustrates an example system (e.g., a computing device 1200) that includes a PCM device (e.g., the PCM device 300 of Fig. 3A-9C) in accordance with various embodiments described herein. Computing device 1200 may include a circuit board, such as motherboard 1202. Motherboard 1202 may include any number of components, including, but not limited to, a processor 1204 and at least one communication component 1206. Processor 1204 may be physically and electrically coupled to motherboard 1202. In some implementations, at least one communication component 1206 may also be physically and electrically coupled to motherboard 1202. In further implementations, communication component 1206 may be part of processor 1204.

[0052] Depending on its applications, computing device 1200 may include other components that may or may not be physically and electrically coupled to motherboard 1202. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., PCM 1208 or ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display device, a touchscreen display device, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, a mass storage device (such as a hard disk drive, compact disk (CD), digital flexible disk (DVD), and so on).

[0053] According to various embodiments, the PCM 1208 may be consistent with embodiments described herein. For example, the PCM 1208 may be a PCM device (e.g., the PCM device 300 of Fig. 3A-9C) as described here.

[0054] The communication component 1206 may enable wireless communication for transferring data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation over a non-fixed medium. The term does not imply that the associated devices do not include wires, although this may be the case in some embodiments. The communication component 1206 may implement any of a number of wireless standards or protocols, including the Institute of Electrical and Electronics Engineers (IEEE) Standards, Wi-Fi (IEEE 802.11 family), IEEE 802.16 Standards (e.g., IEEE 802.16-2005 Amendment), Long Term Evolution Project (LTE Project), along with any amendments, updates, and / or revisions (e.g.,Evolved LTE project, Ultra Mobile Broadband (UBM) project (also referred to as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformance and interoperability tests for the IEEE 802.16 standards. The communication device 1206 can operate in accordance with a Global System for Mobile (GSM), General Purpose Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.The communication component 1206 may operate in accordance with evolved data for GSM evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or evolved UTRAN (E-UTRAN). The communication component 1206 may operate in accordance with code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), evolution data optimized (EV-DO), derivatives thereof, and also all other wireless protocols referred to as 3G, 4G, 5G, and beyond. The communication component 1206 may operate in accordance with other wireless protocols in other embodiments.

[0055] Computing device 1200 may include multiple communication components 1206. For example, a first communication component 1206 may be dedicated to near-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication component 1206 may be dedicated to wider-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.

[0056] In various implementations, computing device 1200 may be a mobile computing device, a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1200 may be any other electronic device that processes data. EXAMPLES

[0057] According to various embodiments, the present disclosure describes a device. Example 1 of a device may include a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include: a phase-change material layer; a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer; and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Example 2 may include the device of Example 1, wherein the individual PCM elements of the plurality of PCM elements further include a bitline disposed on the second electrode layer and in direct contact with the second electrode layer.Example 3 may include the device of Example 2, wherein the individual PCM elements of the plurality of PCM elements are separated by electrically insulating pillars, and material of the second electrode layer is disposed between the bit line and the electrically insulating pillars. Example 4 may include the device of Example 3, wherein material of the first electrode layer is disposed between adjacent pillars of the electrically insulating pillars. Example 5 may include the device of any of Examples 2-4, wherein the individual PCM elements of the plurality of PCM elements further include: a word line; a device select layer; a third electrode layer disposed between the device select layer and the phase change material layer; and a fourth electrode layer disposed between the word line and the device select layer.Example 6 may include the device of any of Examples 2-4, further comprising a plurality of vias disposed in a decoding region in the same plane as the individual PCM elements, wherein the second electrode layer is disposed between the bitline and a via of the plurality of vias. Example 7 may include the device of any of Examples 1-4, wherein the first electrode layer and the second electrode layer have a different chemical composition, and the first electrode layer and the second electrode layer have a resistance in the range of 1 milliohm-centimeter (mOhm-cm) to 100 mOhm-cm. Example 8 may include the device of any of Examples 1-4, wherein the second electrode layer is configured to serve as an etch stop layer for bitline definition.

[0058] According to various embodiments, the present disclosure describes a method. Example 9 of a method may provide providing a substrate and forming a plurality of phase-change memory (PCM) elements on the substrate, wherein individual PCM elements of the plurality of PCM elements include: a phase-change material layer; a first top electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer; and a second top electrode layer disposed on the first top electrode layer and in direct contact with the first top electrode layer.Example 10 may include the method of Example 9, wherein forming the plurality of PCM elements comprises forming a stack of layers by: depositing a wordline layer on the substrate; depositing a bottom electrode layer on the wordline layer; depositing a device select layer on the bottom electrode layer; depositing a middle electrode layer on the device select layer; depositing the phase change material layer on the middle electrode layer; and depositing the first top electrode layer on the phase change material layer; and patterning the stack of layers to provide individual PCM elements. Example 11 may include the method of Example 10, further comprising depositing dielectric material to fill a region between the individual PCM elements.Example 12 may include the method of Example 11, wherein applying the dielectric material comprises conformally applying a dielectric pad on the individual PCM elements and applying a dielectric material on the dielectric pad to fill the area between the individual PCM elements. Example 13 may include the method of Example 11, further comprising recessing the dielectric material to expose the first top electrode layer. Example 14 may include the method of Example 13, further comprising applying the second top electrode layer on the first top electrode layer. Example 15 may include the method of Example 14, further comprising applying a bitline layer on the second top electrode layer.Example 16 may include the method of Example 15, wherein material of the second upper electrode layer is disposed between the bit line layer and the dielectric material.

[0059] According to various embodiments, the present disclosure describes a system. Example 17 of a system may include a board and a chip coupled to the board, the chip comprising a plurality of phase-change memory (PCM) elements, wherein the individual PCM elements of the plurality of PCM elements include: a phase-change material layer; a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer; and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Example 18 may include the system of Example 17, wherein the individual PCM elements of the plurality of PCM elements further include a bitline disposed on the second electrode layer and in direct contact with the second electrode layer.Example 19 may include the system of Example 18, wherein the individual PCM elements from the plurality of PCM elements are separated by electrically insulating pillars, and material of the second electrode layer is disposed between the bit line and the electrically insulating pillars. Example 20 may include the system of any of Examples 17-19, wherein the system is a mobile computing device including one or more of an antenna, a display device, a touchscreen display device, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled to the circuit board.

[0060] Various embodiments may include any suitable combination of the embodiments described above, including alternative (or) embodiments of embodiments described in the subjunctive (and) form above (e.g., the "and" may be "and / or"). Furthermore, some embodiments may include one or more products (e.g., non-transitory computer-readable media) having stored thereon instructions that, when executed, result in actions of any of the embodiments described above. Furthermore, some embodiments may include devices or systems having any suitable means for performing the various operations of the embodiments described above.

[0061] The foregoing description of illustrated implementations, including what is described in the abstract, is not intended to be exhaustive or to limit embodiments of the present disclosure to the precise forms disclosed.

[0062] These modifications may be made to embodiments of the present disclosure in light of the foregoing detailed description. The terms used in the following claims should not be construed to limit the various embodiments of the present disclosure to the specific implementations disclosed in the specification and claims.

Claims

[1] Device comprising: a plurality of phase change memory elements, wherein individual phase change memory elements of the plurality of phase change memory elements include: a phase change material layer; a first electrode layer disposed on the phase change material layer and in direct contact with the phase change material layer; a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer; and a bit line disposed on the second electrode layer and in direct contact with the second electrode layer; wherein the individual phase-change memory elements from the plurality of phase-change memory elements are separated by electrically insulating pillars; and material of the second electrode layer is arranged between the bit line and the electrically insulating pillars. [2] The device of claim 1, wherein material of the first electrode layer is disposed between adjacent columns of the electrically insulating columns. [3] The device according to any one of claims 1-2, wherein the individual phase change memory elements of the plurality of phase change memory elements further include: a word line; a device selection layer; a third electrode layer disposed between the device selection layer and the phase change material layer; and a fourth electrode layer disposed between the word line and the device selection layer. [4] The device of any one of claims 1-2, further comprising: a plurality of vias arranged in a decoding region that is in the same plane as the individual phase change memory elements, wherein the second electrode layer is arranged between the bit line and a via of the plurality of vias. [5] Device according to one of claims 1-2, wherein: the first electrode layer and the second electrode layer have a different chemical composition; and the first electrode layer and the second electrode layer have a resistance in the range of 1 mOhm·cm to 100 mOhm·cm. [6] The device of any one of claims 1-2, wherein the second electrode layer is configured to serve as an etch stop layer for bit line definition. [7] Procedure comprising: Providing a substrate; and Forming a plurality of phase change memory elements on the substrate, wherein individual phase change memory elements of the plurality of phase change memory elements include: a phase change material layer; a first upper electrode layer disposed on the phase change material layer and in direct contact with the phase change material layer; a second upper electrode layer disposed on the first upper electrode layer and in direct contact with the first upper electrode layer; and a bit line arranged on the second electrode layer and in direct contact with the second electrode layer; wherein the individual phase change memory elements from the plurality of phase change memory elements are separated by electrically insulating columns; and Material of the second electrode layer is arranged between the bit line and the electrically insulating columns. [8] The method of claim 7, wherein forming the plurality of phase change memory elements comprises: Forming a stack of layers by: Applying a word line layer to the substrate; Applying a lower electrode layer on the word line layer; Applying a device selection layer on the bottom electrode layer; Applying a middle electrode layer on the device selection layer; Applying the phase change material layer on the middle electrode layer; and Applying the first top electrode layer on the phase change material layer; and patterning the stack of layers to provide individual phase change memory elements. [9] The method of claim 8, further comprising: Applying dielectric material to fill an area between the individual phase change memory elements. [10] The method of claim 9, wherein applying the dielectric material comprises: conformal application of a dielectric substrate to the individual phase change memory elements; and Applying a dielectric material to the dielectric substrate to fill the area between the individual phase change memory elements. [11] The method of claim 9, further comprising: Deepening the dielectric material to expose the first top electrode layer. [12] The method of claim 11, further comprising: Applying the second upper electrode layer on the first upper electrode layer. [13] The method of claim 12, further comprising: Applying the bit line layer on the second upper electrode layer. [14] The method of claim 13, wherein material of the second upper electrode layer is disposed between the bit line layer and the dielectric material. [15] System comprising: a circuit board; and a chip coupled to the board, the chip comprising: a plurality of phase change memory elements, wherein individual phase change memory elements of the plurality of phase change memory elements include: a phase change material layer; a first electrode layer disposed on the phase change material layer and in direct contact with the phase change material layer; a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer; and a bit line arranged on the second electrode layer and in direct contact with the second electrode layer, where the individual phase change memory elements from the plurality of phase change memory elements are separated by electrically insulating columns; and Material of the second electrode layer is arranged between the bit line and the electrically insulating columns. [16] The system of claim 15, wherein the system is a mobile computing device including one or more of an antenna, a display device, a touchscreen display device, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled to the board.

Images