Voltage-proof switch

Abstract

Voltage-resistant switch (10) comprising: a signal input (20); a first FET transistor (30) having a first channel with a first drain terminal (32) with an extended drain, and a first gate terminal (34), wherein the first drain terminal (32) is formed from a higher p-doped region in a p-doped well; a second FET transistor (40) having a second channel with a second drain terminal (46) having an extended drain, and a second gate terminal (44), the second drain terminal (46) being formed from a higher p-doped region in a p-doped well; a control signal terminal (60) connected via a second node (55) to the first gate terminal (34) and the second gate terminal (44) and via a second resistor (53) to the first channel and the second channel; and a signal terminal (70) connected to the second channel.

Description

The invention relates to a voltage-proof switch and to a circuit with the voltage-proof switch.In the case of MOS components, the progressive reductions in the structures of the components and the associated smaller oxide thicknesses at the gate connections result in the problem that the supply voltage V dd for modern circuits has to be reduced ever further. In such circuits, too high supply voltages can lead to damage or even to destruction of the MOS components as a result of the change in the electrical properties.The voltage stability with respect to the drain-source contacts along the channel in so-called high-voltage MOS transistors is substantially achieved by low-doped drift regions. In order not to deteriorate the electrical characteristics of the MOS transistors, the oxide thickness cannot be increased arbitrarily for improving the withstand voltage. In order to be able to switch on a voltage signal with a MOS transistor as far as possible without influencing, the value of the gate potential must be greater than the drain or source potential, taking into account the threshold voltage of the MOS transistor, for example in the case of an NMOS transistor.In some circuits, however, it is often necessary to switch voltages which are greater than the maximum gate-source voltage which is technically permissible. In this case, the maximum permissible gate-source voltage can be exceeded, which can lead to damage or destruction of the MOS transistor. One such example is a programmable EEPROM circuit having a signal input, in which the maximum value of the input signal at the signal input is 5 V in the control mode, but can assume a value of +12 V / -12 V in the programming / erasing mode. The individual components of the circuit are dimensioned such that these components also withstand a maximum value of 5 V and must thus be protected from an input signal with a voltage of >5.5 V.From German Offenlegungsschrift No. DE 1 03 58 048 A1 (Biotronic) discloses a voltage-proof switch which has a switching control unit with a control input and a fuse output which is connected to a switching input of a fuse switch. This fuse switch is arranged and designed in such a way that the fuse switch electrically connects the gate terminal of a first MOS switching transistor to the source terminal of the first MOS switching transistor as a function of a fuse signal when the switching control unit outputs the fuse signal to the fuse input of the fuse switch, wherein the switching control unit is designed to generate and output this fuse signal.U.S. Patent No. US 7 835 126 B2 (Kyocera) discloses a short circuit protection circuit for an internal current source which can be connected to an external unit. The output is provided with two MOS transistors which are conductive in the regulating mode. Upon the occurrence of a short circuit, the voltage at one of the gates of a MOS transistor is increased and the MOS transistor is turned off, i.e. the MOS transistor is no longer conductive. The internal current source is thereby insulated and damage is thus largely avoided.Further, U.S. Patent No. U.S. Pat. No. 6,424,035 B1 describes a switch having a signal input, a first FET transistor and a second FET transistor, and a control signal terminal which is connected via a second node to the first gate terminal and the second gate terminal and via a second resistor to the first channel and the second channel of the first and second FET transistors.The invention will now be described in more detail with reference to figures. The following are shown: FIG. 1 is a schematic circuit diagram of a voltage-proof switch; FIG. 2 schematically shows a second aspect of the circuit arrangement of the voltage-proof switch. FIG. 3 schematically shows a third aspect of the circuit arrangement of the voltage-proof switch. FIG. 4 schematically shows a fourth aspect of the circuit arrangement of the voltage-proof switch; and FIG. 5 shows a section through a single-ended HV PMOS transistor.FIG. 1 schematically shows the circuit arrangement of a voltage-proof switch 10 with a signal input 20, to which an input signal V PAD is applied. The signal input 20 is a so-called pad on a semiconductor chip and can be connected to a plurality of circuits on the semiconductor chip. The voltage-proof switch 10 can be switched on and off via a signal V inon at a control signal terminal 60.For example, an EEPROM circuit comprises circuits which are used for programming the EEPROM circuit and require the input signal V PAD with a higher voltage of e.g. 12 V for programming. The programmed circuits receive an input signal with a maximum value of 5V during the control operation. These programmed circuits are damaged when the input signal V PAD having a higher value, e.g., > 5.5V, is applied. It is therefore necessary either to provide two different types of terminals on the semiconductor chip or to build a voltage resistant protection circuit which prevents the propagation of a signal of a value of 12 V to the programmed circuits.The structure of the voltage-proof switch 10 according to the present invention will now be described. The values and dimensions of the individual components specified in this description are merely exemplary and do not limit the invention.The switching function of the voltage-proof switch 10 is realized from a first FET transistor 30 and a second FET transistor 40 and switched via the control signal terminal 60. The signal input 20 is connected via an input resistor 25 to the first drain terminal 32 of the first FET transistor 30, wherein the input resistor 25 serves mainly as electrostatic discharge protection. The input resistance 25 has a value of 5 kΩ, for example. The first FET transistor 30 is a PMOS transistor and has an extended drain terminal 32 (so-called "extended drain"), and thus can withstand an applied voltage of +12V.In one aspect, the first FET transistor 30 and the second FET transistor 40 are each formed as a HV PMOSFET (high voltage P-channel MOSFET) transistor 500 illustrated in FIG. 5. HV PMOSFET transistors 500 have a p-doped substrate 510 with an n-doped well 520 and typically have five terminals 530: a drain terminal 530d, a gate terminal 530g, a source terminal 530s, at least one bulk terminal 530b and a substrate terminal 530t. A PMOS transistor having the drain terminal 530 d, the gate terminal 530 g, and the source terminal 530 sis formed in the n-type well 520. The drain terminal 530 dis formed from a higher p-doped region 540 in a p-doped well 550. Due to the lower doping in the p-doped well 550, the drain terminal 530 dis more voltage-proof.The first drain terminal 32 (corresponding 530 din FIG. 5 ) of the first FET transistor 30 in FIG. 1 is connected to a first bulk terminal 35 (corresponding 530 bin FIG. 5 ) of the first FET transistor 30 via a high-impedance first resistor 38. This first resistor 38 has a value of 20 kΩ, for example, and together with the input resistor 25 protects the first FET transistor 30 when a voltage of -12 V is applied.The first source terminal 36 is connected to a first node 50, which in turn is connected to a second source terminal 42 of the second FET transistor 40. As mentioned above, the first FET transistor 30 and the second FET transistor 40 together form a switch which is turned on and off by a control signal V inon at a control signal terminal 60. The second FET transistor 40 is also a PMOS transistor and also has a second gate terminal 44 and a second drain terminal 46. The second drain terminal 46 is connected to a signal terminal 70 for the input signal V in for the programmed circuit. The second bulk terminal 45 and the second source terminal 42 are also connected to each other, this connection having no appreciable resistance. The second drain terminal 46 also has an additional well (so-called "extended drain 520 in FIG. 5 ) and can thus withstand higher voltages.The first gate terminal 34 is connected to the second gate terminal 44 via a second node 55. A second resistor 53 is arranged between the first node 50 and the second node 55. The second resistor 53 has a value of 50 kΩ, for example. A third FET transistor 62 having a third gate terminal 64 is connected between the second node 55 and the zero line (ground) 66. The third FET transistor 62 is formed as a high voltage N-channel (MOSFET) transistor in one aspect. The third gate terminal 64 is connected to the control signal terminal 60 to which the control signal V inon for turning on and off the voltage-proof switch 10 is applied. Thus, the third FET transistor 62 is turned on and off by the control signal V inon and the drain in the off state must withstand the voltage of the signal input 20 (12 V).A third node 75 is arranged between the signal terminal 70 and the second drain terminal 46. A fourth FET transistor 80 is disposed between the third node 75 and the zero line in this aspect of the voltage-proof switch 10. The fourth FET transistor 80 has a fourth gate terminal 84 connected to a gate signal. A bulk terminal 85 of the fourth FET transistor 80 is connected to the zero line. The channel of the fourth FET transistor 80 is connected between the third node 75 and the zero line.The gate signal at the gate terminal 84 may be a pulse signal or the supply voltage V dd( FIG. 2 ). This gate terminal 84 can also be driven with the control signal terminal 60 via an inverter 87 (FIG. 1 ) or connected to the supply voltage V dd( FIG. 2 ) via a fifth PMOS transistor 90.The operation of the voltage-proof switch 10 will now be described. In the off state, the control signal V inon at the control signal terminal 60 is off (i.e., V inon=0) and the third FET transistor 62 is thus also "off", i.e., high impedance. The second resistor 53 also makes the first FET transistor 30 and the second FET transistor 40 turned off because the respective gate-source voltages of the first FET transistor 30 and the second FET transistor 40 are 0V. The voltage at the first gate terminal 34 of the first FET transistor 30 thus follows the input signal V PAD on the signal input 20, specifically up to a voltage which corresponds to the breakdown voltage of the two FET transistors 30 and 40. Due to the extended drain at the first drain terminal 32, the breakdown voltage is greater than 12 V and is, for example, 18 V.In the reverse connection, at a voltage between 0 and -12V in the off state, the n-well 520 of the first drain terminal 32 conducts (corresponds to 530 din FIG. 5 ). In this case, the current flows through a diode formed by the n-well 520 and the p-substrate 510. The voltage at the first bulk terminal 35 ( 530 b) is clamped to approximately 0.75 V and the current is limited to approximately 0.5 mA at a voltage of -12 V due to a corresponding dimensioning by the input resistor 25 and the first resistor 38. This small current does not damage the first FET transistor 30 (and also the second FET transistor 40).Note that the protection is also given in the case of a voltage of -12V in an on state. A voltage of +12V does not occur in the on state.In another aspect of the voltage-proof switch 10 shown in FIG. 2, a fourth gate terminal 84 of the fourth NMOS FET transistor 80 is connected to a drain terminal of a fifth PMOS FET transistor 90. A fifth gate terminal 94 of the fifth FET transistor 90 is connected to the ground 66, and thus the fifth FET transistor 90 is conductive. The fourth gate terminal 84 is connected to the supply voltage V dd via the fifth FET transistor 90, and the fourth FET transistor 80 is therefore turned on and operates like a resistor having a value of about 200 kΩ (like resistor 88 in FIG. 3 ).A third aspect of the voltage-proof switching 10 is illustrated in FIG. 3. Instead of the fourth FET transistor 80, a high-resistance resistor 88 is used. In a fourth aspect (FIG. 4 ) of the voltage-proof switch 10, the fourth FET transistor 80 is removed without replacement.In the switched-on state, the control signal V inon is high and the voltage-proof switch 10 can transmit the input signal V PAD with an input voltage at the signal input 20 of 1 V to 5 V. The lower voltage value of 1V is mainly limited by the threshold voltage of the first FET transistor 30 and the second FET transistor 40. The second resistor 38 is selected to have a high impedance (e.g. 20 kΩ) and thus the voltage drop across the third FET transistor 62 is low. The voltage drop across the input resistor 25 and across the first FET transistor 30 is also small. This arrangement brings about a voltage divider function of the voltage-proof switch 10, which functions to attenuate the input voltage at the signal input 20, which is forwarded to the signal connection 70.In the exemplary dimensioning of this embodiment, the input voltage at the signal input 20 is "attenuated" according to one of the following equations.Without fourth FET transistor 80R m80:With fourth FET transistorR m80: having the exemplary values:R is R25=5 kohm (value of input resistor 25)R is R53=50 kohm (value of the second resistor 53)(Value of Channel Resistance of First FET Transistor 30 in Conductive State)(Value of Channel Resistance of Third FET Transistor 30 in Conductive State)(Value of Channel Resistance of First FET Transistor 30 in Conductive State)(Value of Channel Resistance of Fourth FET Transistor 30 in Conductive State)The following "attenuation" results:V. Vpad is the voltage at the signal input and V in1 or V in2 are the voltages at the signal terminal 70.Reference numerals denote reference numerals10 Voltage-proof switch 20 Signal input 25 Input resistance 30 First FET transistor 32 First drain terminal 34 First gate terminal 35 First bulk terminal 36 First source terminal 38 First resistor 40 Second FET transistor 42 Second source terminal 44 Second gate terminal 45 Second bulk terminal 46 Second drain terminal 50 First node 53 Second resistor 55 Second node 60 Control signal terminal 62 Third FET transistor 64 Third gate terminal 66 Zero line 70 Signal terminal 75 Third node 80 Fourth FET transistor 82 Fourth drain terminal 84 Fourth gate terminal 85 Fourth bulk terminal 86 Fourth source terminal 87 Inverter 88 High-resistance resistor 90 Fifth FET transistor 92 Fifth source terminal 94 Fifth gate terminal 96 Fifth drain terminal 500 PMOSFET transistor 510 P-doped substrate 520 N-doped well 530B Bulk terminal 530D Drain terminal 530 g Gate terminal 530S Source terminal 530T Substrate terminal 540 P-doped region 550 P-doped well

Claims

A voltage-proof switch (10) comprising: a signal input (20); a first FET transistor (30) having a first channel with a first drain terminal (32) having an extended drain, and a first gate terminal (34), the first drain terminal (32) being formed from a higher p-doped region in a p-doped well; a second FET transistor (40) having a second channel with a second drain terminal (46) having an extended drain, and a second gate terminal (44), the second drain terminal (46) being formed from a higher p-doped region in a p-doped well; a control signal terminal (60) connected to the first gate terminal (34) and the second gate terminal (44) via a second node (55) and to the first channel and the second channel via a second resistor (53); and a signal terminal (70) connected to the second channel.The voltage-proof switch (10) of claim 1, wherein the control signal terminal (60) comprises a third FET transistor (62) disposed between the second node (55) and a zero line (66), and has a third gate terminal (64) connected to a control signal (V inon).Voltage-proof switch (10) according to one of the preceding claims, wherein the first FET transistor (30) has, with the first drain terminal (32), a first source terminal (36) and a first bulk terminal (35), wherein the first drain terminal (32) is connected to the signal input (20) and the first source terminal (36) is connected to the second channel of the second FET transistor (40), and the first channel runs between the first drain terminal (32) and the first source terminal (36).The voltage-proof switch (10) according to claim 3, wherein the first bulk terminal (35) is connected to the first drain terminal (32) via a first resistor (38).Voltage-proof switch (10) according to one of the preceding claims, wherein the second FET transistor (40) has, with the second drain terminal (46), a second source terminal (42) and a second bulk terminal (45), wherein the second drain terminal (32) is connected to the signal terminal (70) and the second source terminal (42) is connected to the first channel of the first FET transistor (30) and the second channel runs between the second drain terminal (46) and the second source terminal (42).The voltage-proof switch (10) of claim 5, wherein the second bulk terminal (45) is connected to the second drain terminal (42).Voltage-proof switch (10) according to one of the preceding claims, wherein an input resistor (25) is connected between the signal input (20) and the first FET transistor (30).Voltage-proof switch (10) according to one of the preceding claims, wherein a third node (75) between the second channel and the signal terminal (70) is connected to a fourth FET transistor (80), and wherein the fourth FET transistor (80) comprises a fourth drain terminal (82) connected to the third node (75), a fourth source terminal (86) connected to the zero line (66) and a fourth gate terminal (84) to which a further signal can be applied.The voltage-proof switch (10) according to any one of claims 2 to 8, wherein a third node (75) between the second channel and the signal terminal (70) is connected to a fourth FET transistor (80), and wherein the fourth FET transistor (80) comprises a fourth drain terminal (82) connected to the third node (75), a fourth source terminal (86) connected to the third FET transistor (62) via the zero line (66), a fourth gate terminal (84) connected to a fifth FET transistor (90) via the fifth drain terminal (96), and wherein the fifth FET transistor (90) comprises a fifth gate terminal (94), which is connected to the third FET transistor (62) via the zero line (66) and has a fifth source terminal (92) which is connected to a supply voltage (V dd).

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