Method for producing microelectromechanical structures in a layer sequence and a corresponding electronic component with a microelectromechanical structure

Abstract

Method for producing microelectromechanical structures (ME1) in a layer sequence with the steps: Providing a carrier substrate (T1) having a first surface (10); Applying an insulating layer (I1) to the first surface (10); Epitaxial growth of a first silicon layer (S1) on the insulation layer (I1); Structuring the first silicon layer (S1) to form trenches (G) in the first silicon layer (S1), wherein the trenches (G) extend at least partially through the first silicon layer (S1); Passivating the first silicon layer (S1), wherein the trenches (G) are filled and a passivation layer (P) is formed on a side facing away from the first surface (10); Structuring the passivation layer (P), wherein sacrificial regions (O1) and functional regions (F1) are formed in the first silicon layer (S1), and the sacrificial regions (O1) on a side of the first silicon layer (S1) facing away from the carrier substrate (T1) are at least partially free of the passivation layer (P); and Removing the sacrificial areas (O1), wherein the steps of epitaxial growth, structuring and passivation of the first silicon layer and structuring of the passivation layer (P) are repeated before removing the sacrificial regions (O1), and the formation of further sacrificial regions (O2, O3, O4) and further functional regions (F2, F3, F4) depends on the structuring of the further silicon layers (S2, S3, S4) and the further passivation layers (P), characterized in that silicon nitride is used as a dielectric to produce mechanical connections with simultaneous electrical insulation between vertically stacked functional areas.

Description

[0001] The present invention relates to a method for producing microelectromechanical structures in a layer sequence and a corresponding electronic component with a microelectromechanical structure. State of the art

[0002] Although the method described here is applicable to any microelectromechanical structures, the present invention and the problem underlying it are explained using silicon-based MEMS structures (“microelectromechanical systems”).

[0003] Particularly for use in acceleration sensors or angular rate sensors based on capacitive measurement methods (capacitive MEMS) or in electrostatically driven microactuators (e.g., micromirrors), microelectromechanical structures essentially comprise one or more conductive functional layers containing fixed and movable regions. Movable regions are fixed during manufacturing by a so-called sacrificial layer, which is selectively removed at the end of the manufacturing process.

[0004] DE 10 2009 045 385 A1 describes a method for closing a trench of a micromechanical component.

[0005] US 2013 / 0115775 A1 describes a method for forming sacrificial areas.

[0006] DE 10 2006 032 195 A1 describes a method for producing MEMS structures.

[0007] DE 10 2009 029 202 A1 describes a micromechanical system and a method for producing a micromechanical system.

[0008] The documents US 2009 / 0325335 A1 and DE 10 2005 007 540 A1 describe methods for producing microelectromechanical structures in a layer sequence, which partially have features of the method for producing microelectromechanical structures in a layer sequence according to claim 1.

[0009] In particular, the production of large sacrificial cavities is difficult, since, for example, the deposition of correspondingly thick sacrificial layers can result in undesirable deformation of a carrier substrate. This undesirable deformation can be compensated for by complex and costly additional stress-compensating layers. Disclosure of the invention

[0010] The present invention provides a method for producing microelectromechanical structures in a layer sequence having the features of claim 1 and a corresponding electronic component having the features of claim 11.

[0011] Preferred further training is the subject of the respective subclaims. Advantages of the invention

[0012] In particular, the present invention provides a method for producing, for example, complex MEMS structures with high efficiency in a small space. In particular, the method is suitable for producing particularly small MEMS structures and thus meets the required miniaturization.

[0013] In particular, one idea of ​​the invention is to create multilayer MEMS functional structures with a large vertical dimension, for example, greater than 50 micrometers, using the method according to the invention. In particular, the method should also make it possible to provide very large-volume sacrificial layer blocks or sacrificial layer regions that can be removed accordingly, as well as to design mechanical and electrical connections and separations freely and independently of one another.

[0014] In particular, the invention provides a CMOS- and high-temperature-compatible process for producing multilayer or multi-layer MEMS structures made of silicon. In this case, both the functional regions and the sacrificial regions comprise the silicon. This makes it possible, in particular, to simultaneously structure functional regions and sacrificial regions in the same process step and to separate them from one another using passivation layers or insulation layers. The resulting sacrificial regions can be removed, for example, by gas-phase etching after completion of the process for producing microelectromechanical structures.

[0015] For example, the method is suitable for producing multilayer systems with large vertical dimensions and offers the possibility of eliminating wafer bonding. The method according to the invention allows the stacked alternating layer sequences of silicon and passivation layer to be aligned with each other with particular precision.

[0016] Each layer level can be structured and designed independently of the levels above or below it. Interlocking or overlapping functional areas are also possible, particularly with regard to vertical extension. The method also allows for the free definition of electrical connections / insulation and mechanical connections / insulation independently within the functional areas.

[0017] By passivation techniques such as thermal oxidation and / or tetraethylorthosilicate (TEOS) deposition, silicon carbide (SiC) deposition, silicon carbonitride (SiCN) deposition, silicon nitride (Si x N y ) deposition or silicon oxynitride (SiON) deposition protects areas of the silicon layer that are not to be etched from the etching attack. The areas of the silicon layer, i.e., the sacrificial areas, with access to the etching medium are, for example, completely etched. For many applications, it is advantageous to remove an oxide passivation layer after removing or etching the sacrificial areas using HF vapor-phase etching.

[0018] According to the invention, the process steps of epitaxial growth, structuring, and passivation of the first silicon layer and structuring of the passivation layer are repeated before removing the sacrificial regions, and the formation of further sacrificial regions and further functional regions depends on the structuring of the additional silicon layers and / or the additional passivation layers. Thus, a functional layer sequence can be produced in a simple manner. Furthermore, the stacked layers can be precisely aligned with one another.

[0019] According to a further preferred development, after the removal of the sacrificial regions, the passivation layer is removed at least in places. This is possible because the method according to the invention advantageously allows the functional regions to be completely fixed to one another. For example, the removal of the passivation layer or the oxide can be performed by gas-phase etching, plasma etching, and / or wet etching. In other words, the passivation layer can be removed particularly easily. Furthermore, the passivation layer or the oxide can be completely removed by etching.

[0020] According to a further preferred development, the epitaxial growth of the first silicon layer takes place on a SOI (silicon-on-insulator) substrate, or the SOI substrate comprises the first silicon layer. In other words, the SOI substrate has a layer thickness such that its uppermost silicon layer can function as the first silicon layer. This has the advantage that the first silicon layer can, in particular, be monocrystalline. Furthermore, wiring layers, for example, are located on the insulating material of the SOI, resulting in shorter switching times and lower power consumption, particularly with regard to leakage currents.

[0021] According to a further preferred embodiment, the epitaxially grown silicon layer comprises a single-crystalline, polycrystalline, and / or epi-polycrystalline silicon layer. Epi-polycrystalline silicon layers are extremely thick polysilicon layers with thicknesses of up to several tens of micrometers. This has the advantage that the method according to the invention can be used for a variety of coating systems.

[0022] According to a further preferred development, the layer thickness of the epitaxially grown silicon layer is between 0.5 and 100 micrometers. The layer preferably has a thickness of 20 to 60 µm. In the present context, "thickness" refers to a vertical extent of a layer. "Vertical" refers to a direction that extends transversely, in particular perpendicularly, with respect to a plane. In particular, large-volume sacrificial regions can be produced, while simultaneously preventing bending or deformation of the carrier substrate due to stress.

[0023] According to a further preferred development, the insulation layer functions as an etch stop layer. This is advantageous because, in particular, the formation of the trenches in the epitaxially grown silicon layer can be carried out particularly easily. The use of etch stop layers makes it possible to dispense with complex and, in particular, highly fluctuating time-dependent etching processes.

[0024] According to a further preferred development, the trenches are formed using a trench process. Trenches with a width of 1 to 4 micrometers are particularly advantageous. These are passivated by thermal oxidation and / or closed or filled by TEOS deposition. Furthermore, plasma-free etching processes can also be used. For example, plasma-free etching processes are advantageous for epitaxially grown thin silicon layers with a thickness of a few micrometers.

[0025] According to a further preferred embodiment, the passivation layer is structured using a dry etching process and / or a wet etching process. This makes it possible to remove the passivation layer particularly easily without having to resort to a specific etching process.

[0026] According to a further preferred development, after the epitaxial growth of the silicon layer, chemical-mechanical polishing and / or additional doping by implantation or coating are performed. This allows, in particular, the topological irregularities or height differences arising during the epitaxial growth of the silicon layer to be easily planarized. The additional doping by implantation or coating allows a specific resistance to be easily adjusted in the silicon layer.

[0027] According to a further preferred development, the sacrificial areas are removed by plasma-free and / or plasma-assisted etching. Thus, the sacrificial areas can be removed particularly easily without the use of special etching processes. Plasma-free etching can be carried out, for example, by chlorine trifluoride (ClF 3 ), chlorine fluoride (ClF), chlorine pentafluoride (ClF 5), bromine trifluoride (BrF 3 ), bromine pentafluoride (BrF 5 ), iodine pentafluoride (IF 5 ), Iodine heptfluoride (IF 7 ), sulfur tetrafluoride (SF 4 ), xenon difluoride (XeF 2 ) or similar substances. Plasma-assisted etching can be performed, for example, using fluorine plasma, chlorine plasma, and / or bromine plasma. In particular, etching can also be based on a combination of plasma-free and plasma-assisted etching.

[0028] The features disclosed for the method described here also apply to an electronic component manufactured by this method and vice versa. Short description of the drawings

[0029] Further features and advantages of the present invention are explained below using embodiments with reference to the figures.

[0030] They show: Fig. 1-11 are schematic cross-sectional views for explaining a method for producing microelectromechanical structures in a layer sequence according to an embodiment of the present invention; Fig. 12 is a schematic flow diagram for explaining a method according to an embodiment of the present invention for producing microelectromechanical structures in a layer sequence. Embodiments of the invention

[0031] In the figures, the same reference symbols denote the same or functionally identical elements.

[0032] Fig. 1 to 11 show schematic cross-sectional views to explain a method for producing microelectromechanical structures in a layer sequence according to an embodiment of the present invention.

[0033] In Fig. 1, reference symbol T1 denotes a carrier substrate with a first surface 10. In particular, insulation layers I1, I1' or dielectric layers can be deposited on the first surface 10 of the carrier substrate T1. The carrier substrate or the insulation layer I1, I1' of the Fig. 1 further comprise a wiring layer V1.

[0034] A first silicon layer S1 is epitaxially grown on the insulation layers I1, I1'. The epitaxially grown first silicon layer S1 can be undoped, p-doped, or n-doped. The thickness of the first silicon layer S1 can, for example, be between a few hundred nanometers and greater than or equal to 100 micrometers. The thickness of the epitaxially grown silicon layer depends essentially on the desired height of a layer sequence, whereby each silicon layer S1 to S4 can be divided into sacrificial regions O1 or O4 and functional regions F1 to F4 (see Fig. 9 to 11). Furthermore, after the epitaxial growth of the first silicon layer S1, a planarization of a topology or roughness can be carried out by means of CMP (chemical mechanical polishing) and / or additional doping to adjust a specific resistance.

[0035] Alternatively, the first silicon layer S1 can be grown epitaxially on an SOI (silicon-on-insulator), which makes the application of the insulation layers I1, I1' unnecessary.

[0036] In Fig. 2, reference symbol G denotes trenches. The formation of the trenches G can be achieved by a trenching process. The resulting trenches G are preferably arranged above the insulation layer I1, I1', wherein the insulation layer I1' can function, in particular, as an etch stop layer.

[0037] In Fig. 3, reference symbol P denotes a passivation layer which forms during passivation of the first silicon layer S1, wherein the trenches G are filled and a passivation layer P is formed on a side facing away from the first surface 10.

[0038] In Fig. 4, the passivation layer P is structured, wherein sacrificial regions O1 and functional regions F1 are formed in the first silicon layer S1, wherein the sacrificial regions O1 are at least partially free of the passivation layer P on a side facing away from the carrier substrate T1 (see Fig. 9). The locations in a third dimension, which can be free of the passivation layer, are shown in the two-dimensional representation of the Fig. 4. However, it goes without saying that these can be located in the third dimension of the microelectromechanical structure.

[0039] In other words, sacrificial regions O1 and functional regions F1 are separated from each other by suitably narrow trenches G. Sacrificial regions are removed by subsequent sacrificial region or sacrificial layer etching, while functional regions or functional elements remain intact after sacrificial region structuring or sacrificial layer structuring. The lateral extent or width of the trenches depends on the subsequent passivation or sealing technology. Narrow trenches between 1 and 4 micrometers are advantageous; these are passivated by thermal oxidation and / or closed / filled by TEOS deposition. This means that by structuring the passivation layers P, contact points can be created between a surface of the silicon layer S1 and the subsequent silicon layers S2, S3, S4.These contact points serve either for electrical or mechanical contact or for connecting two sacrificial silicon regions or silicon sacrificial planes. Depending on the etching medium, the etching rate differences between the silicon layers S1, S2, S3, S4 and the passivation layer P vary, so alternative passivation materials, such as Si, are also possible. x N y , SiC, SiCN or SiON.

[0040] In particular, in the areas free of the passivation layer P, i.e., the silicon surface, the contact can be established by CVD (chemical vapor deposition) polysilicon deposition. The polysilicon can serve as a thin wiring layer or as a starting layer for thicker epitaxial silicon layers or epi-polysilicon layers. Alternatively, direct epitaxial growth can be performed without a polysilicon layer by choosing a process that allows for spontaneous crystallization nuclei to form.

[0041] In Fig. 5 to 8 are the ones created by means of the Fig. 1 to 4 are repeated accordingly, whereby a second or n-th epitaxially grown silicon layer S2, ..., S n trained.

[0042] It should be mentioned that, in particular, increased roughness or unevenness that develops during epitaxial deposition of thicker silicon layers, as already described above, can be advantageously reduced or planarized by a CMP process (see Fig. 5 and Fig. 6). Existing silicon layers can be modified in their electrical conductivity by suitable doping processes, for example in situ or by implantation or coating. As described in the Fig. 7 and Fig. As shown in Figure 8, the existing second silicon layer S2 can now be divided into sacrificial regions O2 and functional regions F2 by structuring or forming trenches, independently of the underlying division of the first silicon layer S1.

[0043] In Fig. 9, the reference symbols S1, S2, S3, S4 denote epitaxially grown silicon layers produced according to the method according to the invention. By the above-described structuring of the corresponding silicon layers S1 to S4 and their passivation, Fig. 10, sacrificial regions O1 and O4, respectively, which can be removed by etching. Accordingly, the silicon levels comprise the silicon layers S1 to S4, with each silicon layer S1 to S4 having sacrificial regions O1 to O4 and functional regions F1 to F4 per level, respectively.

[0044] The Fig. 11 differs from the Fig. 10 by additionally removing the passivation layer P by an etching process. As in the Fig. As shown in Figure 11, the functional areas F1 to F4 are fixed to one another in such a way that the microelectromechanical structure ME1 is maintained even without the passivation layer P.

[0045] It goes without saying that a division into sacrificial regions O1 to O4 and functional regions F1 to F4 of the epitaxially grown silicon layers S1 to S4 described here is not mandatory. Rather, each of the silicon layers S1 to S4 can also function entirely as a functional region or functional layer. Determining or defining sacrificial regions depends on the desired microelectromechanical structure of the layer sequence and its subsequent function.

[0046] In order to realize mechanical connections with simultaneous electrical insulation in the functional areas, for example for wiring levels, the invention provides for the use of a second dielectric, which ideally is not or only very slightly attacked during the etching of the passivation layer (P) or the silicon layers S1 to S4. When using F-plasma / XeF 2and HF as etching media, silicon nitride is a suitable alternative to an oxide as a second dielectric. Silicon nitride components must be coated similarly to the functional areas in front of XeF 2 protected with the passivation layer P. Depending on the selectivity towards the etching media, a second dielectric may be arranged within the layer sequence described here. Thus, the following connections can be created between two stacked layers: - Functional silicon / functional silicon (direct connection, electrically conductive) - Functional silicon / functional silicon (only mechanical connection via a dielectric) - Functional silicon / sacrificial silicon (and vice versa; connection via a dielectric, which is not or only slightly etched during etching of the sacrificial areas) - Sacrificial silicon / sacrificial silicon (direct connection)

[0047] The further construction of a complex 3D structure (e.g., complex MEMS structures such as acceleration sensors, gyroscopes, micromirrors, etc.) is achieved by repeating the corresponding process steps above. The sacrificial and functional regions produced by epitaxial growth can differ in freely selectable layer thicknesses. Layer thicknesses of the epitaxial or polyepitaxial silicon layers of 0.5 to 100 micrometers are advantageous. Thin silicon layers are suitable, for example, as resilient elements for vertical deflections (e.g., suspensions, bending springs, membranes, etc.), while thick silicon layers are advantageous for producing electrode combs or for filling large volumes or removing them again as sacrificial regions.

[0048] The Fig. 12 shows a schematic flow diagram for explaining a method according to an embodiment of the present invention for producing microelectromechanical structures in a layer sequence.

[0049] In a first step A, a carrier substrate T1 having a first surface 10 is provided. In a second step B, an insulation layer I1 is applied to the first surface 10. In a step C, a first silicon layer S1 is epitaxially grown on the insulation layer I1. In a further step D, the first silicon layer S1 is structured to form trenches G in the first silicon layer S1, wherein the trenches G extend at least partially through the first silicon layer S1. Thereafter, in a step E, the first silicon layer S1 is passivated, wherein the trenches G are filled and a passivation layer P is formed on a side facing away from the first surface.In a next step F, the passivation layer P is structured, wherein sacrificial regions O1 and the functional regions F1 are formed in the first silicon layer S1, wherein the sacrificial regions O1 are at least partially free of the passivation layer P on a side facing away from the carrier substrate.

[0050] Then, in a step G, the sacrificial areas are removed, for example by etching.

[0051] The Fig. 12 shown process steps A to G can be carried out in particular according to the Fig. 12 shown order.

[0052] This makes it possible to create an efficient and cost-effective method for producing microelectromechanical structures in a layer sequence and an electronic component with a micromechanical structure.

Claims

[1] Method for producing microelectromechanical structures (ME1) in a layer sequence with the steps: Providing a carrier substrate (T1) having a first surface (10); Applying an insulating layer (I1) to the first surface (10); Epitaxial growth of a first silicon layer (S1) on the insulation layer (I1); Structuring the first silicon layer (S1) to form trenches (G) in the first silicon layer (S1), wherein the trenches (G) extend at least partially through the first silicon layer (S1); Passivating the first silicon layer (S1), wherein the trenches (G) are filled and a passivation layer (P) is formed on a side facing away from the first surface (10); Structuring the passivation layer (P), wherein sacrificial regions (O1) and functional regions (F1) are formed in the first silicon layer (S1), and the sacrificial regions (O1) on a side of the first silicon layer (S1) facing away from the carrier substrate (T1) are at least partially free of the passivation layer (P); and Removing the sacrificial areas (O1), wherein the steps of epitaxial growth, structuring and passivation of the first silicon layer and structuring of the passivation layer (P) are repeated before removing the sacrificial regions (O1), and the formation of further sacrificial regions (O2, O3, O4) and further functional regions (F2, F3, F4) depends on the structuring of the further silicon layers (S2, S3, S4) and the further passivation layers (P), characterized bythat silicon nitride is used as a dielectric to create mechanical connections and at the same time provide electrical insulation between vertically stacked functional areas. [2] Method according to claim 1, wherein after the removal of the sacrificial regions (O1, O2, O3, O4) the passivation layer (P) is removed at least in places. [3] Method according to one of the preceding claims, wherein the epitaxial growth of the first silicon layer (S1) takes place on a SOI substrate (silicon-on-insulator) or the SOI substrate comprises the first silicon layer (S1). [4] Method according to one of the preceding claims, wherein the epitaxially grown silicon layer (S1) comprises a single-crystalline, polycrystalline and / or an epi-polycrystalline silicon layer (S1). [5] Method according to one of the preceding claims, wherein a layer thickness of the epitaxially grown silicon layer (S1) is between 0.5 and 100 micrometers, preferably 20 to 60 micrometers. [6] Method according to one of the preceding claims, wherein the insulation layer (I1) functions as an etch stop layer. [7] Method according to one of the preceding claims, wherein the formation of the trenches is carried out by means of a trench process. [8] Method according to one of the preceding claims, wherein the structuring of the passivation layer (P) is carried out by a dry etching method and / or a wet etching method. [9] Method according to one of the preceding claims, wherein after the epitaxial growth of the silicon layer (S1, S2, S3, S4) a chemical-mechanical polishing and / or an additional doping by implantation or coating takes place. [10] Method according to one of the preceding claims, wherein the removal of the sacrificial regions (O1, O2, O3, O4) is carried out by plasma-free and / or plasma-assisted etching. [11] Electronic component with a microelectromechanical structure (ME1) comprising: an alternating sequence of structured silicon layers (S1, S2, S3, S4) and structured passivation layers (P), wherein the structure of the passivation layers (P) depends at least in places on the structure of the silicon layers (S1, S2, S3, S4), and wherein each structured silicon layer (S1, S2, S3, S4) comprises sacrificial regions (O1, O2, O3, O4) and / or functional regions (F1, F2, F3, F4) arranged adjacent to one another at least in places, wherein the sacrificial regions (O1, O2, O3, O4) serve to be removed by subsequent sacrificial region or sacrificial layer etching, wherein the functional regions (F1, F2, F3, F4) are retained after sacrificial region structuring or sacrificial layer structuring, characterized by that the electronic component has silicon nitride as a dielectric for establishing mechanical connections and at the same time electrical insulation between vertically arranged functional areas.

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