Deepened STI as gate dielectric of a high-voltage component and manufacturing process

Abstract

Method (300) comprising the following steps: producing a separation region (36) extending into a semiconductor substrate (20); etching an upper part of the separation region (36) to produce a recess (58) in the separation region (36); producing a gate stack (160) in the recess (58) that overlaps a lower part of the separation region (36); and producing a source region (170) and a drain region (170) on opposite sides of the gate stack (160), wherein the gate stack (160), the source region (170) and the drain region (170) are parts of a MOS device (186), wherein a central part of the upper part of the separation region (36) is etched and after etching the upper part of the separation region (36) also has further parts (36A) that remain on one side of the etched central part.

Description

BACKGROUND OF THE INVENTIONHVMOS (high voltage metal-oxide semiconductor) devices are frequently used in electrical devices, such as power supplies for central processing units (CPUs), AC / DC (ac / dc) converters, etc.HVMOS devices have structures other than medium-voltage metal-oxide semiconductor (MVMOS) devices and low-voltage metal-oxide semiconductor (LVMOS) devices. To maintain high voltages applied between the gate and drain of an HVMOS device, the gate dielectric of the HVMOS device is thicker than the gate dielectric of an MVMOS device and than the gate dielectric of an LVMOS device. Moreover, the doping concentrations in high voltage well regions are lower than those in the well regions of MVMOS devices and LVMOS devices to maintain a higher gate-drain voltage.US 2014 / 0 117 444 A1 discloses an HVMOS component which has a multiplicity of insulation regions in a substrate, the surface of an insulation region lying below the surface of the substrate. A first gate electrode is disposed on this isolation region and a second gate electrode is disposed on the surface of the substrate. US 2010 / 0 264 481A1 describes a memory device having a high voltage region in which a gate structure is arranged in a recess in an insulation structure.US 2013 / 0 234 244 A1 describes a semiconductor device having a high-voltage region and a low-voltage region, between which a dummy structure is arranged, which extends into an insulation region.US 2015 / 0 349 050 A1 and U.S. Pat. No. 6,777,293 B1 disclose semiconductor devices which have a gate structure over a semiconductor substrate, a part of the gate structure extending into an insulation region in the semiconductor substrate.Brief Description of the DrawingsAspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 through 18 show cross-sectional views of intermediates in the fabrication of an n-HVMOS device and an n-MVMOS device (or an n-LVMOS device), in accordance with some embodiments. FIG. 19 illustrates a top view of an n-HVMOS device, in accordance with some embodiments. FIG. 20 shows a cross-sectional view of a p-HVMOS device and a p-MV / LVMOS device, in accordance with some embodiments. FIG. 21 illustrates a process flow for the fabrication of a HVMOS device and an MV / LV MOS device, in accordance with some embodiments.Detailed DescriptionThe invention relates to methods for producing a MOS component having the features of claims 1 and 9 and to an integrated circuit structure having the features of claim 16. The following description provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the present invention. For example, in the description below, the formation of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein may also be interpreted accordingly.According to various exemplary embodiments, a HVMOS device and a method for manufacturing the same are provided. The intermediate stages in the production of the HVMOS device are also described. In all illustrations and illustrative embodiments, similar reference symbols are used to designate similar elements.FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 to 18 show sectional views of intermediates in the manufacture of a HVMOS device according to some embodiments. The steps shown in FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 to 18 are also schematically illustrated in the process flow 300 shown in FIG. 21.FIG. 1 shows a wafer 10 comprising a semiconductor substrate 20 and features fabricated on a top surface of the semiconductor substrate 20. According to some embodiments of the present invention, the semiconductor substrate 20 includes crystalline silicon, crystalline germanium, silicon germanium, III-V compounds such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or the like. The semiconductor substrate 20 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. In some example embodiments, the semiconductor substrate 20 is p-type and has a doping concentration of less than about 10 15 / cm 3.The semiconductor substrate 20 has a first part in a device region 100 and a second part in a device region 200. Device region 100 is a high voltage device region in which an HVMOS device 186 (FIG. 18 ) is to be fabricated. Device region 200 is a device region in which a MOS device 286 (FIG. 18 ) is to be fabricated. The MOS device 286 is configured to operate at operating voltages (and supply voltages) that are lower than the respective operating voltages (and supply voltages) of the HVMOS device 186. In some example embodiments, device region 200 is an LVMOS device region or an MVMOS device region. It should be understood that the terms HV, MV and LV are relative to each other. The HVMOS devices are configured to operate at (and have) supply voltages higher than those of the MVMOS devices, and the MVMOS devices are configured to operate at (and have) supply voltages higher than those of the LVMOS devices. In addition, the maximum voltages that can be sustained (without damage) by MV devices are lower than the maximum voltages that can be sustained (without damage) by HV devices, and the maximum voltages that can be sustained (without damage) by LV devices are lower than the maximum voltages that can be sustained (without damage) by HV devices. In some example embodiments, the operating voltages of the HVMOS devices are in the range of about 3.0 V to about 3.3 V, the operating voltages and supply voltages of the MVMOS devices are in the range of about 1.5 V to about 2.0 V, and the operating voltages and supply voltages of the LVMOS devices are in the range of about 0.7 V to about 1.0 V.FIGS. 1, 2, 3 to 4 show the production of STI regions (STI: shallow trench isolation). The corresponding step is indicated as step 302 in the process flow shown in FIG. 21. Referring now to FIG. 1, a pad layer 22 and a mask layer 24 are formed on a semiconductor substrate 20. The pad layer 22 may be a thin film made of silicon oxide and may be formed by a thermal oxidation method, for example. The pad layer 22 may function as an adhesion layer between the semiconductor substrate 20 and the mask layer 24. The pad layer 22 may also function as an etch stop layer in etching the mask layer 24. In some embodiments of the present invention, mask layer 24 is formed of, for example, silicon nitride by low-pressure chemical vapor deposition (LPCVD). In further embodiments, the mask layer 24 is formed by thermal nitriding of silicon, plasma enhanced chemical vapor deposition (PECVD), or anodic plasma nitriding. The mask layer 24 is used as a hard mask layer in the subsequent photolithography process. A photoresist 26 is formed on the mask layer 24 and is then patterned to form openings 28.Referring now to FIG. 2, mask layer 24 and pad layer 22 are etched through openings 28, exposing underlying semiconductor substrate 20. The exposed semiconductor substrate 20 is then etched to form trenches 32. Thereafter, the photoresist 26 is removed. Then, cleaning may be performed to remove the native oxide of the semiconductor substrate 20. Purification may be carried out using dilute HF.As now shown in FIG. 3, one or more dielectric materials 34 are filled into the trenches 32. In some embodiments of the present invention, the dielectric material 34 is an oxide liner that covers the bottom and side walls of the opening 28. The oxide film may be a thermal oxide film formed by oxidizing a surface layer of the exposed substrate 20. In alternative embodiments of the present invention, the oxide coating is prepared by in situ steam generation (ISSG). In further embodiments, the oxide liner is formed by a deposition process that may form conformal oxide layers, such as atomic layer deposition (ALD), selective area chemical vapor deposition (SACVD), or the like. The formation of the oxide coating causes the corners of the trenches 32 (FIG. 2 ) to be rounded, which leads to a reduction in electric fields and thus to an improvement in the performance of the resulting integrated circuits.After the oxide coating has been produced, the remaining parts of the trenches 32 are filled with a further dielectric material. In some embodiments of the present invention, the fill metal is silicon oxide, but other dielectric materials may also be used, such as SiN, SiC, SiON, or the like. The dielectric fill metal may be filled using a high aspect ratio process (HARP), high density plasma (CVD) chemical vapor deposition, SACVD, atmospheric pressure chemical vapor deposition (APCVD), or the like.Then, a steam annealing process is performed. The steam annealing process may include annealing the structure shown in FIG. 3 with introduction of steam (H 2 O) at a higher temperature, for example, in the range of about 600° C. to about 700° C.Planarization, such as chemical mechanical polishing (CMP), is then performed to remove excess portions of dielectric material 34 over the top surface of mask layer 24, thereby forming the structure shown in FIG. 4. The mask layer 24 may function as a CMP barrier layer. The remaining portion of dielectric material 34 forms STI regions 36 and 38. As shown in FIG. 4, the bottom surfaces of STI regions 36 and 38 are at substantially the same level and have, for example, a height difference that is less than about 10% of the heights of STI regions 36 and 38.In subsequent steps, the mask layer 24 and the pad layer 22 are removed, followed by a plurality of cleaning processes. The resulting structure is shown in Figure 5. If the mask layer 24 is made of silicon nitride, it may be removed by a wet cleaning process using hot H 3 PO 4. If the pad layer 22 is made of silicon oxide, it may be removed in a wet etching process using dilute HF.FIGS. 6, 7 to 8 show the production of a plurality of doped regions by a plurality of implantation processes. The plurality of doped regions includes a deep n-well region 40, high-voltage p-well regions (HVPWM regions) 42, high-voltage n-well regions (HVNOW regions) 44, and a p-well region 46. In some example embodiments, a photoresist (not shown) is formed to cover wafer 10, exposing the region where deep n-well region 40 is to be formed to the opening in the photoresist. An n-type dopant, such as phosphorus, arsenic, and / or antimony, is implanted deep into the semiconductor substrate 20 to form the deep n-well region 40. Then, the photoresist is removed.Then, as shown in FIG. 6, a photoresist 48 is prepared and patterned. Subsequently, an implant of a p-type dopant is performed to form the HVPW regions 42. The corresponding step is indicated as step 304 in the process flow shown in FIG. 21. The HVPW regions 42 may be implanted with boron and / or indium. After the implantation, the HVPW regions 42 may have a p-type doping concentration in the range of about 10 15 / cm 3 to about 10 16 / cm 3 in some example embodiments. Thereafter, the photoresist 48 is removed.Then, as shown in FIG. 7, a photoresist 50 is prepared and patterned. Subsequently, an n-type dopant implant is performed to form the HVNW regions 44. The corresponding step is indicated as step 306 in the process flow shown in FIG. 21. The HVNW regions 44 may be implanted with phosphorus, arsenic, or antimony. After the implantation, the HVNW regions 44 may have an n-type doping concentration in the range of about 10 15 / cm 3 to about 10 16 / cm 3 in some example embodiments. Thereafter, the photoresist 50 is removed. The bottom surfaces of the HVNW regions 44 are connected to the deep n-well region 40.FIG. 8 illustrates the formation of the p-well region 46 in the device region 200. In some embodiments of the present invention, a photoresist 52 is formed and patterned to cover the device region 100. Then, p-type impurity implantation is performed to form the p-well region 46. The p-well region 46 may be implanted with boron or indium. The p-well region 46 has a p-type doping concentration that is higher than the doping concentration of the HVNW regions 44 and the HVPW regions 42. For example, in some example embodiments, the p-well region 46 may have a p-type doping concentration in the range of about 10 16 / cm 3 to about 10 17 / cm 3. Thereafter, the photoresist 52 is removed.In a subsequent step shown in FIG. 9, a photoresist 54 is formed and patterned to form an opening 56. A central portion of the STI region 36 is exposed by the opening 56. The STI regions 38, the HVNW regions 44 and some HVPW regions 42 are covered by the photoresist 54.Referring now to FIG. 10, an upper portion of the exposed STI region 36 is etched to form a recess 58 that extends into the STI region 36. The corresponding step is indicated as step 310 in the process flow shown in FIG. 21. The etching may be performed with a dry etching process using an etching gas. In some embodiments of the present invention, the STI region 36 comprises silicon oxide and HF is used as the etching gas. The etching may also be performed with a wet etching process using an etching solution. In some embodiments of the present invention, the STI region 36 comprises silicon oxide and an etching solution with dilute HF is used. The etch removes an upper center portion of the STI region 36 while leaving a lower portion 36B of the STI region 36. Moreover, due to the protection by the photoresist 54, the top portions 36A of the STI region 36 remain on one side (such as the drain side) or on opposite sides of the recess 58.The remaining bottom portion 36B of the STI region 36 has a thickness T 2. The remaining top portions 36A of the STI region 36 have a thickness T 1. The etching process may be adjusted to adjust the withstand voltage and the saturation current of the resulting HVMOS device. The depth D 2 of the recess 58 may be in the range of about 50 nm (about 500 Å) to about 140 nm (about 1400 Å), in some embodiments. The optimal depth D 2 is affected by various factors, such as the thickness of a gate dielectric 276 (FIG. 18 ), the minimum allowable height of a gate stack 274, etc. After the etch, the photoresist 54 is removed as shown in FIG. 11.FIG. 19 shows a top view of the STI region 36 and the corresponding recess 58 in accordance with some embodiments of the present invention. The recess 58 may be surrounded by the STI portion 36A. In further embodiments of the present invention, the recess 58 extends to an edge 36' of the STI region 36, where the edge 36' may be the edge facing one side (such as the source side) of the resulting HVMOS device.Referring now to FIG. 12, gate stacks 160 and 260 are formed in device regions 100 and 200, respectively. The corresponding step is indicated as step 312 in the process flow shown in FIG. 21. The gate stacks 160 and 260 may be removed in subsequent steps and replaced with replacement gates. Thus, in some embodiments, the gate stacks 160 and 260 are dummy gate stacks. The gate stack 160 includes a gate dielectric 164 and a gate electrode 166. The gate stack 260 includes a gate dielectric 264 and a gate electrode 266. The gate dielectrics 164 and 264 may be made of silicon oxide, silicon nitride, silicon carbide, or the like. Gate electrodes 166 and 266 may be formed of polysilicon in some embodiments. The gate electrodes 166 and 266 may also be made of other conductive materials, such as metals, metal lines, metal silicides, metal nitrides, and / or the like. In some embodiments of the present invention, gate stacks 160 and 260 include hard masks 168 and 268, respectively. Hard masks 168 and 268 may be made of, for example, silicon nitride, but other materials may also be used, such as silicon carbide, silicon oxynitride, and the like. In alternative embodiments, hard masks 168 and 268 are not formed.Spacers 162 and 262 are formed on sidewalls of the gate stacks 160 and 260, respectively. The corresponding step is also indicated as step 312 in the process flow shown in FIG. 21. In some embodiments, spacers 162 and 262 each include a silicon oxide layer and a silicon nitride layer on the silicon oxide layer. The fabrication may include depositing protective dielectric layers and then performing an anisotropic etch to remove the horizontal portions of the protective dielectric layers. Available deposition techniques include PECVD, LPCVD, sub-pressure chemical vapor deposition (SACVD), and other suitable deposition techniques.Referring now to FIG. 13, source and drain regions (hereinafter referred to as source / drain regions) 170 are formed in the HVNW regions 44. One of the source / drain regions 170 functions as the source region and the other functions as the drain region. A channel 173 is located directly below the STI region 36 for conducting currents between the S / D regions 170. In addition, source / drain regions 270 are formed in the p-well region 46. The respective steps are indicated as step 314 in the process flow shown in FIG. 21. The source / drain regions 170 and 270 may be simultaneously formed in a same implantation process. The source / drain regions 170 and 270 are n-type and are heavily doped, for example, to an n-type doping concentration in the range of about 10 19 / cm 3 to about 10 21 / cm 3, and are referred to as N+ regions. A photoresist (not shown) is formed to define the position of the source / drain regions 170 and 270. The source / drain regions 170 may be spaced apart from the STI region 36 by the HVNW regions 44. On the other hand, the source / drain regions 170 may have edges aligned with the edges of the gate spacers 262.Moreover, receiving regions 171 which are p-type are formed on the surface of the HVPW regions 42 with a further implantation step. The p-type well regions 171 may also have a p-type doping concentration in the range of about 10 19 / cm 3 to about 10 21 / cm 3 and are referred to as P+ regions.Referring now to FIG. 14, a contact etch stop layer (CESL) 72 is formed over the gate stacks 160 and 260 and the source / drain regions 170 and 270. The corresponding step is indicated as step 316 in the process flow shown in FIG. 21. In some embodiments of the present invention, the CESL 72 is made of a material selected from the group consisting of silicon nitride and silicon carbide, or other dielectric materials. An inter-layer dielectric (ILD) 74 is formed over the CESL 72. The corresponding step is also indicated as step 316 in the process flow shown in FIG. 21. The ILD 74 is formed by protective deposition to a height that extends above the tops of the gate stacks 160 and 260. The ILD 74 may be made of an oxide, for example, by flowable chemical vapor deposition (FCVD). The ILD 74 may also be spin-on glass made by spin-on. The ILD 74 may be made of, for example, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS) oxide, TiN, SiOC, or other low-k nonporous dielectric materials.FIG. 15 shows a planarization step performed by, for example, CMP. The corresponding step is indicated as step 318 in the process flow shown in FIG. 21. CMP is performed to remove excess portions of the ILD 74 and the CESL 72 until the gate stack 160 is exposed. Because the gate stack 160 is formed in the recess in the STI region 36, the top surface of the gate stack 160 is lower than the top surface of the gate stack 260. Therefore, in the planarization, the top of the gate stack 260 is removed, and the height of the remaining gate stack 160 is less than the height of the remaining gate stack 260. Planarization may be stopped on hard mask 168, if desired. Alternatively, the hard mask 168 is removed during planarization and the gate electrode 166 is exposed.FIG. 16 illustrates the formation of replacement gates 174 and 274, in accordance with some embodiments. The gate stacks 160 and 260 (FIG. 15 ) are removed and replaced with the replacement gate stacks 174 and 274, respectively, as shown in FIG. 16. The corresponding step is indicated as step 320 in the process flow shown in FIG. 21. The gate stack 174 includes a gate dielectric 176 and a gate electrode 178. The gate stack 274 includes a gate dielectric 276 and a gate electrode 278.The gate dielectrics 176 and 276 may include a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, or the like. The gate electrodes 178 and 278 may have conductive diffusion layers made of TiN, TaN, or the like. Gate electrodes 178 and 278 may also have conductive layers, such as metal-containing layers over the conductive diffusion barriers, where the metal-containing layers may be made of cobalt, aluminum, or multilayers thereof. The manufacturing methods include PVD, CVD, or the like. A planarization step (e.g., CMP) is then performed to remove excess portions of the gate dielectrics and gate electrodes, leaving the structure of FIG. 16.FIG. 17 illustrates the formation of an ILD 80 over the replacement gates 174 and 274. The corresponding step is indicated as step 322 in the process flow shown in FIG. 21. The ILD 80 may be made of a material selected from the same materials in question as for the manufacture of the ILD 74. The materials for the ILD 74 and the ILD 80 may be the same or different. Because the ILD 74 and the ILD 80 are fabricated in different process steps, there may be a detectable interface 79 between the ILD 74 and the ILD 80, regardless of whether the ILD 74 and the ILD 80 are made of the same material or different materials. In other embodiments, there is no detectable interface between the ILD 74 and the ILD 80.In the embodiments shown in FIGS. 16 and 17, replacement gates are formed by replacing dummy gates, and the ILD 80 is formed over the replacement gates. In alternative embodiments, after planarization as shown in FIG. 15, ILD 80 is fabricated without replacing gate stacks 160 and 260 with replacement gates. Gate dielectrics 164 and 264 and gate electrodes 166 and 266 thus remain in the final structure.Referring now to Fig. 18, source / drain silicide regions 82 and contact pins 84 are formed. The corresponding step is indicated as step 324 in the process flow shown in FIG. 21. The fabrication process may include the steps of: forming contact pin openings in the ILD 74 and the ILD 80 to expose the source / drain regions 170 and 270 and the gate electrodes 176 and 276; forming a metal layer (not shown) to extend into the contact pin openings; annealing to form the source / drain silicide regions 82; removing the unreacted portions of the metal layer; and filling the contact pin openings to form the contact pins 84. In embodiments where gate electrodes 166 and 266 (FIG. 15 ) are not replaced, gate silicides (not shown) may also be deposited on top of gate electrodes 166 and 266. This results in MOS devices 186 and 286. MOS device 186 includes gate electrode 178, a gate dielectric (including 36 and 176), and source / drain regions 170. MOS device 286 includes gate electrode 278, gate dielectric 276, and source / drain regions 270.The MOS device 186 is a HVMOS device. MOS device 286 is an MVMOS device or an LVMOS device, with the thickness of gate dielectric 276 (and 176) selected to match the operating voltage levels of MOS device 286. The gate dielectric of HVMOS device 186 includes the remaining portion of STI region 36 that is thick enough to withstand the high voltage. In addition, the gate dielectric 176 may also be formed as a portion of the gate dielectric of the HVMOS device 186. The MV / LV MOS device 286 has the gate dielectric 276 having a thickness smaller than that of the gate dielectric 36. Moreover, the gate dielectrics 176 and 276 may be formed in one and the same manufacturing process and thus have the same thickness, and are formed of one and the same dielectric material.FIG. 19 shows a top view of portions of a HVMOS device, illustrating source / drain regions 170. The source region 170 may be spaced apart from the STI region 36 or may contact the edge 36' of the STI region 36.FIG. 20 shows a cross-sectional view of a p-HVMOS device 186' and a p-MOS device 286' (an LV or MV device) fabricated on the same semiconductor substrate 20 as the n-MOS devices 186 and 286. The regions shown in Fig. 20 are denoted by the same reference symbols as in Fig. 18, and a symbol (') is added to indicate that they are regions corresponding to those in Fig. 18. The materials and fabrication processes are the same as the fabrication of MOS devices 186 and 286 (FIG. 18 ), with the conductivity types of the various regions depicted in FIG. 20 being reversed from the corresponding regions shown in FIG. 18.The embodiments of the present invention have several advantages. It is desirable that the HVMOS devices and the LV / MV MOS devices share the processes for forming the replacement gates in order to reduce the manufacturing cost. However, the HVMOS devices have thick gate dielectrics, and therefore the top surfaces of the gate dielectrics of the HVMOS devices may be at substantially the same level as or even above the top surfaces of the dummy gate electrodes of the LV / MV MOS devices. As a result, the planarization for exposing the dummy gate electrodes of the LV / MV MOS devices may result in complete removal of the dummy gate electrodes of the HVMOS devices. That is, the replacement gates for the HVMOS devices cannot be formed by commonly using the same process as for forming the replacement gates for the LV / MV MOS devices. By recessing STI regions and forming the gate electrodes of the HVMOS devices in the recesses, the height difference between the tops of the HVMOS devices and the LV / MV MOS devices is reduced and planarization can be performed without complete removal of the dummy gate electrodes of the HVMOS devices. Moreover, in some embodiments of the present invention, the STI regions are used as the gate dielectrics of the HVMOS devices, and thereby manufacturing costs can be lowered.

Claims

A method (300) comprising the steps of: forming a separation region (36) that extends into a semiconductor substrate (20); etching an upper portion of the separation region (36) to form a recess (58) in the separation region (36); forming a gate stack (160) in the recess (58) that overlaps a lower portion of the separation region (36); forming a source region (170) and a drain region (170) on opposite sides of the gate stack (160), wherein the gate stack (160), the source region (170) and the drain region (170) are parts of a MOS device (186), wherein a middle part of the upper part of the separation region (36) is etched and after etching the upper part of the separation region (36) further comprises further parts (36A) remaining on one side of the etched middle part.The method (300) of claim 1, wherein the separation region (36) has a top surface that is substantially coplanar with a top surface of the semiconductor substrate (20) after the etching.The method (300) of claim 1 or 2, wherein a depth (D2) of the recess (58) is in the range of 50 nm to 140 nm.Method (300) according to any of the preceding claims, wherein the recess (58) is surrounded by the remaining further parts (36A) of the upper part of the separation region (36).Method (300) according to one of Claims 1 to 3, wherein the cutout (58) reaches as far as an edge (36') of the separation region (36).The method (300) of claim 5, wherein the edge (36') faces a source side of the MOS device (186).The method (300) of any preceding claim, further comprising the steps of: simultaneously with the formation of the gate stack (160), forming a further gate stack (260) for a further MOS device (286), the further gate stack (260) being directly above a non-recessed portion of the semiconductor substrate (20), the gate stack (160) comprising a first gate dielectric (176), and the further gate stack (260) comprising a second gate dielectric (276), wherein the first gate dielectric (176) and the second gate dielectric (276) are formed in the same manufacturing process.The method (300) of claim 7, wherein a top surface of the gate stack (160) is lower than a top surface of the further gate stack (260).A method (300) comprising the steps of: forming first (36) and second STI regions (38) extending into the semiconductor substrate (20) from a top surface of a semiconductor substrate (20); etching the first STI region (36) to form a recess (58) extending into the first STI region (36) from a top surface of the first STI region (36), the first STI region (36) having a bottom portion (36B) located below the recess (58) and a top portion (36A) remaining on a side of the recess (58); forming a first gate stack (160) in the recess (58) that overlaps the bottom portion (36B) of the first STI region (36); forming a second gate stack (260) over and in contact with a top surface of the semiconductor substrate (20); forming first source / drain regions (170) on opposing sides of the first gate stack (160); and forming second source / drain regions (270) on opposing sides of the second gate stack (260).The method of claim 9, further comprising: depositing an interlayer dielectric (74) over the first source / drain regions (170) and the second source / drain regions (270); and performing planarization to remove excess portions of the interlayer dielectric (74) until the first gate stack (160) has been exposed.The method (300) of claim 10, wherein the first gate stack (160) functions as a stopping layer for planarization, and an upper portion of the second gate stack (260) is removed by planarization.The method (300) of any of claims 9 to 11, wherein the first gate stack (160) is a part of a HVMOS device (186) and the second gate stack (260) is a part of a medium voltage MOS device (286) or a low voltage MOS device (286).The method (300) of claim 12, wherein the bottom portion of the first STI region (36) functions as a portion of a gate dielectric (164) of the HVMOS device (186).The method (300) of any of claims 9 to 13, wherein a portion of the first gate stack (160) is lower than the top surface of the semiconductor substrate (20) and the entire second gate stack (260) is higher than the top surface of the semiconductor substrate (20).The method (300) of any of claims 9 to 14, further comprising replacing the first gate stack (160) and the second gate stack (260) with a first replacement gate (174) and a second replacement gate (274).An integrated circuit structure (10) comprising: a semiconductor substrate (20); an HVMOS device (186) comprising: a gate dielectric (36, 162, 164, 176) having a first portion (36B), wherein a top surface of the first portion (36B) of the gate dielectric (36, 162, 164, 176) is lower than a top surface of the semiconductor substrate (20), and the gate dielectric (36) further comprises a second portion (36A) and a third portion (36A) that are higher than the top surface of the first portion (36B), and a gate electrode (160, 174) over the first portion (36A) of the gate dielectric (36, 162, 164, 176), wherein the gate electrode (160, 174) has a portion, which is lower than the top side of the semiconductor substrate (20), and the second part (36A) and the third part (36A) of the gate dielectric (36, 162, 164, 176) are located on opposite sides of the gate electrode (160, 174); and a source region (170) and a drain region (170) are located on opposite sides of the gate dielectric (36, 162, 164, 176), wherein the second part (36A) of the gate dielectric (36, 162, 164, 176) is located on the source side and the third part (36A) of the gate dielectric (36, 162, 164, 176) is located on the drain side.The integrated circuit structure (10) of claim 16, wherein the HVMOS device (186) further comprises: an HV n-well region (44), referred to as an HVNW region below; and an HV p-well region (42), referred to as an HVPW region below, wherein the HVNW region (44) and / or the HVPW region (42) comprise a portion that is directly below the gate dielectric (36, 162, 164, 176).The integrated circuit structure (10) of claim 16 or 17, wherein the second portion (36A) and the third portion (36A) are coplanar with a top surface of the semiconductor substrate (20).The integrated circuit structure (10) of any of claims 16 to 18, wherein the gate dielectric (36, 162, 164, 176) further comprises a fourth portion (162, 164, 176), the fourth portion (162, 164, 176) comprising a horizontal portion in contact with the first portion (36B) of the gate dielectric (36, 162, 164, 176) and vertical portions connected to opposite ends of the horizontal portion.The integrated circuit structure (10) of claim 19, further comprising a further MOS device (286), the further MOS device (286) comprising a further gate dielectric (276) that is higher than the top surface of the semiconductor substrate (20) and is made of the same material as the fourth portion (162, 164, 176) of the gate dielectric (36, 162, 164, 176).

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