Method for semiconductor mid-end-of-line (MEOL) process

Abstract

Method for forming a semiconductor device, the method comprising: Providing a precursor (100) that includes: a substrate (102) comprising first and second regions (102A, 102B), wherein the first region (102A) comprises an insulator and the second region (102B) comprises source, drain and channel regions (104, 104, 106) of a transistor; a first gate stack (108A, 108C) above the insulator; second and third gate stacks (108E, 108F) above the channel region (106); and a first dielectric layer (110) over the first, second and third gate stacks; partial etching of the first dielectric layer (110); Forming a contact etch stop layer of the second dielectric layer (122) over the back-etched first dielectric layer (110); Forming a (124) over the second dielectric layer (122); and forming an intermediate dielectric layer (126) over the contact etch stop layer (124); Etching of first and second openings (128) in the interlayer dielectric layer (126) above the second and third gate stacks (108E, 108F) respectively; Etching of the contact etch stop layer (124) and the second dielectric layer (122) through the first and second openings (128) to expose the back-etched first dielectric layer (110) over the second and third gate stacks (108E, 108F); Etching of the interlayer dielectric layer (126) in the first region (102A) to expose the contact etch stop layer (124); Etching of the contact etch stop layer (124) in the first region (102A) to expose the second dielectric layer (122); and Etching of the back-etched first dielectric layer (110) to expose the second and third gate stacks (108E, 108F), while the first gate stack (108A, 108C) remains covered by the back-etched first dielectric layer (110) and the second dielectric layer (122) above the back-etched first dielectric layer.

Description

GENERAL STATE OF THE ART

[0001] The integrated circuit (IC) industry has grown exponentially. Technical advances in IC materials and IC design have spawned generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) achievable with a manufacturing process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling-down has also increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are required.

[0002] For example, in mid-end-of-line (MEOL) processes, it is typical for gate via openings to be etched in some areas containing dense vias and in some areas containing isolated vias. It is difficult to control the via etch depth in both the dense and isolated via regions when the vias are partially etched. As a result, the via depth varies from one region to another. This via depth variation can cause problems during subsequent manufacturing. For example, it can cause a leakage problem when gate contacts and source / drain (S / D) contacts are formed in a later step.

[0003] A method for forming a semiconductor device is known from US 2015 / 0 325 690 A1. The method comprises providing a precursor comprising a substrate with source, drain, and channel regions of a transistor, a gate stack over the channel region, and a first dielectric layer over the gate stack. The method further comprises partially etching back the first dielectric layer; forming a second dielectric layer over the etched-back first dielectric layer; and forming a contact etch stop layer over the second dielectric layer.

[0004] US 2015 / 0 270 176 A1 discloses a semiconductor device comprising a substrate with an insulator and channel regions. A gate stack is located above the insulator, and further gate stacks are located above the channel regions. A dielectric layer is formed over the gate stacks.

[0005] The present invention is defined by independent claim 1. Specific embodiments are defined by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. The Fig. 1A and Fig. 1B is a flow diagram of a method of forming a semiconductor device according to various aspects of the present disclosure. The Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2 years, Fig. 2K and Fig. 2L are cross-sectional views of a portion of a semiconductor device formed according to the method in Fig. 1A and Fig. 1B is designed according to one embodiment. Fig. Figure 3 illustrates areas of an IC that have different gate pitches. Fig. Figure 4 illustrates regions of an IC having different via pitches. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional functions may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.

[0008] Furthermore, for ease of discussion, spatially relative terms such as "beneath," "under," "lower," "over," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device during use or operation of the device, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0009] The present disclosure generally relates to semiconductor devices and methods for fabricating them. More particularly, the present disclosure relates to MEOL processes in semiconductor manufacturing. An object of the present disclosure is to provide methods and structures to improve MEOL processes with respect to via depth stress problems associated with unevenly distributed vias in different regions of an IC.

[0010] The Fig. 1A and Fig. 1B show a flowchart of a method 10 for forming a semiconductor device 100 according to various aspects of the present disclosure. The method 10 is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations may be provided before, during, and after the method 10, and some described operations may be exchanged, eliminated, or postponed for additional embodiments of the method. The method 10 is described below in connection with the Fig. 2A to 2L, which are cross-sectional views of the semiconductor device 100 at various stages of a manufacturing process.

[0011] The semiconductor device 100 is provided for illustrative purposes and does not necessarily limit the embodiments of the present disclosure to any number of devices, any number of regions, or any configuration of structures or regions. Furthermore, the semiconductor device 100 may be configured as shown in the Fig. 2A to 2L may be an intermediary device manufactured during processing of an IC or a portion thereof, which may include static random access memory (SRAM) and / or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs such as FinFETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

[0012] In operation 12, procedure 10 ( Fig. 1A) a precursor of the device 100 as shown in Fig. 2A. For ease of description, the precursor of the device 100 is also referred to as the device 100. With reference to Fig. 2A, the device 100 includes a substrate 102 and various features formed therein or thereon. The substrate 102 includes two substrate regions 102A and 102B. In the present embodiment, the substrate region 102A includes an insulator such as shallow trench isolation (STI), while the substrate region 102B includes active regions to form transistors. In the present embodiment, the two substrate regions 102A and 102B serve different purposes for the device 100. For example, the substrate region 102A may be used to form power rails such as power supply and / or ground planes, while the substrate region 102B may be used to form logic circuits. As shown in Fig. As shown in Figure 1A, the substrate region 102B includes various source and drain (S / D) regions 104 and channel regions 106 between the S / D regions 104.

[0013] With further reference to Fig. 1A, the device 100 further comprises a plurality of gate stacks 108A, 108B, 108C, 108D, 108E, 108F, and 108G, wherein the gate stacks 108A-C are disposed above the substrate region 102A and the gate stacks 108D-G are disposed adjacent to the channel regions 106 in the substrate region 102B. The device 100 further includes a dielectric layer 110 disposed over each gate stack 108A-G, and a gate spacer 112 on sidewalls of each gate stack 108A-G and on sidewalls of the corresponding dielectric layer 110. In the present embodiment, the device 100 includes a contact etch stop (CES) layer 114 over the substrate 102 and on sidewalls of the gate spacer 112, and further includes an interlayer dielectric (ILD) layer 116 over the CES layer 114. The device 100 further includes contacts 118A and 118B over the substrate regions 102A and 102B, respectively.Above the substrate region 102A, contacts 118A are disposed above the CES layer 114 between some of the gate stacks (e.g., between gate stacks 108A and 108B). In the present embodiment, contacts 118A are used to form power rails. Therefore, they are also referred to as power contacts 118A. Above the substrate region 102B, contacts 118B are disposed above the S / D regions 104 and in electrical communication with the corresponding S / D regions 104. Therefore, they are also referred to as S / D contacts 118B. The device 100 further includes a dielectric layer 120 over the contacts 118A-B. The various features (or components) of the device 100 are further described below.

[0014] Substrate 102 is a silicon substrate in the present embodiment. In alternative embodiments, substrate 102 comprises other elemental semiconductors such as germanium; a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide; or an alloy semiconductor such as silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In embodiments, substrate 102 may comprise a silicon-on-insulator (SOI) substrate, be strained and / or stressed for performance enhancement, include epitaxial regions, include isolation regions, include doped regions, and / or include other suitable features and layers.

[0015] The substrate region 102A includes an insulator (or isolation structure) and may be formed from silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or another suitable isolation material. The insulator may include STI features. In one embodiment, the insulator is formed by etching trenches in the substrate 102, filling the trenches with an isolation material, and performing a chemical mechanical planarization (CMP) process on the substrate 102 including the isolation material. The substrate region 102A may include other isolation structures such as field oxide and local oxidation of silicon (LOCOS). The substrate region 102A may include a multilayer isolation structure.

[0016] The substrate region 102B may include n-doped regions and / or p-doped regions to form active devices such as transistors. The S / D regions 104 may include highly doped S / D (HDD), lightly doped S / D (LDD), raised regions, strained regions, epitaxially grown regions, and / or other suitable features. The S / D regions 104 may be formed by etching and epitaxial growth, halo implantation, S / D implantation, S / D activation, and / or other suitable processes. In one embodiment, the S / D regions 104 further include silicidation or germanosilicidation. For example, silicidation may be formed by a process that includes depositing a metal layer, annealing the metal layer so that the metal layer can react with silicon to form silicide, and then removing the unreacted metal layer.In one embodiment, the substrate region 102B includes fin-like active regions for forming multi-gate FETs such as FinFETs. To further this embodiment, the S / D regions 104 and the channel regions 106 may be formed in or on the fins. The channel regions 106 are sandwiched between a pair of S / D regions 104. The channel region 106 conducts currents between the corresponding S / D regions 104 when the semiconductor device 100 is in use.

[0017] Each of the gate stacks 108A-G may be a multi-layer structure. Further, the gate stacks 108A-G may have the same or different structures and materials as one another. The following description applies to any of the gate stacks 108A-G. In one embodiment, the gate stacks 108A-G include an interlayer and a polysilicon (or poly) layer over the interlayer. In some embodiments, the gate stacks 108A-G may further include a gate dielectric layer and a metal gate layer disposed between the interlayer and the poly layer. In some embodiments, the gate stack 108A-G includes one or more metal layers instead of the poly layer.In various embodiments, the interlayer may comprise a dielectric such as silicon oxide (SiO2) or silicon oxynitride (SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The poly layer may be formed by suitable deposition processes such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD). The gate dielectric layer may comprise a high-k dielectric layer such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal oxides, or combinations thereof; and may be formed by ALD and / or other suitable methods. The metal gate layer may comprise a p-type work-function metal layer or an n-type work-function metal layer.The p-type work-function metal layer comprises a metal selected, without limitation, from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. The n-type work-function metal layer comprises a metal selected, without limitation, from the group consisting of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), or combinations thereof. The p-type or n-type work-function metal layer may comprise multiple layers and may be deposited by CVD, PVD, and / or another suitable process. The one or more metal layers may comprise aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials and may be formed by CVD, PVD, plating, and / or other suitable processes. The gate stack 108A to G can be formed in a gate-first process or a gate-last process (ie, an exchange gate process).

[0018] The dielectric layer 110 is disposed over the gate stacks 108A-G. In one embodiment, the dielectric layer 110 comprises a metal oxide, a metal nitride, or other suitable dielectrics. For example, the metal oxide may be titanium oxide (TiO2), aluminum oxide (Al2O3), or other metal oxides. For example, the metal nitride may be titanium nitride (TiN), aluminum nitride (AlN), aluminum oxynitride (AlON), tantalum nitride (TaN), or other metal nitrides. The dielectric layer 110 may be formed over the gate stacks 108A-G by one or more deposition and etch processes.

[0019] The gate spacer 112 can be a single layer or a multi-layer structure. In one embodiment, the gate spacer 112 comprises a low-k (e.g., k <7) dielectric. In some embodiments, the gate spacer 112 comprises a dielectric such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), another dielectric, or a combination thereof. In one example, the gate spacer 112 is formed by depositing a first dielectric layer (e.g., a SiO2 layer with a uniform thickness) as a liner layer over the device 100 and a second dielectric layer (e.g., a SiN layer) as a D-shaped main spacer over the first dielectric layer, and then anisotropic etching to remove portions of the dielectric layers and form the gate spacer 112.In the present embodiment, the gate spacer 112 is arranged on sidewalls of the gate stacks 108A to G and on sidewalls of the dielectric layer 110.

[0020] The CES layer 114 may comprise a dielectric such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), and / or other materials. The CES layer 114 may be formed by a PECVD process and / or other suitable deposition or oxidation processes. The ILD layer 116 may comprise materials such as tetraethylorthosilicate (TEOS) oxide, undoped silica glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), synthetic fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectrics. The ILD layer 116 may be deposited by a PECVD process, a flowable CVD (FCVD) process, or another suitable deposition technique. In one embodiment, the CES layer 114 is deposited as a capping layer over the substrate 102, covering various structures thereon, and the ILD layer 116 is deposited over the CES layer 114.Subsequently, portions of the ILD layer 116 and the CES layer 114 are etched back to form trenches for deposition of contacts 118A-B. Portions of the ILD layer 116 are etched above the substrate region 102A (e.g., between the gate stacks 108A and 108B) until the CES layer 114 is exposed. As a result, portions of the CES layer 114 remain above the substrate region 102A between adjacent gate spacers 112. Portions of the ILD layer 116 and the CES layer 114 are etched above the substrate region 102B (e.g., between the gate stacks 108E and 108F) to expose the underlying S / D regions 104.

[0021] Contacts 118A-B are separated by structures including the respective gate stacks 108A-G, gate spacer 112, and CES layer 114. In one embodiment, contacts 118A-B comprise a metal such as aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), combinations thereof, or other suitable conductive material. In one embodiment, the contact metal is deposited using a suitable process such as CVD, PVD, plating, and / or other suitable processes. After the contact metal is deposited, it may be etched back to leave space for the deposition of dielectric layer 120.

[0022] Dielectric layer 120 may comprise a metal oxide (e.g., TiO2 and Al2O3), a metal nitride (e.g., TiN, AlN, AlON, and TaN), or other suitable dielectrics. In various embodiments, dielectric layers 110 and 120 may be made of the same or different materials. Dielectric layer 120 may be deposited using PVD, CVD, or other deposition techniques. In one embodiment, a CMP process is performed to planarize a top surface of device 100 after dielectric layer 120 is deposited. As a result, the top surfaces of the various layers 110, 112, 114, 116, and 120 become coplanar.

[0023] In operation 14, process 10 ( Fig. 1A) the dielectric layer 110 partially back. With reference to Fig. 2B, the dielectric layer 110 above each of the gate stacks 108A-G is etched back. In one embodiment, operation 14 includes an etch process configured to etch the dielectric layer 110 while leaving the other layers 112, 114, 116, and 120 substantially unchanged in the etch process. In embodiments, operation 14 may use a dry etch, a wet etch, or other suitable etch processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCL4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof.For example, a wet etching process may include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH), or another suitable wet etchant.

[0024] In one embodiment, there are different gate pitches (or gate densities) in different areas (or sections) of the device 100. Some examples are shown in Fig. 3 as a plan view of two areas 302 and 304 of the device 100. With reference to Fig. 3, region 302 includes gate stacks 306 with a gate pitch P1, and region 304 includes gate stacks 308 with a gate pitch P2 that is larger than P1. Gate pitches P1 and P2 may be given as center-axis-to-center-axis pitches (as shown) or as edge-to-edge pitches. As illustrated, region 302 has a smaller gate pitch and therefore a higher gate density than region 304. In embodiments, substrate regions 102A and 102B may correspond to regions of device 100 having the same or different gate pitches. For example, substrate region 102A may correspond to a higher gate pitch range and substrate region 102B may correspond to a lower gate pitch range, or vice versa. When dielectric layer 110 is partially etched ( Fig. 2B), which is typically controlled by a timer, the different gate pitches generate different etch stresses in different regions of the device 100. As a result, the dielectric layer 110 is etched more (or deeper) in some regions and less (or shallower) in some other regions. In the present embodiment, another dielectric layer is formed over the etched-back dielectric layer 110, as described below. Therefore, the varying thickness of the etched-back dielectric layer 110 will not cause any problems for subsequent manufacturing processes. In the present embodiment, operation 14 may reduce a thickness of the dielectric layer 110 by approximately 10% to approximately 90%, providing a wide process window.

[0025] In operation 16, the process 10 ( Fig. 1A) a dielectric layer 122 over the etched-back dielectric layer 110. With reference to Fig. 2C, the dielectric layer 122 is disposed over the recessed dielectric layer 110 above each of the gate stacks 108A-G. In one embodiment, operation 16 includes depositing a dielectric over the device 100 and filling the trenches, followed by a CMP process to remove excess dielectric. Due to different thicknesses of the etched-back dielectric layer 110, as described above, the dielectric layer 122 may have different thicknesses over different gate stacks. For example, the dielectric layer 122 may be of different thicknesses over the gate stacks 108A and 108D. The dielectric layer 122 may comprise a metal oxide, a metal nitride, or other suitable dielectrics. For example, the metal oxide may be TiO2, Al2O3, or other metal oxides. For example, the metal nitride may be TiN, AlN, AlON, TaN, or other metal nitrides.In various embodiments, the dielectric layer 122 comprises a material different from that of the dielectric layer 110. The dielectric layer 122 may be formed by ALD, PVD, CVD, spin-on deposition, or other suitable deposition techniques.

[0026] In operation 18, the process 10 ( Fig. 1A) another CES layer 124 above the various layers 112, 114, 116, 120 and 122. In operation 20, the method 10 ( Fig. 1A) another ILD layer 126 (also referred to as patterning layer 126) over the CES layer 124. Referring to Fig. 2D, the CES layer 124 may comprise a dielectric such as SiN, SiO2, and SiON. The ILD layer 126 may comprise an oxide such as TEOS, BPSG, FSG, PSG, and BSG. The ILD layer 126 and the CES layer 124 may each comprise the same materials as the ILD layer 116 and the CES layer 114 or different materials. Furthermore, in the present embodiment, the CES layer 124 may comprise the same material as the dielectric layer 110 and / or the dielectric layer 120. The CES layer 124 may be formed by a PECVD process and / or other suitable deposition or oxidation processes. The ILD layer 126 may be deposited by a PECVD process, an FCVD process, or other suitable deposition processes.

[0027] In operation 22, the process 10 ( Fig. 1A) the ILD layer 126 to form gate via openings 128 over some of the gate stacks 108A to G. Referring to Fig. 2E, in this cross-sectional view, gate via openings 128 are formed in the ILD layer 126 over the gate stacks 108B, 108E, 108F, and 108G, but not over the gate stacks 108A and 108C. In one embodiment, operation 22 includes a photolithography process and an etching process. The photolithography process may include forming a photoresist (or resist) over the ILD layer 126, exposing the resist to a pattern defining various geometric shapes for the gate via openings 128, performing post-exposure bake processes, and developing the resist to form a masking element comprising the resist. The masking element, or a derivative thereof, is then used to etch recesses into the ILD layer 126. The masking element (e.g., a patterned resist) is subsequently removed.The etching processes may include one or more dry etching processes, wet etching processes, and other suitable etching techniques. The CES layer 124 has sufficient etch selectivity with respect to the ILD layer 126 and serves as an etch stop in the etching process.

[0028] Similar to the scenario described above with different gate pitches, there may be different gate via pitches in different areas of the device 100. Some examples are shown in Fig. 4 as a plan view of four areas 402, 404, 406 and 408 of the device 100. With reference to Fig. 4, region 402 has a gate via pitch P3, region 404 has a gate via pitch P4 that is larger than P3, region 406 has a gate via pitch P5 that is larger than P4, and region 408 has a gate via pitch (not labeled) that is larger than P5. In embodiments, substrate regions 102A and 102B may each correspond to a dense via region (having a smaller gate via pitch) or an isolated via region (having a larger gate via pitch). However, since ILD layer 126 is completely etched in operation 22 and the two layers 126 and 124 have sufficient etch selectivity, the difference in the gate via pitches does not produce a large difference in the thus-formed structure.

[0029] In operation 24, process 10 ( Fig. 1B) the CE layer 124 and the dielectric layer 122 through the gate via openings 128, thereby forming a portion of the etched-back dielectric layer 110 over the respective gate stacks 108B, 108E, 108F and 108G ( Fig. 2F). The etch processes may include one or more of dry etching processes, wet etching processes, and other suitable etching techniques. In the present embodiment, operation 24 includes a selective etch process, i.e., an etch process tuned to remove the dielectric layer 122 while leaving the dielectric layer 110 substantially unchanged in the etch process. As a result, operation 24 successfully exposes and stops the etched-back dielectric layer 110 over the respective gate stacks, even though the dielectric layer 122 over the respective gate stacks may have different thicknesses and / or there may be different via pitches over the substrate regions 102A and 102B.

[0030] In operation 26, process 10 ( Fig. 1B) the ILD layer 126 over some of the S / D contacts 118B to form S / D via openings 130 in the ILD layer 126 ( Fig. 2G). In one embodiment, operation 26 includes a photolithography process and an etching process. For example, the photolithography process forms a masking element (e.g., a patterned resist) over device 100 that defines S / D via openings 130; and the etching process etches ILD layer 126 with the masking element as an etch mask. The etching processes may include one or more of dry etching processes, wet etching processes, and other suitable etching techniques. CES layer 124 has sufficient etch selectivity with respect to ILD layer 126 and serves as an etch stop in the etching process. The masking element is subsequently removed.

[0031] In operation 28, the process 10 ( Fig. 1B) the ILD layer 126 over the substrate region 102A. Referring to Fig. 2H, in the present embodiment, operation 28 includes a photolithography process and an etching process. The photolithography process forms a masking element (e.g., a patterned resist) over device 100 that defines trenches to form power rails over first substrate region 102A. The etching process etches ILD layer 126 through the masking element. The etching process may include one or more of dry etching processes, wet etching processes, and other suitable etching techniques. The etching process is tuned to remove ILD layer 126 while leaving CES layer 124 and etched-back dielectric layer 110 substantially unchanged. The masking element is subsequently removed.

[0032] In operation 30, the process 10 ( Fig. 1B) the CES layer 124 and the dielectric layer 120 over the device 100. Referring to Fig. 2I is formed over the substrate region 102A, the CES layer 124 and the dielectric layer 120 (see Fig. 2H). The etched-back dielectric layer 110 and the dielectric layer 122 protect the gate stacks 108A to C from the etching process. As a result, the power contacts 118A and the ILD layer 116 are exposed. With further reference to Fig. 2I is etched over the substrate region 102B, the CES layer 124, and the dielectric layer 120 through the S / D via openings 130, exposing the S / D contacts 118B thereunder. The ILD layer 126 and the etched-back dielectric layer 110 protect other structures, including the gate stacks 108D-G, from the etching process. The etching process may include one or more dry etching processes, wet etching processes, and other suitable etching techniques.

[0033] In operation 32, the process 10 ( Fig. 1B) the portions of the etched-back dielectric layer 110 exposed in the gate via openings 128. The etching process may include one or more of dry etching processes, wet etching processes, and other suitable etching techniques. In the present embodiment, the etching process is tuned to remove the etched-back dielectric layer 110 while leaving the dielectric layer 122 substantially unchanged. Furthermore, other layers of the material, including the gate spacer 112, the CES layers 114 and 124, the ILD layers 116 and 126, and the contacts 118A and 118B, remain substantially unchanged in the etching process of the present embodiment. Referring to Fig. 2J, upper surfaces of gate stacks 108B, 108E, 108F, and 108G are exposed as a result of the etching process, while gate stacks 108A and 108C are still covered by a stack of dielectric layer 122 over etched-back dielectric layer 110. In the present embodiment, dielectric layer 122 serves as a protective layer for etched-back dielectric layer 110. Without dielectric layer 122, etched-back dielectric layer 110 over gate stacks 108A and 108C would also be etched in operation 32. In some cases, the etch depth is difficult to control given different via pitches in different regions of device 100. Therefore, gate stacks 108A and 108C could be inadvertently exposed, causing leakage problems or device failures.In the present embodiment, the dielectric layers 110 and 122 have sufficient etch selectivity such that the etched-back dielectric layer 110 above the gate stacks 108B, 108E, 108F, and 108G is fully etched, while the gate stacks 108A and 108C remain protected by the dielectric layer 122 above the etched-back dielectric layer 110.

[0034] For operation 34, method 10 ( Fig. 1B) deposits a metal layer 132 over the device 100 and fills the various trenches and via openings thereon. Referring to Fig. 2K, the metal layer 132 is in electrical connection with: the gate stacks 108A, 108E, 108F, and 108G; the power contacts 118A (between the gate stacks 108A and 108B and between the gate stacks 108C and 108D); and the S / D contacts 118B (between the gate stacks 108E and 108F and between the gate stacks 108F and 108G). The metal layer 132 is galvanically isolated from the gate stacks 108A, 108C, and 108D by at least the etched-back dielectric layer 110 and the dielectric layer 122. In the present embodiment, the metal layer 132 may comprise aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials and may be formed by CVD, PVD, plating, and / or other suitable processes.

[0035] In operation 36, process 10 ( Fig. 1B) the metal layer 132. With reference to Fig. 2L, in the present embodiment, operation 36 also etches back the ILD layer 126 over the substrate region 102B. In one embodiment, operation 36 includes a CMP process that removes the metal layer 132 and the ILD layer 126 until the CES layer 124 is exposed over the substrate region 102B. As a result, various metallic features are formed in the device 100. A power rail 134 is formed over the substrate region 102A, including a portion of the metal layer 132 and the power contacts 118A. The power rail 134 is in electrical communication with the gate stack 108B, but is galvanically isolated from the gate stacks 108A and 108C by at least the dielectric layer 122 and the etched-back dielectric layer 110.Gate vias (or gate plugs) 136 are formed over the substrate region 102B and electrically connected to the gate stacks 108E, 108F, and 108G; and S / D vias (or S / D plugs) 138 are formed and electrically connected to the S / D regions 104 through the S / D contacts 118B.

[0036] At operation 38, the process 10 ( Fig. 1B) proceeds with further steps to complete the fabrication of device 100. For example, method 10 may form a multilayer interconnect structure connecting gate vias 136 and S / D vias 138 to other portions of device 100 to form a completed IC.

[0037] Although not intended to be limiting, one or more embodiments of the present disclosure provide many advantages to a semiconductor device and an associated formation process. For example, when forming gate and S / D vias in an MEOL process, embodiments of the present disclosure can reliably connect some, but not all, gate stacks to a power rail, despite different via pitches (or via densities) in different regions of the semiconductor device. Those gate stacks that are not to be connected to the power rail are fully protected by at least two dielectric layers. This prevents breakdown problems as well as gate and contact leakage problems. The provided subject matter can be easily integrated into the existing IC manufacturing workflow.

Claims

[1] A method of forming a semiconductor device, the method comprising: Providing a precursor (100) comprising: a substrate (102) having first and second regions (102A, 102B), the first region (102A) comprising an insulator and the second region (102B) comprising source, drain and channel regions (104, 104, 106) of a transistor; a first gate stack (108A, 108C) over the insulator; second and third gate stacks (108E, 108F) over the channel region (106); and a first dielectric layer (110) over the first, second and third gate stacks; partially etching back the first dielectric layer (110); Forming a contact etch stop layer second dielectric layer (122) over the etched-back first dielectric layer (110); Forming a (124) over the second dielectric layer (122); and forming an interlayer dielectric layer (126) over the contact etch stop layer (124); Etching first and second openings (128) in the interlayer dielectric layer (126) above the second and third gate stacks (108E, 108F), respectively; Etching the contact etch stop layer (124) and the second dielectric layer (122) through the first and second openings (128) to expose the etched-back first dielectric layer (110) over the second and third gate stacks (108E, 108F); etching the interlayer dielectric layer (126) in the first region (102A) to expose the contact etch stop layer (124); Etching the contact etch stop layer (124) in the first region (102A) to expose the second dielectric layer (122); and Etching the etched-back first dielectric layer (110) to expose the second and third gate stacks (108E, 108F) while the first gate stack (108A, 108C) remains covered by the etched-back first dielectric layer (110) and the second dielectric layer (122) over the etched-back first dielectric layer. [2] The method of claim 1, wherein the first opening (128) is etched in a region (402) of the semiconductor device having a smaller gate via pitch than where (404, 406, 408) the second opening (128) is etched. [3] The method of claim 1, wherein the first opening (128) is etched in a region (404, 406, 408) of the semiconductor device having a larger gate via pitch than where (402) the second opening (128) is etched. [4] The method of any one of claims 1 to 3, wherein etching the contact etch stop layer (124) and the second dielectric layer (122) comprises an etch process tuned to remove the second dielectric layer (122) while leaving the etched-back first dielectric layer (110) substantially unchanged. [5] The method of any one of claims 1 to 4, wherein etching the etched-back first dielectric layer (110) comprises an etching process tuned to remove the etched-back first dielectric layer (110) while leaving the second dielectric layer (122) substantially unchanged. [6] The method of any one of claims 1 to 5, further comprising, prior to etching the interlayer dielectric layer (126) in the first region (102A): Etching S / D via openings (130) in the interlayer dielectric layer (126) over the S / D regions (104). [7] The method of claim 6, wherein the precursor (100) further comprises: S / D contacts (118B) over the S / D regions (104); and a third dielectric layer (120) over the S / D contacts (104), wherein etching the contact etch stop layer (124) in the second region (102B) comprises etching the contact etch stop layer (124) and the third dielectric layer (120) through the S / D via openings (130) to expose the S / D contacts (118B). [8] The method of claim 7, further comprising: Depositing a metal layer (132) over the first and second regions (102A, 102B), wherein the metal layer contacts the second and third gate stacks (108E, 108F) and the S / D contacts (118B), and wherein the metal layer is insulated from the first gate stack (108A, 108C) by at least the etched-back first dielectric layer (110) and the second dielectric layer (122). [9] The method of claim 8, further comprising: Performing a chemical mechanical planarization (CMP) process to remove portions of the metal layer (132) and the interlayer dielectric layer (126) until the contact etch stop layer (124) is exposed over the second region (102B). [10] The method of any preceding claim, wherein partially etching back the first dielectric layer (110) reduces a thickness of the first dielectric layer by approximately 10% to approximately 90%. [11] The method of any preceding claim, wherein the precursor (100) further comprises a fourth gate stack (108B) over the first region (102A) and the first dielectric layer (110) is formed over the first, second, third and fourth gate stacks, and wherein the method further comprises: Etching an opening (128) in the interlayer dielectric layer (126) above the fourth gate stack (108B); Etching a first portion of the second dielectric layer (122) through the opening (128) above the fourth gate stack (108B) to expose a first portion of the etched-back first dielectric layer (110); and Etching the first portion of the etched-back first dielectric layer (110) to expose the fourth gate stack (108B) while the first gate stack (108A, 108C) remains covered by a second portion of the etched-back first dielectric layer (110) and a second portion of the second dielectric layer (122). [12] The method of claim 11, wherein the metal layer contacts the fourth gate stack (108B). [13] The method of claim 11 or 12, wherein the fourth gate stack (108B) is disposed over the insulator in the first region (102A). [14] The method of any one of claims 11 to 13, wherein etching the first portion of the second dielectric layer (122) comprises an etching process tuned to remove the first portion of the second dielectric layer while leaving the first portion of the etched-back first dielectric layer (110) substantially unchanged. [15] The method of any one of claims 11 to 14, wherein etching the first portion of the etched-back first dielectric layer (110) comprises an etching process tuned to remove the first portion of the etched-back first dielectric layer (110) while leaving the second portion of the second dielectric layer (122) substantially unchanged.

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