Techniques for connecting an upper MRAM-MTJ electrode

Abstract

Integrated circuit (200) comprising: a semiconductor substrate (206); a connection structure (204) arranged above the semiconductor substrate (206) and comprising several dielectric layers (226, 228, 230) and several metal layers (232, 234, 236) stacked alternately on top of each other, the several metal layers (232, 234, 236) comprising a lower metal layer (234) and an upper metal layer (236) arranged above the lower metal layer (234); a lower electrode (254) arranged above the lower metal layer (234) and in electrical contact with it; a magnetic tunnel junction (258) arranged above an upper surface of the lower electrode (254); and an upper electrode (256) arranged above an upper surface of the magnetic tunnel junction (258) and in direct electrical contact with a lower surface of the upper metal layer (236); MRAM sidewall spacer (260),which are arranged along outer walls of the upper electrode (256) and the magnetic tunnel junction (258), wherein the MRAM sidewall spacers (260) have upper sections (127) extending upward beyond an upper face of the upper electrode (256) and into a recess in a lower face of the upper metal layer (236), wherein lower outer walls (132) of the MRAM sidewall spacers (260) are vertical or substantially vertical and meet upper outer walls (134) of the MRAM sidewall spacers (260) at a step (135) or shoulder region, wherein the MRAM sidewall spacers (260) have inner upper inner walls (128) separated by a first distance (d1) near the upper electrode (256), and lower inner walls (130) separated by a second distance (d2) are spaced apart, with the second distance (d2) being greater than the first distance (d1),wherein the inner lowermost sidewalls (130) are inclined at an angle other than 90 degrees corresponding to a normal passing through an upper surface of the lower electrode (254); and wherein a top surface (136) of each MRAM sidewall spacer (260) is rounded or tapered by extending obliquely outward downward from both sides of a tip (806) in the MRAM sidewall spacer (260), and wherein a dielectric liner (138) conformally lies over outer surfaces of the MRAM sidewall spacers (260).

Description

The present invention relates to an integrated circuit comprising: a semiconductor substrate; a interconnect structure arranged above the semiconductor substrate, comprising multiple dielectric layers and multiple metal layers stacked alternately, the multiple metal layers comprising a lower metal layer and an upper metal layer arranged above the lower metal layer; a lower electrode arranged above the lower metal layer and in electrical contact with it; a magnetic tunnel junction arranged above an upper surface of the lower electrode; and an upper electrode arranged above an upper surface of the magnetic tunnel junction and in direct electrical contact with a lower surface of the upper metal layer; MRAM sidewall spacers arranged along outer walls of the upper electrode and the magnetic tunnel junction.wherein the MRAM sidewall spacers have upper sections extending upwards beyond an upper surface of the upper electrode and into a recess in a lower surface of the upper metal layer, wherein lower outer walls of the MRAM sidewall spacers are vertical or substantially vertical and meet upper outer walls of the MRAM sidewall spacers at a shoulder or shoulder area. The invention further relates to an MRAM cell and a method for manufacturing an MRAM cell. An integrated circuit is known, for example, from US 2014 / 0210103 A1. Similar integrated circuits are also known from US 8 710 605 B2, US 2011 / 0 189 796 A1, DE 103 28 350 A1, US 7 211 849 B2, US 2014 / 0 264 222 A1, and US 2013 / 0 234 090 A1. An integrated circuit can also be found in JP 2013-143 548 A. GENERAL STATE OF THE ART Many modern electronic devices contain electronic memory. Electronic memory can be volatile or non-volatile. Non-volatile memory is able to retain its stored data in the absence of power, while volatile memory loses its stored data when power is interrupted. Magnetoresistive random-access memory (MRAM) is a promising candidate for next-generation non-volatile memory due to its advantages over current electronic memory. Compared to current non-volatile memory, such as flash memory, MRAM is typically faster and exhibits better long-term performance.Compared to dynamic random access memory (DRAM) and static random access memory (SRAM), MRAM typically has comparable performance and density, but lower power consumption. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood from the detailed description below when read together with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Rather, the dimensions of the various features may have been enlarged or reduced arbitrarily for clarity of discussion. Fig. 1 shows a cross-sectional view of some embodiments of an MRAM cell comprising a magnetic tunnel junction (MTJ) according to this disclosure. Fig. 2 shows a cross-sectional view of some embodiments of an integrated circuit comprising MRAM cells. Fig. 3 shows a top view of some embodiments of the integrated circuit of Fig. 2 comprising MRAM cells. Fig. 4 shows an enlarged cross-sectional view of an MRAM cell of the integrated circuit of Fig. 2. Figs. 5, 6, 7, 8, and 9Figures 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 to 20 show a series of step-by-step manufacturing processes as a series of cross-sectional views. Figure 21 shows a methodology in a flowchart format, illustrating some embodiments of the present concept. DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is done for the sake of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed. Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly. A magnetoresistive random-access memory (MRAM) cell comprises an upper and a lower electrode and a magnetic tunnel junction (MTJ) located between the upper and lower electrodes. In conventional MRAM cells, the upper electrode is connected to an overlying metal layer (e.g., Metal 1, Metal 2, Metal 3, etc.) by means of a contact or via. Although the use of this coupling contact or via is common, the overall height of this MRAM cell, including this contact or via, is large relative to a typical vertical distance between adjacent metal layers (e.g., between a layer of Metal 2 and a layer of Metal 3).To make this height more similar to the vertical distance between adjacent metal layers, the present disclosure provides techniques for coupling the upper electrode directly to an overlying metal conductor without an intermediate via or contact. With reference to Fig. 1, a cross-sectional view of an MRAM cell 100 according to some embodiments is provided. The MRAM cell 100 comprises a lower electrode 102 and an upper electrode 104, which are separated from each other by a magnetic tunnel junction (MTJ) 106. The lower and upper electrodes 102 and 104 are arranged between a lower metal layer 114 and an upper metal layer 116 and are surrounded by a dielectric material, such as a dielectric intermediate layer (ILD) or a dielectric intermediate metal layer (IMD) 124. The MTJ 106 comprises a lower ferromagnetic electrode 108 and an upper ferromagnetic electrode 110, separated from each other by a tunnel barrier layer 112. In some embodiments, the lower ferromagnetic electrode 108 can have a fixed magnetic orientation, while the upper ferromagnetic electrode 110 has a variable or free magnetic orientation that can be switched between two or more distinguishable magnetic polarities, each representing a different data state, such as a different binary state. In other implementations, however, the MTJ 106 can be vertically flipped so that the lower ferromagnetic electrode has a free magnetic orientation, while the upper ferromagnetic electrode 110 has a fixed magnetic orientation. Instead of a contact or via coupling between the upper electrode 104 and the overlying metal layer 116, the upper electrode 104 itself is in direct contact with the overlying metal layer 116. In some embodiments, the upper electrode 104 and the overlying metal layer 116 meet at a planar interface 122 that extends between adjacent MRAM sidewall spacers 126. Since there is no via or contact between the upper electrode 104 and the overlying metal layer 116, the overall height of the MRAM cell 100 is more easily compatible with back-end-of-line processes. In some embodiments, the MRAM sidewall spacers 126 have upper sections 127 that project upwards beyond an upper surface of the upper electrode 104 and into a recess in a lower surface region of the upper metal layer 116. The MRAM sidewall spacers 126 may also have upper inner walls 128 that are separated from each other by a first distance d1 near the upper electrode 104. The inner walls of the MRAM sidewall spacers may slope outwards towards their lower sections, such that lower inner walls 130 are spaced apart from each other by a second distance d2 near the lower electrode 102 (d2 > d1). Lower outer walls 132 of the MRAM sidewall spacers 126 may be vertical or substantially vertical, and may meet upper outer walls 134 of the MRAM sidewall spacers 126 at a ledge 135 or shoulder area.The upper outer walls 134 of the MRAM sidewall spacers can taper inwards, and the upper surfaces 136 of the MRAM sidewall spacers 126 can be, for example, rounded or tapered, as shown. A dielectric liner 138, such as a silicon dioxide liner, can conform to the lower and upper outer walls of the MRAM sidewall spacers and can extend over a dielectric protective layer 140. The dielectric liner 138 can have a vertical projection 142 that extends upward into a recess between the upper outer walls 134 and the upper metal layer 116. It is understood that the features of Fig. 1 can provide a reduced distance between the lower and upper metal layers 114 and 116 due to direct contact between the upper electrode 104 and the upper metal layer 116, and can also be available for streamlined manufacturing techniques. Fig. 2 shows a cross-sectional view of some embodiments of an integrated circuit 200 comprising MRAM cells 202a, 202b arranged in a connection structure 204 of the integrated circuit 200. The integrated circuit 200 comprises a substrate 206. The substrate 206 can be a bulk substrate (e.g., a bulk silicon substrate) or an SOI substrate (silicon on an insulator). The illustrated embodiment demonstrates one or more STI (shallow trench insulation) regions 208, which can comprise a dielectric-filled trench within the substrate 206. Two word conduction transistors 210 and 212 are arranged between the STI regions 208. Each word conduction transistor 210 and 212 comprises a word conduction gate electrode 214 and 216, respectively, a word conduction gate dielectric 218 and 220, respectively, word conduction sidewall spacers 222, and source / drain regions 224. The source / drain regions 224 are located within the substrate 206 between the word conduction gate electrodes 214 and 216 and the STI regions 208, and are doped such that they exhibit a first conductivity type that is opposite to a second conductivity type of a channel region under the gate dielectrics 218 and 220, respectively. The word-conducting gate electrodes 214, 216 can be, for example, doped polysilicon or a metal, such as aluminum, copper, or combinations thereof. The word-conducting gate dielectrics 218, 220 can be, for example, an oxide, such as silicon dioxide, or a high-k dielectric material.The word-conducting sidewall spacers 222 can, for example, be made of silicon nitride (e.g. Si3N4). The interconnect structure 204 is arranged above the substrate 206 and couples devices (e.g., transistors 210, 212) to one another. The interconnect structure 204 comprises several IMD layers 226, 228, 230 and several metallization layers 232, 234, 236, which are stacked on top of each other in an alternating manner. The IMD layers 226, 228, 230 can, for example, be made of a low-k dielectric, such as undoped silicate glass, or an oxide, such as silicon dioxide, or an extreme-low-k dielectric layer. The metallization layers 232, 234, 236 comprise metal conductors 238, 240, 241, 242, which are formed within grooves and which can be made of a metal, such as copper or aluminum.Contacts 244 extend from the lower metallization layer 232 to the source / drain regions 224 and / or gate electrodes 214, 216; and vias 246 extend between the metallization layers 232, 234, 236. The contacts 244 and the vias 246 extend through dielectric protective layers 250, 252 (which can be made of a dielectric material and can act as an etch stop layer during fabrication). The dielectric protective layers 250, 252 can, for example, be made of an extreme-low-k dielectric material, such as SiC. The contacts 244 and the vias 246, 248 can, for example, be made of a metal, such as copper or tungsten. MRAM cells 202a, 202b, designed to store respective data states, are arranged within the interconnection structure 204 between adjacent metal layers. MRAM cell 202a comprises a lower electrode 254 and an upper electrode 256, both made of a conductive material. Between its upper and lower electrodes 254, 256, MRAM cell 202a includes an MTJ 258. MRAM cell 202a also includes MRAM sidewall spacers 260. The metal conductor 242 has a bottom surface that is coplanar with an upper surface of the upper electrode 256 and is in direct electrical contact with it (e.g., resistively coupled). Fig. 3 illustrates some embodiments of a top view of the integrated circuit 200 of Fig. 2, as shown in the section lines depicted in Figs. 2 to 3. As can be seen, in some embodiments, the MRAM cells 202a, 202b can have a square, rectangular, or circular shape when viewed from above. In other embodiments, however, for example, due to the feasibility of multiple etching processes, the corners of the depicted square shape can be rounded, resulting in the MRAM cells 202a, 202b having a square or rectangular shape with rounded corners, or a circular or oval shape. The MRAM cells 202a, 202b are each arranged over a metal conductor 240 or 241, respectively, and have upper electrodes 256 that are in direct electrical contact with metal conductors 242, without any vias or contacts between them. With reference to Fig. 4, an enlarged cross-sectional view of the MRAM cell 202a from Fig. 2 is provided. As shown, the MRAM cell 202a comprises a lower electrode 254 and an upper electrode 256, with the MTJ 258 arranged between the lower electrode 254 and the upper electrode 256. The lower electrode 254 extends downwards through an opening in the dielectric protective layer 252 to make electrical contact with the underlying metal conductor 240. In the illustrated embodiment, the MTJ 258 comprises a lower ferromagnetic electrode 266 (which may have a fixed magnetic orientation) and an upper ferromagnetic electrode 268 (which may have a free magnetic orientation). A tunnel barrier layer 270 is arranged between the lower and upper ferromagnetic electrodes 266, 268; and a cover layer 272 is arranged over the upper ferromagnetic electrode 268. The lower ferromagnetic electrode 266 can be a synthetic antiferromagnetic structure (SAF structure) comprising an upper fixed ferromagnetic layer 274, a lower fixed ferromagnetic layer 276, and a metal layer 278 arranged between the upper and lower fixed ferromagnetic layers 274, 276. In some embodiments, the upper ferromagnetic electrode 268 comprises Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd, or the like. In some embodiments, the cover layer 272 comprises WO2, NiO, MgO, Al2O3, Ta2O5, MoO2, TiO2, GdO, Al, Mg, Ta, Ru, or the like. In some embodiments, the tunnel barrier layer 270 provides electrical insulation between the upper ferromagnetic electrode 268 and the lower ferromagnetic electrode 266, while still allowing electrons to tunnel through the tunnel barrier layer 270 under suitable conditions. The tunnel barrier layer 270 can, for example, comprise magnesium oxide (MgO), aluminum oxide (e.g., Al2O3), NiO, GdO, Ta2O5, MoO2, TiO2, WO2, or the like. During operation, the variable magnetic polarity of the upper (i.e., the free) ferromagnetic electrode 268 is typically read by measuring the resistance of the MTJ 258. Due to the magnetic tunneling effect, the resistance of the MTJ 258 changes with the variable magnetic polarity. Furthermore, during operation, the variable magnetic polarity is typically changed or switched back and forth using the spin-transfer torque (STT) effect. According to the STT effect, a current is passed through the MTJ 258 to induce a flow of electrons from the lower (i.e., the fixed) ferromagnetic electrode 266 to the upper (i.e., the free) ferromagnetic electrode 268. As electrons pass through the lower ferromagnetic electrode 266, the spins of the electrons become polarized.When the electrons with polarized spins reach the upper ferromagnetic electrode 268, they exert a torque on the changing magnetic polarity and switch the state of the free ferromagnetic electrode (e.g., the upper electrode 268). Alternative approaches for reading or changing the changing magnetic polarity are also possible. For example, in some alternative approaches, the magnetization polarities of the fixed and / or the free ferromagnetic electrode 266 / 268 are perpendicular to an interface between the tunnel barrier layer 270 and the fixed and / or the free ferromagnetic electrode 266 / 268, thus making the MTJ 258 a perpendicular MTJ. Since the upper electrode 256 is in direct electrical contact with the metal conductor 242 above it, the overall height of the MRAM cells 202a, 202b can advantageously be reduced compared to previous approaches. Compared to previous approaches, the reduced height makes the MRAM cells 202a, 202b more compatible with BEOL processes. Therefore, the design of the MRAM cells 202a, 202b provides improved MRAM processes with reduced manufacturing costs. With reference to Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. 20, cross-sectional views of some embodiments of a semiconductor structure incorporating an MRAM cell are provided at various stages of fabrication. Although Figures 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 to 20 are described as a series of processes, it is understood that these processes are not limited in this respect, so that the sequence of the processes can be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some of the processes that are illustrated and / or described can be omitted entirely or partially. Fig. 5 illustrates a cross-sectional view of some embodiments, showing a section of a connection structure 204 arranged over a substrate (not shown in Fig. 5, but shown above in Fig. 2). The connection structure 204 comprises an IMD layer 228 and a metal conductor 240 extending horizontally through the IMD layer 228. The IMD layer 228 can be an oxide, such as silicon dioxide, a low-k dielectric material, or an extreme-low-k dielectric material. The metal conductor 240 can be made of a metal, such as aluminum, copper, or combinations thereof. In some embodiments, the substrate can be a bulk silicon substrate or an SOI (semiconductor on an insulator) substrate (e.g., silicon on an insulator substrate). The substrate can also be, for example, a binary semiconductor substrate (e.g., GaAs), a ternary semiconductor substrate (e.g., AlGaAs), or a higher-order semiconductor substrate.In many cases, the substrate comprises a semiconductor wafer and can have a diameter of, for example, 1 inch (25 mm), 2 inches (51 mm), 3 inches (76 mm), 4 inches (100 mm), 5 inches (130 mm), or 125 mm (4.9 inches); 150 mm (5.9 inches, usually referred to as "6 inches"), 200 mm (7.9 inches, usually referred to as "8 inches"), 300 mm (11.8 inches, usually referred to as "12 inches"), or 450 mm (17.7 inches, usually referred to as "18 inches"). After processing is complete, for example, after the MRAM cells have been formed, such a wafer can optionally be stacked with other wafers or a die and subsequently singulated into individual dies corresponding to individual ICs. A dielectric protective layer 252 is formed over the IMD layer 228 and over the metal conductor 240. The dielectric protective layer 252 is made of a dielectric material, such as an oxide or an ELK dielectric, and acts as an etch stop layer. In some embodiments, the dielectric protective layer 252 comprises SiC having a thickness of approximately 20 nm. A lower electrode layer 254 is formed over the dielectric protective layer 252 and extends downward through an opening in the dielectric protective layer 252, so that it comes into electrical contact with an upper section of the metal conductor 240. The lower electrode layer 254 can be a conductive material, such as titanium nitride, tantalum nitride, titanium, tantalum, or a combination of one or more of the above. Furthermore, in some embodiments the lower electrode layer 254 can be, for example, approximately 10 to 100 nanometers thick.A magnetic tunnel junction stack (MTJ stack) 258' is formed over an upper surface of the lower electrode layer 254, and an upper electrode layer 256 is formed over the MTJ stack 258'. The upper electrode layer 256 can be a conductive material, such as titanium nitride, tantalum nitride, titanium, tantalum, or a combination of one or more of the above. Furthermore, the upper electrode layer 256 can be, for example, approximately 10 to 100 nanometers thick. A mask 502 is arranged over an upper surface of the upper electrode layer 256. In some embodiments, the mask 502 comprises a photoresist mask, but it can also be a hard mask, such as a nitride mask. In the illustrated embodiment, the mask 502 is a hard mask comprising a SiON layer 504, a SiO2 layer 506, and a Si3N4 layer 508.The side walls of the MTJ 258 and / or the upper electrode 256 may be inclined at an angle other than 90 degrees, corresponding to a normal passing through an upper surface of the lower electrode 254. As shown in Fig. 6, a sidewall spacer layer 260' is formed over lateral sections of the lower electrode 254, lines the sidewalls of the MTJ 258', lines the sidewalls of the upper electrode 256, and extends over the sidewalls and the upper surface of the mask 502. In some embodiments, the sidewall spacer layer 260' can be formed using any suitable deposition technique and is typically conformal. Furthermore, the sidewall spacer layer 260' can be formed, for example, from silicon nitride, silicon carbide, Si3N4, SiON, or a combination of one or more of the above. The sidewall spacer layer 260' can even be formed with a thickness of, for example, approximately 50 nm. A dielectric liner 602, such as a conformal oxide, is then formed over the sidewall spacer layer 260'. In Fig. 7, a first etch 700 was performed on the sidewall spacer layer 260' to back-etch the sidewall spacer layer 260' and remove lateral extensions of the sidewall spacer layer 260', thereby forming the sidewall spacers 260. In some embodiments, this first etch 700 is a unidirectional or vertical etch. The first etch 700 can also remove the SiON layer 504 and stop at the SiO2 layer 506. In many cases, the first etch 700 also reduces the height of the SiO2 layer 506, and therefore the original thickness of the SiO2 layer 506 in Fig. 5 is sufficient to provide adequate clearance for the first etch 700. In Fig. 8, a second etch 800 is performed to remove the remaining SiO2 spacer 506 above the silicon nitride layer 508. This second etch 800 may have an etching chemistry different from that of the first etch 700 and is generally selective with respect to the SiO2 material of the SiO2 layer 506. Therefore, the second etch 800 leaves the silicon nitride spacers 260 and the lower silicon nitride layer 508 essentially intact and, in some cases, may round off the top faces of the silicon nitride spacers 260. Thus, a top face of each MRAM sidewall spacer may be rounded or tapered so that it extends downward from both sides of a point 806 in the respective MRAM spacer. In Fig. 9, a dielectric liner 138, such as a silicon dioxide liner, can be conformally deposited over the lateral sections of the dielectric protective layer 252, over the sidewalls and upper surfaces of the MRAM sidewall spacers 260, and over the remaining silicon nitride layer 508. An IMD layer 230, such as an extreme-low-k dielectric layer, is then formed over the dielectric liner 138, for example, by chemical vapor deposition (CVD), plasma vapor deposition (PVD), spin-on techniques, or thermal oxidation. In Fig. 10, a chemical-mechanical polishing or chemical-mechanical planarization process (CMP process) is performed to planarize an upper surface of the IMD layer 230. In Fig. 11, photolithography is performed to structure one or more masks (not shown), and one or more corresponding etching operations are performed to form trench openings 1100 and through-holes 1102. In some embodiments, these openings may be dual damascene openings. In Fig. 12, a metal, such as aluminum or copper, is used to fill the trenches and openings. Therefore, in a storage region, the trench is filled with a metal conductor 242, which is in direct contact with an upper region of the upper electrode 256, thus providing an ohmic connection without a contact or via between the metal conductor 242 and the upper electrode 256. In another region of the integrated circuit, such as a logic region where CMOS logic devices are formed, a metal conductor 1200 is coupled to an underlying metal conductor 1204 via a via 1202. A CMP process is then performed to planarize an upper surface of the metal conductors and an upper surface of the IMD layer 230, resulting in the structure shown in Fig. 12. Figures 13, 14, 15 to 16 illustrate an alternative embodiment in which the mask over the upper electrode comprises a SiO₂ spacer layer 1306 and a SiON cover layer 1304. Compared with the previous Figures 5, 6, 7 to 8, the embodiment shown in Figures 13 to 16 omits the silicon nitride etch stop layer 508 over the upper electrode 256. This omission may streamline processing somewhat, which can reduce costs. In particular, Fig. 13 shows an IMD layer 228, a metal conductor 240, a dielectric protective layer 252, and a lower electrode layer 254. A magnetic tunnel junction stack (MTJ stack) 258' is formed on an upper surface of the lower electrode layer 254, a cover layer is formed over the MTJ stack 258', and an upper electrode layer 256 is formed over the cover layer. A mask 1302, comprising a SiON cover layer 1304 and a SiO2 spacer layer 1306, is arranged over an upper surface of the upper electrode layer 256. In Fig. 14, a sidewall spacer layer 260' is formed over lateral sections of the lower electrode 254, lining the sidewalls of the MTJ 258', the sidewalls of the upper electrode 256, and extending over the sidewalls and the upper surface of the mask 1302. An oxide liner 602, such as a conformal oxide, is then formed over the sidewall spacer layer 260'. In Fig. 15, a first etch 1500 was performed on the sidewall spacer layer 260' to back-etch the sidewall spacer layer 260' and remove lateral extensions of the sidewall spacer layer 260', thereby forming sidewall spacers 260. In some embodiments, this first etch 1500 is a unidirectional or vertical etch. The first etch 1500 can also remove the SiO₂ cover layer 504 and stop on the SiO₂ spacer layer 1306. In many cases, the first etch 1500 also reduces the height of the SiO₂ spacer layer 1306, and therefore the original thickness of the SiO₂ spacer layer 1306 in Fig. 6 is sufficient to provide adequate clearance for the first etch 1500. In Fig. 16, a second etching 1600 is performed to remove the remaining SiO2 spacer 506 above the upper electrode 256 and above the silicon nitride spacer 260'. This second etching 1600 may have an etching chemistry that differs from that of the first etching 1500 and is generally selective with respect to the SiO2 material of the SiO2 layer 506. Therefore, the second etching 1600 leaves the silicon nitride spacer 260 behind, exposes an upper surface of the upper electrode 256, and in some cases may "round off" the upper surfaces of the silicon nitride spacer 260. According to Fig. 16, processes similar to Fig. 9, Fig. 10, Fig. 11 to Fig. 12 can be carried out, although the dielectric liner 138 of Fig. 9 is in direct contact with an upper surface of the upper electrode 256. Figures 17, 18, 19 to 20 show another alternative embodiment. Following the steps described above in Figures 9, 10, 11, 12, 13, 14, 15, 16 to 17, an oxide layer 1702 is formed over the structure of Figure 9. In Figure 18, a CMP process is performed to planarize the oxide layer 1702; and in Figure 19, trench openings and via openings are formed. In Figure 20, a metal is deposited to fill the trench openings and via openings, forming metal conduits 2002 and 2004. The oxide layer 1702 is thicker over the logic area 2006 and thinner over the memory area 2008. Therefore, the final structure in Fig. 20 has both a low-k dielectric 230 and an oxide 1702 at different heights on the sidewalls of the metal conductors. Fig. 21 presents a method 2100 for forming an MRAM cell according to some embodiments. Although this method and other methods presented and / or described herein are presented as a series of operations or events, it is understood that the present disclosure is not limited to the sequence or operations shown. Therefore, in some embodiments, the operations may be carried out in a different sequence than shown, and / or they may be carried out simultaneously. Furthermore, in some embodiments, the operations or events shown may be subdivided into several operations or events that may be carried out at different times or simultaneously with other operations or sub-operations.In some embodiments, some depicted processes or events may be omitted and other processes or events not depicted may be included. Processes 2102 to 2108 can, in some embodiments, correspond, for example, to the structure shown above in Fig. 5. In 2102, an etch stop layer is formed over an upper surface of a dielectric layer. The etch stop layer has an opening that leaves at least a section of an upper surface of an underlying metal conductor exposed. In 2104, a lower electrode layer is formed over the etch stop layer. The lower electrode layer extends downward through the opening to make physical and electrical contact with the underlying metal layer. In 2106, a magnetic tunnel junction layer (MTJ layer) is formed over the lower electrode layer. In 2108, an upper electrode layer is formed over the magnetic tunnel junction layer. In 2110, which corresponds, for example, to the structure shown above in Fig. 5,To correspond to 12, an upper metal layer is formed in such a way that it is in physical and electrical contact with the upper electrode. Some embodiments relate to an integrated circuit comprising a magnetoresistive random-access memory (MRAM) cell. The integrated circuit comprises a semiconductor substrate and an interconnect structure arranged above the semiconductor substrate. The interconnect structure comprises multiple dielectric layers and multiple metal layers stacked alternately. The multiple metal layers comprise a bottom metal layer and an top metal layer arranged above the bottom metal layer. A bottom electrode is arranged above the bottom metal layer and is in electrical contact with it. A magnetic tunnel junction (MTJ) is arranged above an upper surface of the bottom electrode. An upper electrode is arranged above an upper surface of the MTJ and is in direct electrical contact with a bottom surface of the upper metal layer. It is understood that in this written description and in the claims below, the terms "first," "second," "third," etc., are merely generic terms used to simplify the description and to distinguish between different elements of a figure or a series of figures. In and of themselves, these terms do not imply any temporal sequence or structural proximity for these elements and are not intended as descriptions of corresponding elements in other illustrated and / or unillustrated embodiments. For example, "a first dielectric layer" described in connection with a first figure does not necessarily correspond to a "first dielectric layer" described in connection with another figure, nor does it necessarily correspond to a "first dielectric layer" in an unillustrated embodiment.

Claims

Integrated circuit (200) comprising: a semiconductor substrate (206); a connection structure (204) arranged above the semiconductor substrate (206) and comprising several dielectric layers (226, 228, 230) and several metal layers (232, 234, 236) stacked alternately on top of each other, the several metal layers (232, 234, 236) comprising a lower metal layer (234) and an upper metal layer (236) arranged above the lower metal layer (234); a lower electrode (254) arranged above the lower metal layer (234) and in electrical contact with it; a magnetic tunnel junction (258) arranged above an upper surface of the lower electrode (254); and an upper electrode (256) arranged above an upper surface of the magnetic tunnel junction (258) and in direct electrical contact with a lower surface of the upper metal layer (236); MRAM sidewall spacer (260),which are arranged along outer walls of the upper electrode (256) and the magnetic tunnel junction (258), wherein the MRAM sidewall spacers (260) have upper sections (127) extending upward beyond an upper face of the upper electrode (256) and into a recess in a lower face of the upper metal layer (236), wherein lower outer walls (132) of the MRAM sidewall spacers (260) are vertical or substantially vertical and meet upper outer walls (134) of the MRAM sidewall spacers (260) at a step (135) or shoulder region, wherein the MRAM sidewall spacers (260) have inner upper inner walls (128) separated by a first distance (d1) near the upper electrode (256), and lower inner walls (130) separated by a second distance (d2) are spaced apart, with the second distance (d2) being greater than the first distance (d1),wherein the inner lowermost sidewalls (130) are inclined at an angle other than 90 degrees corresponding to a normal passing through an upper surface of the lower electrode (254); and wherein a top surface (136) of each MRAM sidewall spacer (260) is rounded or tapered by extending obliquely outward downward from both sides of a tip (806) in the MRAM sidewall spacer (260), and wherein a dielectric liner (138) conformally lies over outer surfaces of the MRAM sidewall spacers (260). MRAM cell (202a) arranged on a semiconductor substrate (206), the MRAM cell (202a) comprising: a lower electrode (254) arranged above the semiconductor substrate (206); a magnetic tunnel junction (258) arranged above the lower electrode (254); an upper electrode (256) arranged above an upper surface of the magnetic tunnel junction (258); and a metal conductor (242) arranged above the upper electrode (256) and in direct physical and electrical contact with the upper electrode (256), without any via or contact extending between the metal conductor (242) and the upper electrode (256);MRAM sidewall spacers (260) arranged along outer walls of the upper electrode (256) and the magnetic tunnel junction (258), wherein the MRAM sidewall spacers (260) have upper sections (127) extending upward beyond an upper surface of the upper electrode (256) and into a lower surface region of the metal conductor (242), wherein lower outer walls (132) of the MRAM sidewall spacers (260) are vertical or substantially vertical and meet upper outer walls (134) of the MRAM sidewall spacers (260) at a step (135) or shoulder region; wherein the MRAM sidewall spacers (260) have inner upper sidewalls (128) separated by a first gap (d1) near the upper electrode (256) and inner lowest sidewalls (130) that are extended by a are spaced apart by the second distance (d2), where the second distance (d2) is greater than the first distance (d1);wherein the inner lowermost sidewalls (130) are inclined at an angle other than 90 degrees corresponding to a normal passing through an upper surface of the lower electrode (254); and wherein a top surface (136) of each MRAM sidewall spacer (260) is rounded or tapered by extending obliquely outward downward from both sides of a tip (806) in the MRAM sidewall spacer (260), and wherein a dielectric liner (138) conformally lies over outer surfaces of the MRAM sidewall spacers (260). MRAM cell (202a) according to claim 2, wherein the MRAM side wall spacers (260) have bottom surfaces that rest on an upper surface of the lower electrode (254). Method for fabricating an MRAM cell (202a), the method comprising: forming an etch stop layer (252) arranged over an upper surface of a dielectric layer (228), the etch stop layer (252) having an opening that leaves at least a section of an upper surface of an underlying metal conductor (240) exposed; forming a lower electrode layer (254) over the etch stop layer (252), the lower electrode layer (254) extending downward through the opening so that it is in physical and electrical contact with the underlying metal conductor (240); forming a magnetic tunnel junction layer (258) over the lower electrode layer (254); forming an upper electrode (256) over the magnetic tunnel junction layer (258); forming an upper metal layer (242) in direct electrical and physical contact with an upper section of the upper electrode (256);wherein the formation of the upper electrode (256) further comprises: forming an upper electrode layer over the magnetic tunnel junction layer (258); forming a hard mask (502, 504, 506, 508) over the upper electrode layer (256); structuring the magnetic tunnel junction layer (258) and the upper electrode layer (256) to remove sections of both the magnetic tunnel junction layer (258) and the upper electrode layer (256) that are not covered by the hard mask (502, 504, 506, 508) in order to form the upper electrode (256) and the magnetic tunnel junction (258);Forming a conformal MRAM sidewall spacer layer (260) arranged along outer walls of the upper electrode (256) and the magnetic tunnel junction (258), extending over an upper surface of the hard mask (502, 504, 506, 508), the hard mask (502, 504, 506, 508) comprising a SiO2 layer (506) and a SiON layer (504) above the SiO2 layer (506); performing a first etching on the MRAM sidewall spacer layer (260) to remove lateral sections of the MRAM sidewall spacer layer (260), leaving the SiO2 layer (506) above the upper electrode (256) and sections of the MRAM sidewall spacer layer (260) extending upwards along side walls of the extend SiO2 layer (506);and performing a second etching to selectively remove the SiO2 layer (506), leaving behind the sections of the MRAM sidewall spacer layer (260) that extend upwards beyond an upper surface of the upper electrode (256). Method according to claim 4, wherein the hard mask (502, 504, 506, 508) comprises a silicon nitride layer (508) between the SiO2 layer (506) and the upper electrode (256). Method according to claim 4, wherein a lowermost section of the SiO2 layer (506) is directly adjacent to an upper surface of the upper electrode (256). The method of claim 4, further comprising: forming a dielectric layer (138) over the sections of the MRAM sidewall spacer layer (260) and the upper electrode (256); and forming trench and via openings in the dielectric layer (138), wherein a trench opening exposes upper surfaces of the upper electrode (256) and sections of the MRAM sidewall spacer layer (260); and filling the trench and via openings with a conductive material (242) that directly abuts an upper surface of the upper electrode (256).

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