Flash device and method of forming the same

Abstract

The application relates to a FLASH device and a forming method thereof. The forming method of the FLASH device comprises the following steps: forming a substrate, the substrate comprising a substrate, a plurality of unit structures located above the substrate and an isolation groove located between adjacent unit structures, the unit structure comprising a floating gate and a dielectric layer covering the floating gate; forming a filling layer filling the isolation groove and covering the dielectric layer; forming an auxiliary layer covering the filling layer, the etching selection ratio of the auxiliary layer and the filling layer reaching 1:1; etching back the auxiliary layer and the filling layer at the same etching rate, removing the auxiliary layer and part of the filling layer, and the surface of the remaining filling layer away from the substrate being flush with the surface of the dielectric layer away from the substrate. The application reduces or even avoids the generation of a filling layer sharp corner at the edge of the isolation groove, and eliminates the influence of the filling layer sharp corner on the subsequent deposition of an erasing layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a FLASH device and a method for forming the same. Background Technology

[0002] As a core category of non-volatile memory, FLASH devices are widely used in smartphones, solid-state drives (SSDs), embedded systems, and other fields due to their advantages such as data retention after power failure, high read / write speeds, and long lifespan. With the evolution of semiconductor process nodes towards 14nm and below, the feature size of FLASH devices continues to shrink, and the three-dimensional integration of device structures is constantly improving, placing stringent requirements on the fabrication precision and planarization quality of critical layers.

[0003] FLASH devices typically include key layers such as a substrate, tunneling oxide layer, select gate, floating gate, barrier dielectric layer, and erase polysilicon layer. The erase polysilicon layer, covering the select gate and the floating gate, is used to erase electrons from the floating gate. This erase polysilicon layer significantly impacts the erase speed, threshold voltage stability, and lifespan of the FLASH device. During FLASH device manufacturing, after depositing the floating gate material layer, a patterning process is used to form trenches penetrating the floating gate material layer, dividing it into multiple independent floating gates. To prevent uneven thickness of the subsequent erase polysilicon layer deposition due to the presence of these trenches, the trenches are filled with a material such as SiN before deposition, forming a filling layer. To improve the flatness of the wafer surface after the filling layer is formed, a BARC (bottom anti-reflective coating) is usually applied to the wafer surface after the filling layer is formed, followed by planarization through etching. However, during the planarization process, it is difficult to control the etching selectivity ratio of BARC to SIN at 1:1, that is, it is difficult to make the removal rates of BARC and SIN equal during the etching process. As a result, the SIN at the edge of the trench is not fully removed, forming sharp protrusions, i.e., SIN sharp corners. This seriously affects the planarization effect, making it easy for the erased polysilicon layer to accumulate at the sharp corners, affecting the erase performance of FLASH devices, and even causing some devices to fail to erase.

[0004] Therefore, how to solve the problem of sharp corners easily formed in the planarization process before the formation of the erase layer, improve the effect of the planarization process, thereby improving the uniformity of the erase layer thickness distribution and ensuring the performance of FLASH devices, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This invention provides a FLASH device and its formation method, which solves the problem of sharp corners easily formed in the planarization process before the formation of the erase layer, improves the effect of the planarization process, thereby improving the uniformity of the erase layer thickness distribution and ensuring the performance of the FLASH device.

[0006] According to some embodiments, the present invention provides a method for forming a FLASH device, comprising the following steps: A substrate is formed, the substrate including a substrate, a plurality of cell structures located above the substrate and isolation trenches located between adjacent cell structures, the cell structure including a floating gate and a dielectric layer covering the floating gate; A filling layer is formed that fills the isolation trench and covers the dielectric layer; An auxiliary layer is formed to cover the filler layer, wherein the etching selectivity ratio of the auxiliary layer to the filler layer is 1:1; The auxiliary layer and the filler layer are etched back at the same etching rate to remove the auxiliary layer and a portion of the filler layer, and the remaining surface of the filler layer facing away from the substrate is flush with the surface of the dielectric layer facing away from the substrate.

[0007] In some embodiments, the specific steps for forming the substrate include: Provide substrate; A floating gate material layer is formed above the substrate; A dielectric material layer is formed covering the surface of the floating gate material layer opposite to the substrate; The dielectric material layer and the floating gate material layer are etched to form an isolation trench that penetrates the dielectric material layer and the floating gate material layer. The isolation trench divides the floating gate material layer into a plurality of floating gates and the dielectric material layer into a plurality of dielectric layers.

[0008] In some embodiments, the specific steps of forming a filling layer that fills the isolation trench and covers the dielectric layer include: Silicon nitride material is deposited on the substrate to form a filling layer that fills the isolation trench and covers the surface of the dielectric layer opposite to the substrate.

[0009] In some embodiments, the specific steps of forming an auxiliary layer covering the filling layer include: A silica material is deposited on the substrate using a chemical vapor deposition process to form the auxiliary layer covering the filler layer.

[0010] In some embodiments, the thickness of the auxiliary layer is greater than the thickness of the filler layer above the dielectric layer.

[0011] In some embodiments, before re-etching the auxiliary layer and the fill layer at the same etching rate, the following steps are further included: The thickness of the auxiliary layer is reduced by chemical mechanical polishing.

[0012] In some embodiments, the specific steps of re-etching the auxiliary layer and the filler layer at the same etching rate include: The auxiliary layer and the filler layer are etched back using a dry etching process, and the etching parameters of the dry etching process are adjusted so that the etching selection ratio of the auxiliary layer to the filler layer is 1:1.

[0013] In some embodiments, the specific steps of adjusting the etching parameters of the dry etching process so that the etching selection ratio of the auxiliary layer to the filler layer is 1:1 include: A mixed gas comprising fluorocarbon-based gas and oxygen is used as the etching gas, and the ratio of the fluorocarbon-based gas and oxygen is adjusted so that the etching selectivity ratio of the auxiliary layer to the filler layer is 1:1.

[0014] In some embodiments, after re-etching the auxiliary layer and the filler layer at the same etching rate to remove the auxiliary layer and a portion of the filler layer, and after the surface of the remaining filler layer is flush with the surface of the dielectric layer, the method further includes the following steps: An erase layer is formed on the surface of the dielectric layer opposite to the floating gate.

[0015] According to other embodiments, the present invention also provides a FLASH device, formed using the FLASH device formation method described above; the FLASH device includes: The substrate includes a front side and a back side that are relatively distributed. Multiple unit structures are arranged at intervals above the front side of the substrate in a direction parallel to the front side of the substrate. Each unit structure includes a floating gate and a dielectric layer covering the floating gate. A filler layer is filled between adjacent unit structures, and the surface of the filler layer facing away from the substrate is flush with the surface of the dielectric layer facing away from the substrate.

[0016] The FLASH device and its formation method provided by this invention, in the planarization process before forming the erase layer, first forms a fill layer that fills the isolation trench and covers the dielectric layer, and then forms an auxiliary layer covering the fill layer on the substrate. By adjusting the material of the auxiliary layer, the auxiliary layer and the fill layer can be etched back at the same etching rate to remove all of the auxiliary layer and part of the fill layer, and to ensure that the surface of the remaining fill layer facing away from the substrate is flush with the surface of the dielectric layer facing away from the substrate. This improves the planarization effect before the erase layer deposition, reduces or even avoids the formation of sharp corners of the fill layer at the edge of the isolation trench, eliminates the influence of the sharp corners of the fill layer on the subsequent deposition of the erase layer, improves the thickness uniformity of the subsequently formed erase layer, and thus improves the erase performance of the FLASH device. Simultaneously, this invention achieves the same etching rate for the auxiliary layer and the fill layer by adjusting the material of the auxiliary layer. Compared with directly adjusting the etching parameters, this reduces the adjustment difficulty and time cost, simplifies the FLASH device manufacturing process, and also helps to improve the manufacturing efficiency of the FLASH device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of the method for forming a FLASH device in a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the structure after the filling layer is formed according to a specific embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after the auxiliary layer is formed in a specific embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after the auxiliary layer is thinned according to a specific embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after all the auxiliary layers and part of the filler layers have been etched away in a specific embodiment of the present invention. Figure 6 This is a schematic diagram of the structure after the deposition and removal of the material layer in a specific embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after the erasure layer is formed in a specific embodiment of the present invention.

[0019] Explanation of reference numerals in the attached figures 20 floating gate 21 Dielectric Layer 22 Select Gate 23 First Barrier Layer 24 Second Barrier Layer 25 Third Barrier Layer 26 fill layers 27 Depression 28 isolation sidewalls 30 auxiliary layers 60 wipe material layer 61 photoresist layer 70 erase layers Detailed Implementation The specific embodiments of the FLASH device and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0020] This specific embodiment provides a method for forming a FLASH device. Figure 1 This is a flowchart illustrating the method for forming a FLASH device in a specific embodiment of the present invention. For example... Figure 1 As shown, the method for forming the FLASH device includes the following steps: Step S11, forming a substrate, the substrate including a substrate, a plurality of unit structures located above the substrate and isolation trenches located between adjacent unit structures, the unit structure including a floating gate and a dielectric layer covering the floating gate; Step S12: Form a filling layer that fills the isolation trench and covers the dielectric layer; Step S13: An auxiliary layer is formed to cover the filling layer, wherein the etching selectivity ratio of the auxiliary layer to the filling layer is 1:1; Step S14: Etch back the auxiliary layer and the fill layer at the same etching rate to remove the auxiliary layer and part of the fill layer, and the remaining fill layer surface away from the substrate is flush with the dielectric layer surface away from the substrate.

[0021] Figure 2 This is a schematic diagram of the structure after the filling layer is formed according to a specific embodiment of the present invention. In some embodiments, the specific steps for forming the substrate include: Provide substrate; A floating gate material layer is formed above the substrate; A dielectric material layer is formed covering the surface of the floating gate material layer opposite to the substrate; The dielectric material layer and the floating gate material layer are etched to form an isolation trench that penetrates the dielectric material layer and the floating gate material layer. The isolation trench divides the floating gate material layer into a plurality of floating gates 20 and the dielectric material layer into a plurality of dielectric layers 21.

[0022] For example, the substrate includes a front side and a back side distributed opposite to each other. After depositing the floating gate material layer and the dielectric material layer on the front side of the substrate, the floating gate material layer and the dielectric material layer are patterned to form an isolation trench penetrating the dielectric material layer and the floating gate material layer. The isolation trench divides the floating gate material layer into multiple floating gates 20 and the dielectric material layer into multiple dielectric layers 21, thereby forming multiple independent unit structures. In one example, the unit structure also includes a select gate 22, an isolation sidewall 28 located between the select gate 22 and the floating gate 20, and a barrier layer covering the top surface of the select gate 22 (i.e., the surface of the select gate 22 facing away from the substrate). The material of the select gate 22 and the floating gate 20 can be the same, for example, both include polysilicon. The isolation sidewall 28 is used to electrically isolate the select gate 22 and the floating gate 20. The isolation sidewall can be a single-layer structure or a multilayer structure stacked along a direction parallel to the front side of the substrate. For example, the isolation sidewall 28 includes a silicon dioxide layer, a silicon nitride layer, and a silicon dioxide layer stacked sequentially, that is, the isolation sidewall 28 has an ONO structure. In this specific embodiment, "multiple" refers to two or more.

[0023] The barrier layer covers the top surface of the select gate 22 (i.e., the surface of the select gate 22 facing away from the substrate) and the top surface of the isolation sidewall 28 (i.e., the surface of the isolation sidewall 28 facing away from the substrate), and is used to prevent charged particles in the select gate 22 from diffusing upward. In one example, the barrier layer is a single-layer structure. In another example, the barrier layer includes a multilayer structure stacked sequentially in a direction perpendicular to the front side of the substrate. For example, the barrier layer includes a first barrier layer 23 (e.g., a silicon dioxide layer) covering the top surface of the select gate 22, a second barrier layer 24 (e.g., a silicon nitride layer) covering the surface of the first barrier layer 23 facing away from the substrate, and a third barrier layer 25 (e.g., a silicon dioxide layer) covering the surface of the second barrier layer facing away from the substrate. In one example, the top surface of the barrier layer is flush with the top surface of the dielectric layer 21.

[0024] In some embodiments, the specific steps of forming a filling layer 26 that fills the isolation trench and covers the dielectric layer 21 include: Silicon nitride material is deposited on the substrate to form the filling layer 26, which fills the isolation trench and covers the surface of the dielectric layer 21 facing away from the substrate.

[0025] For example, after forming the isolation trench, silicon nitride material can be deposited on the substrate using a chemical vapor deposition process to form a filling layer 26 that fills the isolation trench and continuously covers the surface of the dielectric layer 21 and the surface of the barrier layer, such as... Figure 2 As shown. Using the silicon nitride material to form the filler layer 26 ensures its chemical stability and insulation properties, reduces voids, and improves the filling quality of the isolation trench. Due to the presence of the isolation trench, the top of the formed filler layer 26 has a recess 27 corresponding to the position of the isolation trench, resulting in an uneven top surface of the filler layer 26 (i.e., the surface of the filler layer 26 facing away from the substrate).

[0026] Figure 3 This is a schematic diagram of the structure after the auxiliary layer is formed according to a specific embodiment of the present invention. In some embodiments, the specific steps of forming the auxiliary layer 30 covering the filling layer 26 include: A silica material is deposited on the substrate using a chemical vapor deposition process to form the auxiliary layer 30 covering the filler layer 26, such as... Figure 3 As shown.

[0027] In some embodiments, the thickness of the auxiliary layer 30 is greater than the thickness of the filler layer 26 above the dielectric layer 21.

[0028] For example, a silica material is deposited on the substrate using chemical vapor deposition to form a dense silica layer, which serves as the auxiliary layer 30. Simultaneously, by adjusting deposition parameters such as deposition time and deposition gas flow rate, the thickness of the auxiliary layer 30 is made greater than the thickness of the filler layer 26 above the dielectric layer 21 (e.g., the thickness of the filler layer 26 above the barrier layer). This thicker auxiliary layer 30 reduces the depressions 27 formed during the formation of the filler layer 26, providing a smoother surface for subsequent planarization processes. Furthermore, due to the chemical differences between silica and silicon nitride, the grinding endpoint can be controlled during subsequent polishing.

[0029] Figure 4 This is a schematic diagram of the structure after the auxiliary layer has been thinned according to a specific embodiment of the present invention. In some embodiments, before re-etching the auxiliary layer 30 and the fill layer 26 at the same etching rate, the following steps are also included: The thickness of the auxiliary layer 30 is reduced by a chemical mechanical polishing process, such as... Figure 4 As shown.

[0030] For example, using the filler layer 26 as the polishing stop layer, a portion of the auxiliary layer 30 is removed using a chemical mechanical polishing (CMP) process. For instance, only the auxiliary layer 30 within the recess 27 is retained, so that the top surface of the remaining auxiliary layer 30 (i.e., the surface of the auxiliary layer 30 facing away from the substrate) is flush with the top surface of the filler layer 26. This exposes the top surface of the auxiliary layer 30 after CMP. By removing a portion of the auxiliary layer 30 using CMP before chemical etching, the subsequent chemical etching time can be shortened, improving planarization efficiency. Furthermore, it can quickly remove larger protrusions on the top of the filler layer 26, achieving initial planarization of the filler layer 26, for example, making the top surface of the filler layer 26 flush with the top surface of the dielectric layer 21, laying the foundation for subsequent planarization through chemical etching.

[0031] Figure 5 This is a schematic diagram of the structure after back etching away all the auxiliary layer and part of the fill layer according to a specific embodiment of the present invention. In some embodiments, the specific steps of back etching the auxiliary layer 30 and the fill layer 26 at the same etching rate include: The auxiliary layer 30 and the filler layer 26 are etched back using a dry etching process, and the etching parameters of the dry etching process are adjusted so that the etching selectivity ratio of the auxiliary layer 30 to the filler layer 26 is 1:1.

[0032] In some embodiments, the specific steps of adjusting the etching parameters of the dry etching process so that the etching selectivity ratio of the auxiliary layer 30 to the fill layer 26 is 1:1 include: A mixed gas comprising fluorocarbon-based gas and oxygen is used as the etching gas, and the ratio of the fluorocarbon-based gas and oxygen is adjusted so that the etching selectivity ratio of the auxiliary layer 30 to the filler layer 26 is 1:1.

[0033] For example, a dry etching process can be used to etch back the auxiliary layer 30 and the filler layer 26. By adjusting the etching parameters of the dry etching process, the etching selectivity ratio of the auxiliary layer 30 to the filler layer 26 can be made 1:1. During the adjustment of the etching parameters, a gas capable of chemically reacting with both the auxiliary layer 30 and the filler layer 26 can be used as the etching gas. The etching selectivity ratio of the etching gas for the auxiliary layer 30 and the filler layer 26 can be adjusted to 1:1 by adjusting the proportions of the various components in the etching gas. For example, if the etching gas is a mixed gas, the etching selectivity ratio of the etching gas for the auxiliary layer 30 and the filler layer 26 can be adjusted to 1:1 by adjusting the volume fractions of the various gases in the etching gas. This specific embodiment adjusts the etching parameters of the dry etching process to achieve an etching selectivity ratio of 1:1 between the auxiliary layer 30 and the fill layer 26. This ensures that the removal rates of the auxiliary layer 30 and the fill layer 26 are the same. This not only makes the remaining fill layer 26, the dielectric layer 21, and the barrier layer flush with the surfaces away from the substrate, but also eliminates the micro-defects generated during the chemical mechanical polishing process. This ensures that the top surface of the remaining fill layer 26 in the final isolation trench is flat and significantly reduces the probability of sharp corner defects at the edge of the isolation trench, thus avoiding the impact of sharp corners on subsequent processes.

[0034] The following explanation uses silicon nitride as the material of the filler layer 26 and silicon dioxide as the material of the auxiliary layer 30 as an example. By using a mixed gas comprising fluorocarbon-based gas and oxygen as the etching gas, the fluorocarbon-based gas (e.g., CF4) can chemically react with both silicon nitride and silicon dioxide, thereby achieving simultaneous removal of the filler layer 26 and the auxiliary layer 30. Simultaneously, oxygen can adjust the etching selectivity of the etching gas; for example, oxygen can alter the chemical properties of the material surface, thus affecting the etching rate of the fluorocarbon-based gas (e.g., CF4) on different materials. Therefore, by adjusting the relative volume of the fluorocarbon-based gas and oxygen in the etching gas (i.e., adjusting the relative proportion of the fluorocarbon-based gas and oxygen in the mixed gas), the etching selectivity of the etching gas for the filler layer 26 and the auxiliary layer 30 can be adjusted to 1:1. In one example, the etching gas also includes argon, which can increase the plasma density during dry etching, improving the stability and uniformity of the etching process.

[0035] In some embodiments, during the dry etching process of the auxiliary layer 30 and the filler layer 26, the flow rate of the fluorocarbon gas (e.g., CF4) is 70 sccm to 90 sccm, and the flow rate of oxygen is 10 sccm to 30 sccm. In one example, the flow rate of CF4 is 80 sccm, and the flow rate of oxygen is 20 sccm.

[0036] Figure 6 This is a schematic diagram of the structure after the deposition and erasure of the material layer in a specific embodiment of the present invention. Figure 7 This is a schematic diagram of the structure after the erasure layer is formed according to a specific embodiment of the present invention. In some embodiments, after re-etching the auxiliary layer 30 and the fill layer 26 at the same etching rate to remove the auxiliary layer 30 and part of the fill layer 26, and after the surface of the remaining fill layer 26 is flush with the surface of the dielectric layer 21, the following steps are further included: An erase layer 70 is formed on the surface of the dielectric layer 21 opposite to the floating gate 20, such as Figure 7 As shown.

[0037] For example, polysilicon material is deposited over the substrate to form an eraser material layer 60 that continuously covers the barrier layer, the dielectric layer 21, and the remaining filler layer 26. A patterned photoresist layer 61 is formed on the eraser material layer 60, the photoresist layer 61 having etched windows that expose the eraser material layer 60, such as... Figure 6 As shown. A portion of the erasure material layer 60 is etched away along the etching window, and the remaining erasure material layer 60 is used as the erasure layer 70, as... Figure 7 As shown. The erase layer 70 is located above the floating gate 20, and the erase layer 70 is isolated from the floating gate 20 through the dielectric layer 21.

[0038] This specific embodiment also provides a FLASH device, formed using the FLASH device formation method described above. See [link to documentation]. Figures 1-7 The structure of the FLASH device is shown in [reference needed]. Figure 7 .like Figure 7 As shown, the FLASH device includes: The substrate includes a front side and a back side that are relatively distributed. Multiple unit structures are arranged at intervals above the front side of the substrate in a direction parallel to the front side of the substrate. Each unit structure includes a floating gate 20 and a dielectric layer 21 covering the floating gate 20. A filler layer 26 is filled between adjacent unit structures, and the surface of the filler layer 26 facing away from the substrate is flush with the surface of the dielectric layer 21 facing away from the substrate.

[0039] The FLASH device and its formation method provided in this specific embodiment, in the planarization process before forming the erase layer, first forms a fill layer that fills the isolation trench and covers the dielectric layer, and then forms an auxiliary layer covering the fill layer on the substrate. By adjusting the material of the auxiliary layer, the auxiliary layer and the fill layer can be etched back at the same etching rate to remove all of the auxiliary layer and part of the fill layer, and to ensure that the surface of the remaining fill layer facing away from the substrate is flush with the surface of the dielectric layer facing away from the substrate. This improves the planarization effect before the erase layer deposition, reduces or even avoids the formation of fill layer sharp corners at the edges of the isolation trench, eliminates the influence of fill layer sharp corners on the subsequent deposition of the erase layer, improves the thickness uniformity of the subsequently formed erase layer, and thus improves the erase performance of the FLASH device. At the same time, this specific embodiment achieves the same etching rate for the auxiliary layer and the fill layer by adjusting the material of the auxiliary layer. Compared with directly adjusting the etching parameters, this reduces the adjustment difficulty and time cost, simplifies the FLASH device manufacturing process, and also helps to improve the manufacturing efficiency of the FLASH device.

[0040] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this invention can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0041] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a FLASH device, characterized in that, Includes the following steps: A substrate is formed, the substrate including a substrate, a plurality of cell structures located above the substrate and isolation trenches located between adjacent cell structures, the cell structure including a floating gate and a dielectric layer covering the floating gate; A filling layer is formed that fills the isolation trench and covers the dielectric layer; An auxiliary layer is formed to cover the filler layer, wherein the etching selectivity ratio of the auxiliary layer to the filler layer is 1:1; The auxiliary layer and the filler layer are etched back at the same etching rate to remove the auxiliary layer and a portion of the filler layer, and the remaining surface of the filler layer facing away from the substrate is flush with the surface of the dielectric layer facing away from the substrate.

2. The method for forming a FLASH device according to claim 1, characterized in that, The specific steps for forming the substrate include: Provide substrate; A floating gate material layer is formed above the substrate; A dielectric material layer is formed covering the surface of the floating gate material layer opposite to the substrate; The dielectric material layer and the floating gate material layer are etched to form an isolation trench that penetrates the dielectric material layer and the floating gate material layer. The isolation trench divides the floating gate material layer into a plurality of floating gates and the dielectric material layer into a plurality of dielectric layers.

3. The method for forming a FLASH device according to claim 1, characterized in that, The specific steps for forming a filling layer that fills the isolation trench and covers the dielectric layer include: Silicon nitride material is deposited on the substrate to form a filling layer that fills the isolation trench and covers the surface of the dielectric layer opposite to the substrate.

4. The method for forming a FLASH device according to claim 3, characterized in that, The specific steps for forming the auxiliary layer covering the filling layer include: A silica material is deposited on the substrate using a chemical vapor deposition process to form the auxiliary layer covering the filler layer.

5. The method for forming a FLASH device according to claim 4, characterized in that, The thickness of the auxiliary layer is greater than the thickness of the filler layer above the dielectric layer.

6. The method for forming a FLASH device according to claim 5, characterized in that, Before re-etching the auxiliary layer and the fill layer at the same etching rate, the following steps are also included: The thickness of the auxiliary layer is reduced by chemical mechanical polishing.

7. The method for forming a FLASH device according to claim 4, characterized in that, The specific steps for re-etching the auxiliary layer and the filler layer at the same etching rate include: The auxiliary layer and the filler layer are etched back using a dry etching process, and the etching parameters of the dry etching process are adjusted so that the etching selection ratio of the auxiliary layer to the filler layer is 1:

1.

8. The method for forming a FLASH device according to claim 7, characterized in that, The specific steps for adjusting the etching parameters of the dry etching process to achieve an etching selectivity ratio of 1:1 between the auxiliary layer and the filler layer include: A mixed gas comprising fluorocarbon-based gas and oxygen is used as the etching gas, and the ratio of the fluorocarbon-based gas and oxygen is adjusted so that the etching selectivity ratio of the auxiliary layer to the filler layer is 1:

1.

9. The method for forming a FLASH device according to claim 1, characterized in that, After etching back the auxiliary layer and the filler layer at the same etching rate to remove the auxiliary layer and a portion of the filler layer, and ensuring that the surface of the remaining filler layer is flush with the surface of the dielectric layer, the process further includes the following steps: An erase layer is formed on the surface of the dielectric layer opposite to the floating gate.

10. A FLASH device, characterized in that, The FLASH device is formed using the method for forming a FLASH device as described in claim 1; the FLASH device comprises: The substrate includes a front side and a back side that are relatively distributed. Multiple unit structures are arranged at intervals above the front side of the substrate in a direction parallel to the front side of the substrate. Each unit structure includes a floating gate and a dielectric layer covering the floating gate. A filler layer is filled between adjacent unit structures, and the surface of the filler layer facing away from the substrate is flush with the surface of the dielectric layer facing away from the substrate.

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