Wafer hybrid bonding structure and method

Abstract

A wafer hybrid bonding structure and method includes: a first wafer having a first functional surface, a first dielectric structure located on the first functional surface, and a first conductive structure located within the first dielectric structure. The first dielectric structure includes a first dielectric layer, and the first conductive structure includes a first conductive layer and a first metal barrier layer located on the surface of the first conductive layer. A second wafer bonded to the first wafer has a second functional surface. A second dielectric structure located on the second functional surface and a second conductive structure located within the second dielectric structure, the second conductive structure including a second conductive layer, wherein the first conductive structure and the second conductive structure are bonded to each other, and the first dielectric structure and the second dielectric structure are bonded to each other, which can reduce the diffusion of metal from the first conductive layer to the second dielectric structure, thereby improving the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer hybrid bonding structure and method. Background Technology

[0002] With the development of very large-scale integrated circuits (VLSI) approaching its physical limits, three-dimensional integrated circuits (3D integrated circuits), which offer advantages in both physical size and cost, are an effective way to extend Moore's Law and solve advanced packaging problems. Wafer bonding technology is one of the key technologies for 3D circuit integration, especially hybrid bonding technology, which can achieve internal interconnection of thousands of chips while bonding two wafers, greatly improving chip performance and saving costs.

[0003] Copper hybrid bonding technology is driving the next generation of 2.5D and 3D packaging technologies. Compared to existing stacking and bonding methods, hybrid bonding can provide higher bandwidth and lower power consumption.

[0004] However, existing hybrid bonding techniques need further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a wafer hybrid bonding structure and method to improve the performance of the formed hybrid bonding structure.

[0006] To address the aforementioned technical problems, the present invention provides a wafer hybrid bonding structure, comprising: a first wafer having a first functional surface, a first dielectric structure located on the first functional surface, and a first conductive structure located within the first dielectric structure. The first dielectric structure includes a first dielectric layer, and the first conductive structure includes a first conductive layer and a first metal barrier layer located on the surface of the first conductive layer, wherein the first dielectric structure exposes the first metal barrier layer; a second wafer bonded to the first wafer, the second wafer having a second functional surface; a second dielectric structure located on the second functional surface and a second conductive structure located within the second dielectric structure, the second conductive structure including a second conductive layer, the second dielectric structure exposing the second conductive structure, the first conductive structure and the second conductive structure being bonded to each other, and the first dielectric structure and the second dielectric structure being bonded to each other.

[0007] Optionally, the second conductive structure further includes a second metal barrier layer located on the surface of the second conductive layer, and the first metal barrier layer and the second metal barrier layer are bonded to each other; the material of the second metal barrier layer is a material that makes it difficult for the metal in the second conductive layer to diffuse into the first dielectric structure; the metal in the second conductive layer has a third diffusion capability within the second metal barrier layer, and the metal in the second conductive layer has a fourth diffusion capability within the first dielectric structure, wherein the third diffusion capability is less than the fourth diffusion capability.

[0008] Optionally, the first conductive structure further includes a third metal barrier layer located between the first conductive layer and the first dielectric structure; the second conductive structure further includes a fourth metal barrier layer located between the second conductive layer and the second dielectric structure.

[0009] Optionally, the first metal barrier layer and the third metal barrier layer completely surround the first conductive layer; the second metal barrier layer and the fourth metal barrier layer completely surround the second conductive layer.

[0010] Optionally, the material of the first metal barrier layer includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride; the material of the second metal barrier layer includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride.

[0011] Optionally, the thickness of the first metal barrier layer is less than or equal to 2000 nm; the thickness of the second metal barrier layer is less than or equal to 2000 nm.

[0012] Optionally, the first dielectric structure further includes a dielectric barrier layer located on the surface of the first dielectric layer, wherein the diffusion capacity of the metal in the second conductive layer within the dielectric barrier layer is less than the diffusion capacity of the metal in the second conductive layer within the first dielectric layer; the first metal barrier layer is located within the dielectric barrier layer, and the dielectric barrier layer and the second dielectric structure are bonded to each other.

[0013] Optionally, the material of the first metal barrier layer is a material that makes it difficult for the metal in the first conductive layer to diffuse into the second dielectric structure; the metal in the first conductive layer has a first diffusion capability in the first metal barrier layer, and the metal in the first conductive layer has a second diffusion capability in the second dielectric structure, wherein the first diffusion capability is less than the second diffusion capability.

[0014] Accordingly, the present invention also provides a wafer hybrid bonding method, comprising: providing a first wafer and a second wafer, the first wafer having a first functional surface and the second wafer having a second functional surface; forming a first dielectric structure and a first conductive structure located within the first dielectric structure on the first functional surface, the first dielectric structure including a first dielectric layer, the first conductive structure including a first conductive layer and a first metal barrier layer located on the surface of the first conductive layer, the first dielectric structure exposing the first metal barrier layer; forming a second dielectric structure and a second conductive structure located within the second dielectric structure on the second functional surface, the second conductive structure including a second conductive layer, the second dielectric structure exposing the second conductive structure; and bonding the first wafer and the second wafer with the first conductive structure facing the second conductive structure and the first dielectric structure facing the second dielectric structure.

[0015] Optionally, the method for forming the first dielectric structure and the first conductive structure includes: forming the first dielectric structure on the first functional surface; forming a first opening in the first dielectric structure, the first opening exposing the first functional surface; forming the first conductive layer in the first opening; and forming the first metal barrier layer on the surface of the first conductive layer and in the first opening.

[0016] Optionally, the method for forming the first conductive layer includes: forming a first conductive material layer inside the first opening and on the surface of the first dielectric structure; planarizing the first conductive material layer until the surface of the first dielectric structure is exposed; and after planarizing the first conductive material layer, over-grinding or etching the first conductive material layer so that the top surface of the first conductive material layer is lower than the top surface of the first dielectric structure, thereby forming the first conductive layer.

[0017] Optionally, the first conductive structure further includes a third metal barrier layer, the third metal barrier layer being located between the first conductive layer and the first dielectric structure; the first metal barrier layer and the third metal barrier layer completely surround the first conductive layer; the method of forming the first conductive structure further includes: before forming the first conductive material layer, forming a third metal barrier material layer in the first opening and on the surface of the first dielectric structure, the first conductive material layer being formed on the surface of the third metal barrier material layer; and forming the third metal barrier layer with the third metal barrier material layer.

[0018] Optionally, the method for forming the first metal barrier layer includes: forming a first metal barrier material layer on the surface of the first conductive layer and the surface of the first dielectric structure; planarizing the first metal barrier material layer until the surface of the first dielectric structure is exposed to form the first metal barrier layer.

[0019] Optionally, the method for forming the second dielectric structure and the second conductive structure includes: forming the second dielectric structure on the second functional surface; forming a second opening in the second dielectric structure, the second opening exposing the second functional surface; and forming the second conductive layer in the second opening.

[0020] Optionally, the second conductive structure further includes a second metal barrier layer located on the surface of the second conductive layer, and the second dielectric structure exposes the second metal barrier layer; the method of forming the second conductive structure further includes: forming the second metal barrier layer on the surface of the second conductive layer and within the second opening.

[0021] Optionally, the method for forming the second conductive layer includes: forming a second conductive material layer inside the second opening and on the surface of the second dielectric structure; planarizing the second conductive material layer until the surface of the second dielectric structure is exposed; and after planarizing the second conductive material layer, over-grinding or etching the second conductive material layer so that the top surface of the second conductive material layer is lower than the top surface of the second dielectric structure, thereby forming the second conductive layer.

[0022] Optionally, the second conductive structure further includes a fourth metal barrier layer, the fourth metal barrier layer being located between the second conductive layer and the second dielectric structure; the second metal barrier layer and the fourth metal barrier layer completely surround the second conductive layer; the method of forming the second conductive structure further includes: forming a fourth metal barrier material layer in the second opening and on the surface of the second dielectric structure before forming the second conductive material layer; and forming the fourth metal barrier layer with the fourth metal barrier material layer.

[0023] Optionally, the method for forming the second metal barrier layer includes: forming a second metal barrier material layer on the surface of the second conductive layer and the surface of the second dielectric structure; planarizing the second metal barrier material layer until the surface of the second dielectric structure is exposed, thereby forming the second metal barrier layer.

[0024] Optionally, the first dielectric structure further includes a dielectric barrier layer located on the surface of the first dielectric layer, wherein the diffusion capability of the metal in the second conductive layer within the dielectric barrier layer is less than the diffusion capability of the metal in the second conductive layer within the first dielectric layer; the first metal barrier layer is formed within the dielectric barrier layer; the method for bonding the first wafer and the second wafer further includes: bonding the dielectric barrier layer and the second dielectric structure to each other.

[0025] Optionally, the thickness of the first metal barrier layer is less than or equal to 2000 nm; the thickness of the second metal barrier layer is less than or equal to 2000 nm.

[0026] Optionally, the bonding process parameters include: a bonding temperature range of 100 degrees Celsius to 500 degrees Celsius and a heat treatment time range of 10 minutes to 600 minutes.

[0027] Optionally, the surface of the first conductive structure has a first recess, which extends from the surface of the first conductive structure toward the first functional surface; the depth of the first recess ranges from 0 nm to 20 nm; the surface of the second conductive structure has a second recess, which extends from the surface of the first conductive structure toward the second functional surface; the depth of the second recess ranges from 0 nm to 20 nm.

[0028] Optionally, the surface of the first conductive structure is lower than or flush with the surface of the first dielectric structure; the surface of the second conductive structure is lower than or flush with the surface of the second dielectric structure.

[0029] Optionally, the material of the first metal barrier layer includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride; the material of the second metal barrier layer includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride.

[0030] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0031] In the wafer hybrid bonding structure provided by the present invention, the first conductive structure includes a first conductive layer and a first metal barrier layer located on the surface of the first conductive layer. The first dielectric structure exposes the first metal barrier layer. Since the surface of the first conductive layer is covered by the first metal barrier layer, even when the alignment error is large, the first metal barrier layer can reduce the diffusion of metal in the first conductive layer to the second dielectric structure, which is beneficial to improving the reliability of the device.

[0032] Furthermore, the second conductive structure also includes a second metal barrier layer located on the surface of the second conductive layer. The second dielectric structure exposes the second metal barrier layer. The second metal barrier layer can reduce the diffusion of metal from the second conductive layer to the first dielectric structure, which is beneficial to improving the reliability of the device.

[0033] Furthermore, the first conductive structure also includes a third metal barrier layer, which is located between the first conductive layer and the first dielectric structure; the first metal barrier layer and the third metal barrier layer completely surround the first conductive layer, which helps to reduce the diffusion of metal in the first conductive layer to the surrounding dielectric material.

[0034] Furthermore, the second conductive structure also includes a fourth metal barrier layer, which is located between the second conductive layer and the second dielectric structure; the second metal barrier layer and the fourth metal barrier layer completely surround the second conductive layer, which helps to reduce the diffusion of metal in the second conductive layer to the surrounding dielectric material.

[0035] Furthermore, the first dielectric structure also includes a dielectric barrier layer located on the surface of the first dielectric layer. The diffusion capacity of the metal in the second conductive layer within the dielectric barrier layer is less than that of the metal in the second conductive layer within the first dielectric layer. The presence of the dielectric barrier layer helps to further reduce the diffusion of the metal in the second conductive layer into the first dielectric structure, thereby improving the reliability of the device.

[0036] Furthermore, the thickness of the first metal barrier layer is less than or equal to 2000 nm. The purpose of selecting this thickness range is that the first metal barrier layer of this thickness has little impact on the contact resistance between the bonded first conductive layer and the second conductive layer, and can also play a role in blocking metal diffusion.

[0037] Furthermore, the thickness of the second metal barrier layer is less than or equal to 2000 nm. The purpose of selecting this thickness range is that the second metal barrier layer of this thickness has a minimal impact on the contact resistance between the bonded first and second conductive layers, and can effectively block metal diffusion.

[0038] In the wafer hybrid bonding method provided by the present invention, the first conductive structure is oriented toward the second conductive structure, and the first dielectric structure is oriented toward the second dielectric structure, and the first wafer and the second wafer are bonded together. Since the surface of the first conductive layer is covered by the first metal barrier layer, the metal inside the first conductive layer is less likely to diffuse into the second dielectric structure. Even when the alignment error is large, the first metal barrier layer can reduce the diffusion of the metal inside the first conductive layer into the second dielectric structure, which is beneficial to improving the reliability of the device.

[0039] Furthermore, the second conductive structure also includes a second metal barrier layer located on the surface of the second conductive layer. The second dielectric structure exposes the second metal barrier layer. The second metal barrier layer can reduce the diffusion of metal from the second conductive layer to the first dielectric structure, which is beneficial to improving the reliability of the device.

[0040] Furthermore, the first conductive structure also includes a third metal barrier layer, which is located between the first conductive layer and the first dielectric structure; the first metal barrier layer and the third metal barrier layer completely surround the first conductive layer, which helps to reduce the diffusion of metal in the first conductive layer to the surrounding dielectric material.

[0041] Furthermore, the second conductive structure also includes a fourth metal barrier layer, which is located between the second conductive layer and the second dielectric structure; the second metal barrier layer and the fourth metal barrier layer completely surround the second conductive layer, which helps to reduce the diffusion of metal in the second conductive layer to the surrounding dielectric material.

[0042] Furthermore, the first dielectric structure also includes a dielectric barrier layer located on the surface of the first dielectric layer. The diffusion capacity of the metal in the second conductive layer within the dielectric barrier layer is less than that of the metal in the second conductive layer within the first dielectric layer. The presence of the dielectric barrier layer helps to further reduce the diffusion of the metal in the second conductive layer into the first dielectric structure, thereby improving the reliability of the device.

[0043] Furthermore, the thickness of the first metal barrier layer is less than or equal to 2000 nm. The purpose of selecting this thickness range is that the first metal barrier layer of this thickness has little impact on the contact resistance between the bonded first conductive layer and the second conductive layer, and can also play a role in blocking metal diffusion.

[0044] Furthermore, the thickness of the second metal barrier layer is less than or equal to 2000 nm. The purpose of selecting this thickness range is that the second metal barrier layer of this thickness has a minimal impact on the contact resistance between the bonded first and second conductive layers, and can effectively block metal diffusion. Attached Figure Description

[0045] Figure 1 and Figure 2 This is a schematic diagram of a wafer hybrid bonding structure;

[0046] Figures 3 to 12 This is a schematic diagram of the structure of each step of a hybrid bonding method according to an embodiment of the present invention. Detailed Implementation

[0047] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0048] As described in the background section, the performance of hybrid bonding structures formed using existing hybrid bonding technologies urgently needs improvement. This paper will now illustrate and analyze a wafer hybrid bonding structure.

[0049] Figure 1 and Figure 2 This is a schematic diagram of a wafer hybrid bonding structure.

[0050] Please refer to Figure 1 The wafer hybrid bonding structure includes: a first wafer (not shown); a first dielectric layer located on the surface of the first wafer, the first dielectric layer including a first silicon oxide layer 101, a first silicon nitride layer 102 located on the surface of the first silicon oxide layer 101, and a second silicon oxide layer 103 located on the first silicon nitride layer 102; a first conductive layer 104 located within the first dielectric layer, and the surface of the first dielectric layer exposes the surface of the first conductive layer 104; a second wafer (not shown); a second dielectric layer located on the surface of the second wafer, the second dielectric layer including a third silicon oxide layer 103; and a second dielectric layer located on the surface of the second wafer. The third silicon oxide layer 105, a second silicon nitride layer 106 located on the surface of the third silicon oxide layer 105, a fourth silicon oxide layer 107 located on the second silicon nitride layer 106, and a third silicon nitride layer 108 located on the fourth silicon oxide layer 107; a second conductive layer 109 located within the second dielectric layer, with the surface of the second conductive layer 109 exposed on the surface of the second dielectric layer; a first wafer and a second wafer bonded together, wherein the second silicon oxide layer 103 is bonded to the third silicon nitride layer 108, and the first conductive layer 104 is bonded to the second conductive layer 109.

[0051] In the aforementioned wafer hybrid bonding structure, the bonding interface of the first wafer (i.e., the second silicon oxide layer 103) is made of silicon oxide, the bonding interface of the second wafer (i.e., the third silicon nitride layer 108) is made of silicon nitride, and both the first conductive layer 104 and the second conductive layer 109 are made of copper. During the wafer bonding process, there will be a certain overlay error. Because the silicon nitride at the bonding interface of the second wafer has a good barrier effect on copper, it can prevent the copper in the first conductive layer 104 from diffusing to the second wafer side.

[0052] However, when the alignment error is large, please refer to... Figure 2 There is a situation where the copper of the second conductive layer 109 directly contacts the silicon oxide at the interface of the second silicon oxide layer 103. In this case, since the silicon oxide has a weak barrier to copper, copper diffusion will seriously affect the reliability of the device.

[0053] To improve the aforementioned copper diffusion problem, in one embodiment, the bonding interface material of the first wafer is changed from silicon oxide to silicon nitride, that is, the bonding interface between the first wafer and the second wafer is SiN-SiN bonded. However, compared with the bonding force between silicon oxide and silicon nitride, the bonding force between silicon nitride is poor, and peeling is prone to occur after the bonding process.

[0054] To address the aforementioned issues, this invention provides a wafer hybrid bonding structure and method in which the first conductive structure faces the second conductive structure and the first dielectric structure faces the second dielectric structure, and the first wafer and the second wafer are bonded together. Since the surface of the first conductive layer is covered by the first metal barrier layer, the metal within the first conductive layer is less likely to diffuse into the second dielectric structure. Even when the alignment error is large, the first metal barrier layer can reduce the diffusion of the metal within the first conductive layer into the second dielectric structure, thereby improving the reliability of the device.

[0055] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0056] Figures 3 to 12 This is a schematic diagram of the structure of each step of a hybrid bonding method according to an embodiment of the present invention.

[0057] Please refer to Figure 3 A first wafer 200 and a second wafer 300 are provided, wherein the first wafer 200 has a first functional surface 200a and the second wafer 300 has a second functional surface 300a.

[0058] In this embodiment, the first wafer 200 includes a first device layer (not shown in the figure) and a first interconnect layer (not shown in the figure) located on the first device layer. The first interconnect layer includes a first metal layer 201, and the first functional surface 200a exposes the first metal layer 201.

[0059] In this embodiment, the second wafer 300 includes a second device layer (not shown in the figure) and a second interconnect layer (not shown in the figure) located on the second device layer. The second interconnect layer includes a second metal layer 301, and the second functional surface 300a exposes the second metal layer 301.

[0060] In this embodiment, the first device layer has a plurality of first device structures, including transistors, diodes, triodes, capacitors or inductors, etc.; the second device layer has a plurality of second device structures, including transistors, diodes, triodes, capacitors or inductors, etc.

[0061] Subsequently, a first dielectric structure and a first conductive structure located within the first dielectric structure are formed on the first functional surface 200a, the first dielectric structure including a first dielectric layer, the first conductive structure including a first conductive layer and a first metal barrier layer located on the surface of the first conductive layer, the first dielectric structure exposing the first metal barrier layer; a second dielectric structure and a second conductive structure located within the second dielectric structure are formed on the second functional surface 200b, the second conductive structure including a second conductive layer, the second dielectric structure exposing the second conductive structure.

[0062] Next, we will introduce the methods for forming the first dielectric structure and the first conductive structure. Please refer to [link / reference]. Figures 4 to 8 .

[0063] Please refer to Figure 4 The first medium structure 202 is formed on the first functional surface 200a; a first opening 203 is formed in the first medium structure 202, and the first opening 203 exposes the first functional surface 200a.

[0064] Specifically, the first opening 203 exposes the first metal layer 201.

[0065] The material of the first dielectric structure 202 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0066] In this embodiment, the first dielectric structure 202 includes a first dielectric layer and a dielectric barrier layer 2020, wherein the dielectric barrier layer 2020 is located on the surface of the first dielectric layer. Subsequently, a first metal barrier layer is formed within the dielectric barrier layer 2020, such that the dielectric barrier layer 2020 is bonded to the second dielectric structure, i.e., the surface of the dielectric barrier layer 2020 serves as the bonding surface.

[0067] In another embodiment, the first dielectric structure may include only the first dielectric layer, without the dielectric barrier layer.

[0068] In this embodiment, the material of the dielectric barrier layer 2020 includes silicon nitride.

[0069] In other embodiments, the dielectric barrier layer 2020 may also be other dielectric materials. The key to selecting the material for the dielectric barrier layer 2020 is to ensure that the diffusion ability of the metal within the second conductive layer within the dielectric barrier layer 2020 is less than the diffusion ability of the metal within the second conductive layer within the first dielectric layer.

[0070] In this embodiment, the first dielectric layer has four dielectric material layers.

[0071] Specifically, the first dielectric layer includes: a first etch stop layer 202i, a first dielectric material layer 2021 located on the surface of the first etch stop layer 202i, a second etch stop layer 202ii located on the surface of the first dielectric material layer 2021, and a second dielectric material layer 2022 located on the surface of the second etch stop layer 202ii; the dielectric barrier layer 2020 is formed on the surface of the second dielectric material layer 2022.

[0072] In other embodiments, the first dielectric layer may also be a single-layer dielectric material layer or a multi-layer dielectric material layer.

[0073] The first etch stop layer 202i and the first dielectric material layer 2021 are made of different materials; the second etch stop layer 202ii and the second dielectric material layer 2022 are made of different materials.

[0074] In this embodiment, the first etch stop layer 202i and the second etch stop layer 202ii are both silicon nitride; the first dielectric material layer 2021 and the second dielectric material layer 2022 are both made of silicon oxide.

[0075] In this embodiment, the formation process of the first conductive structure includes a double damask process.

[0076] Specifically, the first opening 203 includes a first groove (not shown in the figure) and a first through hole located below the first groove. The first through hole exposes the surface of the first metal layer 201 and communicates with the first groove. The first through hole is located within the first etch stop layer 202i, the first dielectric material layer 2021 and the second etch stop layer 202ii. The first groove is located within the second dielectric material layer 2022 and the dielectric barrier layer 2020. The first through hole has a first projection on the first functional surface 200a, and the first groove has a second projection on the first functional surface 200a. The first projection is located within the range of the second projection.

[0077] Subsequently, the first conductive layer is formed within the first opening 203. For the method of forming the first conductive layer in this embodiment, please refer to [reference needed]. Figures 5 to 7 .

[0078] Please refer to Figure 5 The first opening 203 (e.g.) Figure 4 A first conductive material layer 204 is formed inside the first dielectric structure 202 and on its surface.

[0079] In this embodiment, before forming the first conductive material layer 204, a third metal barrier material layer 205 is formed in the first opening 203 and on the surface of the first dielectric structure 202, and the first conductive material layer 204 is formed on the surface 205 of the third metal barrier material layer.

[0080] The material of the third metal barrier layer 205 includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride.

[0081] In this embodiment, the third metal barrier material layer 205 is a tan / tan nitride bilayer material.

[0082] The formation process of the first conductive material layer 204 includes an electroplating process.

[0083] In this embodiment, the material of the first conductive material layer 204 is copper.

[0084] In other embodiments, the material of the first conductive material layer may also be other metals, such as aluminum, tungsten, gold, etc.

[0085] Please refer to Figure 6 The first conductive material layer 204 is planarized until the surface of the first dielectric structure 202 is exposed.

[0086] In this embodiment, the process of planarizing the first conductive material layer 204 includes a mechanical chemical polishing process.

[0087] In this embodiment, the third metal barrier material layer 205 is also planarized.

[0088] Please refer to Figure 7 After planarizing the first conductive material layer 204, the first conductive material layer 204 is over-polished or etched so that the top surface of the first conductive material layer 204 is lower than the top surface of the first dielectric structure 202, forming the first conductive layer 206.

[0089] In this embodiment, the first conductive structure further includes a third metal barrier layer 207, which is located between the first conductive layer 206 and the first dielectric structure 202.

[0090] In this embodiment, the method for forming the first conductive structure further includes: forming a third metal barrier layer 207 with the third metal barrier material layer 205.

[0091] The material of the third metal barrier layer 207 includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride. In this embodiment, the third metal barrier layer 207 is a tan / tan nitride bilayer material.

[0092] In this embodiment, during the process of excessively grinding or etching the first conductive material layer 204, the third metal barrier material layer 205 (such as...) is also... Figure 6 (As shown) This causes grinding or etching.

[0093] Preferably, after the first conductive material layer 204 is excessively ground or etched, the sidewalls of the first conductive layer 206 are still completely surrounded by the first metal barrier layer 208, so that the first metal barrier layer 208 and the third metal barrier layer 207 completely surround the first conductive layer 206, reducing the diffusion of metal in the first conductive layer 206 to the surrounding dielectric material.

[0094] In another embodiment, the process of excessively grinding or etching the first conductive material layer may not cause grinding or etching of the third metal barrier material layer.

[0095] In this embodiment, the method for forming the first conductive structure further includes: forming the third metal barrier layer 207 with the third metal barrier material layer 205.

[0096] The third metal barrier layer 207 is used to block the diffusion of the metal from the first conductive layer 206 into the first dielectric structure.

[0097] In this embodiment, the first conductive material layer 204 is overpolished so that the top surface of the first conductive material layer 204 is lower than the top surface of the first dielectric structure 202, forming the first conductive layer 206.

[0098] In another embodiment, the first conductive material layer is etched so that the top surface of the first conductive material layer is lower than the top surface of the first dielectric structure, thereby forming the first conductive layer. The etching process includes one or a combination of dry etching and wet etching processes.

[0099] Please refer to Figure 8 On the surface of the first conductive layer 206 and at the first opening 203 (e.g. Figure 4 The first metal barrier layer 208 is formed within the structure shown. The first conductive structure includes the first conductive layer 206 and the first metal barrier layer 208.

[0100] The metal in the first conductive layer 206 has a first diffusion capability within the first metal barrier layer 208, and the metal in the first conductive layer 206 has a second diffusion capability within the second dielectric structure. The first diffusion capability is less than the second diffusion capability, so that the metal in the first conductive layer 206 does not easily diffuse into the second dielectric structure.

[0101] In this embodiment, the method for forming the first metal barrier layer 208 includes: forming a first metal barrier material layer (not shown in the figure) on the surface of the first conductive layer 206 and the surface of the first dielectric structure 202; planarizing the first metal barrier material layer until the surface of the first dielectric structure 202 is exposed, thereby forming the first metal barrier layer 208.

[0102] In this embodiment, the surface of the first conductive structure is lower than the surface of the first dielectric structure 202. This provides space for the thermal expansion of the first conductive structure and the second conductive structure during subsequent bonding processes.

[0103] In another embodiment, the surface of the first conductive structure is flush with the surface of the first dielectric structure.

[0104] Specifically, the surface of the first conductive structure has a first recess (not shown in the figure), which extends from the surface of the first conductive structure toward the first functional surface 200a.

[0105] It should be noted that the first depression may be caused by a mechanical-chemical polishing process during the formation of the first conductive structure.

[0106] In this embodiment, the depth of the first depression ranges from 0 nm to 20 nm. More preferably, the depth of the first depression is 5 nm.

[0107] In another embodiment, the surface of the first conductive structure is flush with the surface of the first dielectric structure.

[0108] In this embodiment, the thickness of the first metal barrier layer 208 is less than or equal to 2000 nm. More preferably, the thickness of the first metal barrier layer 208 is 20 nm. The purpose of selecting the above thickness range is that the first metal barrier layer 208 of this thickness has little impact on the contact resistance between the bonded first conductive layer and the second conductive layer, and can play a role in blocking metal diffusion.

[0109] The material of the first metal barrier layer 208 is a material that makes it difficult for the metal in the first conductive layer 206 to diffuse into the second dielectric structure.

[0110] In this embodiment, the material of the first metal barrier layer 208 includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride.

[0111] In this embodiment, the material of the first metal barrier layer 208 and the material of the third metal barrier layer 207 are the same, that is, both are tan / tan nitride bilayer materials.

[0112] In other embodiments, the materials of the first metal barrier layer and the third metal barrier layer may be different.

[0113] Next, the method for forming the second dielectric structure and the second conductive structure will be introduced. Please refer to [link / reference]. Figure 9 and Figure 10 .

[0114] Please refer to Figure 9 A second medium structure 302 is formed on the second functional surface 300a; a second opening 303 is formed in the second medium structure 302, and the second opening 303 exposes the second functional surface 300a.

[0115] Specifically, the second opening 303 exposes the second metal layer 301.

[0116] The material of the second dielectric structure 302 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0117] In this embodiment, the second dielectric structure 302 has four dielectric material layers.

[0118] Specifically, the second dielectric structure 302 includes: a third etch stop layer 302iii, a third dielectric material layer 3023 located on the surface of the third etch stop layer 302iii, a fourth etch stop layer 302iv located on the surface of the third dielectric material layer 3023, and a fourth dielectric material layer 3024 located on the surface of the fourth etch stop layer 302iv.

[0119] In other embodiments, the first dielectric layer may also be a single dielectric material layer or multiple dielectric material layers.

[0120] The third etch stop layer 302iii and the third dielectric material layer 3023 are made of different materials; the fourth etch stop layer 302iv and the fourth dielectric material layer 3024 are made of different materials.

[0121] In this embodiment, the third etch stop layer 302iii and the fourth etch stop layer 302iv are both silicon nitride; the third dielectric material layer 3023 and the fourth dielectric material layer 3024 are both made of silicon oxide.

[0122] In this embodiment, the formation process of the second conductive structure includes a double damask process.

[0123] Specifically, the second opening 303 includes a second groove (not shown in the figure) and a second through hole located below the second groove. The second through hole exposes the surface of the second metal layer 301 and communicates with the second groove. The second through hole is located within the third etch stop layer 302iii, the third dielectric material layer 3023 and the fourth etch stop layer 302iv. The second groove is located within the fourth dielectric material layer 3024. The second through hole has a third projection on the second functional surface 300a, and the second groove has a fourth projection on the second functional surface 300a. The third projection is located within the range of the fourth projection.

[0124] Please refer to Figure 10 In the second opening 303 (e.g. Figure 9 The second conductive layer 306 is formed within the layer shown.

[0125] In this embodiment, the second conductive structure includes a second conductive layer 306 and a second metal barrier layer 308. The second metal barrier layer 308 is located on the surface of the second conductive layer 306, and the second dielectric structure 302 exposes the second metal barrier layer 308.

[0126] Here, the metal in the second conductive layer 306 has a third diffusion capability in the second metal barrier layer 308, and the metal in the second conductive layer 306 has a fourth diffusion capability in the first dielectric structure 202. The third diffusion capability is less than the fourth diffusion capability, so that the metal in the second conductive layer 306 does not easily diffuse into the first dielectric structure 202.

[0127] In another embodiment, the second conductive structure may include only the second conductive layer, without including the second metal barrier layer.

[0128] In this embodiment, the method for forming the second conductive layer includes: forming a second conductive material layer (not shown in the figure) inside the second opening 303 and on the surface of the second dielectric structure 302; planarizing the second conductive material layer until the surface of the second dielectric structure 302 is exposed; after planarizing the second conductive material layer, over-grinding or etching the second conductive material layer so that the top surface of the second conductive material layer is lower than the top surface of the second dielectric structure 302, thereby forming the second conductive layer 306.

[0129] In this embodiment, the second conductive structure further includes a fourth metal barrier layer 307, which is located between the second conductive layer 306 and the second dielectric structure 302.

[0130] In this embodiment, the method for forming the second conductive structure further includes: forming a fourth metal barrier material layer (not shown in the figure) in the second opening 303 and on the surface of the second dielectric structure 302 before forming the second conductive material layer; and forming the fourth metal barrier layer 307 with the fourth metal barrier material layer.

[0131] In this embodiment, the method for forming the second conductive structure further includes: forming the second metal barrier layer 308 on the surface of the second conductive layer 306 and within the second opening 303.

[0132] In this embodiment, the method for forming the second metal barrier layer 308 includes: forming a second metal barrier material layer (not shown in the figure) on the surface of the second conductive layer 306 and the surface of the second dielectric structure 302; planarizing the second metal barrier material layer until the surface of the second dielectric structure is exposed, thereby forming the second metal barrier layer 308.

[0133] In this embodiment, the thickness of the second metal barrier layer 308 is less than or equal to 2000 nm. More preferably, the thickness of the second metal barrier layer 308 is 20 nm. The purpose of selecting the above thickness range is that the second metal barrier layer 308 of this thickness has little impact on the contact resistance between the bonded first conductive layer and the second conductive layer, and can play a role in blocking metal diffusion.

[0134] The material of the second metal barrier layer 308 is a material that makes it difficult for the metal in the second conductive layer 306 to diffuse into the first dielectric structure 202.

[0135] In this embodiment, the material of the second metal barrier layer 308 includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride.

[0136] The material of the fourth metal barrier layer 307 includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride.

[0137] In this embodiment, the material of the second metal barrier layer 308 and the fourth metal barrier layer 307 is the same, that is, both are tan / tan nitride bilayer materials.

[0138] In other embodiments, the materials of the second metal barrier layer and the fourth metal barrier layer may be different.

[0139] In this embodiment, the surface of the second conductive structure is lower than the surface of the second dielectric structure 302. This provides space for the thermal expansion of the first and second conductive structures during subsequent bonding processes.

[0140] In another embodiment, the surface of the second conductive structure is flush with the surface of the second dielectric structure.

[0141] In this embodiment, the surface of the second conductive structure has a second recess (not shown in the figure), and the first recess extends from the surface of the first conductive structure toward the second functional surface.

[0142] It should be noted that the second depression may be caused by a mechanical-chemical polishing process during the formation of the second conductive structure.

[0143] In this embodiment, the depth of the second recess ranges from 0 nm to 20 nm. More preferably, the depth of the second recess is 5 nm. The purpose of selecting the above depth range is to provide space for the thermal expansion of the first conductive structure and the second conductive structure in the subsequent bonding process, while not affecting the bonding capability between the first conductive structure and the second conductive structure.

[0144] In this embodiment, the second metal barrier layer 308 and the fourth metal barrier layer 307 completely surround the second conductive layer 306.

[0145] It should be noted that the method for forming the second conductive structure can also refer to the method for forming the first conductive structure described above, and will not be repeated here.

[0146] Please refer to Figure 11 and Figure 12 , Figure 12 The alignment error in the middle is greater than Figure 11 To correct alignment errors, the first metal barrier layer 208 is oriented toward the second metal barrier layer 308, and the first dielectric structure 202 is oriented toward the second dielectric structure 302, and the first wafer 200 and the second wafer 300 are bonded together.

[0147] Since the surface of the first conductive layer 206 is covered by the first metal barrier layer 208, the metal inside the first conductive layer 206 is less likely to diffuse into the second dielectric structure 302. Even when the alignment error is large, the first metal barrier layer 208 can reduce the diffusion of the metal inside the first conductive layer 206 into the second dielectric structure 302, which is beneficial to improving the reliability of the device.

[0148] In this embodiment, the metal within the second conductive layer 306 has a third diffusion capability within the second metal barrier layer 308, and a fourth diffusion capability within the first dielectric structure 202, wherein the third diffusion capability is less than the fourth diffusion capability. The second metal barrier layer 308 can reduce the diffusion of the metal within the second conductive layer 306 into the first dielectric structure 202, further improving the reliability of the device.

[0149] In this embodiment, the first metal barrier layer 208 is oriented toward the second metal barrier layer 308, and the first dielectric structure 202 is oriented toward the second dielectric structure 302, and the first wafer 200 and the second wafer 300 are bonded together.

[0150] Here, since both the first metal barrier layer 208 and the second metal barrier layer 308 are made of metal, the presence of the first metal barrier layer 208 and the second metal barrier layer 308 can be controlled to reduce metal diffusion and control the influence of the presence of the first metal barrier layer 208 and the second metal barrier layer 308 on the contact resistance between the first conductive structure and the second conductive structure, which is beneficial to improving the overall reliability of the device.

[0151] In this embodiment, the diffusion ability of the metal in the second conductive layer 306 within the dielectric barrier layer 2020 is less than the diffusion ability of the metal in the second conductive layer 306 within the first dielectric layer. The presence of the dielectric barrier layer 2021 further reduces the diffusion of the metal in the second conductive layer 306 into the first dielectric structure 202, thereby improving the reliability of the device.

[0152] In this embodiment, the method for bonding the first wafer 200 and the second wafer 300 further includes bonding the dielectric barrier layer 2021 and the second dielectric structure 302 together.

[0153] Specifically, the dielectric barrier layer 2021 and the fourth dielectric material layer 3024 are bonded together.

[0154] In this embodiment, the dielectric barrier layer 2021 is made of silicon nitride, and the fourth dielectric material layer 3024 is made of silicon oxide. Since silicon nitride and silicon oxide have good bonding ability, it is beneficial to improve the bonding strength between the first wafer 200 and the second wafer 300 and improve the device performance stability.

[0155] In this embodiment, the process parameters for the bonding process include: a bonding temperature range of 100 degrees Celsius to 500 degrees Celsius, and a heat treatment time range of 10 minutes to 600 minutes. More preferably, the bonding temperature is 350 degrees Celsius, and the heat treatment time is 30 minutes.

[0156] The first conductive layer 206 has a first dimension along a direction parallel to the first functional surface 200a, and the second conductive layer 306 has a second dimension along a direction parallel to the second functional surface 300a.

[0157] In this embodiment, the first size and the second size are the same. The provision of the first metal barrier layer 208 and the second metal barrier layer 308 reduces the problem of metal diffusion into the dielectric structure caused by alignment error. At the same time, under the condition of small alignment error, the first size and the second size can be set to a smaller size, which is beneficial to improve the input / output (IO) density.

[0158] In another embodiment, the first dimension is smaller than the second dimension, so that the first conductive structure and the second conductive structure form a "large-enclosing-small" structure, which is beneficial to improve the process window.

[0159] Accordingly, embodiments of the present invention also provide a wafer hybrid bonding structure formed using the above method. Please refer to [link / reference needed]. Figure 11 and Figure 12 The first wafer 200 having a first functional surface 200a, a first dielectric structure 202 on the first functional surface 200a, and a first conductive structure within the first dielectric structure 202, wherein the first dielectric structure 202 includes a first dielectric layer, the first conductive structure includes a first conductive layer 206 and a first metal barrier layer 208 on the surface of the first conductive layer 206, and the first dielectric structure 202 exposes the first metal barrier layer 208; a second wafer 300 bonded to the first wafer 200, the second wafer 300 having a second functional surface 300a; a second dielectric structure 302 on the second functional surface 300a and a second conductive structure within the second dielectric structure 302, wherein the second conductive structure includes a second conductive layer 306, the second dielectric structure 302 exposes the second conductive structure, the first metal barrier layer 208 and the second metal barrier layer 308 are bonded to each other, and the first dielectric structure 202 and the second dielectric structure 302 are bonded to each other.

[0160] Since the surface of the first conductive layer 206 is covered by the first metal barrier layer 208, the metal inside the first conductive layer 206 is less likely to diffuse into the second dielectric structure 302. Even when the alignment error is large, the first metal barrier layer 208 can reduce the diffusion of the metal inside the first conductive layer 206 into the second dielectric structure 302, which is beneficial to improving the reliability of the device.

[0161] Specifically, the metal in the first conductive layer 206 has a first diffusion capability in the first metal barrier layer 208, and the metal in the first conductive layer 206 has a second diffusion capability in the second dielectric structure 302. The first diffusion capability is less than the second diffusion capability, so that the metal in the first conductive layer 206 does not easily diffuse into the second dielectric structure 302.

[0162] In this embodiment, the second conductive structure further includes a second metal barrier layer 308, which is located on the surface of the second conductive layer 306. The first metal barrier layer and the second metal barrier layer are bonded to each other. The second metal barrier layer 308 can reduce the diffusion of metal from the second conductive layer 306 to the first dielectric structure 202, further improving the reliability of the device.

[0163] Specifically, the metal in the second conductive layer 306 has a third diffusion capability within the second metal barrier layer 308, and the metal in the second conductive layer 306 has a fourth diffusion capability within the first dielectric structure 202, wherein the third diffusion capability is less than the fourth diffusion capability.

[0164] The material of the first metal barrier layer 208 is a material that makes it difficult for the metal in the first conductive layer 206 to diffuse into the second dielectric structure 302.

[0165] In this embodiment, the material of the first metal barrier layer 208 includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride.

[0166] The material of the second metal barrier layer 308 is a material that makes it difficult for the metal in the second conductive layer 306 to diffuse into the first dielectric structure 202.

[0167] In this embodiment, the material of the second metal barrier layer 308 includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride.

[0168] Since both the first metal barrier layer 208 and the second metal barrier layer 308 are made of metal, the presence of the first metal barrier layer 208 and the second metal barrier layer 308 can be controlled to reduce metal diffusion and control the impact of the presence of the first metal barrier layer 208 and the second metal barrier layer 308 on the contact resistance between the first conductive structure and the second conductive structure, which is beneficial to improving the overall reliability of the device.

[0169] The material of the first dielectric structure 202 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0170] In this embodiment, the first dielectric layer has four dielectric material layers.

[0171] Specifically, the first dielectric layer includes: a first etch stop layer 202i, a first dielectric material layer 2021 located on the surface of the first etch stop layer 202i, a second etch stop layer 202ii located on the surface of the first dielectric material layer 2021, and a second dielectric material layer 2022 located on the surface of the second etch stop layer 202ii; the dielectric barrier layer 2020 is formed on the surface of the second dielectric material layer 2022.

[0172] In other embodiments, the first dielectric layer may also be a single-layer dielectric material layer or a multi-layer dielectric material layer.

[0173] The first etch stop layer 202i and the first dielectric material layer 2021 are made of different materials; the second etch stop layer 202ii and the second dielectric material layer 2022 are made of different materials.

[0174] In this embodiment, the first etch stop layer 2022 and the second etch stop layer 2024 are both silicon nitride; the first dielectric material layer 2023 and the second dielectric material layer 2025 are both made of silicon oxide.

[0175] The material of the second dielectric structure 302 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0176] In this embodiment, the second dielectric structure 302 has four dielectric material layers.

[0177] Specifically, the second dielectric structure 302 includes: a third etch stop layer 302iii, a third dielectric material layer 3023 located on the surface of the third etch stop layer 302iii, a fourth etch stop layer 302iv located on the surface of the third dielectric material layer 3023, and a fourth dielectric material layer 3024 located on the surface of the fourth etch stop layer 302iv.

[0178] In other embodiments, the first dielectric layer may also be a single dielectric material layer or multiple dielectric material layers.

[0179] The third etch stop layer 302iii and the third dielectric material layer 3023 are made of different materials; the fourth etch stop layer 302iv and the fourth dielectric material layer 3024 are made of different materials.

[0180] In this embodiment, the third etch stop layer 302iii and the fourth etch stop layer 302iv are both silicon nitride; the third dielectric material layer 3023 and the fourth dielectric material layer 3024 are both made of silicon oxide.

[0181] In this embodiment, the first dielectric structure 202 further includes a dielectric barrier layer 2020, which is located on the surface of the first dielectric layer. The diffusion ability of the metal in the second conductive layer 306 within the dielectric barrier layer 2020 is less than the diffusion ability of the metal in the second conductive layer 306 within the first dielectric layer. The presence of the dielectric barrier layer 2021 helps to further reduce the diffusion of the metal in the second conductive layer 306 into the first dielectric structure 202, thereby improving the reliability of the device.

[0182] In another embodiment, the first dielectric structure may include only the first dielectric layer, without the dielectric barrier layer.

[0183] In this embodiment, the first metal barrier layer 208 is located within the dielectric barrier layer 2020, and the dielectric barrier layer 2020 and the second dielectric structure 302 are bonded to each other.

[0184] In this embodiment, the dielectric barrier layer 2020 is made of silicon nitride, and the second dielectric structure 302 is made of silicon oxide. Specifically, the fourth dielectric material layer 3024 is made of silicon oxide. Since silicon nitride and silicon oxide have good bonding ability, this improves the bonding strength between the first wafer 200 and the second wafer 300, thereby enhancing device performance stability.

[0185] In other embodiments, the dielectric barrier layer 2020 may also be other dielectric materials. The key to selecting the material for the dielectric barrier layer 2020 is to ensure that the diffusion ability of the metal within the second conductive layer 206 within the dielectric barrier layer 2020 is less than the diffusion ability of the metal within the second conductive layer 206 within the first dielectric layer.

[0186] In this embodiment, the thickness of the first metal barrier layer 208 is less than or equal to 2000 nm. More preferably, the thickness of the first metal barrier layer 208 is 20 nm. The purpose of selecting the above thickness range is that the first metal barrier layer 208 of this thickness has little impact on the contact resistance between the bonded first conductive layer and the second conductive layer, and can play a role in blocking metal diffusion.

[0187] In this embodiment, the thickness of the second metal barrier layer 308 is less than or equal to 2000 nm. More preferably, the thickness of the second metal barrier layer 308 is 20 nm. The purpose of selecting the above thickness range is that the second metal barrier layer 308 of this thickness has little impact on the contact resistance between the bonded first conductive layer and the second conductive layer, and can play a role in blocking metal diffusion.

[0188] In this embodiment, the first wafer 200 has a first metal layer 201, and the first functional surface 200a exposes the first metal layer 201; the first conductive layer 206 is located on the surface of the first metal layer 201.

[0189] In this embodiment, the second wafer 300 has a second metal layer 301, and the second functional surface 300a exposes the second metal layer 301; the second conductive layer 306 is located on the surface of the second metal layer 301.

[0190] In this embodiment, the first conductive structure further includes a third metal barrier layer 207, which is located between the first conductive layer 206 and the first dielectric structure 202; the second conductive structure further includes a fourth metal barrier layer 307, which is located between the second conductive layer 306 and the second dielectric structure 302.

[0191] In this embodiment, the first metal barrier layer 208 and the third metal barrier layer 207 completely surround the first conductive layer 206 to reduce the diffusion of metal in the first conductive layer 206 into the surrounding dielectric material.

[0192] In this embodiment, the second metal barrier layer 308 and the fourth metal barrier layer 307 completely surround the second conductive layer 306 to reduce the diffusion of metal in the second conductive layer 306 into the surrounding dielectric material.

[0193] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A wafer hybrid bonding structure, characterized in that, include: A first wafer having a first functional surface, a first dielectric structure located on the first functional surface, and a first conductive structure located within the first dielectric structure, the first dielectric structure including a first dielectric layer, the first conductive structure including a first conductive layer and a first metal barrier layer located on the surface of the first conductive layer, the first dielectric structure exposing the first metal barrier layer. A second wafer bonded to a first wafer, the second wafer having a second functional surface; A second dielectric structure located on the second functional surface and a second conductive structure located within the second dielectric structure, the second conductive structure including a second conductive layer, the second dielectric structure exposing the second conductive structure, the first conductive structure and the second conductive structure being bonded to each other, and the first dielectric structure and the second dielectric structure being bonded to each other.

2. The wafer hybrid bonding structure as described in claim 1, characterized in that, The second conductive structure further includes a second metal barrier layer, which is located on the surface of the second conductive layer. The first metal barrier layer and the second metal barrier layer are bonded to each other. The material of the second metal barrier layer is a material that makes it difficult for the metal in the second conductive layer to diffuse into the first dielectric structure. The metal in the second conductive layer has a third diffusion capability within the second metal barrier layer, and the metal in the second conductive layer has a fourth diffusion capability within the first dielectric structure, wherein the third diffusion capability is less than the fourth diffusion capability.

3. The wafer hybrid bonding structure as described in claim 2, characterized in that, The first conductive structure further includes a third metal barrier layer, which is located between the first conductive layer and the first dielectric structure; the second conductive structure further includes a fourth metal barrier layer, which is located between the second conductive layer and the second dielectric structure.

4. The wafer hybrid bonding structure as described in claim 3, characterized in that, The first metal barrier layer and the third metal barrier layer completely surround the first conductive layer; the second metal barrier layer and the fourth metal barrier layer completely surround the second conductive layer.

5. The wafer hybrid bonding structure as described in claim 2, characterized in that, The material of the first metal barrier layer includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride; the material of the second metal barrier layer includes one or more of titanium, tan, tin, ruthenium, tan nitride, and titanium nitride.

6. The wafer hybrid bonding structure as described in claim 2, characterized in that, The thickness of the first metal barrier layer is less than or equal to 2000 nm; the thickness of the second metal barrier layer is less than or equal to 2000 nm.

7. The wafer hybrid bonding structure as described in claim 1, characterized in that, The first dielectric structure further includes a dielectric barrier layer located on the surface of the first dielectric layer. The diffusion capacity of the metal in the second conductive layer within the dielectric barrier layer is less than the diffusion capacity of the metal in the second conductive layer within the first dielectric layer. The first metal barrier layer is located within the dielectric barrier layer, and the dielectric barrier layer and the second dielectric structure are bonded to each other.

8. The wafer hybrid bonding structure as described in claim 1, characterized in that, The material of the first metal barrier layer is a material that makes it difficult for the metal in the first conductive layer to diffuse into the second dielectric structure; the metal in the first conductive layer has a first diffusion capability in the first metal barrier layer, and the metal in the first conductive layer has a second diffusion capability in the second dielectric structure, wherein the first diffusion capability is less than the second diffusion capability.

9. A wafer hybrid bonding method, characterized in that, include: A first wafer and a second wafer are provided, the first wafer having a first functional surface and the second wafer having a second functional surface; A first dielectric structure and a first conductive structure located within the first dielectric structure are formed on the first functional surface. The first dielectric structure includes a first dielectric layer, and the first conductive structure includes a first conductive layer and a first metal barrier layer located on the surface of the first conductive layer. The first dielectric structure exposes the first metal barrier layer. A second dielectric structure and a second conductive structure located within the second dielectric structure are formed on the second functional surface. The second conductive structure includes a second conductive layer, and the second dielectric structure exposes the second conductive structure. The first conductive structure is oriented toward the second conductive structure, and the first dielectric structure is oriented toward the second dielectric structure, and the first wafer and the second wafer are bonded together.

10. The wafer hybrid bonding method as described in claim 9, characterized in that, The method for forming the first dielectric structure and the first conductive structure includes: forming the first dielectric structure on the first functional surface; forming a first opening in the first dielectric structure, the first opening exposing the first functional surface; forming the first conductive layer in the first opening; and forming the first metal barrier layer on the surface of the first conductive layer and in the first opening.

11. The wafer hybrid bonding method as described in claim 10, characterized in that, The method for forming the first conductive layer includes: forming a first conductive material layer inside the first opening and on the surface of the first dielectric structure; planarizing the first conductive material layer until the surface of the first dielectric structure is exposed; and after planarizing the first conductive material layer, performing over-grinding or etching on the first conductive material layer so that the top surface of the first conductive material layer is lower than the top surface of the first dielectric structure, thereby forming the first conductive layer.

12. The wafer hybrid bonding method as described in claim 11, characterized in that, The first conductive structure further includes a third metal barrier layer, which is located between the first conductive layer and the first dielectric structure; the first metal barrier layer and the third metal barrier layer completely surround the first conductive layer; The method for forming the first conductive structure further includes: before forming the first conductive material layer, forming a third metal barrier material layer in the first opening and on the surface of the first dielectric structure, wherein the first conductive material layer is formed on the surface of the third metal barrier material layer; The third metal barrier layer is formed by the third metal barrier material layer.

13. The wafer hybrid bonding method as described in claim 10, characterized in that, The method for forming the first metal barrier layer includes: forming a first metal barrier material layer on the surface of the first conductive layer and the surface of the first dielectric structure; planarizing the first metal barrier material layer until the surface of the first dielectric structure is exposed, thereby forming the first metal barrier layer.

14. The wafer hybrid bonding method as described in claim 9, characterized in that, The method for forming the second dielectric structure and the second conductive structure includes: forming the second dielectric structure on the second functional surface; forming a second opening in the second dielectric structure, the second opening exposing the second functional surface; and forming the second conductive layer in the second opening.

15. The wafer hybrid bonding method as described in claim 14, characterized in that, The second conductive structure further includes a second metal barrier layer, which is located on the surface of the second conductive layer, and the second dielectric structure exposes the second metal barrier layer. The method for forming the second conductive structure further includes: forming the second metal barrier layer on the surface of the second conductive layer and within the second opening.

16. The wafer hybrid bonding method as described in claim 15, characterized in that, The method for forming the second conductive layer includes: forming a second conductive material layer inside the second opening and on the surface of the second dielectric structure; planarizing the second conductive material layer until the surface of the second dielectric structure is exposed; and after planarizing the second conductive material layer, subjecting the second conductive material layer to over-grinding or etching so that the top surface of the second conductive material layer is lower than the top surface of the second dielectric structure, thereby forming the second conductive layer.

17. The wafer hybrid bonding method as described in claim 15, characterized in that, The second conductive structure further includes a fourth metal barrier layer, which is located between the second conductive layer and the second dielectric structure; the second metal barrier layer and the fourth metal barrier layer completely surround the second conductive layer; The method for forming the second conductive structure further includes: forming a fourth metal barrier material layer in the second opening and on the surface of the second dielectric structure before forming the second conductive material layer; The fourth metal barrier layer is formed using the fourth metal barrier material layer.

18. The wafer hybrid bonding method as described in claim 15, characterized in that, The method for forming the second metal barrier layer includes: forming a second metal barrier material layer on the surface of the second conductive layer and the surface of the second dielectric structure; planarizing the second metal barrier material layer until the surface of the second dielectric structure is exposed, thereby forming the second metal barrier layer.

19. The wafer hybrid bonding method as described in claim 9, characterized in that, The first dielectric structure further includes a dielectric barrier layer, which is located on the surface of the first dielectric layer. The diffusion ability of the metal in the second conductive layer within the dielectric barrier layer is less than the diffusion ability of the metal in the second conductive layer within the first dielectric layer. The first metal barrier layer is formed within the dielectric barrier layer; The method for bonding the first wafer and the second wafer further includes: bonding the dielectric barrier layer and the second dielectric structure to each other.

20. The wafer hybrid bonding method as described in claim 9, characterized in that, The bonding process parameters include: a bonding temperature range of 100 degrees Celsius to 500 degrees Celsius and a heat treatment time range of 10 minutes to 600 minutes.

21. The wafer hybrid bonding method as described in claim 9, characterized in that, The first conductive structure has a first recess on its surface, which extends from the first conductive structure surface toward the first functional surface; the depth of the first recess ranges from 0 nm to 20 nm. The second conductive structure surface has a second depression, and the first depression extends from the first conductive structure surface toward the second functional surface; the depth of the second depression ranges from 0 nm to 20 nm.

22. The wafer hybrid bonding method as described in claim 9, characterized in that, The surface of the first conductive structure is lower than or flush with the surface of the first dielectric structure; the surface of the second conductive structure is lower than or flush with the surface of the second dielectric structure.

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