Method for manufacturing an optoelectronic component

Abstract

Method for manufacturing an optoelectronic component (100) comprising the steps: A) Providing a growth substrate (1), B) Deposition of a semiconductor layer sequence (2) comprising a top (21) and bottom (22), at least one n-doped semiconductor region (23), at least one p-doped semiconductor region (24) and an active layer (25) arranged between these semiconductor regions for radiation generation, wherein the top (21) faces away from the growth substrate (1) and the bottom (22) faces the growth substrate (1), C) Structuring the semiconductor layer sequence (2) from the top (21) to the bottom (22) of the semiconductor layer sequence (2) to generate side surfaces (26) of the semiconductor layer sequence (2), D) Applying a sacrificial layer (3) to the side surfaces (26) of the semiconductor layer sequence (2) and to surfaces of the growth substrate (1) exposed in step C), which is set up for removal of the growth substrate (1) by laser lifting process, E) Deposition of a metal layer (4) to form a first connection contact on the side of the semiconductor layer sequence (2) facing away from the growth substrate (1), on the side surfaces (26) of the semiconductor layer sequence (2) and on the sacrificial layer (3), G) Forming a second connection contact (8) through the active area (25), H) Applying a permanent support (6) to the side of the semiconductor layer sequence (2) facing away from the growth substrate (1), and I) Detaching the growth substrate (1) and thereby exposing the metal layer (4), wherein the process according to step I) is free of lithographic steps.

Description

[0001] A method for producing an optoelectronic component is specified.

[0002] In optoelectronic components such as surface-emitting light-emitting diodes (LEDs), lithography steps are typically applied on the emission side of the LED chips after detaching a growth substrate. This creates so-called run-out problems, i.e., a change in lateral dimensions due to changes in stress conditions within the layer structures of a wafer. This results in yield losses.

[0003] The document DE 10 2013 105 870 A1 describes an optoelectronic semiconductor chip.

[0004] The document DE 10 2007 022 947 A1 describes an optoelectronic semiconductor body and a method for producing such a body.

[0005] The document US 5 670 798 A describes integrated heterostructures of III-V nitride semiconductor materials.

[0006] The document DE 102 45 631 A1 describes a semiconductor component and a method for its production.

[0007] One object of the invention is to provide an improved optoelectronic component. In particular, the optoelectronic components according to the invention are intended to avoid the need to apply lithography steps on wafers with runout. Furthermore, the object of the invention is to provide a method for producing an optoelectronic component that produces an optoelectronic component with improved properties.

[0008] This object is achieved by a method for producing an optoelectronic component according to independent claim 1. Advantageous embodiments and / or further developments of the invention are the subject of the dependent claims.

[0009] The method for manufacturing an optoelectronic component comprises the following steps: A) Providing a growth substrate, B) applying a semiconductor layer sequence having a top side and a bottom side, at least one n-doped semiconductor region, at least one p-doped semiconductor region and an active layer for generating radiation arranged between these semiconductor regions, wherein the top side faces away from the growth substrate and the bottom side faces the growth substrate, C) Structuring the semiconductor layer sequence from the top side to the bottom side of the semiconductor layer sequence, in particular complete structuring of the semiconductor layer sequence from the top side to the bottom side of the semiconductor layer sequence or complete structuring of the p-doped semiconductor region and the active layer as well as partial structuring of the n-doped semiconductor region to produce side surfaces of the semiconductor layer sequence, D) applying a sacrificial layer to the side surfaces of the semiconductor layer sequence and to the surfaces of the growth substrate exposed in step C), which sacrificial layer is designed to remove the growth substrate by laser lift-off processes, E) depositing a metal layer to form a first connection contact on the side of the semiconductor layer sequence facing away from the growth substrate, on the side surfaces of the semiconductor layer sequence and on the sacrificial layer, F) optionally planarizing by filling areas lateral to the semiconductor layer sequence with a dielectric material up to at least the top of the semiconductor layer sequence, G) Formation of at least or exactly one second connection contact through the active area, H) applying a permanent carrier to the side of the semiconductor layer sequence facing away from the growth substrate, and I) Detaching the growth substrate and thereby exposing the metal layer, whereby

[0010] The process according to step I) is free of lithography steps.

[0011] The method comprises step A), providing a growth substrate. The growth substrate may, for example, be a wafer. The wafer may comprise a material selected from a group comprising silicon, silicon carbide, gallium nitride, germanium, sapphire, metal, plastic, or glass, and combinations thereof. In particular, the growth substrate is a sapphire substrate. For example, the sapphire substrate is a pre-structured sapphire substrate (PSS sapphire substrate).

[0012] The method comprises a step B), applying a semiconductor layer sequence. The semiconductor layer sequence has a top side facing away from the growth substrate. The semiconductor layer sequence has a bottom side facing the growth substrate. In other words, the bottom side forms, in particular, the radiation exit surface in the finished component, i.e., the surface arranged perpendicular to the growth direction of the semiconductor layer sequence.

[0013] The semiconductor layer sequence has at least one n-doped semiconductor region, at least one p-doped semiconductor region, and an active layer for generating radiation arranged between these semiconductor regions. The n-doped and p-doped semiconductor regions are in particular each an n-doped or p-doped semiconductor layer. The semiconductor layers are preferably based on a III-V compound semiconductor material. The semiconductor material can preferably be based on a nitride compound semiconductor material. "Based on a nitride compound semiconductor material" in the present context means that the semiconductor layer sequence or at least one layer thereof comprises a III-nitride compound semiconductor material, preferably In x Al y Ga 1-x-yN, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1. This material does not necessarily have to have a mathematically exact composition according to the above formula. Rather, it can contain one or more dopants as well as additional components that determine the characteristic physical properties of the In x Al y Ga 1-x-y N material does not change significantly. For simplicity, however, the above formula only includes the essential components of the crystal lattice (In, Al, Ga, N), even if these may be partially replaced by small amounts of other substances.

[0014] The optoelectronic component includes an active layer with at least one pn junction and / or one or more quantum well structures. During operation of the optoelectronic component, electromagnetic radiation is generated in the active layer. A wavelength or a wavelength maximum of the radiation is preferably in the ultraviolet and / or visible range, in particular at wavelengths between 200 nm and 680 nm, for example between 350 nm and 480 nm, particularly preferably between 420 nm and 460 nm.

[0015] According to at least one embodiment, the optoelectronic component is a light-emitting diode (LED). The component is then preferably configured to emit blue light or white light.

[0016] The semiconductor layer sequence has an active layer. The active layer is arranged between the semiconductor regions. In particular, the active layer is arranged in direct contact with both the n-doped and the p-doped semiconductor regions. Direct here means direct mechanical and / or electrical contact. The active region of the semiconductor layer sequence is designed in particular to generate radiation, i.e., to emit or absorb radiation. Preferably, the active region is designed to emit or absorb radiation everywhere along its entire lateral extent and forms a luminous area or detection area there. For example, the active layer is formed contiguously within the active region. The active region can also form a pixelated or segmented luminous area.

[0017] According to at least one embodiment, a current spreading structure can be arranged downstream of the p-doped semiconductor region. The current spreading structure is, in particular, a transparent electrically conductive layer. In this way, good current spreading is achieved in the semiconductor layer sequence. The current spreading layer can preferably comprise a transparent conductive oxide (TCO), such as ITO.

[0018] Transparent, electrically conductive oxides (TCO) are transparent, electrically conductive materials, typically metal oxides such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide, indium tin oxide (ITO), or aluminum zinc oxide (AZO). In addition to binary metal-oxygen compounds such as ZnO, SnO2, or In2O3, ternary metal-oxygen compounds such as Zn2SnO4, CdSnO3, ZnSnO3, MgIn2O4, GaInO3, Zn2In2O5, or In4Sn3O are also included. 12or mixtures of different transparent, conducting oxides belong to the group of TCOs. Furthermore, TCOs do not necessarily have a stoichiometric composition and can also be p- or n-doped.

[0019] According to at least one embodiment, a passivation layer can be arranged downstream of the current spreading structure. The passivation layer can be arranged over the entire surface of the current spreading structure.

[0020] In particular, the passivation layer can form a dielectric mirror. In particular, the passivation layer comprises a dielectric material, for example, silicon dioxide or silicon nitride.

[0021] The method comprises step C), structuring the semiconductor layer sequence from the top side to the bottom side of the semiconductor layer sequence to produce side surfaces of the semiconductor layer sequence.

[0022] Structuring in step C) can be performed using lithography. In particular, side surfaces of the semiconductor layer sequence, especially mesa flanks, are created. This creates so-called semiconductor chip trenches, and a so-called bond pad area is etched.

[0023] Preferably, the structuring is carried out from the top side, i.e. in particular from the p-doped semiconductor region, via the active layer to the n-doped semiconductor region up to the growth substrate.

[0024] After step C), the growth substrate thus has a larger lateral extent than the semiconductor layer sequence.

[0025] The method comprises a step D), applying a sacrificial layer to the side surfaces of the semiconductor layer sequence and also to surfaces of the growth substrate exposed in step C), which is configured for removal of the growth substrate by laser lift-off. The sacrificial layer preferably comprises or consists of silicon nitride or silicon dioxide. This allows the growth substrate to be easily removed in a subsequent process step, because the sacrificial layer decomposes at least partially during the so-called laser lift-off process, thus creating a complete separation of the growth substrate.

[0026] If a growth substrate is used that is not suitable for laser lift-off, a mechanical or chemical separation process can be used as an alternative. In this case, the sacrificial layer also serves as a protective layer for the subsequent layers.

[0027] The fact that a layer or element is arranged or applied "on" or "over" another layer or element can mean here and below that one layer or element is arranged in direct mechanical and / or electrical contact with the other layer or element. Furthermore, it can also mean that one layer or element is arranged indirectly on or over the other layer or element. In this case, further layers and / or elements can be arranged between one and the other layer or between one and the other element.

[0028] According to at least one embodiment, the method may comprise an additional step of grinding back and / or polishing the top side of the semiconductor layer sequence.

[0029] According to at least one embodiment of the method, it comprises an additional step: structuring the passivation layer. This allows for easy access to the current spreading structure. The structuring of the passivation layer can be performed, for example, lithographically.

[0030] The method comprises a step E), depositing a metal layer for forming a first connection contact on the side of the semiconductor layer sequence facing away from the growth substrate, on the side surfaces of the semiconductor layer sequence, and on the sacrificial layer. In particular, the deposition is carried out in a structured manner using an etching process with a resist mask or a lift-off technique. For example, the metal layer contains gold, silver, or aluminum.

[0031] In particular, the first terminal contact forms a p-type terminal contact. In other words, the p-type terminal contact forms the p-type contact of the semiconductor layer sequence. The p-type terminal contact can, for example, have a bond pad and / or one or more contact bridges or a contact area.

[0032] In particular, the metal layer covers both the side surfaces of the semiconductor layer sequence and the top surface of the semiconductor layer sequence, as well as the sacrificial layer, at least partially or completely. The metal layer thus preferably performs three functions: First, the function of the p-type terminal contact. Second, the metal layer mirrors or encapsulates the side surfaces of the semiconductor layer sequence, which in particular represent mesa flanks. Third, the metal layer forms a so-called bond pad area, which is exposed in step I).

[0033] According to at least one embodiment of the method, this comprises a step F), planarization by filling regions lateral to the semiconductor layer sequence with a dielectric material up to at least the top side of the semiconductor layer sequence. In particular, the dielectric material can be silicon dioxide. Planarization can be carried out, for example, by means of chemical mechanical polishing (CMP). In other words, the planarization in step F) compensates for the height differences, thus making subsequent process steps easier to perform. Furthermore, topographies for so-called wafer bonding can be avoided.

[0034] According to at least one embodiment, an additional step can be performed after method step E) or F): depositing a dielectric material onto the semiconductor layer sequence and / or the metal layer. In particular, the dielectric material of the planarization produced in step F) and the additionally applied dielectric material form a cladding of the semiconductor layer sequence.

[0035] The method comprises a step G), forming a second terminal contact through the active region. In particular, the second terminal contact is an n-type terminal contact. In other words, the n-type terminal contact contacts the n-doped semiconductor region. Preferably, the n-type terminal contact extends at least from the top side of the semiconductor layer sequence over the active region into the n-doped semiconductor region.

[0036] According to at least one embodiment, the second terminal contact is formed as an approximately rectangular shape in a side view of the optoelectronic component, wherein the side surfaces of the second terminal contact are passivated with a dielectric material. The dielectric material can be created by deposition of silicon dioxide or silicon nitride. The dielectric material can serve to passivate the layers to the p-potential. The contact area to the n-doped semiconductor region can be created by anisotropic back etching.

[0037] The method comprises a process step H), applying a permanent carrier to the side facing away from the growth substrate. The carrier can comprise or consist of, for example, silicon, germanium, metal, ceramic, circuit board, or molybdenum. A solder metal and / or a solder barrier can be applied between the carrier and the growth substrate.

[0038] The process comprises a process step (I): detaching the growth substrate and exposing the metal layer. Detachment can be performed, for example, using a laser lift-off process. This removes the growth substrate.

[0039] Optionally, wet-chemical removal of the sacrificial layer or sacrificial layer residues can be performed. This exposes the metal layer and allows it to serve as a bond pad.

[0040] In particular, the metal layer forms a plane with the underside of the semiconductor layer sequence in side view.

[0041] According to at least one embodiment, no further lithography step is performed after step G). In particular, steps A) to G) are performed in the order described above, with no lithography step being performed after step G).

[0042] According to at least one embodiment, the metal layer deposited in step E) is a p-type terminal contact and forms a mirror coating on the side surfaces of the semiconductor layer sequence. Additionally, the metal layer can form a bond pad, at least after step I).

[0043] According to at least one embodiment, after method step I), an additional step is carried out, namely singulating or severing the semiconductor layer sequence to produce a plurality of semiconductor chips.

[0044] According to at least one embodiment, the sacrificial layer comprises or consists of silicon nitride and / or the dielectric material comprises or consists of silicon oxide.

[0045] According to at least one embodiment, the lateral extent of the semiconductor layer sequence and the carrier, preferably after step I), i.e., of the finished component or element, is the same. In other words, the lateral extent of the semiconductor layer sequence differs from the lateral extent of the carrier by a maximum of 0.1, 0.5, 1, 2, or 5%.

[0046] According to at least one embodiment, the metal layer deposited in step E) is a p-type terminal contact and has a thickness of at least 10 nm or 30 nm. In other words, the metal layer is reflective. The top side of the semiconductor layer sequence is covered by the metal layer. In particular, the radiation emission from the active layer occurs via the bottom side of the semiconductor layer sequence, with the metal layer being arranged laterally and in a plane relative to the n-doped semiconductor region. In particular, the plane is oriented perpendicular to the growth direction of the semiconductor layer sequence.

[0047] According to at least one embodiment, the second terminal contact formed in step G) is an n-terminal contact, wherein the n-terminal contact is arranged laterally and in a plane to the n-doped semiconductor region.

[0048] According to at least one embodiment, the second terminal contact formed in step G) is an n-terminal contact, wherein the n-terminal contact and the metal layer comprise or consist of aluminum.

[0049] According to at least one embodiment, the metal layer is exposed in step I) by wet-chemical removal of the sacrificial layer.

[0050] According to at least one embodiment, an additional step is performed between steps D) and E): depositing a gold layer onto a region of the sacrificial layer arranged on the surface of the growth substrate. In other words, the gold layer thus forms a bond pad in the finished component.

[0051] According to at least one embodiment, the second terminal contact formed in step G) is an n-type terminal contact and comprises silver or is formed from silver. The p-type terminal contact can additionally also be formed from silver or aluminum or comprise these.

[0052] According to at least one embodiment, the metal layer is formed from gold.

[0053] The invention further relates to an optoelectronic component. The optoelectronic component is preferably manufactured using a method described above. All definitions and explanations relating to the method also apply to the optoelectronic component, and vice versa.

[0054] Further advantages, advantageous embodiments, and further developments will become apparent from the exemplary embodiments described below in conjunction with the figures. They show: The Fig. 1A to 1K show a method for producing an optoelectronic component according to an embodiment, the Fig. 2 to 5D each show a method for manufacturing an optoelectronic component according to an embodiment.

[0055] In the exemplary embodiments and figures, identical, similar, or similarly functioning elements may be provided with the same reference numerals. The illustrated elements and their relative sizes are not to be considered to scale. Rather, individual elements, such as layers, components, structural elements, and regions, may be exaggerated for clarity and / or clarity.

[0056] The Fig. 1A to 1K show a method for manufacturing an optoelectronic component.

[0057] In Fig. 1A, a growth substrate 1, for example, made of a pre-structured sapphire substrate, is provided. A semiconductor layer sequence 2 comprising an n-type semiconductor region 23, an active layer (not shown here), and a p-doped semiconductor region 24 is applied to this growth substrate 1. A current spreading structure 12, in particular made of ITO, and then a passivation layer 10, in particular made of silicon dioxide, are arranged downstream of the p-doped semiconductor region 24.

[0058] The semiconductor layer sequence 2 has a top side 21 facing away from the growth substrate 1 and a bottom side 22 facing the growth substrate 1.

[0059] The passivation layer 10 can serve as a dielectric mirror. An annealing step can be performed between the application of the current spreading structure 12, which serves in particular for p-type contacting, and the passivation layer 10.

[0060] In Fig. 1B shows the structuring of the semiconductor layer sequence 2 from the top side 21 to at most the bottom side 22 of the semiconductor layer sequence 2 to produce side surfaces 26 of the semiconductor layer sequence 2. The structuring is carried out, in particular, lithographically.

[0061] In Fig. Figure 1C shows the deposition of a sacrificial layer 3 onto the side surfaces 26 of the semiconductor layer sequence 2 and onto the surfaces 11 of the growth substrate 1 exposed in step C). The sacrificial layer 3 serves for the subsequent removal of the growth substrate 1 by laser lift-off processes, which are performed, for example, in step I).

[0062] Optionally, after the application of the sacrificial layer 3, grinding and / or polishing can be carried out on the top side 21 or the side surfaces 26 of the semiconductor layer sequence 2.

[0063] In Fig. Figure 1D shows the lithographic patterning of the passivation layer 10. This creates, in particular, p-type contact openings to provide access to the current spreading structure 12. This allows a p-type terminal contact to be formed.

[0064] In Fig. 1E shows the deposition of a metal layer 4 to form a first connection contact. The deposition is carried out in a structured and lithographic manner. In particular, the metal layer 4 is formed from aluminum. The metal layer 4 is arranged, in particular, at least in regions on the top side 21 of the semiconductor layer sequence 2, on the side surfaces 26 of the semiconductor layer sequence 2, and on the exposed surfaces 11 of the growth substrate 1. The sacrificial layer 3 is arranged between the exposed surfaces 11 of the growth substrate 1 and the metal layer 4. The metal layer 4 thus serves to connect the semiconductor layer sequence 2 via the current spreading structure 12, i.e., in particular, the p-contact layer. Furthermore, the metal layer 4 serves as a mirror coating and / or encapsulation of the side surfaces 26 of the semiconductor layer sequence 2 and as a bond pad area, which is exposed in a later process step.

[0065] In Fig. 1F shows the optional step of planarization by filling regions lateral to the semiconductor layer sequence 2 with a dielectric material 5 up to at least the top side of the semiconductor layer sequence 2. In particular, the dielectric material 5 extends, as seen in side view, at the level of the metal layer 4 arranged above the semiconductor layer sequence 2. In particular, the dielectric material 5 is silicon dioxide. Preferably, the dielectric material 5 is arranged lateral to the semiconductor layer sequence 2 and / or above the top side 21 of the semiconductor layer sequence 2.

[0066] Planarization can be performed chemically and mechanically, thus avoiding height differences or topographical differences for wafer bonding.

[0067] The Fig. 1G shows the deposition of further dielectric material 5 over the semiconductor layer sequence 2. In other words, the metal layer 4 arranged on the semiconductor layer sequence 2 is also encased by the dielectric material 5.

[0068] In Fig. 1H shows the formation of a second terminal contact 8 through the active region. In particular, the formation of the second terminal contact 8, which is in particular an n-type terminal contact, is carried out by means of lithography. In other words, the second terminal contact extends from the dielectric material 5 across the p-doped semiconductor region and the active region into the n-doped semiconductor region. Thus, the second terminal contact serves as an n-type contact for contacting the n-type semiconductor region. Fig. 1I, the side surfaces of the formed second connection contact are passivated. The passivation is carried out in particular using a dielectric material, for example, silicon dioxide.

[0069] The passivation of the second terminal contact can initially be performed completely, i.e., on the entire surface of the second terminal contact. Subsequently, an anisotropic back etching can be performed to expose the second terminal contact, i.e., the connection to the n-doped semiconductor region.

[0070] In Fig. 1J shows the deposition of a metal for n-type contacting. The metal can be aluminum, for example, and can also serve as a mirror. The metal for the second connection contact 8 can extend both into the n-doped semiconductor region and on top of the semiconductor layer sequence 2. A solder layer 7 can then be applied. The solder layer 7 can consist of or comprise a solder metal. Alternatively or additionally, a solder barrier layer can also be deposited (not shown here). A carrier 6, which is in particular permanent, can then be applied to the solder layer 7. In a subsequent method step, the growth substrate 1 can be removed. The removal can be carried out, for example, by means of a laser lift-off process. Optionally, the sacrificial layer can be removed by wet-chemical removal.

[0071] The semiconductor layer sequence can then be separated, creating multiple semiconductor chips. Singulation or separation can be achieved using plasma, for example.

[0072] In particular, the lateral extent of the semiconductor layer sequence 2 and the lateral extent of the carrier 6 are equal.

[0073] The lithography steps that are usually performed on the n-side of the semiconductor layer sequence 2 are shifted forward to the opposite p-side of the semiconductor layer sequence 2. This avoids the problem that wafers that exhibit runout—that is, a change in lateral dimensions due to a change in stress conditions within the layer structures of the wafer, for example, due to the removal of the growth substrate—must be processed with lithography masks that must compensate for the runout. This avoids a loss of yield. In particular, an optoelectronic component 100 can be produced that has a metal layer 4 as a bond pad, in particular a p-contact as a bond pad, on or lateral to the emission side, that is, to the underside 22 of the semiconductor layer sequence 2.The metal layer 4 simultaneously serves as a current distribution layer for the p-doped semiconductor region, as a side surface mirroring and as a bond pad for the p-contact.

[0074] Run-out issues must always be considered during lithography steps on the n-doped semiconductor region. Eliminating this problem can increase yield. The process flow described here results in complete mirroring of the epitaxial layer on the p-doped semiconductor side and on the side surface of semiconductor layer sequence 2. A second mirror arranged underneath to increase the reflectivity of the chip edge region (combo mirror) can be omitted. Complete encapsulation of the p-doped semiconductor side and the side surfaces of the semiconductor layer sequence with a metal or lithium nitride ideally encapsulates the semiconductor layer sequence and thus contributes to component reliability.

[0075] The epitaxial growth substrate can be exposed through a p-side mesa etch, in which the epitaxial layer in the area of ​​the future bond pad is also etched. The exposed growth substrate can be provided with a sacrificial layer, particularly made of silicon nitride, which later enables the entire surface of the growth substrate to be removed by laser lift-off. The metal layer can be applied in such a way that it has electrical contact with the p-doped semiconductor region or with a previously applied p-connection layer and is simultaneously arranged on the sacrificial layer in the area of ​​the bond pad. The metal layer can be used as a bond pad on the n-side once the laser lift-off process has removed the growth substrate and the exposed sacrificial layer.

[0076] The Fig. 2 shows a schematic side view of an optoelectronic component 100. The component according to the Fig. 2 can be similar to the procedure of Fig. 1A to 1K with the following changes: Before depositing the metal layer 4 (process step of Fig. 1E), a gold layer 9 is applied. The gold layer 9 can be deposited in a lithographically structured manner. In particular, the deposition takes place on the exposed surface 11 of the growth substrate 1, lateral to the semiconductor layer sequence 2. Optionally, additional barrier layers can be applied. In other words, a further lithography step provides a gold surface that can be used as a bond pad.

[0077] The Fig. Figure 3 shows a schematic side view of an optoelectronic component. The optoelectronic component of Fig. 3 can be similar to the procedure of Fig. 1A to 1K with the following modification. Here, a second connection contact 8, which in particular comprises silver, is applied lithographically. In particular, the second connection contact 8 does not extend to the edges of the semiconductor layer sequence. This allows for better contact mirroring to be achieved by means of an additional lithography step.

[0078] In particular, the side surfaces 26 of the semiconductor layer sequence 2 are free of silver. This prevents corrosion and a possible short circuit.

[0079] The Fig. Figure 4 shows a schematic side view of an optoelectronic component. The optoelectronic component can be manufactured analogously to the method of Fig. 1A to 1K can be manufactured with the following change. In the method described here, the metal layer 4 is arranged only on the top side 21 of the semiconductor layer sequence 2. In addition, a gold layer 9 is arranged both on the surface of the sacrificial layer 3 and on the side surfaces 26 of the semiconductor layer sequence 2 and on the surface 21 of the semiconductor layer sequence 2. This can be done lithographically. The additional lithography step can create a wire bond. The loss of the silver mirror coating on the side surfaces of the semiconductor layer sequence 2 and on the edge zone of the semiconductor layer sequence 2 can be compensated for by using silver as the metal layer 4.

[0080] The Fig. 5A to 5D show a method for manufacturing an optoelectronic component according to one embodiment. The component of Fig. 5A was analogous to the component of the process of Fig. 1A to 1E are manufactured. Subsequently, the component of the Fig. 5A, a sacrificial layer 3 is applied. The sacrificial layer 3 is formed, in particular, from silicon nitride. This allows a separation of the first and second connection layers 4, 8. In Fig. 5B shows that a second terminal contact 8 is created. Lithographic structuring and deposition of a metal can be performed to form a second terminal contact 8, in particular an n-contact and an n-bond pad.

[0081] In Fig. Figure 5C shows that a dielectric material 5 is applied laterally to the semiconductor layer sequence 2. In particular, the dielectric material 5 is silicon dioxide. Subsequently, chemical-mechanical planarization can be performed.

[0082] In Fig.5D shows that a thin-film LED chip was produced according to method step E), which has both the first connection contact 4 and the second connection contact 8 on the underside 22, i.e. on the emission side.

[0083] The exemplary embodiments described in conjunction with the figures and their features can also be combined with one another according to further exemplary embodiments, even if such combinations are not explicitly shown in the figures. Furthermore, the exemplary embodiments described in conjunction with the figures can have additional or alternative features according to the description in the general part.

Claims

[1] Method for producing an optoelectronic component (100) comprising the steps: A) Providing a growth substrate (1), B) applying a semiconductor layer sequence (2) which has a top side (21) and a bottom side (22), at least one n-doped semiconductor region (23), at least one p-doped semiconductor region (24) and an active layer (25) arranged between these semiconductor regions for generating radiation, wherein the top side (21) faces away from the growth substrate (1) and the bottom side (22) faces the growth substrate (1), C) Structuring the semiconductor layer sequence (2) from the top side (21) to the bottom side (22) of the semiconductor layer sequence (2) to produce side surfaces (26) of the semiconductor layer sequence (2), D) applying a sacrificial layer (3) to the side surfaces (26) of the semiconductor layer sequence (2) and to surfaces of the growth substrate (1) exposed in step C), which sacrificial layer is designed to remove the growth substrate (1) by laser lift-off processes, E) depositing a metal layer (4) for forming a first connection contact on the side of the semiconductor layer sequence (2) facing away from the growth substrate (1), on the side surfaces (26) of the semiconductor layer sequence (2) and on the sacrificial layer (3), G) forming a second connection contact (8) through the active region (25), H) applying a permanent carrier (6) to the side of the semiconductor layer sequence (2) facing away from the growth substrate (1), and I) Detaching the growth substrate (1) and thereby exposing the metal layer (4), wherein the method according to step I) is free of lithography steps. [2] Method according to claim 1, wherein the metal layer (4) deposited in step E) forms a p-connection contact, a mirror coating on the side surfaces (26) of the semiconductor layer sequence (2) and a bond pad according to step I). [3] Method according to one of the preceding claims, comprising an additional step F) after step E): Planarization by filling areas lateral to the semiconductor layer sequence (2) with a dielectric material (5) up to at least the top side (21) of the semiconductor layer sequence (2). [4] The method of claim 3, wherein the sacrificial layer (3) comprises silicon nitride and the dielectric material (5) is silicon oxide. [5] Method according to one of the preceding claims, wherein the lateral extent of the semiconductor layer sequence (2) and the carrier (6) of the finished component is the same. [6] Method according to one of the preceding claims, wherein the metal layer (4) deposited in step E) is a p-type terminal contact with a thickness of at least 10 nm and covers the upper side (21) of the semiconductor layer sequence (2), wherein radiation emission from the active layer (25) takes place via the lower side (22) of the semiconductor layer sequence (2), wherein the metal layer (4) is arranged laterally and in a plane to the n-doped semiconductor region (23), wherein the plane is oriented perpendicular to the growth direction (1) of the semiconductor layer sequence (2). [7] Method according to one of the preceding claims, wherein the second terminal contact (8) formed in step G) is an n-terminal contact, wherein the n-terminal contact is arranged laterally and in a plane to the n-doped semiconductor region (23). [8] Method according to one of the preceding claims, wherein the second terminal contact (8) formed in step G) is an n-terminal contact, wherein the n-terminal contact and the metal layer (4) comprise aluminum. [9] Method according to one of the preceding claims, wherein the exposure of the metal layer (4) in step I) is carried out by wet-chemical removal of the sacrificial layer (3). [10] Method according to one of the preceding claims, wherein between steps D) and E) an additional step is carried out: depositing a gold layer (9) on a region of the sacrificial layer (3) arranged on the surface of the growth substrate (1). [11] Method according to one of the preceding claims, wherein the second terminal contact (8) formed in step G) is an n-terminal contact and comprises silver. [12] Method according to one of the preceding claims, wherein the metal layer (4) is formed of gold.

Images