Chip, preparation method thereof, radio frequency power amplifier and terminal

Abstract

This application provides a chip and its fabrication method, an RF power amplifier, and a terminal, relating to the field of semiconductor technology, which can ensure sufficient contact between the epitaxial layer and the source conductive layer. The chip includes a first transistor and a second transistor. The method includes: forming an epitaxial layer (11) and a source conductive layer (21) sequentially stacked on a substrate (10); the epitaxial layer includes a first via to form a first epitaxial layer (101) of the first transistor and a second epitaxial layer (102) of the second transistor. The source conductive layer includes a first source (211) of the first transistor and a second source (212) of the second transistor. The edge of the first source (211) is flush with the edge of the first epitaxial layer (101) near the first via, and the edge of the second source (212) is flush with the edge of the second epitaxial layer (102) near the first via. A first conductive layer (13) is formed in the first through hole; the first conductive layer (13) is in contact with the first source electrode (211) and the second source electrode (212); a second through hole is formed; a second conductive layer (14) is formed in the second through hole, the second conductive layer (14) is in contact with the first conductive layer (13) and is grounded.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its fabrication method, a radio frequency power amplifier, and a terminal. Background Technology

[0002] Radio frequency (RF) devices based on compound semiconductor materials are widely used in products such as base stations, radar, and consumer electronics. RF devices, such as transistors, generally include a source, a gate, and a drain, with the source being grounded via conductive leads.

[0003] However, the conductive leads have parasitic inductance. Since the source of the transistor is electrically connected to the conductive leads, the parasitic inductance of the source increases, which reduces the gain of the transistor.

[0004] Therefore, transistors commonly use a substrate back via a via to directly connect the source to ground, instead of bonding it to ground via conductive leads. This reduces parasitic parameters and improves transistor performance. However, since the substrate back via is generally designed directly below the source metal, introducing a substrate back via design inevitably increases the width of the source metal, thereby increasing the transistor chip area and raising the cost of RF devices. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a chip and its fabrication method, an RF power amplifier, and a terminal, which can prevent the source conductive layer from being mistakenly etched while reducing the chip's layout area, thus preventing the epitaxial layer from making sufficient contact with the source conductive layer.

[0006] In a first aspect, this application provides a method for fabricating a chip, the chip including a first transistor and a second transistor. The method includes: firstly, forming an epitaxial layer and a source conductive layer sequentially stacked on a substrate; the epitaxial layer includes a first via to form a first epitaxial layer of the first transistor and a second epitaxial layer of the second transistor. The source conductive layer includes a first source of the first transistor and a second source of the second transistor. The first source is disposed on the side of the first epitaxial layer away from the substrate, and the second source is disposed on the side of the second epitaxial layer away from the substrate. The edge of the first source is flush with the edge of the first epitaxial layer near the first via, and the edge of the second source is flush with the edge of the second epitaxial layer near the first via. Next, a first conductive layer is formed; the first conductive layer fills the first via and contacts the first and second sources respectively. Next, a second via is formed in the substrate, the second via at least partially overlapping the first via. Next, a second conductive layer is formed; the second conductive layer is located in the second via, contacts the first conductive layer, and is grounded.

[0007] The proposed solution employs a front-side photolithography process to form the epitaxial layer, meaning the semiconductor thin film is photolithographically etched along the direction from the source conductive layer to the semiconductor thin film. Furthermore, the photolithography precision of the front-side process can be less than 100nm, far exceeding that of the back-side process. Therefore, during the etching of the semiconductor thin film, photolithography deviations will not cause incorrect etching of the source conductive layer or over-etching of the first and second epitaxial layers, thus ensuring sufficient contact between the first epitaxial layer and the first source, as well as between the second epitaxial layer and the second source. When the first transistor is turned on, the first epitaxial layer effectively transmits current to the first source, and the first source then releases the current to ground through the first and second conductive layers. When the second transistor is turned on, the second epitaxial layer effectively transmits current to the second source, and the second source then releases the current to ground through the first and second conductive layers. Furthermore, compared to related technologies, the transistor of this application does not require the length of the first epitaxial layer protruding from the first source, nor the length of the second epitaxial layer protruding from the second source. Therefore, the layout area of ​​the first transistor, the second transistor, and even the chip can be reduced.

[0008] In one possible implementation, the step of forming an epitaxial layer and a source conductive layer sequentially stacked on a substrate specifically includes: first, forming a semiconductor thin film and a source conductive layer sequentially on the substrate; then, forming a first via in the semiconductor thin film to obtain the epitaxial layer.

[0009] In this case, the edge of the first source electrode is flush with the edge of the first epitaxial layer near the first via, and the edge of the second source electrode is flush with the edge of the second epitaxial layer near the first via. Alternatively, due to process limitations, there may be tolerances between the actual first epitaxial layer and the first source electrode, and between the second epitaxial layer and the second source electrode. The surface of the first epitaxial layer facing away from the substrate may also be flush with the edge of the first source electrode, and the surface of the second epitaxial layer facing away from the substrate may also be flush with the edge of the second source electrode. However, the surface of the first epitaxial layer facing the substrate may also protrude beyond the edge of the first source electrode, and the surface of the second epitaxial layer facing the substrate may also protrude beyond the edge of the second source electrode.

[0010] In another possible implementation, the step of forming a stacked epitaxial layer and a source conductive layer on a substrate specifically includes: first, forming a semiconductor thin film on the substrate; then, forming a first via in the semiconductor thin film to obtain an epitaxial layer; and then, forming a source conductive layer on the side of the epitaxial layer facing away from the substrate. Since the first and second sources are formed after the first and second epitaxial layers, the etching material used to etch the semiconductor thin film will not affect the patterns of the first and second sources.

[0011] In this case, the edge of the first source electrode is flush with the edge of the first epitaxial layer near the first via, and the edge of the second source electrode is flush with the edge of the second epitaxial layer near the first via. Alternatively, a portion of the first source electrode and a portion of the second source electrode may extend into the first via. Alternatively, due to process limitations, there may be tolerances between the actually formed first epitaxial layer and the first source electrode, and between the second epitaxial layer and the second source electrode. The surface of the first epitaxial layer facing away from the substrate may also be flush with the edge of the first source electrode, and the surface of the second epitaxial layer facing away from the substrate may also be flush with the edge of the second source electrode. However, the surface of the first epitaxial layer facing the substrate may also protrude beyond the edge of the first source electrode, and the surface of the second epitaxial layer facing the substrate may also protrude beyond the edge of the second source electrode.

[0012] In some possible implementations, the step of creating a first via in the semiconductor thin film to obtain the epitaxial layer in the two implementations described above specifically includes: firstly, forming a photoresist on the side of the semiconductor thin film away from the substrate; then, exposing the photoresist and developing it to obtain a photoresist pattern; and then, etching the semiconductor thin film along the direction from the epitaxial layer to the substrate to obtain the first epitaxial layer and the second epitaxial layer.

[0013] In some possible implementation methods, front-side photolithography can be used to etch semiconductor thin films. Compared with back-side photolithography, front-side photolithography is more precise, achieving an overlay accuracy of less than 100nm. Therefore, when using front-side photolithography to etch semiconductor thin films, the first and second sources will not be mistakenly etched due to photolithography deviations, and the first and second epitaxial layers will not be over-etched. This ensures that the first source and the first epitaxial layer are in full contact, and that the second source and the second epitaxial layer are in full contact.

[0014] In some possible implementations, although commonly used chlorine-based gases have an etching effect on the materials of the first epitaxial layer, the second epitaxial layer, and the materials of the first and second source electrodes, the chlorine-based gas will not come into contact with the first and second source electrodes due to the high overlay precision achieved by the front-side photolithography process used in this application. Therefore, the chlorine-based gas can also be used to etch the semiconductor thin film to obtain the first and second epitaxial layers.

[0015] In some possible implementations, the step of forming the second via specifically includes etching the substrate in a direction pointing from the substrate to the epitaxial layer to obtain the second via.

[0016] In some possible implementations, the first and second vias are positioned opposite each other. The edge of the first source electrode facing the second source electrode is flush with the edge of the first epitaxial layer facing the second epitaxial layer. In other words, the edge of the first source electrode is flush with the edge of the first epitaxial layer near the first via, and the edge of the second source electrode is flush with the edge of the second epitaxial layer near the first via, so that the second conductive layer contacts the first conductive layer. Furthermore, the length of the first via is the same as the length of the second via along the direction from the first source electrode to the second source electrode. This ensures sufficient contact between the second conductive layer to be formed and the first conductive layer.

[0017] In some possible implementations, the first via and the second via are positioned opposite each other, allowing the second conductive layer to contact the first conductive layer. Furthermore, along the direction from the first source to the second source, the length of the first via is less than the length of the second via. This ensures sufficient contact between the second conductive layer and the first conductive layer, and also allows for a reduction in the length of the first via while maintaining the length of the second via, thereby further reducing the layout area occupied by the first and second transistors.

[0018] In some possible implementations, the first and second vias are not directly opposite each other, but the second conductive layer is still in contact with the first conductive layer. Furthermore, along the direction from the first source to the second source, the length of the first via is less than the length of the second via. This allows for a reduction in the length of the first via while keeping the length of the second via constant, thereby further reducing the layout area occupied by the first and second transistors.

[0019] In some possible implementations, the first and second vias can be positioned directly opposite each other or not, with the second conductive layer in contact with the first conductive layer. Furthermore, the orthogonal projections of the source conductive layer and the first via onto the substrate lie within the area of ​​the second via. Along the direction from the first source to the second source, the total length from the edge of the first source away from the second source to the edge of the second source away from the first source is less than the length of the second via. This ensures sufficient contact between the second conductive layer and the first conductive layer. On the other hand, the first gate is located on the side of the epitaxial layer away from the substrate, and the first gate is located on the side of the first source away from the second source, while the second gate is located on the side of the second source away from the first source. Since the material of the second conductive layer can be a metallic material, and the thermal conductivity of a metallic material is superior to that of the substrate material, when the first and second gates generate heat, the heat on the first gate can be conducted to the second conductive layer through the first epitaxial layer, and vice versa, preventing excessively high temperatures of the first and second gates from affecting transistor performance.

[0020] Secondly, this application provides a chip that can be fabricated by the method described in the first aspect. The chip includes a substrate and a first transistor and a second transistor disposed on the substrate. The first transistor includes a first epitaxial layer and a first source electrode sequentially stacked on the substrate. The second transistor includes a second epitaxial layer and a second source electrode sequentially stacked on the substrate. A first via is provided between the first and second epitaxial layers. The edge of the first source electrode is flush with the edge of the first epitaxial layer adjacent to the first via, and the edge of the second source electrode is flush with the edge of the second epitaxial layer adjacent to the first via. The chip further includes a first conductive layer that contacts both the first and second source electrodes and fills the first via between the first and second epitaxial layers. The substrate includes a second via, and the chip further includes a second conductive layer that fills the second via. The second conductive layer contacts the first conductive layer and is grounded.

[0021] The solution in this application employs a front-side photolithography process to form the first and second epitaxial layers, i.e., photolithography is performed on the semiconductor thin film along the direction from the source conductive layer to the semiconductor thin film. Furthermore, the photolithography precision of the front-side process can be less than 100nm, far more precise than the back-side photolithography process. Therefore, during the etching of the semiconductor thin film, photolithography deviations will not cause mis-etching of the source conductive layer or over-etching of the epitaxial layer, thus ensuring sufficient contact between the epitaxial layer and the first and second sources. When the first transistor is turned on, the first epitaxial layer can effectively transfer current to the first source, and the first source then releases the current to ground through the first and second conductive layers. When the second transistor is turned on, the second epitaxial layer can effectively transfer current to the second source, and the second source then releases the current to ground through the first and second conductive layers. Moreover, compared to related technologies, the transistor in this application does not require a length L2 of epitaxial layer protruding beyond the source, thus reducing the layout area of ​​the first transistor, the second transistor, and even the chip.

[0022] In one possible implementation, the edge of the first source electrode is flush with the edge of the first epitaxial layer near the first via, and the edge of the second source electrode is flush with the edge of the second epitaxial layer near the first via. This structure can be implemented using the process described in the first aspect. Specifically, it can be achieved by first sequentially forming a semiconductor thin film and a source conductive layer on a substrate, and then forming the first via in the semiconductor thin film to obtain the epitaxial layer. Alternatively, it can be achieved by first forming a semiconductor thin film on the substrate, then forming the first via in the semiconductor thin film to obtain the epitaxial layer, and finally forming the source conductive layer on the side of the epitaxial layer away from the substrate.

[0023] In another possible implementation, the edge of the first source electrode facing the second source electrode protrudes beyond the edge of the first epitaxial layer facing the second epitaxial layer; the edge of the second source electrode facing the first source electrode protrudes beyond the edge of the second epitaxial layer facing the first epitaxial layer. Alternatively, a portion of the first source electrode and a portion of the second source electrode extend into the first via. This structure can be implemented using the process described in the first aspect. Specifically, it can be achieved by first forming a semiconductor thin film on a substrate, then creating a first via in the semiconductor thin film to obtain a first epitaxial layer and a second epitaxial layer, then forming a first source electrode on the side of the first epitaxial layer away from the substrate, and forming a second source electrode on the side of the second epitaxial layer away from the substrate.

[0024] Furthermore, due to manufacturing processes, there may be tolerances between the actual first epitaxial layer and the first source electrode, and between the second epitaxial layer and the second source electrode. The surface of the first epitaxial layer facing away from the substrate may also be flush with the edge of the first source electrode, and the surface of the second epitaxial layer facing away from the substrate may also be flush with the edge of the second source electrode. However, the surface of the first epitaxial layer facing the substrate may also protrude beyond the edge of the first source electrode, and the surface of the second epitaxial layer facing the substrate may also protrude beyond the edge of the second source electrode.

[0025] In some possible implementations, the first and second vias are positioned opposite each other. The edge of the first source electrode facing the second source electrode is flush with the edge of the first epitaxial layer facing the second epitaxial layer. In other words, the edge of the first source electrode is flush with the edge of the first epitaxial layer near the first via, and the edge of the second source electrode is flush with the edge of the second epitaxial layer near the first via, so that the second conductive layer contacts the first conductive layer. Furthermore, the length of the first via is the same as the length of the second via along the direction from the first source electrode to the second source electrode. This ensures sufficient contact between the second conductive layer to be formed and the first conductive layer.

[0026] In some possible implementations, the first via and the second via are positioned opposite each other, allowing the second conductive layer to contact the first conductive layer. Furthermore, along the direction from the first source to the second source, the length of the first via is less than the length of the second via. This ensures sufficient contact between the second conductive layer and the first conductive layer, and also allows for a reduction in the length of the first via while maintaining the length of the second via, thereby further reducing the layout area occupied by the first and second transistors.

[0027] In some possible implementations, the first and second vias are not directly opposite each other, but the second conductive layer is still in contact with the first conductive layer. Furthermore, along the direction from the first source to the second source, the length of the first via is less than the length of the second via. This allows for a reduction in the length of the first via while keeping the length of the second via constant, thereby further reducing the layout area occupied by the first and second transistors.

[0028] In some possible implementations, the first and second vias can be positioned directly opposite each other or not, with the second conductive layer in contact with the first conductive layer. Furthermore, the orthogonal projections of the source conductive layer and the first via onto the substrate lie within the area of ​​the second via. Along the direction from the first source to the second source, the total length from the edge of the first source away from the second source to the edge of the second source away from the first source is less than the length of the second via. This ensures sufficient contact between the second conductive layer and the first conductive layer. On the other hand, the first gate is located on the side of the epitaxial layer away from the substrate, and the first gate is located on the side of the first source away from the second source, while the second gate is located on the side of the second source away from the first source. Since the material of the second conductive layer can be a metallic material, and the thermal conductivity of a metallic material is superior to that of the substrate material, when the first and second gates generate heat, the heat on the first gate can be conducted to the second conductive layer through the first epitaxial layer, and vice versa, preventing excessively high temperatures of the first and second gates from affecting transistor performance.

[0029] Thirdly, this application provides a radio frequency (RF) power amplifier, which includes an RF input terminal, a ground terminal, a voltage terminal, an output terminal, and the chip described in the second aspect. The first gate of a first transistor and the second gate of a second transistor in the chip are coupled to the RF input terminal, the first source of the first transistor and the second source of the second transistor are coupled to the ground terminal, and the first drain of the first transistor and the second drain of the second transistor are coupled to the operating voltage terminal and the output terminal, respectively.

[0030] The implementation method of the third aspect corresponds to any implementation method of the second aspect. The technical effects corresponding to the implementation method of the third aspect can be found in the second aspect and the technical effects corresponding to any implementation method of the second aspect mentioned above, and will not be repeated here.

[0031] Fourthly, this application provides a terminal, which includes a transmitter, and the radio frequency transmitter includes the radio frequency power amplifier described in the third aspect.

[0032] The implementation method of the fourth aspect corresponds to any implementation method of the second aspect. The technical effects corresponding to the implementation method of the fourth aspect can be found in the second aspect and the technical effects corresponding to any implementation method of the second aspect mentioned above, and will not be repeated here. Attached Figure Description

[0033] Figure 1 This is a structural block diagram of the terminal provided in the embodiments of this application;

[0034] Figure 2 Circuit diagram of a power amplifier provided in an embodiment of this application;

[0035] Figure 3a A schematic diagram of a transistor structure provided for related technologies;

[0036] Figure 3b for Figure 3a A schematic diagram of the structure when the source of a transistor is mistakenly etched.

[0037] Figure 4a Another schematic diagram of a transistor structure provided for related technologies;

[0038] Figure 4b for Figure 3a A schematic diagram of the structure when etching errors occur in the substrate and epitaxial layer of a transistor;

[0039] Figure 5 A top view of a plurality of transistors provided in an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of a process for fabricating a transistor, provided as an embodiment of this application.

[0041] Figure 7a A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0042] Figure 7b A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0043] Figure 7c A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0044] Figure 7d A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0045] Figure 7e A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0046] Figure 7f A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0047] Figure 7g A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0048] Figure 7h A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0049] Figure 7i A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0050] Figure 7j A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0051] Figure 7k A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0052] Figure 7 is a schematic diagram of the transistor fabrication process provided in an embodiment of this application;

[0053] Figure 7m A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0054] Figure 7n A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0055] Figure 7o A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0056] Figure 8 This is a schematic diagram of another process for fabricating a transistor, provided in an embodiment of this application.

[0057] Figure 9a A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0058] Figure 9b A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0059] Figure 9c A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0060] Figure 9d A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0061] Figure 9e A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0062] Figure 9f A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0063] Figure 9g A schematic diagram of the transistor fabrication process provided in this application embodiment;

[0064] Figure 9h This is a schematic diagram illustrating the process of fabricating a transistor, as provided in an embodiment of this application.

[0065] Figure label:

[0066] 101-Baseband processing unit; 102-Transmitter; 1021-RF signal generation circuit; 1022-Power amplifier; 1023-Filter; 1024-Antenna; 10-Substrate; 11-Epiaxial layer; 101-First epitaxial layer; 102-Second epitaxial layer; 111-Semiconductor thin film; 12-Source; 13-First conductive layer; 14-Second conductive layer; 21-Source conductive layer; 211-First source; 212-Second source; 22-Drain; 221-First drain; 222-Second drain; 231-First gate; 232-Second gate; 33-Third photoresist pattern. Detailed Implementation

[0067] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0068] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0069] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0070] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0071] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0072] This application provides a terminal that can reduce the parasitic capacitance of the transistor source, increase the transistor gain, and save transistor layout area.

[0073] The specific structure and uses of the terminal provided in the embodiments of this application are described below.

[0074] Terminal 1 can also be a base station, computer, tablet computer, personal digital assistant (PDA), smart wearable device, smart home device, etc., and this application embodiment does not limit it.

[0075] Figure 1 The illustration shows an application scenario diagram of terminal 1 provided in an embodiment of this application. Terminal 1 can be a base station, which may include a baseband unit 101 and a transmitter 102. The transmitter 102 may include a radio frequency signal generation circuit 1021, a power amplifier 1022, a filter 1023, and an antenna 1024.

[0076] The baseband processing unit 101 is used to generate baseband digital signals.

[0077] The radio frequency signal generation circuit 1021 is used to process the baseband digital signal to obtain the radio frequency signal.

[0078] Power amplifier 1022 is used to amplify the power of radio frequency signals.

[0079] Filter 1023 is used to filter the amplified radio frequency signal to obtain the signal to be transmitted.

[0080] Antenna 1024 is used to transmit the signal to be transmitted.

[0081] Figure 2 A circuit diagram of the power amplifier 1022 described above is shown. The power amplifier 1022 includes a DC input terminal Vgate, an RF input terminal RF In, a voltage terminal VDD, a transistor, and an output terminal RF Out.

[0082] Taking an N-type transistor as an example and a sine wave as the radio frequency (RF) signal, the transistor's gate receives the DC signal input through the DC input terminal Vgate and the RF signal input through the RF input terminal RFIn. When the RF signal is positive, the transistor is turned on, and the voltage terminal VDD is grounded through the transistor; when the RF signal is negative, the transistor is turned off, the voltage terminal VDD is connected to the output terminal RFOut, and the amplified RF signal is output through the output terminal RFOut.

[0083] As mentioned in the background section, the source of a transistor can currently be grounded via a conductive lead. However, the conductive lead has parasitic inductance, which increases the parasitic inductance of the source and degrades the transistor's performance (reduced gain). Alternatively, it can be grounded via a source substrate via, but this requires reserving space in the chip design to accommodate the via, increasing the chip's layout area and cost.

[0084] Specifically, such as Figure 3a As shown, the transistor includes an epitaxial layer 11, a source 12, a first conductive layer 13, and a second conductive layer 14 disposed on a substrate 10. Vias can be formed in the substrate 10 and the epitaxial layer 11 along the direction from the substrate 10 to the epitaxial layer 11 using a back-side photolithography process. The second conductive layer 14 is disposed in the vias and contacts the first conductive layer 13. Thus, when the transistor is turned on, current flows along the direction from the epitaxial layer 11 to the source 12. The epitaxial layer 11 can transmit the current to the source 12, and the source 12 then transmits the current to the grounded second conductive layer 14 through the first conductive layer 13.

[0085] However, the relevant technical solution involves etching the pattern of the substrate and epitaxial layer 11 using a back-side photolithography process after forming the source electrode 12. On the one hand, such as Figure 3b As shown, the overlay accuracy of the back-side photolithography process is very low (contact photolithography machines are commonly used), and the overlay deviation is generally greater than or equal to 3μm. During the etching of the epitaxial layer 11, this may lead to over-etching of the epitaxial layer 11, resulting in insufficient contact between the epitaxial layer 11 and the source electrode 12. On the other hand, as... Figure 3b As shown, since chlorine-based gases are typically used to etch the epitaxial layer 11, and chlorine-based gases also have an etching effect on the source electrode 12, the source electrode 12 may also be etched during the etching of the epitaxial layer 11. This shortens the length L1 of the source electrode 12, further leading to insufficient and poor contact between the epitaxial layer 11 and the source electrode 12, resulting in abnormal ohmic contact. If the epitaxial layer 11 and the source electrode 12 do not make sufficient contact, the epitaxial layer 11 may be unable to transfer current to the source electrode 12.

[0086] It should be noted that the source 12 pattern is formed before the transistor gate is formed, and the source 12 undergoes high-temperature annealing. Therefore, the source 12 can achieve mutual capacitance with the epitaxial layer 11, forming an ohmic contact. The first conductive layer 13 is formed after the gate. To avoid the annealing process affecting the gate and causing problems with the gate's control over the epitaxial layer 11, no further annealing is performed after the pattern of the first conductive layer 13 is formed. Therefore, even if the first conductive layer 13 is in contact with the epitaxial layer 11, they cannot achieve mutual capacitance (forming an ohmic contact). In other words, the epitaxial layer 11 cannot directly transfer current to the first conductive layer 13.

[0087] like Figure 4a As shown, to address the issue of partial damage to the source 12, related technologies propose that the epitaxial layer 11 protrude beyond the source 12, with a protrusion length of L2. However, this approach increases the transistor layout area, especially since multiple transistors are typically connected in parallel on a chip, significantly increasing the chip area. Furthermore, as... Figure 4b As shown, due to the low overlay precision of the back-side photolithography process, there is still a situation where the vias of the epitaxial layer 11 are formed directly below the source electrode 12, and thus there is still a situation where the source electrode 12 is etched while the epitaxial layer 11 is being etched.

[0088] Based on the above problems, embodiments of this application provide a method for fabricating a chip, such as... Figure 5 As shown, multiple transistors can be disposed on the chip. Each transistor includes a source 211 / 212 and a drain 22. The drain 22 can be disposed between the source 211 and source 212 of two adjacent transistors, so that adjacent transistors can share the same drain 22. The multiple transistors may include a first transistor and a second transistor. The first transistor and the second transistor may be high electron mobility transistors (HEMTs) based on gallium nitride (GaN) or pseudomorphic high electron mobility transistors (PHEMTs) based on gallium arsenide (GaAs), etc.

[0089] This application allows for etching of the first epitaxial layer 101 of the first transistor and the second epitaxial layer 102 of the second transistor using a front-side photolithography process. In other words, the etching can be performed along the direction from the epitaxial layer 11 to the substrate 10, thus avoiding interference with the pattern of the source 12 due to the etching of the first and second epitaxial layers 101 and 102. This also saves the layout area occupied by the first and second transistors. Specifically, the transistor can be formed through the following two embodiments.

[0090] In one embodiment, such as Figure 6 As shown, the steps to form a transistor can be achieved through the following steps:

[0091] S110, such as Figure 7aAs shown, a semiconductor thin film 111 and a source conductive layer 21 are sequentially formed on a substrate 10. The source conductive layer 21 includes a first source 211 and a second source 212 disposed at intervals. Taking a chip including a first transistor and a second transistor as an example, the first source 211 can serve as the source 12 of the first transistor, and the second source 212 can serve as the source 12 of the second transistor.

[0092] In some possible implementations, the specific process of forming the semiconductor thin film 111 and the source conductive layer 21 may include: firstly, sequentially forming the semiconductor thin film 111, the first conductive film, and the first photoresist on the substrate 10; then, exposing the first photoresist, developing it to obtain a first photoresist pattern, and etching the first conductive film under the protection of the first photoresist pattern to obtain the pattern of the source conductive layer 21; removing the first photoresist pattern; and performing a high-temperature annealing treatment on the pattern of the source conductive layer 21 to obtain the source conductive layer 21. Of course, other methods can also be used to form the source conductive layer 21, and the embodiments of this application do not specifically limit this.

[0093] In some possible ways of implementation, such as Figure 7b As shown, while forming the source conductive layer 21, the first drain 221 of the first transistor and the second drain 222 of the second transistor can also be formed using the same semiconductor process, thus eliminating the need for additional processes to form the first drain 221 and the second drain 222, saving one mask. The first drain 221 and the second drain 222 are disposed on the same layer as the first source 211 and the second source 212. The first drain 221 is disposed on the side of the first source 211 facing away from the second source 212, and the second drain 222 is disposed on the side of the second source 212 facing away from the first source 211.

[0094] In some possible ways of implementation, such as Figure 7c As shown, after step S110 and before step S120, the transistor fabrication method may further include: forming a first gate 231 of the first transistor and a second gate 232 of the second transistor. Specifically, the process of forming the first gate 231 and the second gate 232 includes: sequentially forming a gate film and a second photoresist on the side of the semiconductor thin film 111 facing away from the substrate 10; exposing the second photoresist, developing it to obtain a second photoresist pattern, and etching the gate film under the protection of the second photoresist pattern to obtain the patterns of the first gate 231 and the second gate 232; removing the second photoresist pattern; and performing high-temperature annealing on the patterns of the first gate 231 and the second gate 232 to obtain the first gate 231 and the second gate 232. Of course, the steps of forming the first gate 231 and the second gate 232 can also be performed between steps S120 and S130, and this embodiment of the application does not limit this.

[0095] like Figure 7c As shown, the first gate 231 and the second gate 232 are disposed on the side of the semiconductor thin film 111 away from the substrate 10, and the first gate 231 is disposed on the side of the first source 211 away from the second source 212, and the second gate 232 is disposed on the side of the second source 212 away from the first source 211.

[0096] In some possible implementations, the first source 211 and the second source 212 can be a single layer or a stacked layer. The materials of the first source 211 and the second source 212 can include at least one of the following metals: titanium (Ti), titanium nitride (TiN), aluminum (Al), nickel (Ni), platinum (Pt), palladium (Pd), chromium (Cr), and gold (Au); the materials of the first source 211 and the second source 212 can also include oxide conductive materials such as indium tin oxide (ITO). Considering that the first source 211 and the second source 212 can be fabricated using the same semiconductor process, the number of layers in the first source 211 and the second source 212 can be the same, and the material of each layer can be the same.

[0097] S120, such as Figure 7d As shown, a first via is formed in the semiconductor thin film 111 to obtain an epitaxial layer 11 including a first epitaxial layer 101 and a second epitaxial layer 102. The first via is located between the first epitaxial layer 101 and the second epitaxial layer 102. Furthermore, a first source electrode 211 is disposed on the side of the first epitaxial layer 101 facing away from the substrate 10, and a second source electrode 212 is disposed on the side of the second epitaxial layer 102 facing away from the substrate 10.

[0098] In some possible ways of implementation, such as Figure 7d As shown, the specific process of forming a first via in the semiconductor thin film 111 to obtain the epitaxial layer 11 may include: forming a third photoresist on the side of the semiconductor thin film 111 away from the substrate 10; exposing the third photoresist, developing it to obtain a third photoresist pattern 33, and etching the semiconductor thin film 111 under the protection of the third photoresist pattern 33 to obtain the epitaxial layer 11 including the first epitaxial layer 101, the second epitaxial layer 102, and the first via.

[0099] Based on this, after step S120 and before step S130, the chip fabrication method may further include: stripping the third photoresist pattern 33.

[0100] In one possible implementation, although commonly used chlorine-based gases have an etching effect on both the material of the epitaxial layer 11 and the material of the source electrode 12, since this application uses a front-side photolithography process to etch the semiconductor thin film, the overlay accuracy of the front-side photolithography process is very high, much higher than that of the back-side photolithography process. Therefore, when using the photolithography method of this application to etch the semiconductor thin film 111 with chlorine-based gas, the chlorine-based gas will not come into contact with the first source electrode 121 and the second source electrode 122, and thus will not affect the pattern of the first source electrode 121 and the second source electrode 122. This results in the first epitaxial layer 101 failing to make sufficient contact with the first source electrode 121, and the second epitaxial layer 102 failing to make sufficient contact with the second source electrode 122.

[0101] Based on this, this application can use chlorine-based gas to etch the semiconductor thin film 111 along the direction from the source conductive layer 21 to the semiconductor thin film 111 to obtain an epitaxial layer 11 including a first epitaxial layer 101, a second epitaxial layer 102, and a first via. Of course, other etching materials can also be used to etch the semiconductor thin film 111, and this application embodiment does not limit this.

[0102] It should be noted here that, as Figure 7d As shown, the third photoresist pattern 33 can expose the portion of the semiconductor thin film 111 to be formed of the first via; it covers each exposed surface of the source conductive layer 21, as well as other portions of the semiconductor thin film 111 except for the first via to be formed, to prevent the source conductive layer 21 from being accidentally etched during the etching of the semiconductor thin film 111 (especially during the etching of the semiconductor thin film 111 using chlorine-based gas).

[0103] Based on this, since this application uses a front-side photolithography process to form the epitaxial layer 11, that is, photolithography is performed on the semiconductor thin film 111 along the direction from the source conductive layer 21 to the semiconductor thin film 111. Furthermore, the overlay accuracy of the front-side photolithography process can be less than 100 nm, far more precise than the overlay accuracy of the back-side photolithography process. Therefore, when etching the semiconductor thin film 111, the source conductive layer 21 will not be incorrectly etched due to photolithography process deviations, and the first epitaxial layer 101 and the second epitaxial layer 102 will not be over-etched. This ensures that the first epitaxial layer 101 is in full contact with the first source 211, and the second epitaxial layer 102 is in full contact with the second source 212. When the first transistor is turned on, the first epitaxial layer 101 can effectively transfer current to the first source 211, and release the current to ground through the first source 211; when the second transistor is turned on, the second epitaxial layer 102 can effectively transfer current to the second source 212, and release the current to ground through the second source 212.

[0104] Furthermore, in the first and second transistors formed through the above steps S110-S130, the positional relationship between the source conductive layer 21 and the epitaxial layer 11 may vary in the following ways:

[0105] like Figure 7e As shown, the edge of the first source electrode 211 facing the second source electrode 212 can be flush with the edge of the first via near the first source electrode 211; the edge of the second source electrode 212 facing the first source electrode 211 can be flush with the edge of the first via near the second source electrode 212. Alternatively, the edge of the first source electrode 211 is flush with the edge of the first epitaxial layer 101 near the first via, and the edge of the second source electrode 212 is flush with the edge of the second epitaxial layer 102 near the first via. Furthermore, along the direction from the first source electrode 211 to the second source electrode 212, the length L1' of the first source electrode 211 and the length L1'' of the second source electrode 212 are both equal to... Figure 4a The related technology shown has a source electrode 12 length L1. However, in the solution of this application, along the direction from the first source electrode 211 to the second source electrode 212, it is not necessary for the first epitaxial layer 101 to protrude from the first source electrode 211; similarly, along the direction from the second source electrode 212 to the first source electrode 211, it is not necessary for the second epitaxial layer 102 to protrude from the second source electrode 212. In other words, the length of the first epitaxial layer 101 protruding from the first source electrode 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source electrode 212 is 0. This reduces the layout area occupied by the first transistor and the second transistor, thereby reducing the overall chip layout area.

[0106] For example, along the direction from the first source 211 to the second source plate 212, the length L1` of the first source 211 and the length L1`` of the second source 212 are both 8μm; Figure 4a In the related technologies shown, the epitaxial layer 11 protrudes from the source 12 by a length L2 of 8 μm. Therefore, compared with the related technologies, the source 12 layout occupied by a first transistor and a second transistor can be reduced by 2*L2 = 16 μm, a reduction of 50%.

[0107] Or, such as Figure 7fAs shown, in the source conductive layer 21 and epitaxial layer 11 formed by the above process, along the direction from the first source 211 to the second source 212, the first epitaxial layer 101 protrudes from the first source 211, and the length of the protruding portion is L2'; along the direction from the second source 212 to the first source 211, the second epitaxial layer 102 protrudes from the second source 212, and the length of the protruding portion is L2'. However, since this application uses a front-side photolithography process to form the first epitaxial layer 101 and the second epitaxial layer 102, its overlay accuracy is much higher than that of the back-side photolithography process. Therefore, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 can also be much smaller than... Figure 4a In the related technology shown, the epitaxial layer 11 protrudes from the source 12 by a length of L2. This reduces the layout area occupied by the first and second transistors, thereby reducing the overall chip layout area.

[0108] For example, along the direction from the first source 211 to the second source 212, the length L1` of the first source 211 and the length L1`` of the second source 212 are both 8μm; Figure 4a In the related technologies shown, the length L2 of the epitaxial layer 11 protruding from the source 12 is 8 μm. In this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the second epitaxial layer 102 protruding from the second source 212 is both 1 μm. Therefore, compared to the related technologies, using the solution of this application, the source 12 layout occupied by one first transistor and one second transistor can be reduced by 2*(L2-L2') = 14 μm, a reduction of 44%.

[0109] Alternatively, due to manufacturing processes, there may be tolerances between the actually formed first epitaxial layer 101 and the first source 211, and between the second epitaxial layer 102 and the second source 212. Therefore, in some possible implementation scenarios, such as... Figure 7d As shown, the surface of the first epitaxial layer 101 facing away from the substrate 10 may be flush with the edge of the first source 211, and the surface of the second epitaxial layer 102 facing away from the substrate 10 may be flush with the edge of the second source 212. However, the surface of the first epitaxial layer 101 facing the substrate 10 may protrude beyond the edge of the first source 211, and the surface of the second epitaxial layer 102 facing the substrate 10 may protrude beyond the edge of the second source 212.

[0110] In some possible implementations, the first epitaxial layer 101 and the second epitaxial layer 102 may include a multilayer structure. If the first transistor and the second transistor are GaN-based HEMTs, the material of the multilayer structure may include AlxGayN, where 0≤x≤1, 0≤y≤1, and x+y=1. If the first transistor and the second transistor are GaAs-based PHEMTs, the material of the multilayer structure may include AlGaAs or high-purity GaAs. Considering that the first epitaxial layer 101 and the second epitaxial layer 102 can be fabricated using the same semiconductor process, the number of layers in the first epitaxial layer 101 and the second epitaxial layer 102 may be the same, and the material of each layer may be the same.

[0111] S130, such as Figure 7g-7i As shown, a first conductive layer 13 is formed. The first conductive layer 13 fills the first through-hole and contacts the first source 211 and the second source 212, respectively.

[0112] In some possible implementations, the specific process of forming the first conductive layer 13 may include: firstly, sequentially forming a second conductive film and a fourth photoresist on the side of the source conductive layer 21 away from the substrate 10; then, exposing the fourth photoresist, developing it to obtain a fourth photoresist pattern, and etching the second conductive film under the protection of the fourth photoresist pattern to obtain the first conductive layer 13; and finally removing the fourth photoresist pattern. Of course, other methods can also be used to form the source conductive layer 21, and this application embodiment does not specifically limit this.

[0113] In some possible implementations, the specific location of the first conductive layer 13 is not limited in the embodiments of this application, as long as the first conductive layer 13 fills the first through-hole and contacts the first source 211 and the second source 212 respectively. Optionally, such as Figure 7g As shown, the first conductive layer 13 fills the first via and completely covers the surface of the source conductive layer 21 facing away from the substrate 10. Alternatively, as... Figure 7h As shown, the first conductive layer 13 fills the first via and is disposed on the side of the source conductive layer 21 facing away from the substrate 10, and partially covers the surface of the source conductive layer 21 facing away from the substrate 10. Alternatively, as... Figure 7i As shown, the first conductive layer 13 fills only the first via and contacts the side of the first source 211 facing the second source 212 and the side of the second source 212 facing the first source 211, respectively. Compared to Figure 7h and Figure 7i The two schemes shown are Figure 7gIn the illustrated scheme, on the one hand, the first source 211 and the second source 212 can make sufficient contact with the first conductive layer 13; on the other hand, it can also avoid the first conductive layer 13 failing to make sufficient contact with the first source 211 and / or the second source 212 due to process errors.

[0114] In some possible implementations, the first conductive layer 13 can be a single layer or a stack of layers. The material of the first conductive layer 13 can be metals such as Ti, TiN, Al, Ni, Pt, Pd, Cr, Au, or oxide conductive materials such as ITO.

[0115] S140, such as Figure 7j As shown, a second via is formed in the substrate 10 along the direction from the substrate 10 to the epitaxial layer 11. The second via at least partially overlaps with the first via.

[0116] In some possible implementations, a back-side photolithography process can be used to etch the substrate 10 to obtain the second via. Taking the substrate 10 as an example, where the material is silicon carbide (SiC) or silicon (Si), a fluorine-based gas can be used to etch the substrate 10 to obtain the second via. Since the fluorine-based gas has high selectivity for etching the materials of the epitaxial layer 11, the first conductive layer 13, and the second conductive layer 14 to be formed, it can remain on the surface of the second via without affecting the subsequent step S150 to form the second conductive layer 14, nor will it affect the pattern of the already formed first epitaxial layer 101, second epitaxial layer 102, and first conductive layer 13, thus ensuring normal contact between the second conductive layer 14 and the first conductive layer 13.

[0117] In some possible implementations, the specific location of the second through-hole is not limited in the embodiments of this application, as long as it can be ensured that the second conductive layer 14 filled in the second through-hole can contact the first conductive layer 13. The location of the second through-hole is related to the second conductive layer 14 to be formed. The location of the second through-hole will be described in detail when the second conductive layer 14 is introduced in step S150.

[0118] S150, such as Figures 7k-7o As shown, a second conductive layer 14 is formed in the second via. The second conductive layer 14 is in contact with the first conductive layer 13 and is grounded. In this way, the current transmitted from the first epitaxial layer 101 to the first source 211 and the first conductive layer 13, and the current transmitted from the second epitaxial layer 102 to the second source 212 and the first conductive layer 13, can be transmitted to the second conductive layer 14 and released to ground.

[0119] In some possible ways of implementation, such as Figures 7k-7nAs shown, an electroplating process can be used to form a second conductive layer 14 in the second via. The thickness of the second conductive layer 14 is less than the depth of the second via in the direction from the substrate 10 to the epitaxial layer 11. The second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10. Furthermore, as... Figure 7o As shown, the second conductive layer 14 can also be filled throughout the second through hole.

[0120] In some possible implementations, the embodiments of this application do not limit the specific position of the second conductive layer 14 relative to the first conductive layer 13, as long as the two are in contact.

[0121] The first case, such as Figure 7k As shown, the first and second through holes are positioned opposite each other. The edge of the first source 211 facing the second source 212 is flush with the edge of the first epitaxial layer 101 facing the second epitaxial layer 102. In other words, the edge of the first source 211 is flush with the edge of the first epitaxial layer 101 near the first through hole, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 near the first through hole, so that the second conductive layer 14 contacts the first conductive layer 13. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first through hole is the same as the length L4 of the second through hole. This ensures that the second conductive layer 14 to be formed makes full contact with the first conductive layer 13.

[0122] The second scenario, such as Figure 7l As shown, the first and second vias are positioned opposite each other, allowing the second conductive layer 14 to contact the first conductive layer 13. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first via is less than the length L4 of the second via. This ensures sufficient contact between the second conductive layer 14 and the first conductive layer 13, and also allows for a reduction in the length L3 of the first via while keeping the length L4 of the second via constant, thereby further reducing the layout area occupied by the first and second transistors.

[0123] The third scenario, such as Figure 7m As shown, the first and second vias are not directly opposite each other, but the second conductive layer 14 and the first conductive layer 13 are still in contact. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first via is less than the length L4 of the second via. In this way, the length L3 of the first via can be reduced while keeping the length L4 of the second via constant, thereby further reducing the layout area occupied by the first and second transistors.

[0124] The fourth case, such as Figure 7n and 7oAs shown, the first and second vias can be directly opposite each other or not directly opposite each other, and the second conductive layer 14 is in contact with the first conductive layer 13. Furthermore, the orthogonal projections of the source conductive layer 21 and the first via on the substrate 10 are located within the area of ​​the second via. Along the direction from the first source 211 to the second source 212, the total length L5 from the edge of the first source 211 away from the edge of the second source 212 away from the edge of the second source 211 is less than the length L4 of the second via. In this way, on the one hand, the second conductive layer 14 to be formed can be in sufficient contact with the first conductive layer 13. On the other hand, as... Figure 5 and Figure 7n-7o As shown, the first gate 231 is disposed on the side of the epitaxial layer 11 away from the substrate 10, and the first gate 231 is located on the side of the first source 211 away from the second source 212, while the second gate 232 is located on the side of the second source 212 away from the first source 211. Since the material of the second conductive layer 14 can be a metallic material, and the thermal conductivity of a metallic material is better than that of the substrate 10 material, when the first gate 231 and the second gate 232 generate heat, the heat on the first gate 231 can be conducted to the second conductive layer 14 through the first epitaxial layer 101, and the heat on the second gate 232 can be conducted to the second conductive layer 14 through the second epitaxial layer 102 (the heat conduction path is as follows). Figure 7n and Figure 7o (As shown by the straight line with arrows in the middle), to prevent the transistor performance from being affected by excessively high temperatures of the first gate 231 and the second gate 232.

[0125] For example, such as Figure 7n As shown, the first via and the second via are positioned opposite each other. Along the direction from the first source 211 to the second source 212, the length L' of the first source 211 and the length L" of the second source 212 are both 8 μm. The length L3 of the first via is 8 μm, and the size L4 of the second via is 25 μm. The orthogonal projection of the source conductive layer 21 and the first via on the substrate 10 is located within the range of the second via, and the second via protrudes from the first source 211 and the second source 212 respectively. In this way, the heat of the gate 23 can be discharged through the second conductive layer 14 filled in the second via.

[0126] In the fourth case, the thickness of the second conductive layer 14 is less than the depth of the second via, and the second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10. Figure 7n The second conductive layer 14 fills the entire second through-hole. Figure 7o (This provides better thermal conductivity for gate 23.)

[0127] Furthermore, in the fourth case, the first through hole and the second through hole can be positioned directly opposite each other or not. Along the direction from the first source 211 to the second source 212, the length L3 of the first through hole can be equal to or less than the length L4 of the second through hole.

[0128] It should be noted that the first through hole and the second through hole are positioned opposite each other, which can also be understood as the center of the first through hole and the center of the second through hole coinciding.

[0129] Furthermore, all four of the aforementioned cases apply to GaN-based HEMTs. For GaAs-based PHEMTs, since the materials of the substrate 10 and the first epitaxial layer 101 and the second epitaxial layer 102 both include GaAs, the first epitaxial layer 101 and the second epitaxial layer 102 may be mistakenly etched when the substrate 10 is dry-etched using a back-side photolithography process. Therefore, along the direction from the first source 211 to the second source 212, the size L4 of the second via in the substrate 10 should be less than or equal to the length L3 of the first via.

[0130] In another embodiment, such as Figure 8 As shown, the steps to form the first transistor and the second transistor can be implemented through the following steps:

[0131] S210, such as Figure 9a As shown, a semiconductor thin film 111 is formed on the substrate 10.

[0132] S220, such as Figure 9b As shown, a first via is formed in the semiconductor thin film 111 to obtain an epitaxial layer 11 including a first epitaxial layer 101 and a second epitaxial layer 102.

[0133] In some possible implementations, the specific process of forming a first via in the semiconductor thin film 111 to obtain the epitaxial layer 11 may include: forming a fifth photoresist on the side of the semiconductor thin film 111 opposite to the substrate 10; exposing the fifth photoresist, developing it to obtain a fifth photoresist pattern, and etching the semiconductor thin film 111 under the protection of the fifth photoresist pattern to obtain the epitaxial layer 11 including the first epitaxial layer 101, the second epitaxial layer 102, and the first via. Before step S230, the fifth photoresist pattern may also be stripped off.

[0134] In one possible implementation, a chlorine-based gas can be used to etch the semiconductor thin film 111 along the direction from the semiconductor thin film 111 to the substrate 10 to obtain the first epitaxial layer 101 and the second epitaxial layer 102. Of course, other etching materials can also be used to etch the semiconductor thin film 111, and this application embodiment does not limit this.

[0135] In some possible implementations, since this application uses a front-side photolithography process to form the first epitaxial layer 101 and the second epitaxial layer 102, that is, photolithography is performed on the semiconductor thin film 111 along the direction from the source conductive layer 21 to the semiconductor thin film 111. Furthermore, the overlay accuracy of the front-side photolithography process can be less than 100 nm, far more precise than the overlay accuracy of the back-side photolithography process. Therefore, when etching the semiconductor thin film 111, the first epitaxial layer 101 and the second epitaxial layer 102 will not be over-etched due to photolithography process deviations. This ensures that the first epitaxial layer 101 is in full contact with the first source 211, and that the second epitaxial layer 102 is in full contact with the second source 212. When the first transistor is turned on, the first epitaxial layer 101 can effectively send current to the first source 211, and release the current to ground through the first source 211; when the second transistor is turned on, the second epitaxial layer 102 can effectively send current to the second source 212, and release the current to ground through the second source 212.

[0136] In some possible implementations, the first epitaxial layer 101 and the second epitaxial layer 102 may include a multilayer structure. If the first transistor and the second transistor are GaN-based HEMTs, the material of the multilayer structure may include AlxGayN, where 0≤x≤1, 0≤y≤1, and x+y=1. If the first transistor and the second transistor are GaAs-based PHEMTs, the material of the multilayer structure may include AlGaAs or high-purity GaAs. Considering that the first epitaxial layer 101 and the second epitaxial layer 102 can be fabricated using the same semiconductor process, the number of layers in the first epitaxial layer 101 and the second epitaxial layer 102 may be the same, and the material of each layer may be the same.

[0137] S230, such as Figure 9c and Figure 9d As shown, a source conductive layer 21 is formed on the side of the epitaxial layer 11 facing away from the substrate 10. Alternatively, a first source 211 is formed on the side of the first epitaxial layer 101 facing away from the substrate 10, and a second source 212 is formed on the side of the second epitaxial layer 102 facing away from the substrate 10. Taking a chip including a first transistor and a second transistor as an example, the first source 211 can serve as the source 12 of the first transistor, and the second source 212 can serve as the source 12 of the second transistor.

[0138] It should be noted that since the first source 211 and the second source 212 are formed after step S220, the etching material used to etch the semiconductor thin film 111 will not affect the patterns of the first source 211 and the second source 212.

[0139] In some possible implementations, the specific process of forming the source conductive layer 21 may include: firstly, forming a first conductive film and a first photoresist sequentially on the side of the first epitaxial layer 101 and the second epitaxial layer 102 away from the substrate 10; then, exposing the first photoresist, developing it to obtain a first photoresist pattern, and etching the first conductive film under the protection of the first photoresist pattern to obtain the pattern of the source conductive layer 21; removing the first photoresist pattern; and performing a high-temperature annealing treatment on the pattern of the source conductive layer 21 to obtain the first source 211 and the second source 212. Of course, other methods can also be used to form the first source 211 and the second source 212, and the embodiments of this application do not specifically limit this.

[0140] Among some possible implementation methods, refer to Figure 7b As shown, while forming the first source 211 and the second source 212, the first drain 221 of the first transistor and the second drain 222 of the second transistor can also be formed using the same semiconductor process, thus eliminating the need for additional processes to form the first drain 221 and the second drain 22, saving a mask step. The first drain 221 and the second drain 222 are disposed on the same layer as the first source 211 and the second source 212. The first drain 221 is disposed on the side of the first source 211 facing away from the second source 212, and the second drain 222 is disposed on the side of the second source 212 facing away from the first source 211.

[0141] In some possible implementations, the first source 211 and the second source 212 can be a single layer or a stacked layer. The materials of the first source 211 and the second source 212 can include at least one of metals such as Ti, TiN, Al, Ni, Pt, Pd, Cr, and Au; the materials of the first source 211 and the second source 212 can also include oxide conductive materials such as ITO. Considering that the first source 211 and the second source 212 can be fabricated using the same semiconductor process, the number of layers of the first source 211 and the second source 212 can be the same, and the material of each layer of both can be the same.

[0142] Among some possible implementation methods, refer to Figure 7cAs shown, after step S230 and before step S240, the transistor fabrication method may further include: forming a first gate 231 of the first transistor and a second gate 232 of the second transistor. Specifically, the specific process of forming the first gate 231 and the second gate 232 includes: sequentially forming a gate film and a second photoresist on the side of the semiconductor thin film 111 away from the substrate 10; exposing the second photoresist, developing it to obtain a second photoresist pattern, and etching the gate film under the protection of the second photoresist pattern to obtain the patterns of the first gate 231 and the second gate 232; removing the second photoresist pattern; and performing high-temperature annealing on the patterns of the first gate 231 and the second gate 232 to obtain the first gate 231 and the second gate 232.

[0143] In the first and second transistors formed through the above steps S210-S230, the positional relationship between the source conductive layer 21 and the epitaxial layer 11 may vary as follows:

[0144] refer to Figure 7e As shown, the edge of the first source electrode 211 facing the second source electrode 212 can be flush with the edge of the first via near the first source electrode 211; the edge of the second source electrode 212 facing the first source electrode 211 can be flush with the edge of the first via near the second source electrode 212. Alternatively, the edge of the first source electrode 211 is flush with the edge of the first epitaxial layer 101 near the first via, and the edge of the second source electrode 212 is flush with the edge of the second epitaxial layer 102 near the first via. Furthermore, along the direction from the first source electrode 211 to the second source electrode 212, the length L1' of the first source electrode 211 and the length L1'' of the second source electrode 212 are both equal to... Figure 4a The related technology shown has a source electrode 12 length L1. However, in the solution of this application, along the direction from the first source electrode 211 to the second source electrode 212, it is not necessary for the first epitaxial layer 101 to protrude from the first source electrode 211; similarly, along the direction from the second source electrode 212 to the first source electrode 211, it is not necessary for the second epitaxial layer 102 to protrude from the second source electrode 212. In other words, the length of the first epitaxial layer 101 protruding from the first source electrode 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source electrode 212 is 0. This reduces the layout area occupied by the first transistor and the second transistor, thereby reducing the overall chip layout area.

[0145] For example, along the direction from the first source 211 to the second source 212, the length L1` of the first source 211 and the length L1`` of the second source 212 are both 8μm; Figure 4aIn the related technologies shown, the epitaxial layer 11 protrudes from the source 12 by a length L2 of 8 μm. Therefore, compared with the related technologies, the source 12 layout occupied by a first transistor and a second transistor can be reduced by 2*L2 = 16 μm, a reduction of 50%.

[0146] Or, such as Figure 9d As shown, in the source conductive layer 21 and epitaxial layer 11 formed by the above process, the first source 211 protrudes from the first epitaxial layer 101 along the direction from the first source 211 to the second source 212; and the second source 212 protrudes from the second epitaxial layer 102 along the direction from the second source 212 to the first source 211. Alternatively, a portion of the first source 211 and a portion of the second source 212 extend into the first via. Furthermore, in the solution of this application, along the direction from the first source 211 to the second source 212, it is not necessary for the first epitaxial layer 101 to protrude from the first source 211; and along the direction from the second source 212 to the first source 211, it is not necessary for the second epitaxial layer 102 to protrude from the second source 212. Alternatively, the length of the first epitaxial layer 101 protruding from the first source 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source 212 is 0. This reduces the layout area occupied by the first and second transistors, thereby reducing the overall layout area of ​​the chip.

[0147] Or, such as Figure 9e As shown, in the source conductive layer 21 and epitaxial layer 11 formed by the above process, along the direction from the first source 211 to the second source 212, the first epitaxial layer 101 protrudes from the first source 211, and the length of the protruding portion is L2'; along the direction from the second source 212 to the first source 211, the second epitaxial layer 102 protrudes from the second source 212, and the length of the protruding portion is L2'. However, since this application uses a front-side photolithography process to form the epitaxial layer 11, its photolithography precision is much higher than the overlay precision of the back-side photolithography process. Therefore, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 can also be much smaller than... Figure 4a In the related technology shown, the epitaxial layer 11 protrudes from the source 12 by a length of L2. This reduces the layout area occupied by the first and second transistors, thereby reducing the overall chip layout area.

[0148] For example, along the direction from the first source 211 to the second source 212, the length L1` of the first source 211 and the length L1`` of the second source 212 are both 8μm; Figure 4aIn the related technologies shown, the length L2 of the epitaxial layer 11 protruding from the source 12 is 8 μm. However, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 are both 1 μm. Therefore, compared to the related technologies, using the solution of this application, the source 12 layout occupied by one first transistor and one second transistor can be reduced by 2*(L2-L2') = 14 μm, a reduction of 44%.

[0149] Alternatively, due to manufacturing processes, there may be tolerances between the actually formed first epitaxial layer 101 and the first source 211, and between the second epitaxial layer 102 and the second source 212. Therefore, in some possible implementation scenarios, such as... Figure 9c As shown, the surface of the first epitaxial layer 101 facing away from the substrate 10 may be flush with the edge of the first source 211, and the surface of the second epitaxial layer 102 facing away from the substrate 10 may be flush with the edge of the second source 212. However, the surface of the first epitaxial layer 101 facing the substrate 10 may protrude beyond the edge of the first source 211, and the surface of the second epitaxial layer 102 facing the substrate 10 may protrude beyond the edge of the second source 212.

[0150] S240, such as Figure 9f As shown, a first conductive layer 13 is formed. The first conductive layer 13 fills the first through-hole and contacts the first source 211 and the second source 212, respectively.

[0151] In some possible implementations, the specific process of forming the first conductive layer 13 may include: firstly, sequentially forming a second conductive film and a fourth photoresist on the side of the source conductive layer 21 away from the substrate 10; then, exposing the fourth photoresist, developing it to obtain a fourth photoresist pattern, and etching the second conductive film under the protection of the fourth photoresist pattern to obtain the first conductive layer 13; and finally removing the fourth photoresist pattern. Of course, other methods can also be used to form the source conductive layer 21, and this application embodiment does not specifically limit this.

[0152] In some possible implementations, the specific location of the first conductive layer 13 is not limited in the embodiments of this application, as long as the first conductive layer 13 fills the first through-hole and contacts the first source 211 and the second source 212 respectively. Optionally, refer to Figure 7f As shown, the first conductive layer 13 fills the first via and completely covers the surface of the source conductive layer 21 facing away from the substrate 10. Alternatively, refer to... Figure 7g As shown, the first conductive layer 13 fills the first via and is disposed on the side of the source conductive layer 21 facing away from the substrate 10, and partially covers the surface of the source conductive layer 21 facing away from the substrate 10. Alternatively, refer to... Figure 7hAs shown, the first conductive layer 13 fills only the first via and contacts the side of the first source 211 facing the second source 212 and the side of the second source 212 facing the first source 211, respectively. Compared to Figure 7g and Figure 7h The two schemes shown are Figure 7f In the illustrated scheme, on the one hand, the first source 211 and the second source 212 can make sufficient contact with the first conductive layer 13; on the other hand, it can also avoid the first conductive layer 13 failing to make sufficient contact with the first source 211 and / or the second source 212 due to process errors.

[0153] In some possible implementations, the first conductive layer 13 can be a single layer or a stack of layers. The material of the first conductive layer 13 can be metals such as Ti, TiN, Al, Ni, Pt, Pd, Cr, Au, or oxide conductive materials such as ITO.

[0154] S250, such as Figure 9g As shown, a second via is formed in the substrate 10 along the direction from the substrate 10 to the epitaxial layer 11. The second via at least partially overlaps with the first via.

[0155] In some possible implementations, a back-side photolithography process can be used to etch the substrate 10 to obtain the second via. Taking the substrate 10 as an example, which is made of SiC or Si, a fluorine-based gas can be used to etch the substrate 10 to obtain the second via. Since the fluorine-based gas has high selectivity for etching the materials of the epitaxial layer 11, the first conductive layer 13, and the second conductive layer 14 to be formed, it can remain on the surface of the second via without affecting the subsequent step S150 to form the second conductive layer 14, nor will it affect the pattern of the already formed first epitaxial layer 101, second epitaxial layer 102, and first conductive layer 13, thus ensuring normal contact between the second conductive layer 14 and the first conductive layer 13.

[0156] In some possible implementations, the specific location of the second through-hole is not limited in the embodiments of this application, as long as it can be ensured that the second conductive layer 14 filled in the second through-hole can contact the first conductive layer 13. The location of the second through-hole is related to the second conductive layer 14 to be formed. The location of the second through-hole will be described in detail when the second conductive layer 14 is introduced in step S150.

[0157] S260, such as Figure 9hAs shown, a second conductive layer 14 is formed in the second via. The second conductive layer 14 is in contact with the first conductive layer 13 and is grounded. In this way, the current transmitted from the first epitaxial layer 101 to the first source 211 and the first conductive layer 13, and the current transmitted from the second epitaxial layer 102 to the second source 212 and the first conductive layer 13, can be transmitted to the second conductive layer 14 and released to ground.

[0158] Among some possible implementation methods, refer to Figures 7l-7n As shown, an electroplating process can be used to form a second conductive layer 14 in the second via. The thickness of the second conductive layer 14 is less than the depth of the second via in the direction from the substrate 10 to the epitaxial layer 11. The second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10. Furthermore, refer to... Figure 7o As shown, the second conductive layer 14 can also be filled throughout the second through hole.

[0159] In some possible implementations, the embodiments of this application do not limit the specific position of the second conductive layer 14 relative to the first conductive layer 13, as long as the two are in contact.

[0160] The first scenario, see reference. Figure 7k As shown, the first and second through holes are positioned opposite each other. The edge of the first source 211 facing the second source 212 is flush with the edge of the first epitaxial layer 101 facing the second epitaxial layer 102. In other words, the edge of the first source 211 is flush with the edge of the first epitaxial layer 101 near the first through hole, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 near the first through hole, so that the second conductive layer 14 contacts the first conductive layer 13. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first through hole is the same as the length L4 of the second through hole. This ensures that the second conductive layer 14 to be formed makes full contact with the first conductive layer 13.

[0161] The second scenario, see reference. Figure 7l As shown, the first and second vias are positioned opposite each other, allowing the second conductive layer 14 to contact the first conductive layer 13. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first via is less than the length L4 of the second via. This ensures sufficient contact between the second conductive layer 14 and the first conductive layer 13, and also allows for a reduction in the length L3 of the first via while keeping the length L4 of the second via constant, thereby further reducing the layout area occupied by the first and second transistors.

[0162] The third scenario, see reference. Figure 7mAs shown, the first and second vias are not directly opposite each other, but the second conductive layer 14 and the first conductive layer 13 are still in contact. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first via is less than the length L4 of the second via. In this way, the length L3 of the first via can be reduced while keeping the length L4 of the second via constant, thereby further reducing the layout area occupied by the first and second transistors.

[0163] The fourth scenario, see reference. Figure 7n and 7o As shown, the first and second vias can be directly opposite each other or not directly opposite each other, and the second conductive layer 14 is in contact with the first conductive layer 13. Furthermore, the orthogonal projections of the source conductive layer 21 and the first via onto the substrate 10 lie within the range of the second via. Along the direction from the first source 211 to the second source 212, the total length L5 from the edge of the first source 211 away from the edge of the second source 212 away from the edge of the second source 212 is less than the length L4 of the second via. In this way, on the one hand, the second conductive layer 14 to be formed can be in sufficient contact with the first conductive layer 13. On the other hand, as... Figure 5 and Figure 7n-7o As shown, the first gate 231 is disposed on the side of the epitaxial layer 11 away from the substrate 10, and the first gate 231 is located on the side of the first source 211 away from the second source 212, while the second gate 232 is located on the side of the second source 212 away from the first source 211. Since the material of the second conductive layer 14 can be a metallic material, and the thermal conductivity of a metallic material is better than that of the substrate 10 material, when the first gate 231 and the second gate 232 generate heat, the heat on the first gate 231 can be conducted to the second conductive layer 14 through the first epitaxial layer 101, and the heat on the second gate 232 can be conducted to the second conductive layer 14 through the second epitaxial layer 102 (the heat conduction path is as follows). Figure 7n and Figure 7o (As shown by the straight line with arrows in the middle), to prevent the transistor performance from being affected by excessively high temperatures of the first gate 231 and the second gate 232.

[0164] Example, reference Figure 7n As shown, the first via and the second via are positioned opposite each other. Along the direction from the first source 211 to the second source 212, the length L' of the first source 211 and the length L'' of the second source 212 are both 8μm. The length L3 of the first via is 8μm, and the size L4 of the second via is 25μm. The orthogonal projection of the source conductive layer 21 and the first via on the substrate 10 is located within the range of the second via, and the second via protrudes from the first source 211 and the second source 212 respectively. In this way, the heat of the gate 23 can be discharged through the second conductive layer 14 filled in the second via.

[0165] In the fourth case, the thickness of the second conductive layer 14 is less than the depth of the second via, and the second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10. Figure 7n The second conductive layer 14 fills the entire second through-hole. Figure 7o (This provides better thermal conductivity for gate 23.)

[0166] Furthermore, in the fourth case, the first through hole and the second through hole can be positioned directly opposite each other or not. Along the direction from the first source 211 to the second source 212, the length L3 of the first through hole can be equal to or less than the length L4 of the second through hole.

[0167] Furthermore, all four of the aforementioned cases apply to GaN-based HEMTs. For GaAs-based PHEMTs, since the materials of the substrate 10 and the first epitaxial layer 101 and the second epitaxial layer 102 both include GaAs, the first epitaxial layer 101 and the second epitaxial layer 102 may be mistakenly etched when the substrate 10 is dry-etched using a back-side photolithography process. Therefore, along the direction from the first source 211 to the second source 212, the size L4 of the second via in the substrate 10 should be less than or equal to the length L3 of the first via.

[0168] In another embodiment, this application also provides a chip, such as... Figure 5 As shown, the chip includes a substrate 10 and a first transistor and a second transistor disposed on the substrate 10. Figure 7j and Figure 9h As shown, the first transistor includes a first epitaxial layer and a first source 211 stacked sequentially, and the second transistor includes a second epitaxial layer and a second source 212 stacked sequentially. The first epitaxial layer is disposed between the substrate 10 and the first source 211, and the second epitaxial layer is disposed between the substrate 10 and the second source 212. A first via is formed between the first epitaxial layer 101 and the second epitaxial layer 102. The edge of the first source 211 is flush with the edge of the first epitaxial layer 101 near the first via, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 near the first via.

[0169] Based on this, the chip may further include a first conductive layer 13 and a second conductive layer 14. The first conductive layer 13 is in contact with the first source 211 and the second source 212, respectively, and fills the first via between the first epitaxial layer and the second epitaxial layer. The substrate 10 includes a second via, and the second conductive layer 14 is filled in the second via. The second conductive layer 14 is in contact with the first conductive layer 3 and is grounded.

[0170] It should be noted that the chip can be prepared by the chip preparation method provided in any of the foregoing embodiments.

[0171] In some possible implementations, the first source 211 and the second source 212 can be a single layer or a stacked layer. The materials of the first source 211 and the second source 212 can include at least one of metals such as Ti, TiN, Al, Ni, Pt, Pd, Cr, and Au, or oxide conductive materials such as ITO. If the first source 211 and the second source 212 are fabricated using the chip fabrication method described in the foregoing embodiments, the first source 211 and the second source 212 can be fabricated using the same semiconductor process, the number of layers of the first source 211 and the second source 212 can be the same, and the material of each layer of both can be the same.

[0172] In some possible implementations, since the first and second epitaxial layers, like the first and second sources 211 and 212, are all obtained through front-side photolithography, the overlay accuracy of front-side photolithography can be less than 100 nm, far exceeding that of back-side photolithography. Therefore, during the etching of the semiconductor thin film 111, photolithography deviations will not cause mis-etching of the source conductive layer 21 or over-etching of the first and second epitaxial layers 101 and 102. This ensures sufficient contact between the first epitaxial layer 101 and the first source 211, and between the second epitaxial layer 102 and the second source 212. When the first transistor is turned on, the first epitaxial layer 101 can effectively transfer current to the first source 211, and release the current to ground through the first source 211; when the second transistor is turned on, the second epitaxial layer 102 can effectively transfer current to the second source 212, and release the current to ground through the second source 212.

[0173] Furthermore, in the first and second transistors formed by the above method, the positional relationship between the source conductive layer 21 and the epitaxial layer 11 may vary in the following ways:

[0174] like Figure 7e As shown, the edge of the first source electrode 211 facing the second source electrode 212 can be flush with the edge of the first via near the first source electrode 211; the edge of the second source electrode 212 facing the first source electrode 211 can be flush with the edge of the first via near the second source electrode 212. Alternatively, the edge of the first source electrode 211 is flush with the edge of the first epitaxial layer 101 near the first via, and the edge of the second source electrode 212 is flush with the edge of the second epitaxial layer 102 near the first via. Furthermore, along the direction from the first source electrode 211 to the second source electrode 212, the length L1' of the first source electrode 211 and the length L1'' of the second source electrode 212 are both equal to... Figure 4aThe related technology shown has a source electrode 12 length L1. However, in the solution of this application, along the direction from the first source electrode 211 to the second source electrode 212, it is not necessary for the first epitaxial layer 101 to protrude from the first source electrode 211; similarly, along the direction from the second source electrode 212 to the first source electrode 211, it is not necessary for the second epitaxial layer 102 to protrude from the second source electrode 212. In other words, the length of the first epitaxial layer 101 protruding from the first source electrode 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source electrode 212 is 0. This reduces the layout area occupied by the first transistor and the second transistor, thereby reducing the overall chip layout area.

[0175] For example, along the direction from the first source 211 to the second source 212, the length L1` of the first source 211 and the length L1`` of the second source 212 are both 8μm; Figure 4a In the related technologies shown, the first epitaxial layer 101 protrudes from the first source 211 by a length L2 of 8 μm, and the second epitaxial layer 102 protrudes from the second source 212 by a length L2 of 8 μm. Therefore, compared with the related technologies, using the solution of this application, the source 12 layout occupied by one first transistor and one second transistor can be reduced by 2*L2 = 16 μm, a reduction of 50%.

[0176] Or, such as Figure 7f As shown, in the source conductive layer 21, the first epitaxial layer 101, and the second epitaxial layer 102 formed by the above process, the first epitaxial layer 101 protrudes from the first source 211 along the direction from the first source 211 to the second source 212, and the length of the protruding portion is L2'; the second epitaxial layer 102 protrudes from the second source 212 along the direction from the second source 212 to the first source 211, and the length of the protruding portion is L2'. However, since this application uses a front-side photolithography process to form the first epitaxial layer 101 and the second epitaxial layer 102, its overlay accuracy is much higher than that of the back-side photolithography process. Therefore, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 can also be much smaller than... Figure 4a In the related technology shown, the epitaxial layer 11 protrudes from the source 12 by a length of L2. This reduces the layout area occupied by the first and second transistors, thereby reducing the overall chip layout area.

[0177] For example, along the direction from the first source 211 to the second source 212, the length L1` of the first source 211 and the length L1`` of the second source 212 are both 8μm; Figure 4aIn the related technologies shown, the length L2 of the first epitaxial layer 101 protruding from the first source 211 and the length L2 of the second epitaxial layer 102 protruding from the second source 212 are both 8 μm. However, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 are both 1 μm. Therefore, compared to the related technologies, using the solution of this application, the source 12 layout occupied by one first transistor and one second transistor can be reduced by 2*(L2-L2') = 14 μm, a reduction of 44%.

[0178] Or, such as Figure 9d As shown, in the source conductive layer 21 and epitaxial layer 11 formed by the above process, the first source 211 protrudes from the first epitaxial layer 101 along the direction from the first source 211 to the second source 212; and the second source 212 protrudes from the second epitaxial layer 102 along the direction from the second source 212 to the first source 211. Furthermore, in the solution of this application, along the direction from the first source 211 to the second source 212, it is not necessary for the first epitaxial layer 101 to protrude from the first source 211; and along the direction from the second source 212 to the first source 211, it is not necessary for the second epitaxial layer 102 to protrude from the second source 212. In other words, the length of the first epitaxial layer 101 protruding from the first source 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source 212 is 0. This reduces the layout area occupied by the first transistor and the second transistor, thereby reducing the overall chip layout area.

[0179] Alternatively, due to manufacturing processes, there may be tolerances between the actually formed first epitaxial layer 101 and the first source 211, and between the second epitaxial layer 102 and the second source 212. Therefore, in some possible implementation scenarios, such as... Figure 7d As shown, the surface of the first epitaxial layer 101 facing away from the substrate 10 may be flush with the edge of the first source 211, and the surface of the second epitaxial layer 102 facing away from the substrate 10 may be flush with the edge of the second source 212. However, the surface of the first epitaxial layer 101 facing the substrate 10 may protrude beyond the edge of the first source 211, and the surface of the second epitaxial layer 102 facing the substrate 10 may protrude beyond the edge of the second source 212.

[0180] In some possible implementations, the first epitaxial layer 101 and the second epitaxial layer 102 may comprise a multilayer structure. If the first transistor and the second transistor are GaN-based HEMTs, the material of the multilayer structure may include Al. x Ga yN, where 0≤x≤1, 0≤y≤1, x+y=1; if the first transistor and the second transistor are GaAs-based PHEMTs, the material of the multilayer structure can include AlGaAs or high-purity GaAs. Considering that the first epitaxial layer 101 and the second epitaxial layer 102 can be prepared by the same semiconductor process, the number of layers of the first epitaxial layer 101 and the second epitaxial layer 102 can be the same, and the material of each layer is the same.

[0181] In some possible implementations, the specific location of the first conductive layer 13 is not limited in the embodiments of this application, as long as the first conductive layer 13 fills the first through-hole and contacts the first source 211 and the second source 212 respectively. Optionally, such as Figure 7g As shown, the first conductive layer 13 fills the first via and completely covers the surface of the source conductive layer 21 facing away from the substrate 10. Alternatively, as... Figure 7h As shown, the first conductive layer 13 fills the first via and is disposed on the side of the source conductive layer 21 facing away from the substrate 10, and partially covers the surface of the source conductive layer 21 facing away from the substrate 10. Alternatively, as... Figure 7i As shown, the first conductive layer 13 fills only the first via and contacts the side of the first source 211 facing the second source 212 and the side of the second source 212 facing the first source 211, respectively. Compared to Figure 7h and Figure 7i The two schemes shown are Figure 7g In the illustrated scheme, on the one hand, the first source 211 and the second source 212 can make full contact with the first conductive layer 13; on the other hand, it can also avoid the first conductive layer 13 failing to make contact with the first source 211 and / or the second source 212 due to process errors.

[0182] In some possible implementations, the first conductive layer 13 can be a single layer or a stack of layers. The material of the first conductive layer 13 can be metals such as Ti, TiN, Al, Ni, Pt, Pd, Cr, Au, or oxide conductive materials such as ITO.

[0183] In some possible implementations, the specific location of the second through hole is not limited in the embodiments of this application, as long as it can be ensured that the second conductive layer 14 filled in the second through hole can contact the first conductive layer 13.

[0184] In some possible implementations, the embodiments of this application do not limit the specific position of the second conductive layer 14 relative to the first conductive layer 13, as long as the two are in contact.

[0185] The first case, such as Figure 7kAs shown, the first and second through holes are positioned opposite each other. The edge of the first source 211 facing the second source 212 is flush with the edge of the first epitaxial layer 101 facing the second epitaxial layer 102. In other words, the edge of the first source 211 is flush with the edge of the first epitaxial layer 101 near the first through hole, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 near the first through hole, so that the second conductive layer 14 contacts the first conductive layer 13. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first through hole is the same as the length L4 of the second through hole. This ensures that the second conductive layer 14 to be formed makes full contact with the first conductive layer 13.

[0186] The second scenario, such as Figure 7l As shown, the first and second vias are positioned opposite each other, allowing the second conductive layer 14 to contact the first conductive layer 13. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first via is less than the length L4 of the second via. This ensures sufficient contact between the second conductive layer 14 and the first conductive layer 13, and also allows for a reduction in the length L3 of the first via while keeping the length L4 of the second via constant, thereby further reducing the layout area occupied by the first and second transistors.

[0187] The third scenario, such as Figure 7m As shown, the first and second vias are not directly opposite each other, but the second conductive layer 14 and the first conductive layer 13 are still in contact. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first via is less than the length L4 of the second via. In this way, the length L3 of the first via can be reduced while keeping the length L4 of the second via constant, thereby further reducing the layout area occupied by the first and second transistors.

[0188] The fourth case, such as Figure 7n As shown in Figure 7, the first and second vias can be directly opposite each other or not directly opposite each other, and the second conductive layer 14 is in contact with the first conductive layer 13. Furthermore, the orthogonal projections of the source conductive layer 21 and the first via on the substrate 10 lie within the range of the second via. Along the direction from the first source 211 to the second source 212, the total length L5 from the edge of the first source 211 away from the edge of the second source 212 away from the edge of the second source 211 is less than the length L4 of the second via. In this way, on the one hand, the second conductive layer 14 to be formed can be in sufficient contact with the first conductive layer 13. On the other hand, as... Figure 5 and Figure 7n-7oAs shown, the first gate 231 is disposed on the side of the epitaxial layer 11 away from the substrate 10, and the first gate 231 is located on the side of the first source 211 away from the second source 212, while the second gate 232 is located on the side of the second source 212 away from the first source 211. Since the material of the second conductive layer 14 can be a metallic material, and the thermal conductivity of a metallic material is better than that of the substrate 10 material, when the first gate 231 and the second gate 232 generate heat, the heat on the first gate 231 can be conducted to the second conductive layer 14 through the first epitaxial layer 101, and the heat on the second gate 232 can be conducted to the second conductive layer 14 through the second epitaxial layer 102 (the heat conduction path is as follows). Figure 7n and Figure 7o (As shown by the straight line with arrows in the middle), to prevent the transistor performance from being affected by excessively high temperatures of the first gate 231 and the second gate 232.

[0189] For example, such as Figure 7n As shown, the first via and the second via are positioned opposite each other. Along the direction from the first source 211 to the second source 212, the length L' of the first source 211 and the length L" of the second source 212 are both 8 μm. The length L3 of the first via is 8 μm, and the size L4 of the second via is 25 μm. The orthogonal projection of the source conductive layer 21 and the first via on the substrate 10 is located within the range of the second via, and the second via protrudes from the first source 211 and the second source 212 respectively. In this way, the heat of the gate 23 can be discharged through the second conductive layer 14 filled in the second via.

[0190] In the fourth case, the thickness of the second conductive layer 14 is less than the depth of the second via, and the second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10. Figure 7n The second conductive layer 14 fills the entire second through-hole. Figure 7o (This provides better thermal conductivity for gate 23.)

[0191] Furthermore, in the fourth case, the first through hole and the second through hole can be positioned directly opposite each other or not. Also, along the direction from the first source 211 to the second source 212, the length L3 of the first through hole can be equal to or less than the length L4 of the second through hole.

[0192] Furthermore, all four of the aforementioned cases apply to GaN-based HEMTs. For GaAs-based PHEMTs, since the materials of the substrate 10 and the first epitaxial layer 101 and the second epitaxial layer 102 both include GaAs, the first epitaxial layer 101 and the second epitaxial layer 102 may be mistakenly etched when the substrate 10 is dry-etched using a back-side photolithography process. Therefore, along the direction from the first source 211 to the second source 212, the size L4 of the second via in the substrate 10 should be less than or equal to the length L3 of the first via.

[0193] Furthermore, other explanations and beneficial effects of the embodiments of this application are the same as those of the foregoing two embodiments, and will not be repeated here.

[0194] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for fabricating a chip, characterized in that, The chip includes a first transistor and a second transistor, and the method for fabricating the chip includes: An epitaxial layer and a source conductive layer are sequentially stacked on a substrate; the epitaxial layer includes a first via to form a first epitaxial layer of the first transistor and a second epitaxial layer of the second transistor; the source conductive layer includes a first source of the first transistor and a second source of the second transistor, the first source being disposed on the side of the first epitaxial layer away from the substrate, and the second source being disposed on the side of the second epitaxial layer away from the substrate; the edge of the first source is flush with the edge of the first epitaxial layer near the first via, and the edge of the second source is flush with the edge of the second epitaxial layer near the first via; A first conductive layer is formed; the first conductive layer at least fills the first via and contacts the first source electrode and the second source electrode respectively; A second through-hole is formed in the substrate; the second through-hole at least partially overlaps with the first through-hole. A second conductive layer is formed; the second conductive layer is located in the second through hole, and the second conductive layer is in contact with the first conductive layer and grounded.

2. The chip fabrication method according to claim 1, characterized in that, The process of forming an epitaxial layer and a source conductive layer sequentially stacked on a substrate includes: A semiconductor thin film and the source conductive layer are sequentially formed on the substrate; The first through-hole is formed in the semiconductor thin film to obtain the epitaxial layer.

3. The chip fabrication method according to claim 1, characterized in that, The process of forming an epitaxial layer and a source conductive layer sequentially stacked on a substrate includes: A semiconductor thin film is formed on the substrate; The first through-hole is formed in the semiconductor thin film to obtain the epitaxial layer; The source conductive layer is formed on the side of the epitaxial layer opposite to the substrate.

4. The method for fabricating a chip according to claim 2 or 3, characterized in that, The step of forming the first through-hole in the semiconductor thin film to obtain the epitaxial layer includes: A photoresist is formed on the side of the semiconductor thin film facing away from the substrate; The photoresist is exposed and developed to obtain a photoresist pattern. The semiconductor thin film is etched along the direction from the epitaxial layer to the substrate to obtain the epitaxial layer.

5. The method for fabricating a chip according to claim 4, characterized in that, The overlay precision for etching the semiconductor thin film is less than 100 nm.

6. The method for fabricating a chip according to claim 5, characterized in that, The etching of the semiconductor thin film to obtain the epitaxial layer includes: The semiconductor thin film is etched using a chlorine-based gas to obtain the epitaxial layer.

7. The method for fabricating a chip according to any one of claims 1-6, characterized in that, The process of forming a second through-hole in the substrate includes: The substrate is etched along the direction from the substrate to the epitaxial layer to obtain the second via.

8. The method for fabricating a chip according to any one of claims 1-7, characterized in that, Along the direction from the first source electrode to the second source electrode, the size of the first through hole is smaller than the size of the second through hole.

9. The method for fabricating a chip according to claim 8, characterized in that, The orthographic projection of the source conductive layer and the first via on the substrate is located within the range of the second via, and along the direction from the first source to the second source, the total length from the edge of the first source away from the second source to the edge of the second source away from the first source is less than the size of the second via. Before forming the second conductive layer, the method for fabricating the transistor further includes: A first gate of a first transistor and a second gate of a second transistor are formed on the side of the epitaxial layer opposite to the substrate; The first gate is located on the side of the first source opposite to the second source, and the second gate is located on the side of the second source opposite to the first source.

10. The method for fabricating a chip according to any one of claims 1-7, characterized in that, Along the direction from the first source electrode to the second source electrode, the size of the first via is greater than or equal to the size of the second via.

11. The method for fabricating a chip according to any one of claims 8-10, characterized in that, The center of the first through hole coincides with the center of the second through hole.

12. A chip, characterized in that, Includes a substrate and a first transistor and a second transistor disposed on the substrate; The first transistor includes a first epitaxial layer and a first source electrode stacked sequentially on the substrate; the second transistor includes a second epitaxial layer and a second source electrode stacked sequentially on the substrate; a first via is provided between the first epitaxial layer and the second epitaxial layer; the edge of the first source electrode is flush with the edge of the first epitaxial layer near the first via, and the edge of the second source electrode is flush with the edge of the second epitaxial layer near the first via; the chip further includes a first conductive layer, which contacts the first source electrode and the second source electrode respectively, and fills the first via. The substrate includes a second via, and the chip further includes a second conductive layer; the second conductive layer fills the second via, and the second conductive layer is in contact with the first conductive layer and grounded.

13. The chip according to claim 12, characterized in that, Along the direction from the first source electrode to the second source electrode, the size of the first through hole is smaller than the size of the second through hole.

14. The chip according to claim 13, characterized in that, The first transistor further includes a first gate, and the second transistor further includes a second gate; the first gate is disposed on the side of the first epitaxial layer away from the substrate, and is located on the side of the first source away from the second source; the second gate is disposed on the side of the second epitaxial layer away from the substrate, and is located on the side of the second source away from the first source; The orthographic projections of the first source electrode, the first via, and the second source electrode onto the substrate are located within the range of the second via electrode, and along the direction from the first source electrode to the second source electrode, the total length from the edge of the first source electrode away from the second source electrode to the edge of the second source electrode away from the first source electrode is less than the size of the second via electrode.

15. The chip according to claim 12, characterized in that, Along the direction from the first source electrode to the second source electrode, the size of the first via is greater than or equal to the size of the second via.

16. The chip according to any one of claims 12-15, characterized in that, The center of the first through hole coincides with the center of the second through hole.

17. A radio frequency power amplifier, characterized in that, Includes an RF input terminal, a ground terminal, a voltage terminal, an output terminal, and the chip described in any one of claims 12-16; The first gate and the second gate in the chip are coupled to the radio frequency input terminal, and the first source and the second source are coupled to the ground terminal; the first transistor of the chip also includes a first drain, and the second transistor of the chip also includes a second drain, and the first drain and the second drain are coupled to the voltage terminal and the output terminal, respectively.

18. A terminal, characterized in that, Includes a transmitter, said transmitter comprising the radio frequency power amplifier of claim 17.

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