Control unit for an electrical power inverter

Abstract

Inverter control device (30) for use in a system comprising a 3-phase inverter (20) with a plurality of switching devices (Sup, Sun, Svp, Svn, Swp, Swn) corresponding to the respective phases of the 3-phase inverter (20), and a rotating 3-phase machine (10) with respective phase windings electrically connected to the inverter control device (30), wherein the inverter control device (30) comprises a plurality of switching devices (Sup, Sun, Svp, Svn, Swp, Swn) and an operating signal generation circuit (30k) that generates PWM operating signals (Su, Sv, Sw), i.e., pulse width modulation operating signals, for controlling the switching devices (Sup, Sun, Svp, Svn, Swp, Swn) to generate alternating current flows in the rotating machine (10). wherein in each of successive processing periods (A and B, C and D) the operating signal generation circuit (30k) generates the PWM operating signals (Su, Sv, Sw) such that a first condition and a second condition are satisfied, wherein the first condition is that a state of a switching device corresponding to a highest phase of the 3-phase inverter (20) is held fixed over the entire processing period (A and B, C and D), wherein the highest phase has a phase voltage which is the highest among the respective phase voltages of the three phases during the processing period (A and B, C and D), wherein the processing period (A and B, C and D) has a first sub-period (A, C) and a second sub-period (B, D), each corresponding to half of the processing period (A and B, C and D), wherein the second condition is that a switching device corresponding to a lowest phase of the 3-phase inverter (20) undergoes a higher number of switching operations during the processing period (A and B, C and D) than a switching device corresponding to an intermediate phase of the 3-phase inverter (20) during the first sub-period (A, C), and that the switching device corresponding to the lowest phase of the 3-phase inverter (20) undergoes the same number of switching operations as the switching device corresponding to the intermediate phase of the 3-phase inverter (20) during the second sub-period (B, D), wherein the lowest phase has a phase voltage,which is the lowest among the respective phase voltages of the three phases during the processing period (A and B, C and D), and the intermediate phase has a phase voltage that is between the respective phase voltages of the highest phase and the lowest phase during the processing period (A and B, C and D).

Description

BACKGROUND OF THE INVENTION

[0001] DE 10 2012 203 684 A1 discloses a converter device that drives a rotating multiphase electric machine with variable speed using a switching element provided for each phase. An example of the converter device for the rotating electric machine includes: a frequency setting unit for determining and setting a carrier frequency of a carrier signal for use in controlling the switching element for each phase depending on the state of each phase of the rotating electric machine for each specified electrical angle obtained by evenly dividing a cycle of electrical angles; and a signal generation unit for generating a control signal for controlling the switching element of each phase using the carrier signal of the carrier frequency set for each phase by the frequency setting unit.The carrier frequency of each phase is an integer multiple of the phase voltage frequency at the specified electrical angle.

[0002] German patent application DE 10 2007 012 352 A1 discloses a dynamic pulse-width modulation (PWM) selection device that automatically switches between discontinuous PWM control methods (DPWM control methods). The PWM selection device comprises a PWM control module. The PWM control module determines a desired pulse width of a switching control signal according to a desired output signal. The PWM control module controls the current pulse width of the switching control signal according to the desired pulse width and a first PWM control method. A selection module determines whether the desired pulse width exceeds a pulse width threshold. The selection module selects a second PWM control method if the desired pulse width exceeds the pulse width threshold.

[0003] The present invention relates to a control device for an electrical power inverter (hereinafter generally referred to simply as an inverter) that performs a conversion between direct current and alternating current electrical power. In particular, the invention relates to a control device for a 3-phase inverter with three pairs of switching devices connected in series, each corresponding to one of the three phases, wherein the inverter is used to operate a synchronous rotating 3-phase machine.

[0004] Harmonic frequency components resulting from PWM (pulse width modulation) control of the switching operations of a 3-phase inverter are superimposed on the alternating currents flowing between the inverter and the rotating machine. These harmonic components generate audible noise by causing vibrations in parts of the rotating machine and also result in increased switching losses. Therefore, it is desirable to reduce the effects of such harmonic frequency components.

[0005] One proposed method to address this problem is to increase the inverter's switching frequency (PWM carrier frequency) above the audible frequency range, for example, above 20 kHz, while using conventional 3-phase modulation. However, increasing the switching frequency leads to a greater magnitude of switching losses.

[0006] To reduce switching losses, it is possible to use 2-phase modulation. With 2-phase modulation, in each of successive modulation periods, the operating state of one of the switching devices is held fixed according to the three phases U, V, W, while PWM modulation is only applied to the other two phases.

[0007] However, two-phase modulation is ineffective at reducing the problem of audible noise caused by harmonic frequency components. Therefore, there is a need for improved technology that can suppress audible noise without significantly increasing switching losses. SUMMARY OF THE INVENTION

[0008] Therefore, it is desirable to solve the problems described above by providing an inverter control device for controlling a 3-phase inverter, which, when the inverter is connected to a rotating machine, can suppress audible noise resulting from the operation of the rotating machine (due to harmonic frequency components superimposed on the currents flowing between the inverter and the rotating machine), while avoiding an increase in switching losses.

[0009] This problem is solved by an inverter control device as specified in claim 1.

[0010] Advantageous embodiments are specified in the dependent patent claims.

[0011] A 3-phase inverter according to the present invention has a plurality of switching devices corresponding to the respective phases and is applicable to a rotating 3-phase machine with respective phase windings that are electrically connected to the switching devices of the 3-phase inverter. The inverter control device has an operating signal generation circuit that provides PWM operating signals for controlling the switching devices of the 3-phase inverter to generate alternating current flows in the rotating machine.

[0012] The PWM operating signals are generated such that the first and second predetermined conditions are met in each of successive processing periods (successive modulation periods). The phase of the 3-phase inverter that has the highest phase voltage (of the three phases) during a processing period is designated as the "highest phase" for that processing period. Likewise, the phase with the lowest voltage is designated as the "lowest phase" for that processing period, and the phase with a voltage between the highest and lowest phases is designated as the "intermediate phase." The first predetermined condition is that in each processing period, the state of a switching device corresponding to the highest phase is held fixed for the entire processing period.The second predetermined condition is that during each processing period, the state of a switching device corresponding to the lowest phase experiences a greater number of switching state transitions than a switching device corresponding to the intermediate phase.

[0013] The magnitude of switching losses in the system, consisting of the inverter and the rotating machine, increases with an increase in the inverter's switching frequency and the level of the current being switched. As a result of fulfilling the first predetermined condition, the switching frequency for high phase current values ​​is reduced, thereby decreasing switching losses. As a result of fulfilling the second predetermined condition, only the switching frequency for low phase current values ​​is increased. This allows the switching frequency to be raised sufficiently above the audible frequency range to eliminate the problem of audible mechanical noise (interference).However, since switching is only performed at times when the phase current is low, there is no significant increase in switching losses caused by the increase in switching frequency. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows an overall system representation of a motor control system in which a first embodiment for an inverter control device is used. Fig. Figure 2 shows a block diagram according to the first embodiment of an inverter control device, Fig. Figure 3 shows a representation of a stress vector in a dq coordinate system. Fig. 4A and Fig. Figure 4B shows diagrams describing the relationships between voltage vectors and operating signals that control the switching of the inverter control device. Fig. 5a and Fig. Figure 5B shows representations illustrating modulation by voltage vectors in a range (0° ≤ θv < 60°). Fig. 6A and Fig. Figure 6B shows representations illustrating modulation by voltage vectors in a range (60° ≤ θv < 120°). Fig. 7A and Fig. Figure 7B shows representations illustrating modulation by voltage vectors in a range (120° ≤ θv < 180°). Fig. 8A and Fig. Figure 8B shows representations illustrating modulation by voltage vectors in a range (180° ≤ θv < 240°). Fig. 9A and Fig. Figure 9B shows representations illustrating modulation by voltage vectors in a range (240° ≤ θv < 300°). Fig. 10A and Fig. Figure 10B shows representations illustrating modulation by voltage vectors in a range (300° ≤ θv < 360°). Fig. Figure 11 shows a representation for comparing operating signals according to the present invention, a 2-phase modulation and a 3-phase modulation, Fig. Figure 12 shows a representation comparing the relationships between switching losses and switching frequency for the case of results obtained with the present invention, 2-phase modulation and 3-phase modulation respectively. Fig. Figure 13 shows a block diagram according to a second embodiment of an inverter control device, and Fig. Figure 14 shows a representation illustrating a phase difference between a voltage vector and a current vector in a dq coordinate system. DESCRIPTION OF PREFERRED EXAMPLES First example

[0014] A first embodiment is described, which is an inverter control unit for installation in a motor vehicle such as an electric vehicle or a hybrid vehicle. The inverter control unit according to this embodiment controls a 3-phase power inverter connected to a 3-phase motor-generator of the vehicle. The operation of the motor-generator as a 3-phase synchronous motor is described below.

[0015] Fig. Figure 1 shows a general circuit diagram of a vehicle's engine control system. As shown, the engine control system comprises a motor-generator 10, an inverter 20, and an inverter control unit 30, which controls the motor-generator 10 via a switching control signal generation section 25. The motor-generator 10 is the vehicle's main drive unit and is coupled to the vehicle's road wheels (not shown in the drawings). According to the exemplary embodiment, the motor-generator 10 is an IPMSM (internal permanent magnet synchronous motor) type.

[0016] The motor generator 10 is connected via the inverter 10 to a battery 22, which serves as a DC power source generating an output voltage of several hundred volts. A smoothing capacitor 24 is connected in parallel with the battery 22 between the battery 22 and the inverter 20 to smooth the supply voltage to the inverter 20.

[0017] It would be possible to connect a voltage booster between battery 22 and inverter 20. In this case, the voltage booster would form the DC power source for inverter 20.

[0018] The switching devices of inverter 20 consist of switches of an upper branch Sup, Svp, Swp and switches of a lower branch Sun, Svn and Swn, wherein the switches Sup, Sun are connected in series, the switches Svp, Svn are connected in series, and the switches Swp, Swn are connected in series. As it is in Fig. As shown in Figure 1, the U-phase line of the motor generator 10 is connected to the junction of switches Sup and Sun, the V-phase line of the motor generator 10 is connected to the junction of switches Svp and Svn, and the W-phase line of the motor generator 10 is connected to the junction of switches Swp and Swn. According to this embodiment, semiconductor devices, in particular IGBTs (insulated-gate bipolar transistors), are used as the upper branch switches Sup, Svp, and Swp, and the lower branch switches Sun, Svn, and Swn. Freewheeling diodes Dup, Dvp, Dwp, Dun, Dvn, and Dwn are each connected in reverse parallel to switches Sup, Svp, Swp, Sun, Svn, and Swn, respectively.

[0019] The motor control system also includes a phase current sensing section, a voltage sensing section, and a rotation angle sensing section, as described below. The phase current sensing section detects the level of a current flow from at least two of the three phases. According to this embodiment, the phase current sensing section uses a V-phase current sensor 42v and a W-phase current sensor 42w to detect, respectively, the levels of the V-phase current and the W-phase current flowing between the motor generator 10 and the inverter 20. The voltage sensing section includes a voltage sensing device 44 that detects the input voltage of the inverter 20, i.e., the voltage occurring between the terminals of the smoothing capacitor 24.The rotation angle detection section uses a rotation angle sensor 46 (for example, a resolver) to detect the rotation angle of the motor generator 10 in order to obtain a detected phase angle value, which is referred to as the electrical phase angle θe.

[0020] The inverter control unit 30 is based on a processor (for example, a microcomputer) that executes a stored program to perform various functions described below, and one or more memory devices containing pre-stored data that maps various input variable values ​​to corresponding output values ​​for use by the microcomputer during the execution of the stored program. The inverter control unit 30 thereby controls the inverter 20 to drive the motor-generator 10 such that the generated torque is brought to a target torque designated as Trq* (in this embodiment, the control variable of the motor-generator 10).The inverter control unit 30 generates a U-phase operating signal Su corresponding to the U-phase, a V-phase operating signal Sv corresponding to the V-phase, and a W-phase operating signal Sw corresponding to the W-phase, which are fed to the switching control signal generation section 25. The switching control signal generation section 25 thereby generates switching control signals CSup and CSun for the respective control of the U-phase switches Sup, Sun, CSvp and CSvn for the respective control of the V-phase switches Svp, Svn, and CSwp and CSwn for the respective control of the W-phase switches Swp, Swn. Each of the switches of the upper branch Sup, Svp, Swp performs a complementary switching operation with respect to the corresponding switch of the lower branch Sun, Svn, and Swn.The phase currents that flow in the U, V and W stator windings of the motor generator 10, which are designated as the U phase current Iu, the V phase current Iv and the W phase current Iw, are sinusoidal and differ in phase by 120 degrees.

[0021] The target value of the torque Trq* can, for example, be supplied from an external control device that has a higher degree than the inverter control device 30.

[0022] The torque control of the motor generator 10, which is carried out by the inverter control unit 30, is described with reference to Fig. 2 described.

[0023] As it is in Fig. As shown in Figure 2, the inverter control unit 30 consists of a two-phase conversion section 30a, a command current setting section 30b, subtractors 30c and 30d, a d-axis command voltage calculation section 30e, a q-axis command voltage calculation section 30f, a voltage amplitude calculation section 30g, a voltage phase calculation section 30h, a duration time calculation section 30j, an adder 30j, and an operating signal generation section 30k. According to this embodiment, each period, designated as a "processing period," corresponds to a PWM modulation period with a duration Ts.Based on samples of the V-phase current Iv detected by the voltage sensor 41v and the W-phase current Iw detected by the current sensor 42w, and the electrical phase angle θe detected by the rotation angle sensor 46, the two-phase conversion section 30a converts the values ​​of the U-phase current Iu, the V-phase current Iv, and the W-phase current Iw into a 3-phase coordinate system, and then into values ​​of a d-axis current Idr and a q-axis current Iqr in a rotating 2-phase coordinate system (dq coordinate system). The value of the U-phase current Iu is calculated from the V-phase current Iv and the W-phase current Iw using Kirchhoff's law.

[0024] The command current setting section 30b sets values ​​of d-axis and q-axis command currents Id* and Iq* based on the target torque Trq* and pre-stored data (characteristic map data) relating to the electrical and torque characteristics of the motor generator 10. The subtractor 30c obtains a d-axis current error ΔId by subtracting the d-axis current Idr from the d-axis command current Id*. The subtractor 30d obtains a q-axis current error ΔIq by subtracting the q-axis current Iqr from the q-axis command current Iq*.

[0025] Based on the d-axis current error ΔId, the d-axis command voltage calculation section 30e calculates a d-axis command voltage Vd as a control variable for regulating the d-axis command current Id*. Based on the q-axis current error ΔIq, the d-axis command voltage calculation section 30e calculates a q-axis command voltage Vq as a control variable for regulating the q-axis command current Iq*. According to this embodiment, a PI (proportional-integral) control is used.

[0026] The voltage amplitude calculation section 30g calculates the magnitude of a voltage vector (command voltage vector) Vdq of the inverter 20. As described in Fig. As illustrated in Figure 3B, the stress vector Vdq is expressed in a rotating coordinate system on the basis of the d-axis and q-axis command stresses Vd and Vq, where the magnitude is denoted as Vr (which is calculated as the square root of the sum of the squares of the d-axis and q-axis command stresses Vd and Vq).

[0027] Based on the d-axis and q-axis command voltages Vd and Vq, the voltage phase calculation section 30h calculates the phase angle of the voltage vector Vdq, which is referred to as the voltage phase angle δ. According to this embodiment, as described in Fig. As shown in Figure 3, the positive direction of an increase in δ is defined as the counterclockwise rotation from the d-axis as a reference angle (i.e., the rotation from the positive direction of the d-axis to the positive direction of the q-axis). The stress vector Vdq with magnitude Vr, calculated by the stress amplitude calculation section 30g, and phase angle δ, calculated by the stress phase calculation section 30h, for a processing period is applied as the command stress vector for that processing period.

[0028] The adder 30i calculates the sum of the voltage phase angle δ and the electrical phase angle θe to obtain an angle value, here referred to as the true phase angle θv. This is the phase angle of the voltage vector Vdq, expressed in terms of the U-phase angle in a fixed rectangular coordinate system of the inverter control device 30, which is represented as a space vector diagram in Fig. Figure 4B shows that, according to this embodiment, the voltage vector Vdq (command voltage vector) rotates counterclockwise from the U-phase angle as a (0°) reference, representing a positive direction of increase in the phase angle.

[0029] The processing carried out by the duration calculation section 30j and by the operating signal generation section 30k is described below. As it is in Fig. As shown in Figure 4B, there are 8 basic voltage vectors, each corresponding to the 8 different (1, 0) combinations of the operating signals Su, Sv, Sw generated by the inverter control unit 30, which are in Fig. Figure 4A shows 8 combinations of switching states of the three pairs of switching devices (U-phase switch Sup, Sun; V-phase switch Svp, Svn; W-phase switch Swp, Swn). The voltage vectors are labeled V0 [0,0,0], V1 [1,0,0], V2 [1,1,0], V3 [0,1,0], V4 [0,1,1], V5 [0,0,1], V6 [1,0,1], and V7 [1,1,1]. In particular, the operating signal state “1” in Fig. 4A means that the switching device of the upper branch of the corresponding pair is in the ON (conducting) state, and the switching device of the lower branch is in the OFF (non-conducting) state, whereas “0” means that the switching device of the lower branch of the pair is in the ON state, while the switching device of the upper branch is in the OFF state. The voltage vectors V1-V6, which have a magnitude greater than 0, are called “valid vectors” and differ successively in phase by 60°. The voltage vectors V0 and V7, which each have a magnitude of 0, are called “0 vectors”.

[0030] The fundamental function of the duration calculation section 30j and the operating signal generation section 30k is to generate a spatial vector modulation of the respective voltages applied to the U, V, and W phase windings of the motor generator 10 (i.e., by determining the timing (time control) and sequence of voltage vector selection in each processing period) based on the operating signals Su, Sv, and Sw, in order to bring an average phase voltage vector close to the command voltage vector in each processing period. This is achieved by determining the respective sequence positions and duration times of selected voltage vectors within each processing period. According to this embodiment, two of the six valid vectors and one of the zero vectors are selected to be set during a processing period.The two selected valid vectors are those that are currently adjacent to the command voltage vector.

[0031] For example, in a processing period, if the instruction vector is as in Fig. As shown in Figure 4B, the valid vectors V1 and V2 are closest to the command voltage vector and are therefore selected to be set during this processing period.

[0032] In each processing period, the one of the three U, V, W phases of inverter 20 that will have the highest phase voltage is hereinafter referred to as the “highest phase” for that processing period, whereas the phase whose (average) phase voltage will be the lowest (i.e., closest to a median value of the phase voltages) of the three is referred to as the “lowest phase” for that processing period, and the phase whose (average) phase voltage lies between the highest and lowest values ​​is referred to as the intermediate phase.

[0033] The spatial vector modulation according to this embodiment (i.e., setting sequence positions and duration times for the voltage vectors of the inverter 20 within each processing period) is carried out such that two predetermined processing conditions are met.

[0034] The first processing condition is that in each processing period, the state of the switching devices corresponding to the highest phase remains unchanged throughout the entire processing period (i.e., the operating signal Su, Sv, or Sw corresponding to the highest phase is held unchanged). The effect of applying the first condition is to reduce switching losses, as the frequency of switching high current values ​​is reduced.

[0035] The second processing condition is as described below. The number of switching operations of the switching devices corresponding to the lowest phases during each processing period is increased relative to the number of switching operations of the switching devices corresponding to the intermediate phase (increased by one in this embodiment). This means that the operating signal Su, Sv, or Sw corresponding to the lowest phase undergoes a greater number of state transitions than the operating signal corresponding to the intermediate phase.

[0036] The effect of the second processing condition is to increase the switching frequency (counteracting the decrease in switching frequency resulting from applying the first condition) without essentially increasing the switching losses, since only low values ​​of current are switched.

[0037] By applying the first and second processing conditions, the frequency of harmonic components superimposed on the currents flowing in the motor generator 10 can be sufficiently raised above the audible frequency range, while avoiding a significant increase in switching losses. The effects obtained are in Fig. Figure 12 illustrates the results obtainable according to the present embodiment with those obtained using conventional 2-phase modulation or 3-phase modulation where the PWM frequency is increased above the audible range.

[0038] The durations and sequence positions of the voltage vectors are described below based on six periods, each designated as Period 1 to Period 6, covering a range of 0° to 360° variation in the true phase angle θv. Each of Periods 1 to 6 consists of two successive processing periods (in this embodiment, each processing period corresponds to a 30° variation in θv). The first processing period consists of two successive sub-periods designated A and B, and the second processing period consists of two successive sub-periods designated C and D (i.e., each sub-period corresponds to a duration Ts / 2 and a 15° variation in θv). It is assumed that the motor-generator 10 operates with a power factor of 1.

[0039] Sections (a) to (e) of Fig. Section 5A shows the following changes that occur during the No. 1 period. Section (a) shows the changes in the phase current, section (b) shows the changes in the operating signals Su, Sv, Sw for the respective phases, and section (c) shows the phases for which the operating condition is held fixed. Section (d) shows the valid vectors selected within the No. 1 period. The time and duration for which a valid voltage vector and a zero vector are selected are determined according to the true phase angle θv (which is fed to the persistence time calculation section 30j, as described above with reference to Fig. 2 has been described). Section (e) shows the zero vectors that have been selected, where vector V7 is selected within the first half of the No. 1 period and vector V0 is selected within the second half. Sections (a), (b), (c), (d) of Fig. 5B shows the times and duration for their Operation during the No. 1 period (0°≤θv<60°)

[0040] With reference to the Fig. 5A, Fig. Section 5B initially describes the No.-1 period (range 0° to 60° of the true phase angle θv). In the first half of the No.-1 period (0° ≤ θv < 30°, under period pair A, B), the No.-1 vector V1 and the No.-2 vector V2 are selected as the valid vectors. The highest phase is the U-phase. Thus, to satisfy the first processing condition, the upper branch switch Sup of the U-phase is held in the ON state and the lower branch switch Sun is held in the OFF state throughout the entire sub-periods A, B (i.e., throughout the entire first processing period in the No.-1 period).

[0041] The lowest phase is the V-phase, so the W-phase is the intermediate phase.

[0042] In sub-period A, the voltage vector sequence is set to vector #1 V1, vector #2 V2, and then vector #7 V7. In the subsequent sub-period B, the voltage vector sequence is set to vector #7 V7, vector #2 V2, vector #1 V1, and then vector #2 V2. Since vector #2 V2 is selected after vector #1 V1, the number of switching operations of phase V, which is the lowest phase, is increased compared to phase W, which is the intermediate phase. Thus, the second processing condition for the first processing period is fulfilled in phase #1.

[0043] The operating signals Su, Sv, Sw corresponding to the respective voltage vectors during the sub-periods A and B (first processing period) of the No.-1 period are generated essentially as described below according to this embodiment.

[0044] The inverter control unit 30 has a memory section (not shown in the drawings) that stores data (pulse patterns) expressing the operating signals Su, Sv, Sw. The inverter control unit 30 samples the phase current values ​​Iv, Iw, and the voltage value Vdc, etc., in each processing period. The adder 30i calculates the true phase angle θv in each processing period by adding the respective values ​​of θe and δ. The operating signal generation section 30k selects a voltage vector sequence according to the true phase angle θv, and the duration calculation section 30j calculates the respective durations for the selected voltage vectors, also according to the true phase angle θv. "Duration" here means the duration for which a voltage vector is selected during each of the two sub-periods of a processing period.

[0045] Below is a valid voltage vector whereby only the switch of the upper branch of a single switch pair is in the ON state (voltage vector V1, V3 or V5 according to Fig. 4B), referred to as a “1-phase ON vector”. A valid voltage vector whereby the respective switches of the upper branch of two pairs of switches (i.e., each corresponding to two from the UVW phases) are in the ON state (voltage vector V2 or V4 according to Fig. 4B), is described as a “2-phase ONE vector”.

[0046] The duration time calculation section 30j calculates the duration time ta of each 1-phase EIN vector based on the following equation (1). ta=Ts22VrVdcsin(π3−θv)

[0047] In equation (1), Vdc is the voltage value detected by the voltage detection device 44. The duration of the propagation time ta is determined according to an increase in the voltage magnitude Vr (command vector magnitude, which is applied in Fig. 3 is shown) and increases accordingly by a reduction in the voltage level Vdc.

[0048] The duration time calculation section 30j calculates the duration time tb of each 2-phase EIN vector based on the following equation (2): tb=Ts22VrVdcsinθv

[0049] The duration time calculation section 30j calculates the duration time tz for each zero vector on the basis of the following equation (3): tz=Ts2−ta−tb

[0050] In sub-periods A and B of the No. 1 period (first processing period), the No. 1 vector V1 is the 1-phase ON vector, whereas the No. 2 vector V2 is the 2-phase ON vector, and the No. 7 vector V7 is the zero vector. Thus, voltage amplitude calculation section 30g calculates the duration time t1 of the No. 1 vector V1 in each of sub-periods A and B of the No. 1 period based on equation (1) described above, using the command voltage vector magnitude Vr, the input voltage Vdc, and the true phase angle θv as input values. Duration time calculation section 30j also uses these input values ​​(Vr, Vdc, and θv) to calculate the duration time t2 of the No. 2 vector V2 in each of sub-periods A and B based on equation (2) described above. The duration time calculation section 30j also adds the duration times t1, t2 of the No. 1 vector V1 and the No.-2-vector V2 together and subtracts the result from Ts / 2 (the equation (3) described above) to obtain the persistence time t7 for the No.-7 vector V7 in each of the subperiods A, B of the No.-1 period, as described in sections (a), (b) of . Fig. 5A is shown.

[0051] Additionally, the duration time calculation section 30j divides the duration time t2 of the No.-2 vector V2 (which is calculated using equation (2) described above) by two and presents the result (t2 / 2) as two duration times of the No.-2 vector V2 within subperiod B of the No.-1 period, as described in section (b) of Fig. 5B is shown.

[0052] For example, using a timer function, the operating signal generation section 30k provides the operating signals Su, Sv, Sw during the processing period (the sub-periods A, B) based on the duration times calculated by the voltage amplitude calculation section 30g, the time elapsed since the start of sub-period A, and stored operating signal data (i.e., the data stored in Fig. 4A illustrates the relationships shown.

[0053] In sub-periods C and D (30° ≤ θv < 60°, second processing period) of the No. 1 period, the No. 1 vector V1 and the No. 2 vector V2 are continuously selected as the valid vectors, and the W phase is the highest phase. Thus, to satisfy the first processing condition in sub-periods C and D, the upper branch switch Swp of the W phase is fixed in the OFF state, and the lower branch switch Swn is fixed in the ON state. During sub-periods C and D, the lowest phase is continuously the V phase, so the U phase is the intermediate phase.

[0054] In sub-period C of the No.-1 period, the No.-1 vector V1, the No.-2 vector V2, the No.-1 vector V1, and the No.-0 vector V0 are selected consecutively. The No.-1 vector V1 is selected before the No.-2 vector V2, so that the number of switching operations of the V-phase (the lowest phase) in the second processing period (sub-periods A, B) of the No.-1 period is greater than that of the intermediate phase (the U-phase). Thus, the second processing condition is fulfilled.

[0055] In sub-period D of the No.-1 period, the stress vector sequence is set as the No.-0 vector V0, the No.-1 vector V1 and the No.-2 vector V2.

[0056] As described above, it is ensured that the phase voltages of the U, V, and W phases are switched sequentially (i.e., individually). This prevents current surges that could damage the switching devices and that would result from switching two or more phases simultaneously. Operation during the No. 2 period (60°≤θv<120°)

[0057] Operation in the No. 2 period (range 60° to 120° of the true phase angle θv) is described with reference to Fig. 6 described. Only the differences compared to the operation in the No. 1 period are described.

[0058] In subperiods A and B (60° ≤ θv < 90°) of period No. 2, vectors V2 and V3 of No. 2 are selected as the valid vectors, and the highest phase is phase W. Therefore, to satisfy the first processing condition, the switch of the upper branch Swp of phase W is fixed in the OFF state, and the switch of the lower branch Swn is fixed in the ON state.

[0059] During sub-periods A and B of the No. 2 period, the lowest phase is the U-phase, making the V-phase the intermediate phase. In sub-period A, the voltage vector sequence is set to No. 2 vector V2, No. 3 vector V3, and No. 0 vector V0. In the subsequent sub-period B, the voltage vector sequence is set to No. 0 vector V0, No. 3 vector V3, No. 2 vector V2, and then No. 3 vector V3. Because No. 3 vector V3 is selected after No. 2 vector V2, the number of switching operations of the U-phase, which is the lowest phase, is increased compared to the V-phase, which is the intermediate phase. Thus, the second processing condition for the first processing period of the No. 2 period is fulfilled.

[0060] In subperiods C and D (90° ≤ θv < 120°) of the No. 2 period, the No. 2 vector V2 and the No. 3 vector V3 remain the valid vectors, and the V phase is the highest phase. Therefore, to satisfy the first processing condition in subperiods C and D, the upper branch switch Svp of the V phase is fixed in the ON state, and the lower branch switch Svn is fixed in the OFF state. During subperiods C and D, the lowest phase remains the U phase, making the W phase the intermediate phase.

[0061] In sub-period C of period No. 2, the voltage vector sequence is set as No. 2 vector V2, No. 3 vector V3, No. 2 vector V2, and No. 7 vector V7. No. 2 vector V2 is set before No. 3 vector V3, so that the number of switching operations of the U-phase (the lowest phase) is greater than that of the intermediate phase (the W-phase).

[0062] Then, in subperiod D, the stress vector sequence is set as No. 7 vector V7, No. 2 vector V2 and No. 3 vector V3. Operation during the No. 3 period (120°≤θv<180°)

[0063] Operation in the No. 3 period (range 120° to 180° of the true phase angle θv) is described with reference to Fig. 7 described.

[0064] In sub-periods A and B (120° ≤ θv < 150°, first processing period) of the No. 3 period, the No. 3 vector V3 and the No. 4 vector V4 are selected as the valid vectors, and the highest phase is the V phase. Thus, to satisfy the first processing condition, the switch of the upper branch Svp of the V phase is fixed in the ON state, and the switch of the lower branch Svn is fixed in the OFF state.

[0065] During sub-periods A and B, the U-phase is the intermediate phase, since the lowest phase is the W-phase.

[0066] In sub-period A of period No. 3, the voltage vector sequence is set to No. 3 vector V3, No. 4 vector V4, and No. 7 vector V7. In the following sub-period B, the voltage vector sequence is set to No. 7 vector V7, No. 4 vector V4, No. 3 vector V3, and No. 4 vector V4. Because No. 4 vector V4 is selected after No. 3 vector V3, the number of switching operations in the W phase (the lowest phase) is increased compared to the U phase (the intermediate phase).

[0067] In subperiods C and D (150° ≤ θv < 180°), the No. 3 vector V3 and the No. 4 vector V4 remain the valid vectors, and the U phase is the highest phase. Therefore, to satisfy the first processing condition in subperiods C and D, the switch of the upper branch Sup of the U phase is fixed in the OFF state, and the switch of the lower branch Sun is fixed in the ON state. During subperiods C and D, the lowest phase remains the W phase, making the V phase the intermediate phase.

[0068] In sub-period C, the voltage vector sequence is set as No. 3 vector V3, No. 4 vector V4, No. 3 vector V3, and No. 0 vector V0. The No. 3 vector V3 is set before the No. 4 vector V4, so that the number of switching operations of the lowest phase (the W phase) is greater than that of the intermediate phase (the V phase).

[0069] Then, in the sub-period D, the stress vector sequence is set as No. 0 vector V0, No. 3 vector V3 and No. 4 vector V4. Operation during the No. 4 period (180°≤θv<240°)

[0070] Operation during the No. 4 period (180° ≤ θv < 240°)

[0071] Operation in the No. 4 period (range 180° to 240° of the true phase angle θv) is with reference to Fig. 8 described.

[0072] In subperiods A and B (180° ≤ θv < 210°) of period No. 4, vectors V4 and V5 of No. 4 are selected as the valid vectors, and the highest phase is phase W. Therefore, to satisfy the first processing condition, the switch of the upper branch Swp of phase W is fixed in the ON state, and the switch of the lower branch Swn is fixed in the OFF state.

[0073] During sub-periods A and B, the U-phase is the intermediate phase, since the lowest phase is the V-phase.

[0074] In sub-period A, the voltage vector sequence is set to No. 7 vector V7, No. 4 vector V4, and No. 5 vector V5. In the following sub-period B, the voltage vector sequence is set to No. 4 vector V4, No. 5 vector V5, No. 4 vector V4, and then No. 7 vector V7. Because No. 4 vector V4 is selected before No. 5 vector V5, the number of switching operations of the V-phase, which is the lowest phase, is increased compared to the U-phase, which is the intermediate phase.

[0075] In periods C and D (210° ≤ θv < 240°), the No. 4 vector V4 and the No. 5 vector V5 remain the valid vectors, and the U phase is the highest phase. Therefore, to fulfill the first processing condition in sub-periods C and D (second processing period), the switch of the upper branch Sup of the U phase is fixed in the OFF state, and the switch of the lower branch Sun is fixed in the ON state. The lowest phase remains the V phase, making the W phase the intermediate phase.

[0076] In sub-period C, the voltage vector sequence is set as vector number 0 V0, vector number 5 V5, vector number 4 V4, and vector number 5 V5. Vector number 3 V3 is set after vector number 4 V4, so that the number of switching operations in the V-phase (the lowest phase) is greater than that in the intermediate phase (the W-phase).

[0077] Then, in subperiod D, the stress vector sequence is set as No. 4 vector V4, No. 5 vector V0 and No. 4 vector V4. Operation during the No. 5 period (240°≤θv<300°)

[0078] Operation in the No. 5 period (range 240° to 300° of the true phase angle θv) is described with reference to Fig. 9 described.

[0079] In subperiods A and B (240° ≤ θv < 270°) of period No. 5, vectors V5 and V6 of No. 5 are selected as the valid vectors, and the highest phase is phase W. Therefore, to satisfy the first processing condition, the switch of the upper branch Swp of phase W is fixed in the ON state, and the switch of the lower branch Swn is fixed in the OFF state.

[0080] During sub-periods A and B, the V-phase is the intermediate phase, since the lowest phase is the U-phase.

[0081] In sub-period A, the voltage vector sequence is selected as No. 5 vector V5, No. 6 vector V6, and then No. 7 vector V7. In the following sub-period B, the voltage vector sequence is selected as No. 7 vector V7, No. 6 vector V6, No. 5 vector V5, and then No. 6 vector V6. Since No. 6 vector V6 is set to occur after No. 5 vector V5, the number of switching operations of the U-phase, which is the lowest phase, is increased compared to the V-phase, which is the intermediate phase.

[0082] In subperiods C and D (270° ≤ θv < 300°), vectors V5 (number 5) and V6 (number 6) are selected as the valid vectors, and phase V is the highest phase. Therefore, to satisfy the first processing condition in subperiods C and D, the upper branch switch Svp of phase V is fixed in the OFF state, and the lower branch switch Svn is fixed in the ON state. Phase U is the lowest phase, making phase W the intermediate phase.

[0083] In sub-period C, the voltage vector sequence is set as No. 5 vector V5, No. 6 vector V6, No. 5 vector V5, and No. 0 vector V0. The No. 5 vector V5 is selected before the No. 6 vector V6, so that the number of switching operations of the U-phase (the lowest phase) is greater than that of the intermediate phase (the W-phase).

[0084] Then, in the sub-period D, the stress vector sequence is set as No. 0 vector V0, No. 5 vector V5 and No. 6 vector V6. Operation during the No. 6 period (300° ≤ θv < 360°)

[0085] Operation in the No. 6 period (range 300° to 360° of the true phase angle θv) is described with reference to Fig. 9 described.

[0086] In subperiods A and B (300° ≤ θv < 330°), the No. 1 vector V1 and the No. 6 vector V6 are selected as the valid vectors, and the highest phase is the U phase. Therefore, to satisfy the first processing condition, the switch of the upper branch Sup of the U phase is fixed in the ON state, and the switch of the lower branch Sun is fixed in the OFF state.

[0087] During sub-periods A and B, the V-phase is the intermediate phase, since the lowest phase is the W-phase.

[0088] In sub-period A, the voltage vector sequence is set to No. 7 vector V7, No. 6 vector V6, and then No. 1 vector V1. In the following sub-period B, the voltage vector sequence is set to No. 6 vector V6, No. 1 vector V1, No. 6 vector V6, and then No. 7 vector V7. Because No. 6 vector V6 is selected before No. 1 vector V5, the number of switching operations of the W phase, which is the lowest phase, is increased compared to the V phase, which is the intermediate phase.

[0089] In subperiods C and D (330° ≤ θv < 360°), the No. 1 vector V1 and the No. 6 vector V6 are selected as the valid vectors, and the V phase is the highest phase. Therefore, to satisfy the first processing condition in subperiods C and D, the switch of the upper branch Svp of the V phase is fixed in the OFF state, and the switch of the lower branch Svn is fixed in the ON state. The lowest phase remains the U phase, making the W phase the intermediate phase.

[0090] In sub-period C, the voltage vector sequence is set as No. 0 vector V0, No. 1 vector V1, No. 6 vector V6, and No. 1 vector V1. No. 1 vector V1 is positioned after No. 6 vector V6, so that the number of switching operations in the W phase (the lowest phase) is greater than that in the intermediate phase (the U phase).

[0091] Then, in the sub-period D, the stress vector sequence is set as No. 6 vector V6, No. 1 vector V1 and No. 0 vector V0.

[0092] The effects obtained according to the present invention are described below with reference to Fig. 11 and Fig. 12 described. First, the switching transitions of the operating signals Su, Sv, Sw are compared for the case of the present invention and the case of a (conventional) 2-phase modulation, with reference to diagrams (d) and (c) of Fig. 11. As shown, in the case according to the present invention (first embodiment), the switching frequency of the operating signals Su, Sv, Sw is increased compared to the use of 2-phase modulation. Diagram (d) of Fig. Figure 11 shows the switching transitions of the operating signals Su, Sv, Sw for the case of a conventional 3-phase modulation.

[0093] The switching frequencies and switching losses obtained for the cases according to the present invention (according to the preceding embodiment), 2-phase modulation and 3-phase modulation, when each is in Fig. 12 compared.

[0094] According to the present invention, the number of switching transitions in each processing period (i.e., a duration equal to a PWM modulation carrier period) is increased compared to two-phase modulation. Thus, the frequency of mechanical noise due to switching can be raised above the audible frequency range while using a longer PWM modulation carrier period (lower carrier frequency) than would be required with two-phase modulation. This is achieved without significantly increasing switching losses, thereby avoiding the problem that arises when using three-phase modulation, and the modulation frequency is sufficiently increased to raise the mechanical noise above the audible frequency range.

[0095] Furthermore, the results can be obtained without increasing the carrier frequency of the PWM modulation and correspondingly shortening the processing period (Ts) of the current control. A consequent increase in the processing load imposed on the inverter control unit 30 due to shortening the processing period can thus be avoided. Second embodiment

[0096] A second embodiment is described with reference to Fig. 13. Only the features that differ from those according to the first embodiment are specifically described. According to the second embodiment, as described in Fig. As shown in Figure 13, the inverter control unit 30 further comprises a phase difference calculation section 30m and a current phase calculation section 30p. The main purpose of this configuration is to reduce switching losses more reliably than according to the first embodiment. The switching losses of each of the U, V, and W phases are approximately proportional to the absolute value of the phase current. Thus, to reduce the switching losses, it is necessary to fix the state of the switching devices of the phase corresponding to the highest absolute value of the phase current in each of the successive processing periods.

[0097] According to the first embodiment, it is assumed that the motor-generator 10 operates at a power factor of 1. However, in practice, the power factor can differ from 1; that is, there can be a phase difference between the applied voltage and the current of each U, V, or W phase, depending on the operating conditions of the motor-generator 10. Thus, the highest phase in each processing period may be incorrectly selected, which poses a risk of increased switching losses.

[0098] Thus, according to the second embodiment, the current phase calculation section 30p calculates the phase angle (hereinafter referred to as the current phase angle β) of the current vector Idq based on the d-axis and q-axis currents Idr, Iqr. According to this embodiment, as it is described in Fig.As shown in Figure 14, the current phase angle β has the positive direction of the d-axis as a reference and takes on increased values ​​with rotation in the counterclockwise direction from this reference.

[0099] The phase difference calculation section 30m calculates the phase difference ΔΦ between the voltage vector Vdq and the current vector Idq by subtracting the current phase angle β from the voltage phase angle δ.

[0100] According to the first embodiment, the operating signal generation section 30k and the duration calculation section 30j determine the No. 1 to No. 6 periods based on the values ​​of the true phase angle θv. However, according to the second embodiment, the No. 1 to No. 6 periods are determined based on θv and the phase difference δΦ. For example, the No. 1 period is set as the range (0° ≤ (θv - ΔΦ) < 60°) of variation of the true phase angle θv, as opposed to the range (0° ≤ θv < 60°) in the case according to the first embodiment. In other respects, the operation is identical to that of the first embodiment described above.

[0101] The second embodiment thus offers the advantages described for the first embodiment, while ensuring that switching losses are reduced more reliably when the power factor of the rotating machine differs from 1.

[0102] A command vector calculation circuit, as described in the appended claims, corresponds to the voltage amplitude calculation section 30g and the voltage phase calculation section 30h according to the embodiments described above, in combination. The operating signal generation circuit, as described in the statements, corresponds, for example, to the duration time calculation section 30j and the operating signal generation section 30k according to the embodiments described above, in combination.In the formulation “a switching device corresponding to a highest phase”, “a switching device corresponding to a lowest phase” or “a switching device corresponding to an intermediate phase” in the attached patent claims, “a switching device” corresponds, for example, to the pair of switching devices Sup, Sun (of the U phase), or Svp, Svn (of the V phase), or Swp, Swn (of the W phase) according to the embodiments described above. Other examples of implementation

[0103] The present invention is not limited in scope to the embodiments described above, and various modifications of these or other embodiments may be considered. For example, the invention is not limited to the application for controlling an IPMSM-type motor-generator and would also be applicable to the control of an SPMSM (surface permanent magnet synchronous motor)-type motor-generator or a field-winding synchronous machine. Furthermore, the invention is not limited to application on a motor-generator or a motor installed in a vehicle. Moreover, the invention is not only applicable to the application for controlling a motor-generator but would be generally applicable to the control of three-phase synchronous machines.

[0104] As described above, an inverter control device performs PWM control of a 3-phase inverter connected to a rotating machine by operating switching devices corresponding to the respective phases. In each of successive processing periods, the PWM control is applied such that the first and second conditions are met. The first condition is that the state of switching devices corresponding to a phase with the highest voltage of the inverter is kept fixed throughout the entire processing period. The second condition is that the switching devices corresponding to a phase with the lowest voltage of the inverter undergo a greater number of switching operations during the processing period than switching devices corresponding to a phase with the medium voltage of the inverter.The frequency of harmonic components in alternating currents flowing in the rotating machine can thereby be raised above the audible range in order to suppress audible mechanical disturbances without significantly increasing the magnitude of switching losses.

Claims

[1] Inverter control device (30) for use in a system comprising a 3-phase inverter (20) with a plurality of switching devices (Sup, Sun, Svp, Svn, Swp, Swn) corresponding to the respective phases of the 3-phase inverter (20), and a rotating 3-phase machine (10) with respective phase windings electrically connected to the inverter control device (30), wherein the inverter control device (30) comprises a plurality of switching devices (Sup, Sun, Svp, Svn, Swp, Swn) and an operating signal generation circuit (30k) that generates PWM operating signals (Su, Sv, Sw), i.e. pulse width modulation operating signals, for controlling the switching devices (Sup, Sun, Svp, Svn, Swp, Swn) to generate alternating current flows in the rotating machine (10), wherein in each of successive processing periods (A and B, C and D) the operating signal generation circuit (30k) generates the PWM operating signals (Su, Sv, Sw) such that a first condition and a second condition are satisfied, wherein the first condition is that a state of a switching device corresponding to a highest phase of the 3-phase inverter (20) is held fixed over the entire processing period (A and B, C and D), wherein the highest phase has a phase voltage which is the highest among the respective phase voltages of the three phases during the processing period (A and B, C and D), wherein the processing period (A and B, C and D) has a first sub-period (A, C) and a second sub-period (B, D), each corresponding to half of the processing period (A and B, C and D), wherein the second condition is that a switching device corresponding to a lowest phase of the 3-phase inverter (20) undergoes a higher number of switching operations during the processing period (A and B, C and D) than a switching device corresponding to an intermediate phase of the 3-phase inverter (20) during the first sub-period (A, C), and that the switching device corresponding to the lowest phase of the 3-phase inverter (20) undergoes the same number of switching operations as the switching device corresponding to the intermediate phase of the 3-phase inverter (20) during the second sub-period (B, D), wherein the lowest phase has a phase voltage,which is the lowest among the respective phase voltages of the three phases during the processing period (A and B, C and D), and the intermediate phase has a phase voltage that is between the respective phase voltages of the highest phase and the lowest phase during the processing period (A and B, C and D). [2] Inverter control device (30) according to claim 1, with a command vector calculation circuit (30g, 30h) that calculates a command voltage vector according to a control variable of the rotating machine (10), wherein, where respective combinations of states of the PWM operating signals (Su, Sv, Sw) are represented as voltage vectors of a space vector coordinate system in which the command voltage vector rotates with respect to the voltage vectors, and voltage vectors with a magnitude greater than zero are designated as respective valid vectors, the operating signal generation generates the PWM operating signals (Su, Sv, Sw) such that each of the first predetermined condition and the second predetermined condition is satisfied in each of the successive processing periods (A and B, C and D) by selecting a pair of the valid vectors and determining a sequence and respective values ​​of a persistence time during which the pair of valid vectors is applied during the processing period (A and B, C and D), and wherein the pair of valid vectors is considered to be each adjacent in phase to the command vector during the processing period (A and B,C and D) is selected. [3] Inverter control device (30) according to claim 1, wherein during each of the first sub-periods (A, C) the switching device corresponding to the lowest phase experiences one more switching state transition than the switching device corresponding to the intermediate phase. [4] Inverter control device (30) according to claim 1, further comprising: a command vector calculation circuit (30g, 30h) that calculates a command voltage vector expressing phase voltages that currently need to be applied to the rotating machine (10), a current phase calculation circuit (30p) that calculates a phase angle of the alternating currents flowing in the rotating machine (10), and a phase difference calculation circuit (30m) that calculates a difference (ΔΦ) between a phase angle of the command voltage vector and the phase angle of the alternating currents, wherein in each of the processing periods (A and B, C and D) the operating signal generation circuit (30k) identifies the highest phase and the lowest phase based on the difference (ΔΦ) calculated by the phase difference calculation circuit (30m).

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