METHOD FOR PRODUCEING A SELF-ADJUSTED CONTACT IN A SEMI-CONDUCTOR DEVICE AND SEMI-CONDUCTOR DEVICE

Abstract

Semiconductor device comprising: a source / drain region (110, 130), with a stress material (110, 130) that has a different lattice constant than a channel region; a gate structure (20A, 20B, 30A, 30B) arranged over a substrate; Sidewall spacers (11A, 11B, 81A, 81B, 95A, 95B, 145A, 145B) arranged on both sidewalls of the gate structure (20A, 20B, 30A, 30B), wherein: the side wall spacers (11A, 11B, 81A, 81B, 95A, 95B, 145A, 145B) have at least four spacer layers (11A, 11B, 81A, 81B, 95A, 95B, 145A, 145B) comprising the first to fourth spacer layers (11A, 11B, 81A, 81B, 95A, 95B, 145A, 145B) in this order starting from the gate structure (20A, 20B, 30A, 30B); wherein the second spacer layer (11A, 11B, 31A, 31B, 111, 131) comprises an oxide layer (111, 131) over the stress material (110, 130) of the source / drain region (110, 130), and wherein bottoms of the third and fourth spacer layers (95A, 95B, 145A, 145B) are located on both side walls of the gate structure (20A, 20B, 30A, 30B) over the source / drain region (110, 130) and on the oxide layer (111, 131); and a metallized layer (115) which is formed on an exposed surface of the stress material (110, 130).

Description

TECHNICAL FIELD

[0001] The disclosure relates to a method of manufacturing a semiconductor device and, more particularly, to a structure and a manufacturing method for self-aligned source / drain (S / D) contacts BACKGROUND

[0002] With the reduction in size of semiconductor devices, self-aligned contacts (SACs) have been widely used, for example, to create a source / drain contact closer to gate structures in a field-effect transistor (FET). Typically, a SAC is fabricated by patterning an interlayer dielectric (ILD), under which a contact etch stop layer (CESL) is formed over the gate structure, which includes sidewall spacers. The initial etch of the ILD layer stops at the CESL, and then the CESL is etched to form the SACs. As device density increases (i.e., the dimensions of the semiconductor device are reduced), the thickness of the sidewall spacers becomes smaller, which can lead to a short circuit between the S / D contact and the gate electrodes.Therefore, it became necessary to provide SAC structures and a manufacturing process with improved electrical isolation between the S / D contacts and the gate electrodes.

[0003] US 2014 / 0 087 535 A1 discloses a method for fabricating semiconductor devices, wherein a plurality of sidewall spacers are formed above a gate electrode to laterally protect the gate electrode. Source / drain regions are defined lithographically and formed by etching the substrate and regrowing a stress material. Gaps that may arise as a result of misalignment of the lithography step and a subsequent etching process beneath the sidewall spacers are filled by conformally growing a protective layer, and sidewall spacers are formed from the resulting material stack.

[0004] US 2015 / 0 137 234 A1 discloses a method for fabricating semiconductor devices with sidewall spacers. The method comprises forming first and second sidewall spacers and forming self-aligned source / drain regions adjacent to the sidewall spacers. Subsequently, additional sidewall spacer layers are formed and subsequently partially removed by a selective etching process, creating floating sidewall spacers. The resulting gap is filled with an etch stop layer.

[0005] US Pat. No. 8,729,627 B2 discloses a method for fabricating semiconductor devices, wherein the channel region of a transistor is stressed by epitaxially grown silicon-germanium sections. The epitaxially grown sections are self-aligned by sidewall spacers.

[0006] US 2011 / 0 241 128 A1 discloses a multilayer sidewall spacer comprising three spacer layers, wherein the second spacer layer is made of an amorphous material to break the continuity of a grain boundary in the first spacer layer. Self-aligned source / drain regions can then be formed adjacent to the multilayer sidewall spacer.

[0007] US 2011 / 0 298 053 ​​A1 discloses a method for fabricating a gate stack, wherein a metallic oxygen-trapping sacrificial layer is formed as lateral sidewall spacers instead of as part of the metal gate stack. The oxygen-trapping sacrificial layer can be formed together with the gate electrode in a region delimited by a dielectric sidewall spacer layer.

[0008] US Pat. No. 8,455,952 B2 discloses a manufacturing method for a semiconductor device with sidewall spacers, wherein a first multilayer sidewall spacer is used to define a portion of a source / drain region. A second sidewall spacer may be formed over the first sidewall spacer to define the position of a silicide layer. An etch stop layer may be formed over the sidewall spacers and the silicide layer.

[0009] The document US 2011 / 0 101 457 A1 discloses a method for manufacturing semiconductor transistors, wherein sidewall spacers are used to define a doped region, wherein ion implantation can be performed through an insulating layer.

[0010] Publication US 2003 / 0 181 028 A1 discloses a semiconductor device on a substrate, wherein sidewall spacers are used around a gate structure to define source / drain regions and to form contacts. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The solution to the aforementioned problem is provided by an apparatus and method according to the independent claims. The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale and are for descriptive purposes only. Indeed, the dimensions of the various elements may be arbitrarily enlarged or reduced for clarity of discussion. Fig. 1A shows an exemplary perspective view of a FinFET after a dummy gate structure has been formed, and Fig. 1B shows an exemplary perspective view of a planar-type FET after the dummy gate structure has been formed, according to an embodiment of the present disclosure. Fig. 2A to 11B show exemplary cross-sectional views illustrating a sequential manufacturing method of a semiconductor device according to an embodiment of the present disclosure. Fig. 12A and Fig. 12B show enlarged cross-sectional views of the S / D contact hole regions according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] It should be understood that the following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Dimensions of the elements, for example, are not limited to disclosed ranges or values, but may depend on process conditions and / or desired characteristics of the device. Further, in the following description, forming a first element over or on top of a second element may include, for example, embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact.Different elements may be drawn at different scales for simplicity and clarity.

[0013] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be differently oriented (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly. Additionally, the term "made of" can mean either "comprising" or "consisting of."

[0014] Fig. 1A shows an exemplary structure after a gate structure GATE has been formed over a fin structure. One method for implementing the gate structure is referred to as a "gate-last" or "replacement-gate" process. In such a process, a dummy gate structure is initially formed using polysilicon, various processes related to the semiconductor device are performed, and the dummy gate is subsequently removed and replaced with a metal gate. In this embodiment, the FinFET device includes an n-type FinFET 11 and a p-type FinFET 12 (not explicitly shown).

[0015] First, a fin structure FIN is formed over a substrate SUB. The fin structure FIN is formed over a substrate SUB and protrudes from an isolation insulating layer STI. To produce a fin structure FIN according to one embodiment, a mask layer is formed over a substrate. The mask layer is formed, for example, by a thermal oxidation process and / or a chemical vapor deposition (CVD) process. The substrate is, for example, a p-type silicon substrate with an impurity concentration in the range of approximately 1×10 15 cm -3 up to about 1×10 18 cm -3 . In other embodiments, the substrate is an n-type silicon substrate having an impurity concentration in the range of about 1×10 15 cm -3 up to about 1×10 18 cm -3. The mask layer comprises, for example, a pad oxide layer (e.g., silicon dioxide) and a silicon nitride mask layer, in some embodiments.

[0016] Alternatively, the substrate may comprise other elemental semiconductors, for example, germanium; a compound semiconductor including IV-IV compound semiconductors such as SiC and SiGe; III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In one embodiment, the substrate is a silicon layer of an SOI (silicon-on-insulator) substrate. If an SOI substrate is used, the ridge structure may protrude from the silicon layer of the SOI substrate or from the insulating layer of the SOI substrate. In the second case, the silicon layer of the SOI substrate is used to form the ridge structure. The substrate may contain various regions appropriately doped with impurities (e.g., p-type or n-type conductivity).

[0017] The pad oxide layer can be formed using thermal oxidation or a CVD process. The silicon nitride mask layer can be formed using physical vapor deposition (PVD), such as a sputtering process, CVD, plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high-density plasma CVD (HDPCVD), atomic layer deposition (ALD), and / or other processes.

[0018] The thickness of the pad oxide layer ranges from about 2 nm to about 15 nm, and the thickness of the silicon nitride mask layer ranges from about 2 nm to about 50 nm in some embodiments. A mask pattern is further formed over the mask layer. The mask pattern is, for example, a resist layer formed by lithography techniques. By using the mask pattern as an etch mask, a hard mask pattern of the pad oxide layer and the silicon nitride mask layer is formed. The width of the hard mask pattern ranges from about 4 nm to about 40 nm in some embodiments. In certain embodiments, the width of the hard mask patterns ranges from about 4 nm to about 12 nm.

[0019] By using the hard mask structure as an etch mask, the substrate is patterned into a ridge structure FIN by trench etching using a dry etching process and / or a wet etching process. The height of the ridge structure (z-direction) is in the range of about 20 nm to about 100 nm. In certain embodiments, the height is in the range of about 30 nm to about 60 nm. If the height of the ridge structures is not uniform, the height from the substrate may be measured from the plane corresponding to the average heights of the ridge structures. The width of the ridge structure 20 is in the range of about 5 nm to about 40 nm in some embodiments and in the range of about 7 nm to about 15 nm in certain embodiments.

[0020] As in Fig. 1A, a fin structure FIN extending in the y-direction is arranged above the substrate SUB; in this embodiment, one fin structure for an n-type FET and one fin structure for a p-type FET (not explicitly shown) are arranged. However, the number of fin structures is not limited to one. There may be two, three, four, or five or more fin structures arranged in the x-direction. In addition, one or more dummy fin structures may be arranged adjacent to both sides of the fin structure to improve pattern fidelity in the patterning process. When multiple fin structures are arranged, the space between the fin structures is in the range of about 8 nm to about 80 nm in some embodiments and in the range of about 7 nm to about 15 nm in other embodiments.However, one skilled in the art will recognize that the dimensions and values ​​mentioned in the descriptions are only examples and can be changed to suit different sizes of integrated circuits.

[0021] After the fin structure FIN is formed, an isolation insulating layer STI is formed over the fin structure. The isolation insulating layer STI comprises one or more layers of insulating materials, such as silicon oxide, silicon oxynitride, or silicon nitride, formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, flowable dielectric materials are deposited instead of silicon oxide. Flowable dielectric materials, as their name suggests, can "flow" during deposition to fill gaps or spaces with a high aspect ratio. Typically, various chemicals are added to silicon-containing precursors to flow the deposited film. In some embodiments, nitrogen hydride bonds are added.Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include silicate, siloxane, methylsilsesquioxane (MSQ), hydrogensilsesquioxane (HSQ), MSQ / HSQ, perhydrosilazane (TCPS), perhydropolysilazane (PSZ), tetraethylorthosilicate (TEOS), or a silylamine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multi-step process. After the flowable film is deposited, it is cured and then annealed to remove unwanted element(s) to form silicon oxide. Once the unwanted element(s) are removed, the flowable film densifies and shrinks. In some embodiments, multiple annealing processes are performed. The flowable film is cured and annealed more than once. The flowable film can be doped with boron and / or phosphorus.The separation insulating layer can be formed by one or more layers of SOG, SiO, SiON, SiOCN and / or fluoride-doped silicate glass (FSG).

[0022] After the isolation layer has been formed over the fin structure, a planarization process is performed to remove a portion of the isolation layer and the mask layer (the pad oxide layer and the silicon nitride mask layer). The planarization process may include chemical mechanical polishing (CMP) and / or an etch-back process. The isolation layer is then further removed (recessed) to expose the upper layer of the fin structure.

[0023] A dummy gate structure GATE is formed over the exposed fin structure FIN. A dielectric layer and a polysilicon layer are formed over the isolation insulating layer and the exposed fin structure, and then patterning operations are performed to obtain a dummy gate structure GATE comprising a dummy gate electrode layer made of polysilicon and a dummy gate dielectric layer. In some embodiments, the patterning of the polysilicon layer is performed using a hard mask having a silicon nitride layer formed over a silicon oxide layer. In other embodiments, the hard mask comprises a silicon oxide layer over a silicon nitride layer. The dummy gate dielectric layer is made of silicon oxide formed by CVD, PVD, ALD, electron beam evaporation, or other suitable methods.In some embodiments, the gate dielectric layer comprises one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some embodiments, a thickness of the gate dielectric layer is in the range of about 5 nm to about 20 nm, and in the range of about 5 nm to about 10 nm in other embodiments.

[0024] In some embodiments, the width of the dummy gate electrode layer GATE is in the range of about 5 nm to about 40 nm. In some embodiments, a thickness of the gate electrode layer is in the range of about 5 nm to 200 nm and is in the range of about 5 nm to 100 nm in other embodiments.

[0025] If a planar type FET, as in Fig. 1B, instead of the fin FETs, a dummy dielectric layer and a dummy polysilicon layer are formed over the substrate SUB, and then patterning operations are performed using a hard mask layer to obtain the dummy gate structure GATE.

[0026] Fig. 2A to 11B show exemplary cross-sectional views illustrating a sequential manufacturing method of a semiconductor device according to an embodiment of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes described in the Fig. 2A to 11B, and that some of the operations described below may be replaced or removed in further embodiments of the method. The order of the operations / methods may be reversed. Although the Fig. 2A to 11B show a sequential manufacturing process of a FinFET as used in Fig. 1A, the manufacturing method can be applied to a planar type FET as shown in Fig. 1B. In such a case, the "web structure" may be understood as the "substrate" in the following description.

[0027] After the gate structure GATE has been formed, a first insulating layer 10 is formed over the dummy gate structure and the fin structure. Fig. Figure 2A shows exemplary cross-sectional views for an n-channel region for an n-type FET 11 and a p-channel region for a p-type FET 12 along the line AA' of Fig. 1A.

[0028] How Fig. As shown in Figure 2A, the dummy gate for the n-type FET 11 includes a dummy gate dielectric layer 20A, a dummy gate electrode 30A, and a hard mask having a first mask layer 40A and a second mask layer 50A. Similarly, the dummy gate for the p-type FET 12 includes a dummy gate dielectric layer 20B, a dummy gate electrode 30B, and a hard mask having a first mask layer 40B and a second mask layer 50B. In some embodiments, the dummy gate dielectric layers 20A, 20B include one or more layers of dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the dummy gate dielectric layers 20A, 20B are made of silicon oxide. The dummy gate electrode layers 30A, 30B are made of a suitable material such as polysilicon and amorphous silicon. In this embodiment, the dummy gate electrode layers 30A, 30B are made of polysilicon.The first hard mask layers 40A, 40B are made of, for example, silicon nitride and the second hard mask layers 50A, 50B are made of, for example, silicon oxide, in some embodiments.

[0029] The thickness of the dummy gate electrodes 30A, 30B above the fin structure (channel region) is in the range of about 100 nm to about 150 nm. The thickness of the mask layers (the sum of the first and second mask layers) is in the range of about 50 nm to about 100 nm.

[0030] The first insulating layer 10 comprises one or more layers of dielectric materials such as silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and SiOCN. In some embodiments, the first insulating layer 10 is made of a silicon nitride-based compound. In this embodiment, SiCN is used. The thickness of the first insulating layer 10 ranges from about 3 nm to about 5 nm. The first insulating layer can be formed by CVD or ALD.

[0031] In one embodiment, the ALD process comprises a step of introducing a precursor material as a silicon source, including, without limitation, disilane (DIS), dichlorosilane (DCS), hexachloride disilane (HCD), or silane. Then, a carbon source gas, the hydrocarbon gas (C x H y), such as, without limitation, ethylene (C2H4), and a nitrogen source gas such as, without limitation, ammonia (NH3), are introduced, thereby forming a single layer of SiCN. By repeating the above processes, a SiCN layer with a desired thickness can be obtained.

[0032] Next, as in Fig. 2B, the p-channel region is covered by a resist layer 70B, and ion implantation (NLDD) for a lightly doped drain (LDD) is applied to the n-channel layer. A dopant for NLDD is phosphorus and / or arsenic, and a dose is in the range of approximately 1×10 14 cm -2 up to about 1×10 15 cm -2Ion implantation is performed by tilting the substrate relative to the ion beam direction and can be performed repeatedly by rotating the substrate 90, 180, and 270 degrees. After ion implantation, the resist layer 70B is removed, for example, by a plasma ashing process.

[0033] After removing the resist layer 70B, a post-annealing process is performed to recrystallize the amorphization regions created by the ion implantation and activate the implanted impurities. The annealing process may consist of a rapid thermal annealing (RTA) process at a temperature in the range of about 900°C to about 1400°C for about 1 millisecond to about 5 seconds. The annealing process may include a preheating step at a temperature of about 200°C to about 700°C for about 50 to about 300 seconds. In the present embodiment, the preheating step is performed at a temperature of about 500-600°C for about 180 seconds. Additionally, in some embodiments, the RTA process is performed at a temperature greater than about 1000°C and for more than 1.5 seconds. In some embodiments, the annealing process is a millisecond thermal annealing (MSA) process that can reach a temperature up to 1.400°C for a few milliseconds or less, for example, about 0.8 milliseconds to about 100 milliseconds. The annealing process can be performed after the LDD implantation for the p-channel region is completed.

[0034] As in Fig. As shown in Figure 2C, the n-channel region is covered by a resist layer 70A, and PLDD ion implantation for an LDD is applied to the p-channel layer. A dopant for PLDD is boron (BF2+), and a dose ranges from about 1*1014 cm2 to about 3*1015 cm2. Ion implantation is performed by tilting the substrate with respect to the ion beam direction and can be performed repeatedly by rotating the substrate by 90, 180, and 270 degrees. After ion implantation, the resist layer 70A is removed, for example, by a plasma ashing method, and then an annealing process can be performed. The order of NLDD ion implantation and PLDD ion implantation can be interchanged.

[0035] After the LDD implantation, a second insulating layer 80 is formed over the first insulating layer 10 and a third insulating layer 90 is formed over the second insulating layer 80, as shown in Fig. 3A. The third insulating layer 90 protects the p-channel region from the subsequent manufacturing processes applied to the n-channel region. The second and third insulating layers are formed by dielectric materials such as silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and SiOCN. In some embodiments, the second insulating layer 80 is made of SiCN and the third insulating layer 90 is made of SiN. The thickness of the second insulating layer 80 is in the range of about 3 nm to about 5 nm, and the thickness of the third insulating layer 90 is in the range of about 3 nm to about 10 nm, in some embodiments. The second and third insulating layers may be formed by CVD or ALD.

[0036] Then, as in Fig. As shown in Figure 3B, the p-channel region is covered by a resist layer 75B, and anisotropic etching is applied to the stacked insulating layers in the n-channel region, so that the sidewall spacers are formed on both side surfaces of the dummy gate structures. The sidewall spacers in the n-channel region at this stage consist of the first insulating layer 10A, the second insulating layer 80A, and the third insulating layer 90A.

[0037] After the sidewall spacers for the n-channel region have been formed, the fin structure NFIN is recessed in the n-channel region below the upper surface of the isolation insulating layer STI, as shown in Fig. 3B to form recessed portions 100. Then, as shown in Fig. 3C, the resist layer 75B is removed.

[0038] How Fig. As shown in Figure 4A, a stress material for the source / drain is epitaxially formed in the recessed portions 100. By using a stress material 110 having a lattice constant different from that of the channel region of the ridge structure, appropriate pressure is applied to the channel region to increase carrier mobility in the channel region. For the n-type FET, when the channel region is made of Si, a silicon compound comprising P (SiP) and / or C (SiC) is used. In this embodiment, SiP is epitaxially formed in the recessed portions 110.

[0039] After the stress material 110 has been formed, the third insulating layers 90A in the sidewall spacers of the n-channel region and 90 in the p-channel region are removed using suitable etching techniques, as shown in Fig. 4B. When the third insulating layer is made of SiN, wet etching with H3PO4 is used.

[0040] Then, as in Fig. 4C, a fourth insulating layer 120 is formed over the n-channel region and the p-channel region. The fourth insulating layer 120 protects the n-channel region from the subsequent manufacturing processes applied to the p-channel region. The fourth insulating layer is formed from dielectric materials such as silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and SiOCN. In some embodiments, the fourth insulating layer 120 is made of SiN. The thickness of the fourth insulating layer 120 ranges from about 3 nm to about 10 nm in some embodiments. The fourth insulating layer may be formed by CVD or ALD.

[0041] As in Fig. As shown in Figure 5A, after the n-channel region is covered by a resist layer 75A, anisotropic etching is applied to the stacked insulating layers in the p-channel region, so that the sidewall spacers of the fourth insulating layer are formed on both sides of the dummy gate structures of the p-channel region. The sidewall spacers in the p-channel region at this stage consist of the first insulating layer 10B, the second insulating layer 80B, and the fourth insulating layer 120B.

[0042] After the sidewall spacers for the p-channel region have been formed, the ridge structure PFIN is recessed in the p-channel region to below the upper surface of the isolation insulating layer STI, as shown in Fig. 5B to form recessed portions 105. Then, as shown in Fig. 5C, the resist layer 75A is removed.

[0043] As in Fig. As shown in Figure 5C, a stress material for the source / drain is epitaxially formed in the recessed portions 105. By using a stress material 130 having a lattice constant different from that of the channel region of the ridge structure, appropriate pressure is applied to the channel region to increase carrier mobility in the channel region. For the p-type FET, when the channel region is made of Si, a silicon compound containing germanium (SiGe) or Ge is used. In this embodiment, SiGe is epitaxially formed in the recessed portions 105.

[0044] After the stress material 130 has been formed, the fourth insulating layer 120B in the sidewall spacers of the p-channel region 120 and in the n-channel region is removed using suitable etching techniques, as shown in Fig. 6A. When the fourth insulating layer is made of SiN, wet etching with H3PO4 is used. At this stage, the width W1 of the sidewall spacers at the level of the top surface of the dummy gate electrode (30A or 30B) is in the range of about 5 nm to about 10 nm.

[0045] Then, as in Fig. 6B, a layer of organic material 140 is formed over the resulting structure, which in Fig. 5A. The organic layer 140 comprises resist or anti-reflective coating material. The organic layer 140 is formed such that the dummy gate structures are completely embedded in the organic layer 140.

[0046] The thickness of the formed organic layer 140 is reduced, for example, by an etching-back process, as in Fig. 6C. By adjusting the etching time, an organic layer 140 with a desirable thickness can be obtained. In one embodiment, the thickness of the organic layer 140 is reduced to a height substantially equal to the height of the upper surface of the dummy gate electrode layers 30A and 30B.

[0047] Next, the first mask layers 40A, 40B and the second mask layers 50A, 50B are removed using an etch-back process. The organic material layer 140 is then removed, for example, by an ashing operation using O2 plasma.

[0048] Through the processes to remove the mask layers and the organic material layer, the upper portions of the sidewall spacers 10A, 80A of the n-channel region and the sidewalls 10B, 80B of the p-channel region are also removed. The resulting structure is shown in Fig. 7A. In Fig. 7A and thereafter, the sidewall structures of 10A, 80A and 10B, 80B are shown for simplicity by a layer of sidewall spacers 81A and 81B, respectively.

[0049] During the process of removing the mask layers, the surfaces of the sidewalls 81A and 81B and the upper surface of the dummy gate electrodes 30A and 30B are oxidized, forming oxide layers 11A and 11B (on the sidewalls), 31A and 31B (on the dummy gate electrodes), and 111 and 131 (on the stress materials in the S / D), as shown in Fig. 7A. The oxidized layers 11A and 11B are made of silicon dioxide or silicon dioxide containing carbon and / or nitrogen (collectively referred to as silicon oxide-based material).

[0050] Then, as in Fig. 7B, sidewall spacers 95A and 95B are formed by depositing a fifth insulating layer and anisotropically etching the deposited fifth insulating layer.

[0051] The fifth insulating layer is formed by an ALD process at a temperature of approximately 450 to approximately 550°C. The etching process uses transformer-coupled plasma (TCP) with process gases including CH4, CHF3, O2, HBr, He, Cl2, NF3, and / or N2, with varying current and / or bias conditions to obtain the desired sidewall spacer structure. The etching is followed by a wet cleaning process to remove the polymer residues formed during the etching process.

[0052] In some embodiments, the fifth insulating layer is made of SiCN, SiOCN, or SiN. The thickness of the fifth insulating layer, as deposited, is in the range of about 2 nm to about 4 nm. The width W2 of the sidewall spacers 95A and 95B at the level of the top surface of the dummy gate electrode (30A or 30B) is in some embodiments in the range of about 8 nm to about 14 nm.

[0053] In some embodiments, the interface L1A (L1B) between the sidewall 95A (95B) and the oxide layer 11A (11B) is located at the interface between the stress material layer 110 (130) and the fin structure NFIN (PFIN) at its surface, as shown in Fig. 7B. In other words, the thickness of the side walls 81A (81B) and the thickness of the oxide layer 11A (11B) are adjusted to control the position of the interface L1A (L1B). Thus, as shown in Fig. 7B, the lateral lower end of sidewall 95A (95B) over the S / D stress material layer 110 (130). By using sidewalls 95A and 95B, the electrical isolation between the later-formed S / D contacts and the gate electrodes can be improved.

[0054] After the side walls 95A and 95B have been formed, as shown in Fig. 7C, a contact etch stop layer (CESL) 145 over the resulting structure of Fig. 7B. The CESL 145 comprises one or more layers of silicon nitride-based compounds such as SiN, SiON, SiCN, or SiOCN. In this embodiment, SiN is used as the CESL 145. The thickness of the CESL 145 ranges from about 3 nm to about 5 nm. The CESL 145 can be formed by CVD or ALD.

[0055] After the CESL 145 has been formed, an interlayer dielectric layer (ILD) 150 is deposited over the resulting structure of Fig. 7C trained. As in Fig. As shown in Figure 8A, the ILD layer 150 is formed such that the dummy gate structures with the sidewall spacers are completely embedded in the ILD layer 150.

[0056] The ILD layer 150 can be formed by CVD, HDPCVD, flowable CVD, spin-on coating, PVD, or sputtering, or other suitable processes. The ILD layer 150 comprises silicon oxide, silicon oxynitride, a low-k material, and / or other suitable dielectrics. The ILD layer 150 is conformally deposited and then planarized by a CMP process, as shown in Fig. 8B. The dummy gate structures serve as a planarization stop for the CMP process. In other words, the CMP process is stopped upon exposing the upper surface of the dummy gate structures, as shown in Fig. 8B is shown.

[0057] As in Fig. As shown in Figure 8C, the dummy gate electrodes 30A, 30B and the dummy gate dielectric layers 20A, 20B are removed, creating openings 155A and 155B between the spacers 81A in the n-channel region and the spacers 81B in the p-channel region, respectively. The dummy gate electrodes 30A and 30B are removed using an etching solution such as aqueous ammonia and / or another suitable etchant. In an alternative embodiment, the dummy gate electrodes 30A and 30B are removed using a suitable dry etching process. Example etchants include chlorine-based etchants. In some embodiments, the dummy gate dielectric layers 20A and 20B are removed using an etching process (wet etch, dry etch, plasma etch, etc.). Removing the dummy gate dielectric layers 20A and 20B exposes an upper surface of the channel layers in the fin structures.

[0058] As in Fig. As shown in Figure 9A, metal gate structures are formed in the openings 155A, 155B, which are created by removing the dummy gate structures. The gate structure for the n-type FET includes a gate dielectric layer 161A and a metal gate layer 170A, and the gate structure for the n-type FET includes a gate dielectric layer 161B and a metal gate layer 170B.

[0059] In some embodiments, the gate dielectric layers 161A and 161B comprise one or more layers of metal oxides, such as high-k metal oxides. Examples of metal oxides used for the high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof. In this embodiment, hafnium oxide (HfO2) is used. The gate dielectric layers 161A and 161B may be formed by ALD, CVD, PVD, and / or other suitable methods.

[0060] The metal gate layers 170A and 170B comprise one or more layers of Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, other conductive materials with a work function comparable to that of the substrate material, or combinations thereof. The metal gate layers 170A and 170B may be formed by CVD, PVD, plating, and / or other suitable processes. One or more CMP processes may be performed during the formation of the gate structures. A damascene process may be used to fabricate the gate structures.

[0061] In some embodiments, one or more work function adjustment layers (not shown) are disposed between the gate dielectric layer 161A, 161B and the metal gate layer 170A, 170B. The work function adjustment layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi is used as the work function adjustment layer, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co is used as the work function adjustment layer.

[0062] Next, the metal gate layers 170A and 170B are etched back to a certain depth to partially remove the metal gate layers to form buried gate electrodes 171A and 171B, as shown in Fig. 9B. A sixth insulating layer 180 is deposited to fill the recessed portions formed by partially removing the metal gate layers 170A and 170B. The sixth insulating layer may comprise one or more layers of a silicon nitride-based compound, such as SiN, SiON, SiCN, or SiOCN. In this embodiment, SiN is used as the sixth insulating layer 180. The sixth insulating layer 180 may be formed by PVD, CVD, PECVD, APCVD, LPCVD, HDPCVD, ALD, and / or other methods. By applying a planarization process such as a CMP process, the sixth insulating layer 180 formed on the ILD layer 150 is removed, leaving cap layers 181A and 181B on the buried metal gate electrodes 171A and 171B, as shown in Fig. 9C is shown.

[0063] Then, a resist layer is patterned by a lithography process to form contact hole structures over the S / D regions of the n-channel FET and the p-channel FET. Using the patterned resist mask, the ILD layer 150 is etched to form S / D contact holes 157A and 157B, as shown in FIGS. Fig. 10A and Fig. 10B. In one embodiment, the etching is preferably performed in an HDP with an etching gas such as C4F8 and CH3F to obtain high selectivity to the SiN layers. As shown in FIG. 10A, the etching of the ILD layer made of silicon oxide or oxide-based insulating material stops at the CESL 145A, 145B made of SiN or nitride-based insulating material. Therefore, even if the contact hole resist patterns are shifted laterally relative to the gate electrode due to misalignment in the lithography process, the etching of the ILD layer does not remove the CESL on the sidewalls of the gate structure, and the contact holes do not touch the gate electrodes. Therefore, the contact holes are formed by being self-aligned with the S / D regions (i.e., SACs are formed).Furthermore, since additional sidewall layers 95A and 95B are formed, electrical insulation between the later formed S / D contacts and the gate electrodes can be further improved.

[0064] After the etching at the CESL stops, another etching process is performed to remove the CESL on the bottom of the contact holes 157A and 157B, as shown in Fig. 10B. In some embodiments, the oxide layers 111 and 131 formed on the stress material of the S / D regions are also removed during or after the CESL etch.

[0065] After the surface of the stress materials 110 and 130 of the S / D regions of the n-type FET and p-type FET, respectively, has been exposed, metallized layers 115 for the S / D regions of the n-type FET and 135 for the S / D regions of the p-type FET are formed, as shown in Fig. 10C. The metallized layers include one or more silicide layers such as TiSi, TaSi, WSi, NiSi, CoSi, or other suitable transition metal silicides. Silicide layer 115 for the n-type FET may be the same as or different from silicide layer 135 for the p-type FET.

[0066] The Fig. 11A and Fig. 11B illustrates an S / D contact formation process. Adhesion layers 200A and 200B, made of Ti or Ti-W, for example, may be formed on the side surfaces of contact holes 157A and 157B by CVD, PVD, plating, and / or other suitable methods. Then, barrier layers 210A and 210B, made of TiN, for example, are deposited over adhesion layers 200A, 200B by a sputtering or evaporation process. Adhesion layer 200A and / or barrier layer 210A for the n-type FET may be the same as or different from adhesion layer 200B and / or barrier layer 210B for the p-type FET.

[0067] Next, a tungsten (W) layer 190 is deposited by CVD as shown in Fig. 11A. By performing a CMP process to remove the W layer 190 deposited on the ILD layer 150, the S / D contact with W plug structures 190A and 190B can be obtained, as shown in Fig. 11B is shown.

[0068] Fig. 12A and Fig. 12B shows the enlarged cross-sectional view of the S / D contact hole regions. Fig. 12A and Fig. 12B, for example, correspond to the n-channel regions of the Fig. 9C and 11B respectively. In the Fig. 12A and Fig. 12B are, however, unlike in the Fig. 9C and Fig. 11B, two gate structures, i.e., a first and a second gate structure, are arranged for two n-channel FETs. The first gate structures include the high-k gate dielectric layers 161A, the metal gate electrode layer 171A, the cap layer 181A, and sidewall spacers including 81A, 11A, and 95A, and the CESL 145A, while the second gate structures include the high-k gate dielectric layer 161A', the metal gate electrode layer 171A', the cap layer 181A', and sidewall spacers including 81A', 11A', and 95A', and the CESL 145A. The first and second gate structures are fabricated simultaneously, and the materials and configurations are substantially the same. Further, as shown in Fig. 12A, the stress layer 110 for the S / D region is arranged between the first and second gate structures.

[0069] As in Fig. 12A, has in the stage after the formation of the covering layer 181A, which is shown in Fig. 9C, the sidewall spacer 81A has a thickness Wa at the top surface of the metal gate electrode layer 171A in the range of about 6 nm to about 10 nm. The sidewall spacer 95A has a thickness Wb at the top surface of the metal gate electrode layer 171A in the range of about 2 nm to about 4 nm. The CESL 145A has a thickness Wc at the top surface of the metal gate electrode layer 171A in the range of about 3 nm to about 5 nm. The oxide layer 11A has a thickness at the top surface of the metal gate electrode layer 171A in the range of about 0.5 nm to about 1 nm.

[0070] As in Fig. 12B, at the stage after the W-plug has been formed, as shown in Fig. 11B, the sidewall spacers including 81A, 11A, 95A and 145A have a thickness We at the level of the top surface of the metal gate electrode layer 171A in the range of about 8 nm to about 16 nm. As shown in Fig. As shown in FIG. 12B, the sidewall spacer layer includes at least four layers 81A, 11A, 95A, and 145A. Since the sidewall spacer layer 81A may have two or more layers (e.g., 10A and 80A), the number of sidewall spacer layers may be five or more. The spacer layers 95A and 145A are made of the same material, and it is not possible to clearly distinguish these two layers, while the sidewall spacer may have three layers, which may include the layer 81A of a silicon nitride-based material, the layer 11A of a silicon oxide-based material, and a silicon nitride-based material (layers 95A and 145A).

[0071] Below the sidewall spacers, the bottom surfaces of spacer layer 95a and CESL 145A lie above the S / D region stress layer 110. Furthermore, the height of the sidewall spacers is the same as the height of cap layer 181A or a few nanometers lower than the height of cap layer 181A, meaning the height of the sidewall spacers is essentially the same as the height of cap layer 181A.

[0072] Since layer 95A is disposed between oxide layer 11A and CESL 145A, the overall thickness of the sidewall spacer can be increased and the electrical isolation between the S / D contact (W plug) and the gate electrode can be improved.

[0073] It is understood that the device in Fig. 11B undergoes further CMOS processes, such as forming various elements such as interconnect metal layers, dielectric layers, passivation layers, etc.

[0074] The various embodiments or examples described herein offer several advantages over the prior art. By introducing an additional sidewall spacer (e.g., 95A, 95B), it is possible to improve the insensitivity to etching solutions for the spacer dielectric region (e.g., dilute HF and / or aqueous ammonia), for example, due to surface tension and capillary forces. It is also possible to improve the electrical insulation between the gate electrode and the S / D contact (W plug), and device lifetime can also be improved during wear due to hot carrier injection.

[0075] According to one aspect of the present disclosure, a semiconductor device includes a gate structure disposed over a substrate and sidewall spacers disposed on both sidewalls of the gate structure. The sidewall spacers include at least four spacer layers, including first to fourth spacer layers stacked in this order from the gate structure.

[0076] In accordance with another aspect of the present disclosure, in a method of fabricating a semiconductor device, a gate structure is formed over a substrate. A first sidewall spacer layer is formed on a sidewall of the gate structure. An oxide layer is formed as a second sidewall spacer layer on the first sidewall spacer layer. A third sidewall spacer layer is formed on the second sidewall spacer layer. A contact etch stop layer is formed on the third sidewall spacer layer and the substrate.

[0077] According to yet another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first dummy gate structure for an n-channel transistor is formed over a substrate with a mask layer disposed thereon. A first insulating layer is formed over the first dummy gate structure. First ions are implanted through the first insulating layer for the n-channel transistor. A second insulating layer is formed over the first insulating layer. A third insulating layer is formed over the second insulating layer. The first to third insulating layers are etched, thereby forming a first n-type sidewall spacer layer on a sidewall of the first dummy gate structure. A first source / drain structure is formed in the substrate on a side portion of the first n-type sidewall spacer.After forming the first source / drain structure, the third insulating layer is removed from the first n-type sidewall spacer layer. An oxide layer is formed as a second sidewall spacer layer on the first n-type sidewall spacer layer. A third n-type sidewall spacer layer is formed on the second sidewall spacer layer. A contact etch stop layer is formed on the third n-type sidewall spacer layer and the substrate.

Claims

[1] A semiconductor device comprising: a source / drain region (110, 130) comprising a stress material (110, 130) having a different lattice constant than a channel region; a gate structure (20A, 20B, 30A, 30B) disposed over a substrate; Sidewall spacers (11A, 11B, 81A, 81B, 95A, 95B, 145A, 145B) arranged on both sidewalls of the gate structure (20A, 20B, 30A, 30B), wherein: the sidewall spacers (11A, 11B, 81A, 81B, 95A, 95B, 145A, 145B) have at least four spacer layers (11A, 11B, 81A, 81B, 95A, 95B, 145A, 145B) comprising first to fourth spacer layers (11A, 11B, 81A, 81B, 95A, 95B, 145A, 145B) in this order from the gate structure (20A, 20B, 30A, 30B); wherein the second spacer layer (11A, 11B, 31A, 31B, 111, 131) comprises an oxide layer (111, 131) over the stress material (110, 130) of the source / drain region (110, 130), and wherein bottoms of the third and fourth spacer layers (95A, 95B, 145A, 145B) lie on both sidewalls of the gate structure (20A, 20B, 30A, 30B) over the source / drain region (110, 130) and on the oxide layer (111, 131); and a metallized layer (115) formed on an exposed surface of the stress material (110, 130). [2] A semiconductor device according to claim 1, wherein: the first, third and fourth spacer layers (81A, 81B, 95A, 95B, 145A, 145B) are made of a silicon nitride-based material and the second spacer layer (11A, 11B, 31A, 31B, 111, 131) is made of a silicon oxide-based material. [3] The semiconductor device according to claim 2, wherein the silicon nitride-based material comprises SiN, SiCN, SiON or SiOCN and the silicon oxide-based material comprises silicon oxide. [4] A semiconductor device according to any one of the preceding claims, wherein the first spacer layer (81A, 81B) is made of SiCN. [5] A semiconductor device according to any one of the preceding claims, wherein the fourth spacer layer (145A, 145B) is made of SiN. [6] A semiconductor device according to any one of the preceding claims, wherein the third spacer layer (95A, 95B) is made of SiCN or SiN. [7] A semiconductor device according to any one of the preceding claims, wherein the third spacer layer (95A, 95B) is made of a different material than the fourth spacer layer (145A, 145B). [8] A semiconductor device according to any one of the preceding claims, further comprising: a contact plug (200A, 200B, 210A, 210B, 190A, 190B) in contact with a part of the source / drain region (110, 130), wherein the fourth spacer layer (145A, 145B) is in contact with the contact plug (200A, 200B, 210A, 210B, 190A, 190B). [9] A semiconductor device according to any one of the preceding claims, wherein the gate structure comprises: a gate dielectric layer (161A, 161A', 161B); a gate electrode layer (171A, 171A', 171B) disposed over the gate dielectric layer (161A, 161A', 161B), and a cover layer (181A, 181A', 181B) made of an insulating material and arranged over the gate electrode (171A, 171A', 171B), wherein a height of the sidewall spacers (11A, 11B, 81A, 81B, 95A, 95B, 145A, 145B) is equal to the height of the cover layer (181A, 181A', 181B). [10] A method of manufacturing a semiconductor device, comprising: Forming a gate structure (20A, 20B, 30A, 30B) over a substrate; Forming a first sidewall spacer layer (81A, 81B) on both sidewalls of the gate structure (20A, 20B, 30A, 30B); Forming a source / drain region (110, 130) with a stress material (110, 130) having a different lattice constant than a channel region; Forming an oxide layer (11A, 11B) as a second sidewall spacer layer (11A, 11B, 31A, 31B, 111, 131) on the first sidewall spacer layer (81A, 81B) and over the stress material (110, 130) of the source / drain region (110, 130); Forming a third sidewall spacer layer (95A, 95B) on the second sidewall spacer layer (11A, 11B, 31A, 31B, 111, 131); Forming a contact etch stop layer (145A, 145B) on the third sidewall spacer layer (95A, 95B) and the substrate, wherein bottoms of the third and fourth spacer layers (95A, 95B, 145A, 145B) on both sidewalls of the gate structure (20A, 20B, 30A, 30B) lie above the stress material (110, 130) and on the oxide layer (111, 131); Etching the contact etch stop layer (145A, 145B) and the oxide layer (111, 131) over the source / drain region (110, 130) to expose a surface of the stress material (110, 130); and Forming a metallized layer (115) on the exposed surface of the stress material (110, 130). [11] The method of claim 10, wherein: the first and third spacer layers (81A, 81B, 95A, 95B) and the contact etch stop layer (145A, 145B) are made of SiN, SiCN, SiON or SiOCN. [12] The method of claim 10 or 11, further comprising, after forming the contact etch stop layer (145A, 145B): Forming an intermediate dielectric (150) over the gate structure (20A, 20B, 30A, 30B) with the first to third spacer layers (11A, 11B, 81A, 81B, 95A, 95B) and the contact etch stop layer (145A, 145B); Forming a contact hole (157A, 157B) in the intermediate dielectric (150) by using the contact etch stop layer (145A, 145B) as the etch stop layer; Removing the contact etch stop layer (145A, 145B) in the contact hole (157A, 157B); and Filling the contact hole (157A, 157B) with a conductive material. [13] The method according to any one of claims 10 to 12, wherein the oxide layer (11A, 11B) is formed by oxidizing the first sidewall spacer layer (81A, 81B). [14] A method according to any one of claims 10 to 13, wherein: the gate structure (20A, 20B, 30A, 30B) is a dummy gate structure (20A, 20B, 30A, 30B) and the method further comprises, after forming the contact etch stop layer (145A, 145B): Forming an intermediate dielectric (150) over the dummy gate structure (20A, 20B, 30A, 30B) with the first to third spacer layers (11A, 11B, 81A, 81B, 95A, 95B) and the contact etch stop layer (145A, 145B); Removing the dummy gate structure (20A, 20B, 30A, 30B) to form a gate opening (155A, 155B); and Forming a metal gate structure comprising a metal gate electrode layer (171A, 171A', 171B) disposed over a high-k gate dielectric layer (161A, 161A', 161B) in the opening (155A, 155B). [15] The method of claim 14, further comprising, after forming the metal gate structure: Deepening the metal gate electrode layer (171A, 171A', 171B); and Forming a cap layer (181A, 181A', 181B) over the recessed gate electrode layer (171A, 171A', 171B). [16] The method of any one of claims 10 to 15, wherein forming a first sidewall spacer layer (81A, 81B) comprises forming a lower layer (10A, 10B) and forming an upper layer (80A, 80B) over the lower layer (10A, 10B), wherein ion implantation through the lower layer (10A, 10B) is performed between forming a lower layer (10A, 10B) and forming an upper layer (80A, 80B) over the lower layer (10A, 10B). [17] A method of manufacturing a semiconductor device, comprising: Forming a first dummy gate structure (20A, 30A) for an n-channel transistor, a mask layer (40A, 50A) being disposed thereon over a substrate; Forming a first insulating layer (10A) over the first dummy gate structure (20A, 30A); Implanting first ions through the first insulating layer (10A) for the n-channel transistor; Forming a second insulating layer (80A) over the first insulating layer (10A); Forming a third insulating layer (90A) over the second insulating layer (80A); Etching the first to third insulating layers (10A, 80A, 90A), thereby forming a first n-type sidewall spacer layer (81A, 81B) on a sidewall of the first dummy gate structure (20A, 30A); Forming a first source / drain structure (110) in the substrate on a side portion of the first n-sidewall spacer (81A) comprising a stress material (110) having a different lattice constant than a channel region; after forming the first source / drain structure (110), removing the third insulating layer (90A) from the first n-sidewall spacer layer (81A); Forming an oxide layer (11A, 31A, 111) as a second sidewall spacer layer (11A) on the first n-sidewall spacer layer (81A) and over the stress material (110) of the first source / drain structure (110); Forming a third n-sidewall spacer layer (95A) on the oxide layer (11A, 31A, 111) on both sides of the gate structure (20A, 20B, 30A, 30B); Forming a contact etch stop layer (145A) on the third n-sidewall spacer layer (95A), the oxide layer (11A, 31A, 111) and the substrate; Etching the contact etch stop layer (145A) and the oxide layer (111) over the source / drain region (110, 130) to expose a surface of the stress material (110); and Forming a metallized layer (115) on the exposed surface of the stress material (110). [18] The method of claim 17, further comprising: Forming a second dummy gate structure (20B, 30B) for a p-channel transistor, a mask layer (40B, 50B) being disposed thereon over the substrate; Forming the first insulating layer (10B) over the second dummy gate structure (20B, 30B); Implanting second ions through the first insulating layer (10B) for the p-channel transistor; Forming the second insulating layer (80B) over the first insulating layer (10B); Forming the third insulating layer (90B) over the second insulating layer (80B); after forming the third insulating layer (90B), removing the third insulating layer (90B); Forming a fourth insulating layer (120) over the second insulating layer (80B) after removing the third insulating layer (90B); Etching the first, second and fourth insulating layers (10B, 80B, 120), thereby forming a first p-type sidewall spacer layer (81B) on a sidewall of the second dummy gate structure (20B, 30B); Forming a second source / drain structure (130) in the substrate on a side portion of the first p-type sidewall spacer (81A, 81B); after forming the second source / drain structure (130), removing the fourth insulating layer (120) from the first p-type sidewall spacer layer (81A, 81B); Forming an oxide layer (11B, 31B, 131) on the first p-sidewall spacer layer (81A, 81B); Forming a third p-sidewall spacer layer (95A, 95B) on the oxide layer (11B, 31B, 131); and Forming a contact etch stop layer (145A, 145B) on the third p-sidewall spacer layer (95A, 95B) and the substrate.

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