SEMICONDUCTOR DEVICE HAVING A STRUCTURE FOR PROTECTING AGAINST ELECTROSTATIC DISCHARGE

Abstract

Semiconductor device (10) comprising: a semiconductor body (100) having a first surface (101) and a second surface (102) opposite the first surface (101), a first insulation layer (200) over the first surface (101) of the semiconductor body (100), and an electrostatic discharge protection structure (310) over the first insulation layer (200), wherein the electrostatic discharge protection structure (310) has a first connection region (312) of a first conductivity type and a second connection region (314) of a second conductivity type opposite to the first conductivity type, wherein at least two first regions (316) of the second conductivity type and at least two second regions (318) of the first conductivity type are arranged alternately between the first connection region (312) and the second connection region (314) along a lateral direction (x), and further comprising: a second insulation layer (400) over the structure (310) for protection against electrostatic discharge, a first electrode (500) and a second electrode (600) above the second insulation layer (400), wherein the first electrode (500) is electrically coupled to the first connection region (312) via a first contact element (810) and the second electrode (600) is electrically coupled to the second connection region (314) via a second contact element (910), and a terminal shunting structure (920) electrically connecting a junction between the second terminal region (314) and the second contact element (910) in parallel or in shunt, wherein the first contact element (810) and the second contact element (910) comprise polysilicon.

Description

BACKGROUNDA key component in semiconductor applications is a solid state switch. As an example, switches turn on and off loads of automotive or industrial applications. Solid state switches typically include, for example, field effect transistors (FETs) such as metal oxide semiconductor FETs (MOSFETs) or insulated gate bipolar transistors (IGBTs).In these applications, damage to a gate dielectric between gate and source of the transistors may be caused by an electrostatic discharge event between a gate contact region and a source contact region of the semiconductor device. To protect the gate dielectric from an electrostatic discharge event, electrostatic discharge protection (ESD) structures are provided that protect the transistors from electrostatic discharge during, for example, assembly or operation. These ESD protection structures require a non-negligible area within the integrated semiconductor device.Moreover, if a symmetric electrostatic discharge protection (ESD) structure is provided between a gate and source contact structure, asymmetric device robustness with respect to ESD polarity between gate and source results in limitations in semiconductor device testing.Accordingly, it is desirable to provide a semiconductor device structure with improved ESD protection and thermal properties while at the same time having optimized area efficiency.Document US 2013 / 0 127 063 A1 relates to a semiconductor device having a heat dissipation structure. Here, a p-n-p-n junction semiconductor controlled rectifier (SCR) has alternately arranged regions of different conductivity type, so that a pnpn structure is formed. The edge regions with p-doping or n-doping are contacted via connection regions, wherein the connection regions have a strong doping in order to avoid Schottky contact with the corresponding regions. The document DE 10 2014 105 790 A1 relates to a semiconductor device having an electrostatic discharge protection structure. In this case, a first terminal and a second terminal have the same conductivity type, wherein the first terminal and the second terminal can have the same conductivity type as the first regions. The structure thus creates a symmetrical ESD protection structure, wherein the first and the second terminal have the same conductivity type. The publication US 2005 / 0 077 577 A1 describes an ESD protection structure. In this case, a series circuit of two p + in +- diodes is provided, wherein this p + in + p + in +- structure is arranged on a substrate and is contacted with contact regions in the substrate.The publication DE 10 2006 023 429 A1 relates to an ESD protection element. In this case, an ESD protection element comprises a series circuit of p + in +- diodes, wherein adjacent p +- regions and n +- regions are doped so strongly that the pn junctions act illustratively and approximately as ohmic junctions. The dopant concentration in the first doped regions and / or the second doped regions may be, for example, greater than 10 20 cm -3.Further components are known from the publications US 2012 / 0 049 187 A1 and US 2012 / 0 220 091 A1.SUMMARYThe above problem is solved by the teachings of the independent claims. Further embodiments are defined in the dependent claims.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this disclosure. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles. Other embodiments of the invention and intended advantages will be immediately appreciated as they become better understood by reference to the following detailed description. FIG. 1A is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment. FIG. 1B is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment. FIGS. 2A and 2B are schematic plan views of a portion of a semiconductor device according to various embodiments. FIG. 3 is a schematic cross-sectional view of a portion of a semiconductor device taken along a sectional plane A-A' of FIG. 2A or 2B, according to an embodiment. FIG. 4 is a detailed view of a portion of a semiconductor device of FIG. 3. FIG. 5 is a schematic plan view of a portion of a semiconductor device according to an embodiment. FIG. 6 is a schematic cross-sectional view of a portion of a semiconductor device taken along a sectional plane B-B' of FIG. 5. FIG. 7A is a schematic plan view of a portion of a semiconductor device according to another embodiment. FIG. 7B is a schematic cross-sectional view of a portion of a semiconductor device taken along a sectional plane C-C' of FIG. 7A. FIG. 8A is a schematic plan view of a portion of a semiconductor device according to another embodiment. FIG. 8B is a schematic cross-sectional view of a portion of a semiconductor device taken along a sectional plane D-D' of FIG. 8A. FIG. 9 is a schematic cross-sectional view of a portion of a semiconductor device taken along a sectional plane A'-A of FIG. 2A or 2B, according to an embodiment. FIG. 10 illustrates a schematic working flow diagram of a method for manufacturing a semiconductor device according to an embodiment. FIGS. 11A to 11J are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. For example, features illustrated or described for one embodiment may be used in or in conjunction with other embodiments to arrive at yet another embodiment. It is intended that the present invention cover such modifications and variations. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements are provided with corresponding reference numerals throughout the several drawings unless otherwise stated.The terms "have," "include," "comprise," "have," and similar terms are open ended terms, and these terms indicate the presence of stated structures, elements, or features, but do not exclude the presence of additional elements or features.The terms "one by one", "successively", and the like indicate a loose order of elements, and additional elements placed between the ordered elements are not excluded.The indefinite articles and the definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.In this specification, n-type or n-doped refers to a first conductivity type, while p-type or p-doped refers to a second conductivity type. Semiconductor devices may be formed with opposite doping relationships, such that the first conductivity type may be p-doped and the second conductivity type may be n-doped. Moreover, some figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type. For example, "n -" means a doping concentration lower than the doping concentration of an "n" doping region, while an "n +" doping region has a higher doping concentration than an "n" doping region. However, an indication of the relative doping concentration does not mean that doping regions of the same relative doping concentration have the same absolute doping concentration unless otherwise stated. For example, two different n +- regions may have different absolute doping concentrations. The same applies to an n +- and a p +- region, for example.The first conductivity type may be an n- or p-type, provided that the second conductivity type is complementary.The term "electrically connected" describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the relevant elements or a low-ohmic connection via a metal and / or a highly doped semiconductor.The terms "wafer", "substrate", "semiconductor body", or "semiconductor substrate" used in the following description may include any semiconductor-based structure having a semiconductor surface. Wafers and structures are understood to include silicon (Si), silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor substrate, and other semiconductor structures. The semiconductor need not be silicon based. The semiconductor could also be silicon germanium (SiGe), germanium (Ge) or gallium arsenide (GaAs). According to other embodiments, silicon carbide (SiC) or gallium nitride (GaN) may form the semiconductor substrate material.The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a first or major surface of a semiconductor substrate or body. This may be, for example, the surface of the wafer or a die or a chip.The term "vertical" as used in this specification is intended to describe an orientation which is arranged substantially perpendicular to the first surface, i.e. parallel to the normal direction of the first surface of the semiconductor substrate or semiconductor body.Processing a semiconductor wafer may result in semiconductor devices having terminal contacts, such as contact pads / pads (or electrodes), that allow for making electrical contact with the integrated circuits or a separate semiconductor device included in the semiconductor body. The electrodes may comprise one or more electrode metal layers applied to the semiconductor material of the semiconductor chips. The electrode metal layers may be formed with any desired geometric shape and material composition. The electrode metal layers may be in the form of a layer covering a region, for example. Any desired metal, for example, Cu, Ni, Sn, Au, Ag, Pt, Pd, and an alloy of one or more of these metals can be used as the material. The electrode metal layer or layers need not be made homogeneously of just one material, i.e., various compositions and concentrations of the materials contained in the electrode metal layers are possible. As an example, the electrode layers may be sized large enough to be bonded with a wire.In embodiments disclosed herein, one or more conductive layers, in particular electrically conductive layers, are employed. It should be emphasized that such terms as "formed" or "applied" are to be understood to cover all types and techniques of applying layers. In particular, they mean to include techniques in which layers are applied at once, for example, as a whole, e.g., lamination techniques, as well as techniques in which layers are applied in a sequential manner, such as by sputtering, plating, forming, CVD (chemical vapor deposition), PVD (physical vapor deposition), evaporation, hybrid physical chemical vapor deposition (HPCVD), and so forth.The deposited conductive layer may include, among other things, one or more layers of metal such as Cu or Sn or an alloy thereof, a layer of conductive paste, and a layer of bonding material. The layer of metal may be a homogeneous layer. The conductive paste may comprise metal particles dispersed in a evaporable or curable polymer material, wherein the paste may be a fluid, viscous or waxy. The bonding material can electrically and mechanically fix or connect the semiconductor chip, for example to a carrier or, for example, a contact clip. A soft solder material or, in particular, a solder material capable of forming diffusion solder bonds may be used, for example, solder material comprising one or more of Sn, SnAg, SnAu, SnCu, In, InAg, InCu and InAu.A dicing process may be used to split the wafer into individual chips. Any technique of dicing may be used, such as knife dicing (sawing), laser dicing, etching, and so forth. The semiconductor body, for example a semiconductor wafer, may be divided by applying the semiconductor wafer to a tape, in particular a dicing tape, applying the dicing pattern, in particular a rectangular pattern, to the semiconductor wafer, for example according to one or more of the above mentioned techniques, and pulling the tape, for example along four orthogonal directions in the plane of the tape. By pulling the tape, the semiconductor wafer is divided into a plurality of semiconductor dies (chips).It should be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.FIG. 1A is a schematic cross-sectional view of a portion of a semiconductor device 10 according to an embodiment. The semiconductor device 10 comprises a semiconductor body 100 having a first surface 101 and a second surface 102 opposite the first surface 101. The semiconductor device 10 further comprises a first insulation layer 200 on or above the first surface 101 of the semiconductor body 100 and a structure 310 for protection against electrostatic discharge on or above the first insulation layer 200. The electrostatic discharge protection structure 310 comprises a first terminal region 312 of a first conductivity type and a second terminal region 314 of a second conductivity type opposite to the first conductivity type.FIG. 1B is a schematic cross-sectional view of a portion of a semiconductor device 10 according to an embodiment. A second insulating layer 400 is provided on or over the electrostatic discharge protection structure 310. On or above the second insulating layer 400, a first electrode 500 and a second electrode 600 are formed. The first electrode 500 is electrically coupled to the first connection region 312 via a first contact element 810, and the second electrode 600 is electrically coupled to the second connection region 314 via a second contact element 910. The second contact element 910 is of a first conductivity type and the second connection region 314 is of a second conductivity type opposite the first conductivity type. A shunt structure 920 of the terminal electrically connects a pn junction between the second terminal region 314 and the second contact element 910 in parallel.Due to the provision of the terminal shunting structure 920 electrically shunting a pn junction between the second terminal region 314 and the second contact element 910, a bidirectional asymmetric electrostatic discharge protection structure may be provided having different breakdown voltages depending on the polarity of the voltage applied between the first and second terminal regions 312, 314.The semiconductor device 10 may include power semiconductor elements such as IGBTs (insulated gate bipolar transistors), e.g., RC-IGBTs (reverse conducting IGBTs), RB-IGBTs (reverse blocking IGBTs), and IGFETs (insulated gate field effect transistors) including MOSFETs (metal oxide semiconductor field effect transistors). The semiconductor device 10 may also include a superjunction transistor, a trench field effect transistor, or any other transistor device that controls a load current via a control terminal.Reducing the chip size of the semiconductor device 10 results in a reduced input capacitance resulting in an increased risk of damage caused by an electrostatic discharge event between the gate and the source of the semiconductor device 10. Consequently, the electrostatic discharge protection structure 310 may be used in a power semiconductor element to protect a gate dielectric between a gate and a source of a transistor from damage by dissipating energy generated by an electrostatic discharge event between a gate contact region and a source contact region. Usually monolithically integrated Zener diode cascades of polysilicon are inherently bi-directional symmetrical devices. For negative gate pulses of an electrostatic discharge, the window of an electrostatic discharge is too small. Human body model (ESD HBM) destruction occurs mainly for negative ESD HBM stress.FIGS. 2A and 2B are schematic plan views of portions of a semiconductor device 10 according to various embodiments. As shown in FIG. 2A, the first electrode 500 is provided in a corner region of the semiconductor device 10 and may serve as a gate contact structure 510 (see FIG. 9 ) which may include a gate pad. The gate pad may be used to provide a bonding or solder contact with the first electrode 500 to be connected to an external device or element. The second electrode 600 is arranged next to the first electrode 500 and can serve as a source contact structure 610 (cf. FIG. 9 ), by means of which source zones 150 of transistor cells 20 in the semiconductor body 100 are contacted.When the semiconductor device 10 is formed as a power semiconductor element, a resulting thickness of metallization of the first electrode 500 and the second electrode 600 may be in a range of 1 μm to 10 μm or 3 μm to 7 μm, and the first electrode 500 and the second electrode 600 may be spaced apart by a minimum distance B in a range of 5 μm to 20 μm or 10 μm to 15 μm. As shown in FIG. 2B, the first electrode 500 may also be disposed in a central portion of the semiconductor device 10, wherein the second electrode 600 surrounds the first electrode 500. Possible locations of the structure 310 for protection against electrostatic discharge are indicated by dashed lines, wherein the indicated locations are only exemplary and should not be understood as limiting.FIG. 3 is a schematic cross-sectional view of a portion of the semiconductor device 10 taken along a sectional plane A-A' of FIG. 2A or 2B, according to an embodiment.The semiconductor body 100 may be formed of a single crystalline semiconductor material, for example, silicon Si, silicon carbide SiC, germanium Ge, a silicon germanium crystal SiGe, gallium nitride GaN or gallium arsenide GaAs. A distance between the first and second surfaces 101, 102 is selected to achieve a certain voltage blocking capability and may be at least 3 μm or at least 10 μm or at least 20 μm, for example at least 50 μm. In particular, if a SiC semiconductor body is provided, the distance between the first and second surfaces 101, 102 may be in a range from 5 μm to 20 μm or in a range from 3 μm to 10 μm. Other embodiments may provide semiconductor bodies 100 having a thickness of several 100 μm. The semiconductor body 100 can have a quadrangular shape with an edge length in the range of several millimeters.The normal to the first and second surfaces 101, 102 defines a vertical direction z, and directions orthogonal to the normal direction are lateral directions. For example, as can be seen from FIGS. 2A and 2B, the lateral direction x is defined to extend between the first terminal region 312 and the second terminal region 314. Consequently, the lateral direction x is effectively parallel to the direction of a breakdown current within the electrostatic discharge protection structure 310. For a clear understanding of the invention, the lateral direction x may be defined to extend along the sectional plane A-A' of FIG. 2A or 2B. However, one skilled in the art will readily understand that within an electrostatic discharge protection structure 310' as shown in FIG. 2A, the lateral direction x must be defined as a direction that is orthogonal to the lateral direction x defined above. Moreover, as can be seen from FIG. 9, the lateral direction x can even be allowed to extend in opposite directions.The first insulation layer 200 is formed on the first surface 101 of the semiconductor body 100. The first isolation layer 200 may comprise any dielectric or a combination of dielectrics suitable for isolating the semiconductor body 100 from the electrostatic discharge protection structure 310 on the first isolation layer 200. The first insulating layer 200 may include, for example, one or any combination of an oxide, nitride, oxynitride, a high-k material, an imide, an insulating resin, or glass. The first insulation layer 200 may comprise a field dielectric such as a field oxide and / or a gate dielectric such as a gate oxide. The first isolation layer 200 may include a field oxide formed by a local oxidation of silicon (LOCOS) process, deposited oxide, or STI (shallow trench isolation), for example. The thickness of the field dielectric of the first insulation layer 200 may be in a range from 0.5 μm to 5 μm or 1 μm to 3 μm, the thickness of the gate dielectric of the first insulation layer 200 may be in a range from 5 nm to 200 nm or 40 nm to 120 nm.The second insulating layer 400 is formed on the electrostatic discharge protection structure 310 and the first insulating layer 200. The second insulation layer may include silicon nitride. The second isolation layer 400 may include a stack of first and second dielectric layers 410 and 420. According to an embodiment, the first dielectric layer 410 may include a film of tetraethylorthosilicate (TEOS) / undoped silicate glass (USG). The thickness of the first dielectric layer of the second insulation layer 400 may be in a range of 50 nm to 500 nm. The second dielectric layer 420 may include a phosphosilicate glass (PSG) or a borophosphosilicate (BPSG). The thickness of the second dielectric layer of the second insulation layer 400 may be in a range of 200 nm to 2 μm.The first electrode 500 is formed on the second insulating layer 400. In addition to the first electrode 500, the second electrode 600 is formed on the second insulation layer 400, which can be spaced apart from the first electrode 500 by the distance B (cf. also FIGS. 2A and 2B ). A passivation layer 1000 is formed on the first electrode 500 and the second electrode 600, which may comprise, for example, one or any combination of an imide, a nitride, an oxide or an oxynitride.The first electrode 500 and the second electrode 600 may be separate parts, e.g. due to lithographic patterning of a common metal wiring layer of a same wiring level, wherein the semiconductor device 10 comprises only a single metal wiring layer. The first electrode 500 and the second electrode 600 may be formed as a metal layer structure, which may consist of or contain as main constituent(s) aluminum Al, copper Cu or alloys of aluminum or copper, for example AlSi, AlCu or AlSiCu. According to other embodiments, the first electrode 500 and the second electrode 600 may include one, two, three, or more sub-layers, each sub-layer including, as a main component, at least one of nickel Ni, titanium Ti, silver Ag, gold Au, tungsten W, platinum Pt, tantalum Ta, and palladium Pd. For example, a sub-layer may include a metal nitride or a metal alloy including Ni, Ti, Ag, Au, W, Pt, Co and / or Pd.The electrostatic discharge protection structure 310 may include a series circuit of at least one polysilicon diode. As shown in FIG. 3, the electrostatic discharge protection structure 310 may include a polysilicon layer 300 on the first insulation layer 200 having first regions 316 and second regions 318 of an opposite conductivity type arranged alternately along the lateral direction x. According to the embodiment, as shown in FIG. 3, the first connection region 312 and the second connection region 314 are located in a region within the polysilicon layer 300 which is electrically contacted by the first and second contact elements 810 and 910, respectively. Consequently, the term "connection region" needs to be understood as a part of the polysilicon layer 300 forming the structure 310 for protection against electrostatic discharge. A terminal region 312 or 314 may thus be part of a first region 316 or the second region 318 within the polysilicon layer 300 forming the electrostatic discharge protection structure 310. Consequently, if the first terminal region 312 is part of a first region 316, the first terminal region 312 has the same conductivity type as the first regions 316. If the first terminal region 312 is part of a second region 318, the first terminal region 312 has the same conductivity type as the second regions 318. If the second connection region 314 is part of a first region 316, the second connection region 314 has the same conductivity type as the first regions 316. If the second connection region 314 is part of a second region 318, the second connection region 314 has the same conductivity type as the second regions 318.Specifically, the electrostatic discharge protection structure 310 may be formed by forming the polysilicon layer 300 of a first conductivity type on the first insulating layer 200. After forming the polysilicon layer 300, a mask layer (not shown), e.g., a hard mask layer or a resist layer, may be formed on the polysilicon layer 300 and is patterned by a lithographic process such that the second regions 318 are not covered by the mask layer. In a subsequent implantation process, dopants of a second conductivity type are introduced into the exposed second regions 318, which are not covered by the mask layer on the polysilicon layer 300, to form the second regions 318 of the second conductivity type. Thus, each of the first regions 316 and second regions 318 comprises first dopants of the first conductivity type, and the second regions 318 further comprise second dopants of the second conductivity type that overcompensate the first dopants of the first conductivity type. In another embodiment, each of the first regions 316 may include first dopants of the first conductivity type, and the second regions 318 may include only second dopants of the second conductivity type without overcompensating the first dopants of the first conductivity type. Herein, the first dopants are respectively introduced into the first regions 316, and the second dopants are introduced into the second regions 318 in a separate process, e.g. by ion implantation and / or diffusion, wherein overlapping regions between the first and second regions 316, 318 may comprise first and second dopants due to diffusion of the dopants.As a result, a polysilicon diode chain or row arranged in a lateral direction x with alternating pn junctions (diodes) is formed at the region boundaries of the first and second regions 316, 318 in the polysilicon layer 300. In an embodiment, the doping concentrations of the regions are adjusted such that a series connection of Zener diodes is formed within the polysilicon layer 300. By the number of consecutive diodes, each comprising a first region 316 and a second region 318, the breakdown voltage of the electrostatic discharge protection structure 310 may be adjusted.Reducing the voltage window for positive and negative voltages is important for optimal matching of the electrostatic discharge protection structure 310 to tests of a metal-oxide semiconductor device under load with an integrated diode for electrostatic discharge. The smaller the variance of the device parameters, the closer the breakdown voltage of an anti-serial diode string can be brought to a desired value, such as a maximum allowable voltage between gate and source (VGS value).If the electrical breakdown behavior of the gate oxide of the metal oxide semiconductor device under load is asymmetric, the electrical behavior of an ESD protection diode can be adjusted to the metal oxide semiconductor device under load.That is, if the metal oxide semiconductor device under load has a lower gate oxide breakdown voltage for one direction, the positive and negative voltage electrostatic discharge voltage window of the electrostatic discharge diode (ESD) may be asymmetrically selected to achieve an increased ESD HBM (human body model) capability of the metal oxide semiconductor device under load.The polysilicon layer 300 deposited on the first insulating layer 200 may have a large grain size of polysilicon. Consequently, the lateral dimension of the electrostatic discharge protection structure 310 having a poly-zener diode string may be in a range of, for example, 1 μm to 10 μm or 3 μm to 5 μm. By extending the electrostatic discharge protection structure 310 over a plurality of grain boundaries of the polysilicon layer 300, a stable breakdown characteristic of the electrostatic discharge protection structure 310 is provided. In some embodiments, a plurality of grain boundaries within the polysilicon layer 300 may result in an electron mobility in a range of 1 cm 2 / Vs to 5 cm 2 / Vs. If the granular structure of the polysilicon layer 300 is improved, the electron mobility may be increased to 50 cm 2 / Vs due to fewer grain limitations within the polysilicon layer 300. Further improvement may be achieved by depositing amorphous silicon followed by a laser melting process. Such a polycrystalline silicon is called low temperature polysilicon (LTPS). The electron mobility of a low temperature polysilicon is in a range of 100 cm 2 / Vs to 700 cm 2 / Vs.Even higher levels of electron mobility can be achieved by polycrystalline silicon with even larger grain boundary sizes. An example of such a polycrystalline silicon is a continuous-grain silicon (CGS) which results in electron mobility in a range of 500 cm 2 / Vs to 700 cm 2 / Vs. By providing a silicon with a uniform grain size within the polysilicon layer 300, values of an electron mobility may be achieved which are comparable to those within the ground region of the semiconductor body 100.The polysilicon layer 300 may thus include a low temperature polysilicon (LTPS) and / or a uniform grain size silicon (CGS).The length of the electrostatic discharge protection structure 310 between the first terminal region 312 and the second terminal region 314 may be in a range of 5 μm to 150 μm or 15 μm to 50 μm, respectively. An area of the electrostatic discharge protection structure 310 of FIGS. 2A and 2B or FIGS. 3 and 8 may be in a range of 100 μm×50 μm×2=10000 μm 2 by providing a small gate pad length of 100 μm, wherein an electrostatic discharge protection structure 310 is on two orthogonal sides (FIG. 2A ) or symmetrically on two opposite sides (FIG. 2B ) of the gate pad. The area of the electrostatic discharge protection structure 310 may be up to 500 μm×50 μm×2=50000 μm 2 or up to 2000 μm×50 μm×2=1200,000 μm 2 by providing a large gate pad length of 1000 μm. The area of the electrostatic discharge protection structure 310 does not increase the entire chip area because the diode is constructed between the metal and partially below it.An electrostatic discharge protection structure 310 having a diode width in a range between 1000 μm and 2000 μm may be integrated along the gate contact structure 510 or further within an edge termination structure of the semiconductor device 10, wherein the semiconductor device 10 may be a superjunction field effect transistor device of a metal oxide semiconductor or an insulated gate bipolar transistor (IGBT) device. Such an embodiment may be advantageous if a semiconductor device 10 having a small die area (less than 1 mm 2) is provided, wherein a robustness of the electrostatic discharge protection structure 310 with respect to HBM (human body model) tests may be in a range of 1 kV to 4 kV. Assuming a breakdown current of 1 mA per μm diode width, a robustness of the electrostatic discharge protection structure 310 with respect to HBM (human body model) tests may be in a range of 300 V to 4 kV.The area of the electrostatic discharge protection structure 310 may be appropriately selected to dissipate energy generated by an electrostatic discharge (ESD) event between the first electrode 500 and the second electrode 600.The first electrode 500 may be electrically coupled to the first contact element 810 with the first terminal region 312 of the electrostatic discharge protection structure 310 via a first contact structure 800, and the second electrode 600 may be electrically coupled to the second contact element 910 with the second terminal region 314 of the electrostatic discharge protection structure 310 via a second contact structure 900. The shunting structure 700 extends through the second insulating layer 400, wherein the first end 701 is in direct contact with the electrostatic discharge protection structure 310 and the second end 702 is not in direct electrical contact with any conduction region such as the first electrode 500 or the second electrode 600. Consequently, a first electrode 500 is formed over the second insulation layer 400, wherein the first electrode 500 is electrically coupled to the first connection region 312. In addition, a second electrode 600 is provided over the second insulation layer 400, wherein the second electrode 600 is electrically coupled to the second connection region 314. As discussed above, the first electrode 500 may include a gate contact structure 510 or a gate pad, and the second electrode 600 may include a source contact structure 610 or a source pad of transistor cells 20, as will be discussed further in detail with FIG. 9.As shown in FIG. 3, the second end 702 is in direct contact with an electrically insulating region formed by the passivation layer 1000 covering the second insulation layer 400. The second end 702 is thus electrically insulated from the first terminal region 312 and the second terminal region 314, provided that the connection of the second end 702 to the first and second terminal regions 312, 314 via the first end 701 of the shunting structure 700 and the electrostatic discharge protection structure 310 is not taken into account. In other words, there is no further conductive path from the second end 702 to the first and second connection regions 312, 314, except for the conductive path via the first end 701 and the electrostatic discharge protection structure 310. According to an embodiment, the shunting structure 700 may be embedded within an electrically insulating region formed by the second insulating layer 400 and the passivation layer 1000, wherein only the first end 701 of the shunting structure 700 is in direct electrical contact with the electrostatic discharge protection structure 310.The shunting structure 700 may be formed simultaneously with the first and second contact structures 800 and 900 by forming trenches 450, 450 a, 450 bthrough the second isolation layer 400 and the polysilicon layer 300, as discussed below. The simultaneous formation of the first and second contact structures 800 and 900 together with the shunting structure 700 leads to an advantageous manufacturing process. When the first electrode 500 and the second electrode 600 are formed on the second insulating layer 400 to be electrically coupled to the first contact structure 800 and the second contact structure 900, respectively, the bottom 501 (FIG. 3 ) of the first electrode 500 and the bottom 601 of the second electrode 600 are at a same vertical level as the second end 702 of the shunting structure 700. The second end 702 of the shunting structure 700 may be flush with the top surface 402 of the second isolation layer 400 if the second isolation layer 400 has a planarized top surface 402.Consequently, a bottom 501 of the first electrode 500 and the second end 702 of the shunting structure 700 may be at a same vertical level. Moreover, the shunting structure 700 and the first contact structure 800 may comprise a same material. In addition, the shunting structure 700 and the second contact structure 900 may include a same material. Moreover, the shunting structure 700 and the first contact structure 800 electrically coupled to the first connection region 312 may extend through or penetrate the second insulation layer 400.According to the embodiment of FIG. 3, the second connection region 314 is of a second conductivity type, wherein the first contact element 810, the second contact element 910 and the first connection region 312 are of a first conductivity type. The second contact structure 900 comprises the terminal shunting structure 920 provided to connect the pn junction between the second contact element 910 and the second terminal region 314 in parallel or in shunt, as will be discussed in more detail below.The electrostatic discharge protection structure 310 embedded between the first insulating layer 200 and the second insulating layer 400 has a high thermal impedance due to thermal insulation by materials such as PSG, TEOS, poly oxide, or field oxides. The thickness of the electrostatic discharge protection structure 310 may be, for example, in a range from 100 nm to 1000 nm or in a range from 200 nm to 600 nm, or may be in a range between 200 nm to 500 nm. Due to the small thickness of the electrostatic discharge protection structure 310 compared to its lateral dimensions, the transient heat capacity, i.e. the heat capacity that may buffer short thermal dissipation peaks, is low, which may result in a degradation of the electrostatic discharge protection structure 310 or further damage of the semiconductor device 10.Because of the provision of the shunting structure 700, the heat capacity of the electrostatic discharge protection structure 310 is increased. A thickness of the shunting structure 700 along a lateral direction (extending from the first terminal region 312 to the second terminal region 314 of the electrostatic discharge protection structure 310) may be in a range of 100 nm to 3000 nm, and a thickness of the shunting structure 700 along a vertical direction may be in a range of 1000 nm to 2000 nm or 350 nm to 3500 nm.Consequently, a ratio of a thickness of the shunting structure 700 along the vertical direction z and a thickness of the electrostatic discharge protection structure 310 along the vertical direction z may be greater than 1, greater than 2, greater than 3, or greater than 10. By providing the shunting structure 700, the effective thickness relevant to the heat capacity is increased, resulting in an improved electrostatic discharge protection structure 310 with increased thermal robustness.As can be seen from FIG. 3, the first end 701 of the shunting structure 700 is in contact with a pn junction between one of the first regions 316 and one of the second regions 318 of the electrostatic discharge protection structure 310, such that the pn junction between the respective first and second regions 316, 318 is electrically connected in parallel.A detailed view of a portion of the semiconductor device 10 of FIG. 3 is shown in FIG. 4. The shunting structure 700 includes a shunting element 710 oriented such that a first end 711 of the shunting element 710 is in electrical contact with both one of the first regions 316 and one of the second regions 318, and a second end 712 of the shunting element 710 is in direct contact with an electrically insulating region. As can be seen from FIG. 4, the shunting structure 700 may further include an intermediate region 320. The intermediate region 320 is arranged between one of the first regions 316 and one of the second regions 318 along the lateral direction x. The intermediate region 320 is further arranged between the first insulation layer 200 and the first end 711 of the shunting element 710 along the vertical direction z. Consequently, the shunting structure 700 comprises a shunting element 710 and an intermediate region 320, wherein the intermediate region 320 extends along a vertical direction z into the electrostatic discharge protection structure 310. The intermediate region 320 may further be arranged between one of the first regions 316 and one of the second regions 318 along the lateral direction x. Consequently, the shunting structure 700 may include a shunting element 710 having a first end 711 in electrical contact with both one of the first regions 316 and one of the second regions 317 and a second end 712 in direct contact with an electrically insulating region.The first end 711 of the shunting element 710 is a planar surface of the shunting element 710 facing the boundary surface between the electrostatic discharge protection structure 310 and the second insulating layer 400. The first end 711 of the shunting element 710 is a planar boundary surface between the shunting element 710 and the intermediate region 320. As can be seen from FIG. 4, the first end 711 is a planar surface flush with the boundary surface between the electrostatic discharge protection structure 310 on the polysilicon layer 300 and the second insulating layer 400.As will be explained below, the intermediate region 320 is formed by creating a trench penetrating the second insulation layer 400 and the polysilicon layer 300, wherein the trench is filled with a polysilicon or metal material. Consequently, the first end 711 is not a boundary surface between regions of different material composition. Rather, the material composition of the intermediate region 320 and the shunting element 710 may be the same. Thus, the intermediate region 320 and the shunting element 710 may comprise a same material. The intermediate region 320 may include polysilicon having a net dopant concentration that is higher than 1×10 19 cm -3. The intermediate region 320 may also include a metal material such as tungsten.As can be seen from FIG. 4, the intermediate region 320 may comprise a vertically stacked layer structure of a first polysilicon layer 322 and a second polysilicon layer 326 of a different conductivity type. Herein, the intermediate region 320 may include a metal silicide layer 324 disposed between the first and second polysilicon layers 322, 326 in a vertical direction z. Consequently, the shunting structure 700 may include the metal silicide layer 324 in contact with the electrostatic discharge protection structure 310. Due to the provision of the shunting structure 700 with the shunting element 710 and the intermediate region 320, a pn junction between one of the second regions 318 and one of the first regions 316 is shunt connected. Consequently, there is no further pn-junction or diffusion junction formed between two adjacent first and second regions 316, 318 if a shunting structure 700 is formed at the location of a previously created pn-junction between the respective first and second regions 316, 318.Specifically, the first polysilicon layer 322 may be of a second conductivity type and have a net dopant concentration that is higher than 1×10 19 cm -3. Consequently, an electrical contact is provided between the first polysilicon layer 322 and the second region 318 having the same conductivity type. Similarly, the second polysilicon layer 326 may be of a first conductivity type and may have a net dopant concentration that is greater than 1×10 19 cm -3. An electrical contact is thus provided between the second polysilicon layer 326 and the first region 316 having the same conductivity type. By providing the metal silicide layer 324 disposed between the first and second polysilicon layers 322, 326, an electrical contact is provided between the polysilicon layer 322 and the second polysilicon layer 326, since due to the high doping concentration of the first and second polysilicon layers 322, 326, a Schottky contact between the first and second polysilicon layers 322, 326 and the metal silicide layer 324 is prevented.Due to the provision of the stacked layer of the first polysilicon layer 322 of a second conductivity type on the first insulation layer 200, the metal silicide layer 324 formed directly on the first polysilicon layer 322 of a second conductivity type, and the second polysilicon layer 326 of a first conductivity type formed directly on the metal silicide layer 324, a pn junction between adjacent first and second regions 316, 318 may be shunt connected or prevented. The second polysilicon layer 326 and the shunting element 710 of the shunting structure 700 comprise the same material as polysilicon of a first conductivity type. Due to the provision of the shunting element 710 of the shunting structure 700, heat may moreover be dissipated. Consequently, the shunting structure 700 may also serve as a heat dissipation structure. The ratio of a thickness of the shunting structure 700 along a vertical direction z and a thickness of the electrostatic discharge protection structure 310 along a vertical direction z herein may be greater than 1, or may be greater than 5, or may be greater than 10, or may be greater than 20. The thickness of the polysilicon layer 300 in a vertical direction z may be in a range of 100 nm to 1000 nm. The thickness of the second insulating layer 400 may be in a range of 350 nm to 3500 nm.According to an embodiment, the shunting element 710 may include a metal material such as tungsten. In addition, the first and second contact elements 810, 910 may also include a metal material such as tungsten. In contrast to the case where a shunting element 710 or first and second contact elements 810, 910 are provided with a highly doped polysilicon material of a first conductivity type, if a shunting element 710 or first and second contact elements 810, 910 are provided with a metal material such as tungsten (with a TiSi2and a TiN barrier), an additional contact implantation of ions of a first conductivity type such as P or As ions may be performed to electrically contact the first terminal region 312 of a first conductivity type (with a net dopant concentration of about 1*10 17 to 1*10 19 cm -3). Additional contact implantation of ions of a second conductivity type, such as B ions, may not be necessary to electrically contact the second terminal region 314 of a second conductivity type if it has a net dopant concentration of about 1*10 19 to 1*10 21 cm -3. If second regions of a second conductivity type are provided with lower net dopant concentrations, an additional contact implantation of ions of a second conductivity type, such as B ions, may be performed at a dose higher than 1*10 15 cm -2. Thus, as can be seen from FIG. 4, the shunting element 710 (and accordingly the first and second contact elements 810, 910) may extend into the polysilicon layer 300 to the first polysilicon layer 322 (or accordingly 822 and 922), wherein the contact implantation is performed with the first polysilicon layer 322, 822 or 922. In other words, the intermediate region 320, 820 and 920 consequently has a sandwich structure of the first polysilicon layer 322, 822, 922 and a metal material of the shunting element 710 or the first and second contact elements 810, 910.FIG. 5 is a schematic plan view of a portion of a semiconductor device 10 according to an embodiment, wherein FIG. 6 is a schematic cross-sectional view of a portion of a semiconductor device 10 taken along a section plane B-B' of FIG. 5. the embodiment shown in FIGS. 5 and 6 differs from the embodiment shown in FIGS. 3 and 4 in that the shunting structure 700 includes two shunting elements 710 having first ends 711 in electrical contact with one of the first regions 316 and one of the second regions 318 and second ends 712, respectively, which are electrically interconnected by a shunting element 720.As can be further seen from FIG. 6, the first electrode 500 and the second electrode 600 are simultaneously formed together with the shunting element 720, for example, by structuring a same metal layer. The embodiment as shown in FIGS. 5 and 6 may be used if the first electrode 500 and the second electrode 600 comprise a metal layer having an extension along the vertical direction z of less than 2 μm. The internal structure of the shunting structure 700 and respective intermediate regions 320 extended into the electrostatic discharge protection structure 310 may be the same as described above with respect to FIGS. 3 and 4.However, as can be seen from FIG. 6, due to the provision of two shunting elements 710 that separately contact one of the first regions 316 and one of the second regions 318, a pn junction still exists between adjacent first and second regions 316 and 318, but is shunt connected across the first shunting element 710, the shunting element 720, and the second shunting element 710. In the embodiment as shown in FIGS. 5 and 6, a seven cell pn diode cascade is shown. The polysilicon layer 300 may have a thickness of about 100 to 1000 nm or 300 to 600 nm. The cell pitch of each diode formed by respective first and second regions 316, 318 may be in a range between 1 μm (in the case of a polysilicon layer 300 having a thickness in a vertical direction z of about 100 nm) to 6 μm or 3 μm to 5 μm. The extension in lateral direction x of the shunting structure 700 comprising polysilicon filled contact trenches may be in a range between 100 nm to 3000 nm or 150 nm to 1000 nm. The respective pn junctions are shorted by the metal / n ++- poly plug / silicide / p ++- plugs as described above.According to an embodiment, the electrostatic discharge protection structure 310 may include at least 2 or 3 first regions 316 and at least 2 or 3 second regions 318, or may include at least 5 first regions 316 and at least 5 second regions 318, or may include at least 7 first regions 316 and at least 7 second regions 318.FIG. 7A is a schematic plan view of a portion of a semiconductor device 10 according to another embodiment, and FIG. 7B is a schematic cross-sectional view of a portion of a semiconductor device 10 taken along a second plane C-C' of FIG. 7A.As can be seen from FIGS. 7A and 7B, the semiconductor device 10 of FIGS. 7A and 7B is similar to the semiconductor device 10 as illustrated in FIGS. 3 and 4 subject to providing a higher number of first and second regions 316, 318. The embodiment as shown in FIGS. 3 and 4 and in FIGS. 7A and 7B may be used if the first electrode 500 and the second electrode 600 comprise a metal layer having an extension along the vertical direction z of at least 3-5 μm. An example of a first electrode 500 and a second electrode 600 having such a thickness of metallization is the provision of the first electrode 500 as a gate contact structure 510 or a gate pad and the provision of the second electrode 600 as a source contact structure 610 or a source pad, as will be discussed below with reference to FIG. 9. Due to the different metal design rules, the shunting elements 720, as shown in FIGS. 5 and 6, may not be formed between the first electrode 500 and the second electrode 600 in the same metallization patterning process. Thus, the pn junction between one of the first regions 316 and one of the second regions 318 is only shunt connected by a shunting element 710 without providing a shunting element 720. The structure of the shunting structure 700 is the same as described in detail above with respect to FIGS. 3 and 4.As can be further seen from FIG. 7B, the structures of the first contact structure 800, the second contact structure 900 with the second contact element 910, and the terminal shunting structure 920 and the shunting structure 700 are the same. Consequently, the first contact structure 800, the second contact structure 900 and the shunting structure 700 may be formed simultaneously. As can be seen from FIGS. 7A and 7B, a seven cell pn diode cascade is provided. The thickness of the polysilicon layer 300 is in a range between 100 nm-1000 nm or 200-600 nm or 300-500 nm, the cell pitch of each diode is in a range between 1 μm to 6 μm or 3-5 μm, whereas the length of the polysilicon-filled contact trenches of the shunting structure 700 in a lateral direction x is in a range between 100 nm to 3 μm or 250 nm to 1000 nm, wherein the corresponding pn junctions between a respective first and second region 316, 318 are significantly overlapped.As can be seen from the embodiment as shown in Figures 7A and 7B, the polysilicon plugs can be positioned embedded locally in two pn junctions. Moreover, with respect to the thickness of the polysilicon layer 300 increased from 400 to 1000 nm, an implanted p ++- contact zone of a p-body together with the silicide TiSi 2 are relevant, since they do not disappear in the field oxide of the first insulation layer 200.Thus, a bidirectional asymmetric electrostatic discharge structure having k gate-source positive voltage pn blocking junctions and only, for example, (k-1) gate-source negative voltage pn blocking junctions may be provided. In previous devices, the ESD HBM capability was about 2.3 kV for positive pulses, but only about 1.7 kV for negative gate pulses. Therefore, the total ESD capability was limited to 1.7 kV. There is some freedom in the selection of the negative breakdown voltage of the ESD protection diode. Generally, the ESD capability of an ESD diode cascade improves as the breakdown voltage of the diode is reduced; for example, a high voltage transistor including an ESD diode with (k-2) stripes has an ESD HBM (Human Body Model) capability that is higher than 3 kV, and a high voltage transistor including an ESD diode with k stripes has an ESD HBM capability of 2.3 kV. Thus, by providing the above-described embodiment, the above limitations can be overcome.FIG. 8A is a schematic plan view of a portion of a semiconductor device 10 according to another embodiment, and FIG. 8B is a schematic cross-sectional view of a portion of a semiconductor device 10 taken along a second plane D-D' of FIG. 8A.As can be seen from FIGS. 8A and 8B, the shunting structure 700 of FIGS. 7A and 7B has been omitted, wherein a bidirectional asymmetric electrostatic discharge structure having k pn blocking junctions for a positive gate-source voltage and only, for example, (k-1) pn blocking junctions for negative gate-source voltage is provided by the specific structure of the second contact structure 900 having the second contact element 910 and the terminal shunting structure 920. Herein, the terminal shunting structure 920 shunt connects a pn junction between the second terminal region 314 of a second conductivity type and the second contact element 910 of the first conductivity type. Thus, for a transistor device, the breakdown voltage of an electrostatic discharge diode (ESD) may be set to be about VDB=k*VDB0(=k pn junctions each having VDBO). The negative breakdown voltage of an electrostatic discharge diode (ESD) is set to be about (k-1)*VDB0(=(k-1) pn junctions each having VDBO). Specifically, this means that two pn junctions of the monolithically integrated Zener diode cascade are designed from polysilicon with 2*k pn junctions with complementary contact zones or connections. FIG. 9 is a schematic cross-sectional view of a portion of a semiconductor device 10 taken along a sectional plane A'-A of FIG. 2A or 2B, according to an embodiment.As can be seen from FIG. 9, the first insulation layer 200 may be a gate dielectric. The first insulation layer 200 may thus include one of a gate dielectric and a field dielectric, the first insulation layer 200 may have a thickness in a vertical direction z in a range from 5 nm to 3000 nm. The electrostatic discharge protection structure 310 may be formed on the first insulation layer 200, which results in a reduced thermal transient impedance due to the increased thermal coupling between the electrostatic discharge protection structure 310 and the semiconductor body 100. The gate dielectric may be a silicon oxide having a thickness in a range from 5 nm to 200 nm or in a range from 40 nm to 120 nm. Furthermore, the semiconductor device 10 comprises transistor cells 20 arranged in an overlap region between the source contact structure 610 and the semiconductor body 100. Each of the transistor cells 20 includes a gate electrode 330 formed on the first insulation layer 200, source zones 150 that are in contact with the first surface 101 of the semiconductor body 100 and extend into the semiconductor body 100, and body zones 160 in which the source zones 150 are embedded. The source zones 150 are of the first conductivity type and the body zones 160 are of the second conductivity type. Moreover, at the second surface 102 of the semiconductor body 100, the drain region 110 of the first conductivity type is provided. The drift region 120 is formed between the drain region 110 and the body zones 160 and is of a first conductivity type. In the case of a superjunction device, pillars or bubbles of the first conductivity type and the second conductivity type may be implemented below both the semiconductor well region 140 and the array of active transistor cells. Moreover, pillars or bubbles of the second conductivity type may overlap with the semiconductor well region 140. The well region 140 is of a second conductivity type and is used as an electrical shield. Moreover, body contact zones 160 aare provided to provide an electrical contact between the second contact structure 900 connected to the source contact structure 610 and the respective body zones 160. The body contact zones 160 aare formed by an ion implantation process of dopants of a second conductivity type, for example, as discussed in detail below.According to an embodiment, the gate electrode 330 is provided simultaneously with the electrostatic discharge protection structure 310 and may be part of the polysilicon layer 300. The second contact structure 900 is provided to electrically connect the source contact structure 610 to the second terminal region 314 of the electrostatic discharge protection structure 310. The second contact structure 900 may further be provided to connect the source contact structure 610 to the source zones 150 of the transistor cells 20. Consequently, the first electrode 500 may include a gate contact structure 510, and the second electrode 600 may include a source contact structure 610 of transistor cells 20.Although a multi-layer metallization structure is not illustrated, the electrostatic discharge protection structure 310 may be used in discrete semiconductor devices or integrated circuits with multi-layer wiring systems as described above when polysilicon plugs are used.FIG. 10 is a schematic flow diagram to illustrate a method 2000 for manufacturing a semiconductor device 10.It will be appreciated that although method 2000 is illustrated and described below as a series of acts or events, the illustrated order of such acts or events is not to be interpreted in a limiting sense. For example, some operations may occur in different orders and / or concurrently with other operations or events other than those illustrated and / or described herein. In addition, not all illustrated operations may be required to practice one or more aspects of embodiments of the disclosure herein. Also, one or more of the operations depicted therein may be performed in one or more separate operations and / or phases.FIG. 10 illustrates a schematic flow diagram for illustrating a method 2000 for producing a semiconductor device.Process feature S 100 includes providing a semiconductor body having a first surface and a second surface opposite the first surface.Process feature S 110 includes forming a first insulation layer over the first surface of the semiconductor body.Process feature S 120 includes forming an electrostatic discharge protection structure over the first insulating layer, the electrostatic discharge protection structure having a first terminal region of a first conductivity type and a second terminal region of a second conductivity type opposite the first conductivity type.As can be seen from FIGS. 11A to 11J, a method for manufacturing the semiconductor device 10 according to an embodiment will be described with reference to cross-sectional views for illustrating selected processes.In FIG. 11A, a semiconductor body 100 is provided as described above.As illustrated in FIG. 11B, the first insulating layer 200, such as a silicon oxide layer, is formed on the semiconductor body 100. The oxide layer of the first insulation layer 200 may be formed by a field oxidation or deposition process or may be formed as a gate oxide layer. The oxide layer of the first isolation layer 200 may also be local oxidation of silicon (LOCOS) or shallow trench isolation (STI).As shown in FIG. 11C, a polysilicon layer 300 of a first conductivity type is formed on the first insulating layer 200. The polysilicon layer 300 may be patterned to have a structure within the lateral plane as shown in FIG. 2A or 2B (see the structures in FIGS. 2A and 2B defined by the dashed lines). The thickness of the polysilicon layer 300 in a vertical direction z may be in a range of 100 nm to 1000 nm or 200 nm to 600 nm or 200 nm to 500 nm. The thickness of the polysilicon layer 300 may be limited by the penetration depth of the dopants of the first conductivity type in an ion implantation and diffusion process.As shown in FIG. 11D, the electrostatic discharge protection structure 310 may be formed on the first insulating layer 200 by an implantation process to form first regions 316 and second regions 318 as described above.As can be seen from FIG. 11E, the second insulation layer 400 is formed on the polysilicon layer 300. As discussed above, the second isolation layer 400 may include a first dielectric layer 410 and a second dielectric layer 420, wherein the first dielectric layer 410 may include a USG layer having a thickness in a vertical direction z in a range between 50 nm to 500 nm or 200 nm to 400 nm. The second dielectric layer 420 may include a BPSG layer having a thickness in a range of 200 nm to 2000 nm or 1100 nm to 1300 nm. The first and second dielectric layers 410 and 420 may further include the materials or a structure as described above.In FIG. 11F, a trench 450 is formed penetrating the second insulating layer 400 and the polysilicon layer 300. The trench 450 may extend into the polysilicon layer 300 to a distance of 300 nm. The trench 450 may completely penetrate the polysilicon layer 300 to reach the first insulation layer 200, as can be seen from FIG. 11F. However, the trench 450 may also not extend entirely to the first insulation layer 200, but may only reach the top surface of the remaining polysilicon layer 300 forming the first polysilicon layer 322 after implantation of dopants of a second conductivity type, as illustrated in FIG. 11G. The trench 450 may be formed simultaneously together with the trenches 450 aand 450 bto be filled with the first contact structure 800 and the second contact structure 900, respectively.As can be seen from FIG. 11G, the first polysilicon layer 322 is formed in the trench 450. Simultaneously, a first polysilicon layer 822 and 922 may be formed in the trenches 450 aand 450 b, respectively. The first polysilicon layers 322, 822, and 922 may be formed either by depositing undoped polysilicon or polysilicon having a net intrinsic dopant concentration, or may be formed by creating trenches 450, 450 a, and 450 b, which do not extend all the way to the first isolation layer 200, leaving the respective polysilicon layers 322, 822, and 922. The remaining first polysilicon layers 322, 822, and 922 may then be treated by ion implantation to increase the net dopant concentration of the respective first polysilicon layers 322, 822, and 922. As discussed above, a high net dopant concentration of the first polysilicon layers 322, 822, and 922 prevents a Schottky contact from forming to a metal silicide layer 324 to be formed on the first polysilicon layers 322, 822, and 922. Thus, the net dopant concentration of the first polysilicon layer 322, 822, and 922 may be higher than 1×10 19 cm -3. According to the embodiment of FIG. 9, the implantation of ions of a second conductivity type to form the first polysilicon layers 322, 822 and 922 may be performed simultaneously with the implantation of ions of a second conductivity type to form the body contact zones 160 ain the same process.As can be seen from FIG. 11H, a metal silicide layer 324, 824, and 924 is deposited on the first polysilicon layer 322, 822, and 922 of a first conductivity type in the trenches 450, 450 a, and 450 b, respectively.As can be seen from FIG. 11I, the trenches 450, 450 aand 450 bare filled with a polysilicon layer of a first conductivity type, thus forming the second polysilicon layers 326, 826 and 926 together with a shunting element 710, the first contact element 810 and the second contact element 910, respectively. The net dopant concentration of the second polysilicon layer 326, 826 and 926 may be higher than 1×10 19 cm -3. The net dopant concentration of the shunting element 710, the first contact element 810, and the second contact element 910 may be higher than 1×10 19 cm -3. Although the first contact structure 800, the second contact structure 900, and the shunting structure 700 have been described as being simultaneously formed and having the same structure, the shunting structure 700 may be omitted as can be seen from FIGS. 8A and 8B. It is also possible that only the second contact structure 900 is provided in a manner as described above.As can be seen from FIG. 11J, after filling the trenches 450, 450 aand 450 b, the fill material such as polysilicon of the trenches 450, 450 aand 450 bmay be removed by a planarization process, e.g., by a chemical mechanical polishing (CMP) process. By this process, a planarized top surface 402 of the second isolation layer 400 may be formed with first and second contact structures 800, 900 and the shunting structure 700. The second end 702 of the shunting structure 700 may be in direct contact with the passivation layer 1000 covering the first electrode 500, the second insulation layer 400, and the second electrode 600.As can be seen from the above description of the manufacturing method and the respective embodiments, the first contact element 810 and the second contact element 910 may be of a same conductivity type. Further, the first terminal region 312 and the second terminal region 314 may be of opposite conductivity types. The first electrode 500 may include a gate contact structure 510, and the second electrode 600 may include a source contact structure 610 of transistor cells 20. The gate contact structure 510 and the source contact structure 610 comprise a metal layer having an extension along the vertical direction z of at least 3 μm. The electrostatic discharge protection structure 310 may include a polysilicon layer 300. The first contact element 810 and the second contact element 910 may comprise polysilicon. The terminal shunting structure 920 may include polysilicon having a net dopant concentration that is greater than 1×10 19 cm -3. The terminal shunting structure 920 may include a metal. The terminal shunting structure 920 may include a vertically stacked layer structure of a first polysilicon layer 922 and a second polysilicon layer 926 of a different conductivity type. The terminal shunting structure 920 may further include a metal silicide layer 924 disposed between the first and second polysilicon layers 922, 926.As described above, an asymmetric electrostatic discharge protection structure is provided to satisfy an enhanced ESD HBM (human body model) capability for power metal oxide semiconductor devices. The ESD diode breakdown voltage may be set to about k*VDB0, which is achieved by providing k pn junctions with a breakdown voltage of VDBO each. Therefore, the ESD diode negative breakdown voltage can be set to about (k-1) to (k-3)*VDB0, which is achieved by providing (k-1) to (k-3) pn junctions having a breakdown voltage of VDBO, respectively. According to the embodiment of FIGS. 8A and 8B, the ESD diode negative breakdown voltage may be set to about (k-1)*VDBO, which is achieved by providing (k-1) pn junctions having a breakdown voltage of VDBO, respectively. Since one or two pn junctions of the monolithically integrated Zener diode cascade of polysilicon with a total of 2*k pn junctions are electrically short-circuited by the introduction of electron-hole converters, the asymmetrical ESD protection behavior can be achieved. This significantly increases ESD windows for negative pulses at the gate pin.

Claims

A semiconductor device (10) comprising: a semiconductor body (100) having a first surface (101) and a second surface (102) opposite the first surface (101), a first insulation layer (200) over the first surface (101) of the semiconductor body (100), and an electrostatic discharge protection structure (310) over the first insulation layer (200), wherein the electrostatic discharge protection structure (310) has a first terminal region (312) of a first conductivity type and a second terminal region (314) of a second conductivity type opposite the first conductivity type, wherein at least two first regions (316) of the second conductivity type and at least two second regions (318) of the first conductivity type are alternately arranged between the first terminal region (312) and the second terminal region (314) along a lateral direction (x), and further comprising: a second insulating layer (400) over the electrostatic discharge protection structure (310), a first electrode (500) and a second electrode (600) over the second insulating layer (400), wherein the first electrode (500) is electrically coupled to the first terminal region (312) via a first contact element (810) and the second electrode (600) is electrically coupled to the second terminal region (314) via a second contact element (910), and a terminal shunting structure (920) electrically connecting a junction between the second terminal region (314) and the second contact element (910) in parallel, wherein the first contact element (810) and the second contact element (910) comprise polysilicon.The semiconductor device (10) of claim 1, wherein the second contact element (910) is of the first conductivity type and the terminal shunting structure (920) electrically shunts a pn junction between the second terminal region (314) and the second contact element (910).The semiconductor device (10) of any of claims 1 to 2, wherein the first electrode (500) comprises a gate contact structure (510) and the second electrode (600) comprises a source contact structure (610) of transistor cells (20).The semiconductor device (10) according to any one of the preceding claims, wherein the electrostatic discharge protection structure (310) comprises a polysilicon layer (300).The semiconductor device (10) of any preceding claim, wherein the terminal shunting structure (920) comprises polysilicon having a net dopant concentration greater than 1×10 19 cm -3.The semiconductor device (10) of any preceding claim, wherein the terminal shunting structure (920) comprises a metal.The semiconductor device (10) of any preceding claim, wherein the terminal shunting structure (920) comprises a vertically stacked layered structure of a first polysilicon layer (922) and a second polysilicon layer (926) of a different conductivity type.The semiconductor device (10) of claim 7, wherein the terminal shunting structure (920) further comprises a metal silicide layer (924) disposed between the first and second polysilicon layers (922, 926).The semiconductor device (10) of any preceding claim, further comprising a shunting structure (700) electrically shunting a pn junction between one of the first regions (316) and one of the second regions (318) of the electrostatic discharge protection structure (310).The semiconductor device (10) of claim 9, wherein the shunting structure (700) comprises an intermediate region (320), the intermediate region (320) being extended along a vertical direction (z) into the electrostatic discharge protection structure (310).The semiconductor device (10) of claim 10, wherein the intermediate region (320) is arranged between one of the first regions (316) and one of the second regions (318) along the lateral direction (x).The semiconductor device (10) of claim 10 or 11, wherein the intermediate region (320) has a same structure as the terminal shunting structure (920).The semiconductor device (10) of any one of claims 9 to 12, wherein a ratio of a thickness of the shunting structure (700) along a vertical direction (z) and a thickness of the electrostatic discharge protection structure (310) along a vertical direction (z) is greater than 1.The semiconductor device (10) according to any one of the preceding claims, wherein the first insulation layer (200) comprises one of a gate dielectric or a field dielectric, wherein the first insulation layer (200) has a thickness in a vertical direction (z) in a range of 5 nm to 3000 nm.A method (2000) of manufacturing a semiconductor device (10), comprising: providing a semiconductor body (100) having a first surface (101) and a second surface (102) opposite the first surface (101); forming a first insulation layer (200) over the first surface (101) of the semiconductor body (100); forming an electrostatic discharge protection structure (310) over the first insulation layer (200), wherein the electrostatic discharge protection structure (310) has a first terminal region (312) of a first conductivity type and a second terminal region (314) of a second conductivity type opposite the first conductivity type, wherein at least two first regions (316) of the second conductivity type and at least two second regions (318) of the first conductivity type are arranged alternately between the first connection region (312) and the second connection region (314) along a lateral direction (x) and further comprising: forming a second insulation layer (400) over the structure (310) for protection against electrostatic discharge, forming a first electrode (500) and a second electrode (600) over the second insulation layer (400), wherein the first electrode (500) is electrically coupled to the first connection region (312) via a first contact element (810) and the second electrode (600) is electrically coupled to the second connection region (314) via a second contact element (910), and forming a connection shunting structure (920), connecting a junction between the second terminal region (314) and the second contact element (910) electrically in parallel, wherein the first contact element (810) and the second contact element (910) comprise polysilicon.

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