SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF

Abstract

A method for manufacturing a semiconductor component, comprising the following steps: forming a first gate structure (40) and a second gate structure over a portion of a first fin structure (20A, 210) and a portion of a second fin structure (20B, 220) arranged over a substrate (10), extending in a first direction, being arranged parallel to one another in a second direction intersecting the first direction, and protruding from an insulating separation layer (30), the first and second gate structures extending in the second direction and being arranged parallel to one another in the first direction; forming an insulating interlayer (50) over the first and second gate structures (40) and the first and second fin structures (20B, 220);Forming a first mask layer having a first opening over the insulating interlayer (50), the first opening being located over the first and second gate structures (40); separating the first and second gate structures (40) through the first opening and etching the insulating separation layer (30) and the insulating interlayer (50) disposed between the first gate structure and the second gate structure through the first opening to form a first recess; forming an insulating layer in the first recess; forming a second mask layer having a second opening to expose a portion of the insulating layer in the first recess and a portion of the insulating interlayer (50), the second opening being located over the first fin structure (20A, 210);Etching the exposed portion of the insulating interlayer (50) through the second opening to create at least one second recess above the first fin structure (20A, 210); and depositing a conductive material in the at least one second recess to create a first source / drain contact layer (80, 810).

Description

Field of the InventionThe invention relates to methods of manufacturing semiconductor devices and semiconductor devices, and more particularly to self-aligned contact (SAC) structures over source / drain (S / D) regions and methods of manufacturing the same.BACKGROUND OF THE INVENTIONAs the dimensions of semiconductor devices are reduced, SAC has found wide application in the fabrication of, for example, S / D contacts that are disposed in a field effect transistor (FET) closer to gate structures. Normally, a SAC is formed by patterning an ILD (inter-layer) layer, under which a contact etch stop layer (CESL) has been formed over the gate structure having sidewall spacers. The first etch of the ILD layer terminates at the CESL, and then the CESL is etched to form the SAC. As the device density increases (i.e., the dimensions of the semiconductor device become smaller), the thickness of the sidewall spacers becomes thinner, which may result in a short circuit between the S / D contact and the gate electrodes. The separation between two adjacent S / D contacts has become tight. Therefore, SAC structures and fabrication methods need to be provided with improved electrical isolation between the S / D contacts.US 2015 / 0 235 106 A1 discloses a method for producing a semiconductor component in which the source / drain and gate of adjacent transistors are separated with a common cut.US 2013 / 0 015 529 A1 discloses a semiconductor component structure and a method for producing the same. The method comprises: forming at least one continuous gate line on a semiconductor substrate; forming a gate spacer surrounding the gate line; forming source / drain regions in the semiconductor substrate on both sides of the gate line; forming a conductive spacer surrounding the gate spacer; and performing electrical isolation between the devices in a predetermined region, wherein isolated portions of the gate line form gates of the respective devices and isolated portions of the conductive spacer form contacts of the respective devices.For technological background, reference is made to US 2013 / 0 164 924 A1.Brief Description of the DrawingsThe present invention will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale and are for explanation purposes only. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1A to 8D show various stages of an exemplary sequential manufacturing process for a semiconductor device according to an embodiment of the present invention.FIGS. 9 and 10 show exemplary layout structures of a semiconductor device according to an embodiment of the present invention.FIGS. 11A to 15D show various stages of an exemplary sequential manufacturing process for a semiconductor device according to an embodiment of the present invention.FIGS. 16A to 20D show various stages of an exemplary sequential manufacturing process for a semiconductor device according to an embodiment of the present invention.FIGS. 21A to 21D show an exemplary structure of a semiconductor device according to an embodiment of the present invention.Detailed DescriptionIt should be understood that the following description provides many different embodiments or examples for implementing different features of the invention. Specific embodiments or examples of components and arrangements will be described below to simplify the present illustration. For example, the dimensions of elements are not limited to the specified range or values, but may be dependent on process conditions and / or desired characteristics of the device. In addition, the formation of a first element over or on a second element in the description below may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. For simplicity and clarity, different elements may be arbitrarily drawn at different scales.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly in a similar manner. Moreover, the term "made of" may mean either "comprises" or "consisting of".FIGS. 1A to 8D show various stages of an exemplary sequential manufacturing process for a semiconductor device according to an embodiment of the present invention.FIGS. 1A to 1C show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view, FIG. 1B is a sectional view taken along the line X 1-X 1 of FIG. 1A, and FIG. 1C is a sectional view taken along the line Y 1-Y 1 of FIG. 1A.FIGS. 1A to 1C show a structure of a semiconductor device after the formation of gate structures. In FIGS. 1A through 1C, a gate structure 40 is formed over a channel layer, for example, a portion of a fin structure 20, formed over a substrate 10. The gate structure 40 is disposed over the fin structure 20 in the Z direction. A plurality of gate structures 40 extend in the Y direction and are arranged parallel to each other. The plurality of gate structures 40 are spaced apart from each other in the X direction. A plurality of fin structures 20 extend in the X direction and are arranged parallel to each other. The plurality of fin structures 20 are spaced apart from each other in the Y direction, as shown in FIG. 1A. The thickness (height H 1) of the gate structures 40 is in the range of about 15 nm to about 50 nm in some embodiments. In one embodiment of the present invention, the gate structure 40 is a metal layer that includes a gate dielectric layer (see FIG. 1D ) formed by one or more layers of dielectric materials and a metal gate electrode (see FIG. 1D ) formed by one or more layers of conductive materials. The metal gate structures 40 further include a capping insulating layer disposed over the metal gate electrode in some embodiments. The gate structure 40 (shown in FIG. 1D ) is fabricated using the gate replacement technology in some embodiments. In some embodiments, the gate structure 40 includes a gate dielectric layer and a polysilicon gate electrode. The width of the gate structure 40 is in the range of about 5 nm to about 15 nm in some embodiments.As shown in FIG. 1B, sidewall spacers 42 (not shown in FIG. 1A ) are formed on both sidewalls of the gate structure 40. The layer thickness of the sidewall spacers 42 at the bottom of the sidewall spacers is in the range of about 1 nm to about 10 nm in some embodiments and is in the range of about 2 nm to about 8 nm in other embodiments.As shown in FIGS. 1B and 1C, a dielectric separation layer 30 is formed over the substrate 10. A portion of the fin structure 20 is embedded in the dielectric separation layer 30, and an upper portion (channel layer) of the fin structure 20 protrudes from the dielectric separation layer 30. In addition, the gate structure 40 is formed over the dielectric isolation layer 30.Referring now to FIGS. 1A through 1C, two gate structures 40 and four fin structures 20 are shown. However, the number of the gate structures 40 and the fin structures 20 is not limited to two and four, respectively.FIG. 1D shows an exemplary structure of the metal gate structure 40. the metal gate structure 40 includes a gate dielectric layer 13 and a metal gate electrode 17. The metal gate electrode 17 includes one or more layers of a metal material such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, or other conductive materials. The gate dielectric layer 13 is disposed between the channel layer of the fin structure 20 and the metal gate electrode 17 and includes one or more layers of metal oxides, such as a high-k metal oxide. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof. In some embodiments, an interlayer dielectric layer 11 made of, for example, silicon dioxide is formed between the channel layer and the gate dielectric layer.In some embodiments, one or more work function adjustment layers 15 are laminated between the gate dielectric layer 13 and the metal gate electrode 17. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more elements / compounds selected from the group consisting of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as the work function adjustment layer, and for the p-channel FET, one or more elements / compounds selected from the group consisting of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as the work function adjustment layer.A capping insulating layer 19 disposed over the metal gate electrode 17 includes one or more layers of an insulating material, such as silicon nitride-based materials, including SiN, SiCN, and SiOCN.The material for the sidewall spacer 42 includes one or more compounds selected from the group consisting of SiO 2, SiN, SiOC, and SiOCN. Moreover, as shown in FIGS. 1B and 1C, a first ILD layer 50 is formed over the dielectric isolation layer 30, and the gate structures 40 are embedded in the ILD layer 50. In FIG. 1A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.The structure comprising the gate structure 40 of FIGS. 1A to 1C may be fabricated with the following steps. In this embodiment, fin field effect transistors (FinFETs) fabricated with a gate replacement process are used.First, a fin structure 20 is formed over a substrate 10. The fin structure 20 has a lower region and an upper region as a channel region. The substrate is, for example, a p-type silicon substrate having a doping concentration in the range of about 1×10 15 cm -3 to about 1×10 18 cm -3. In other embodiments, the substrate is, for example, an n-type silicon substrate having a doping concentration in the range of about 1×10 15 cm -3 to about 1×10 18 cm -3. Alternatively, the substrate may comprise another elemental semiconductor such as germanium; a compound semiconductor comprising Group IV-IV compound semiconductors such as SiC and SiGe, and Group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In one embodiment, the substrate is a silicon layer of a silicon-on-insulator (SOI) substrate.After the fin structure is formed, an insulating isolation layer 30 is formed over the fin structure. The dielectric separating layer is also referred to as STI (shallow trench isolation). The dielectric separation layer comprises one or more layers of insulating materials such as silicon oxide, silicon oxynitride, or silicon nitride, which are formed by LPCVD (Low Pressure Chemical Vapor Deposition), plasma CVD, or flowable CVD. The dielectric separation layer may be made of one or more layers of spin-on glass (SOG), SiO, SiON, SiOCN and / or fluorosilicate glass (FSG).After the dielectric isolation layer is formed over the fin structure, a planarization process is performed to remove a portion of the dielectric isolation layer. The planarization process may include chemical mechanical polishing (CMP) and / or etchback. Then, the dielectric separation layer is further removed (recessed) so that the top portion of the fin structure is exposed.A dummy gate structure is formed over the exposed fin structure. The dummy gate structure includes a dummy gate electrode layer made of polysilicon and a dummy gate dielectric layer. In addition, sidewall spacers including one or more layers of insulating materials are formed on sidewalls of the dummy gate electrode layer. After the dummy gate structure is formed, the fin structure not covered by the dummy gate structure is recessed under the top surface of the dielectric isolation layer. An S / D region is then formed over the recessed fin structure using an epitaxial growth method. The S / D region may include a stressed material to apply stress to the channel region.An ILD layer 50 is then formed over the dummy gate structure and the S / D region. After planarization, the dummy gate structure is removed, forming a gate gap. Then, a metal gate structure including a metal gate electrode and a gate dielectric layer such as a high-k dielectric layer is formed in the gate space.FIGS. 2A to 2C show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 2A is a plan view, FIG. 2B is a sectional view taken along the line X 1-X 1 of FIG. 2A, and FIG. 2C is a sectional view taken along the line Y 1-Y 1 of FIG. 2A. In FIG. 2A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.After the gate structures 40 are formed over the fin structures 20 and the dielectric isolation layer 30, the process shown in FIGS. 2A-2C cuts the gate structures 40 into multiple portions for respective transistors. Over the structure shown in FIGS. 1A to 1C, a mask layer, for example, a photoresist layer or a hard mask layer having an opening extending in the X direction is formed, and then patterning processes such as dry etching and / or wet etching are performed to cut the gate structures. Then, the first ILD layer 50 and the dielectric separation layer 30 are also etched to form an opening 45. The dielectric isolation layer 30 is etched (recessed) to a depth D 1 that is less than about 80 nm and is in the range of about 30 nm to about 60 nm in some embodiments. The width W 1 of the opening 45 is in the range of about 20 nm to about 80 nm in some embodiments. In some embodiments, the dielectric separation layer 30 is not etched (i.e., D1=0).FIGS. 3A to 3C show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 3A is a plan view, FIG. 3B is a sectional view taken along the line X 1-X 1 of FIG. 3A, and FIG. 3C is a sectional view taken along the line Y 1-Y 1 of FIG. 3A. In FIG. 3A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.After the gate patterns 40 are cut into a plurality of gate pattern parts, as shown in FIGS. 3A to 3C, the opening 45 is filled with an insulating material to produce a separator 60. The separator 60 includes one or more layers of an insulating material that has a higher etch selectivity to the materials of the dielectric separator 30 and the first ILD layer 50. These materials include silicon nitride-based materials such as SiN, SiON, or SiOCN, or aluminum-based materials such as aluminum oxide (which may be collectively referred to as AlO), aluminum oxynitride (which may be collectively referred to as AlON), or aluminum nitride (which may be collectively referred to as AlN). In one embodiment, SiN is used for the separator 60.To form the separator 60, a protective layer of an insulating material, for example, SiN, is deposited over the structure of FIGS. 2A-2C, and then a planarization process, such as etch back and / or CMP, is performed. The thickness T 1 of the separator 60 is in the range of about 30 nm to about 60 nm in some embodiments.FIGS. 4A to 4D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 4A is a plan view, FIG. 4B is a sectional view taken along the line X 1-X 1 of FIG. 4A, FIG. 4C is a sectional view taken along the line Y 1-Y 1 of FIG. 4A, and FIG. 4D is a sectional view taken along the line X 2-X 2 of FIG. 4A. In FIG. 4A, the substrate 10, the dielectric separation layer 30, the first ILD layer 50, and a mask layer 70 are not illustrated.After the separator 60 is formed, a mask layer 70 having an opening 75 extending in the Y direction, for example, a photoresist layer or a hard mask layer, is formed over the structure shown in FIGS. 3A to 3C. The opening 75 corresponds to sources / drains of respective transistors. The edges of the opening 75 along the Y direction may or may not overlap the gate structures 40.In the present embodiment, a first transistor TR 1, a second transistor TR 2, a third transistor TR 3, and a fourth transistor TR 4 are fabricated as illustrated in FIG. 4A (by broken lines). The first transistor TR 1 and the second transistor TR 2 use one and the same S / D region 25A, and the third transistor TR 1 and the fourth transistor TR 4 use one and the same S / D region 25B. In the present embodiment, the S / D regions 25A and 25B are each formed over two fin structures. Note that in this diagram, a source and a drain are used only to distinguish them from each other, and they may be interchanged. A source / drain refers to a source or a drain.FIGS. 5A to 5D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 5A is a plan view, FIG. 5B is a sectional view taken along the line X 1-X 1 of FIG. 5A, FIG. 5C is a sectional view taken along the line Y 1-Y 1 of FIG. 5A, and FIG. 5D is a sectional view taken along the line X 2-X 2 of FIG. 5A. In FIG. 5A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.After the process in FIGS. 4A to 4D, using the mask layer 70 as an etching mask, the first ILD layer 50 is partially etched to expose the S / D regions 25A and 25B, as shown in FIGS. 5A and 5C. Because the separator 60 is made of a silicon nitride-based material (e.g., SiN) and the first ILD layer 50 is made of a silicon oxide-based material (e.g., SiO 2) openings 26A and 26B over the S / D regions 25A and 25B can be formed into separate structures self-aligned in the Y direction. If the sidewall spacers 42 and the capping insulating layer 19 of the gate structure 40 are made of a silicon nitride-based material (e.g., SiN), the openings 26A and 26B over the S / D regions 25A and 25B may also be formed self-aligned in the X direction.FIGS. 6A to 6D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 6A is a plan view, FIG. 6B is a sectional view taken along the line X 1-X 1 of FIG. 6A, FIG. 6C is a sectional view taken along the line Y 1-Y 1 of FIG. 6A, and FIG. 6D is a sectional view taken along the line X 2-X 2 of FIG. 6A. In FIG. 6A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.After the S / D openings 26A and 26B are formed, a conductive material is deposited in the openings to form an S / D contact layer 80. The S / D contact layer 80 includes one or more layers of a conductive material such as W, Cu, Co, Ni, or its silicide. To form the S / D contact layer 80, a protective layer of the conductive material is formed, for example, by CVD, physical vapor deposition (PVD), such as sputtering or atomic layer deposition (ALD), or other suitable layer formation method. Then, a planarization process such as etch back and / or CMP is performed, so that the structure of FIGS. 6A to 6D is obtained. Prior to depositing the conductive material, an adhesion layer and / or a barrier layer may be formed.FIGS. 7A to 7D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 7A is a plan view, FIG. 7B is a sectional view taken along the line X 1-X 1 of FIG. 7A, FIG. 7C is a sectional view taken along the line Y 1-Y 1 of FIG. 7A, and FIG. 7D is a sectional view taken along the line X 2-X 2 of FIG. 7A. In FIG. 7A, the substrate 10, the dielectric separation layer 30, the first ILD layer 50, and a second ILD layer 85 are not illustrated.After the S / D contact layers 80 are formed, a second ILD layer 85 and a first via pin 90 are formed, as shown in FIGS. 7A-7D. The second ILD layer 85 includes one or more layers of insulating materials, such as SiO 2, SiOC, SiOCN, or a low-k dielectric material (e.g., k<3). The first via pin 90 may be formed using a damascene process. The first via pin 90 includes one or more layers of W, Co, Ni, Ti, TiN, Ta, TaN, or other suitable conductive materials. In this embodiment, the first via pin 90 connects two S / D contact layers 80 for the S / D regions 25A and 25B.FIGS. 8A to 8D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 8A is a plan view, FIG. 8B is a sectional view taken along the line X 1-X 1 of FIG. 8A, FIG. 8C is a sectional view taken along the line Y 1-Y 1 of FIG. 8A, and FIG. 8D is a sectional view taken along the line X 2-X 2 of FIG. 8A. In FIG. 8A, the substrate 10, the dielectric separation layer 30, the first ILD layer 50, the second ILD layer 85, and a third ILD layer 95 are not illustrated.A third ILD layer 95 and a first metal line 100 are sequentially formed over the structure of FIGS. 7A-7D. The third ILD layer 95 includes one or more layers of insulating materials, such as SiO 2, SiOC, SiOCN, or a low-k dielectric material (e.g., k<3). The first metal line 100 includes one or more layers of Cu, Al, Ti, TiN, Ta, TaN, or other suitable conductive materials. The first metal line 100 may be formed by a damascene process.As shown in FIGS. 8A-8D, a first fin structure 20A and a second fin structure 20B separated from the first fin structure 20A by a dielectric separation layer 30 are disposed over a substrate 10. Over the first fin structure 20A, a first fin field effect transistor (FinFET) TR 1 and a second FinFET TR 2 (see FIG. 4A ) are fabricated. The first FinFET TR 1 includes a first gate electrode 40A, and the second FinFET TR 2 includes a second gate electrode 40B. A first S / D region 25A (see FIG. 4A ) is shared by and is interposed between the first FinFET TR 1 and the second FinFET TR 2. An ILD layer 50 is disposed over the first and second fin structures, the first and second FinFETs, and the first S / D region. A first S / D contact layer 80 is disposed on the first S / D region and extends to the second fin structure such that a portion of the first S / D contact layer 80 is over the isolation dielectric layer 30. On this portion of the first S / D contact layer 80, a first via pin 90 is disposed and is located over the dielectric isolation layer 30. a first metal line layer 100 is disposed on the first via pin 90. One end of the first S / D contact layer 80 is in contact with a separation element 60 made of an insulating material different from that of the dielectric separation layer 30 and the first ILD layer 50. Further, ends of the gate structures 40A and 40B and an end of the first S / D contact layer 80 are in contact with one and the same surface of the separator 60.It is understood that the device shown in FIGS. 8A-8D may be subjected to further CMOS processes to fabricate various features, such as metal interconnect layers, dielectric layers, passivation layers, etc.FIG. 9 illustrates an exemplary layout structure of a semiconductor device according to an embodiment of the present invention.In FIG. 9, a plurality of gate patterns 41A to 48A and 41B to 48B extend in the Y direction and are arranged in the X direction. In some embodiments, the plurality of gate structures 41A to 48A and 41B to 48B are arranged at a constant pitch in the X direction. The separator 60 extends in the X direction and separates the gate structures 41A to 48A from the gate structures 41B to 48B. A S / D region disposed between the gate structures 43A and 44A is electrically connected to an S / D region disposed between the gate structures 43B and 44B by the first via pin 90, and the first via pin 90 is connected to the first metal line 100. In FIG. 9, more than two gate structures and more than two S / D contact layers are in contact with one and the same surface of the separator 60.FIG. 10 illustrates an exemplary layout structure of standard cells for a semiconductor device according to an embodiment of the present invention.In FIG. 10, a standard cell Cell CB is disposed between standard cells Cell CA and Cell CC in the Y direction. At the boundaries of the cells, power supply lines Vdd and Vss are arranged, running in the X direction. The power supply lines Vdd and Vss are formed by the first metal lines 100.The structure and the manufacturing method illustrated in FIGS. 1A to 8D correspond to the manufacturing of an enclosed area A in FIG. 10. the structure and the manufacturing method illustrated in FIGS. 11A to 15D correspond to the manufacturing of an enclosed area B in FIG. 10, the structure and the manufacturing method illustrated in FIGS. 16A to 20D correspond to the manufacturing of an enclosed area C in FIG. 10, and the structure and the manufacturing method illustrated in FIGS. 21A to 21D correspond to the manufacturing of an enclosed area D in FIG. 10.In the region A, two S / D contact layers adjacent to each other in the Y direction are connected to the power supply line formed by the metal line 100 via the first via pin 90. In the region A, a first fin structure 210 and a second fin structure 220 separated from the first fin structure 210 by a dielectric separation layer are disposed. A first fin field effect transistor (FinFET) TR 10 and a second FinFET TR 20 are both fabricated over the first fin structure 210. The first FinFET TR 10 includes a first gate electrode 410 and the second FinFET TR 20 includes a second gate electrode 420. A first S / D region 310 is shared by and is disposed between the first FinFET TR 10 and the second FinFET TR 20. A first S / D contact layer 810 is disposed on the first S / D region 310 and extends to the second fin structure 220 such that a portion of the first S / D contact layer 810 is over the isolation dielectric layer. On this portion of the first S / D contact layer 810, a contact pin 910 is disposed and is located over the dielectric isolation layer. On the contact pin 910, a first metal line layer 1010 (e.g., Vdd) is disposed. One end of the first S / D contact layer 810 is in contact with a separator 610.In addition, a third FinFET TR 30 and a fourth FinFET TR 40 are formed over the second fin structure 220. The third FinFET TR 30 includes a third gate electrode 430, and the fourth FinFET TR 40 includes a fourth gate electrode 440. A second S / D region 320 is shared by and is disposed between the third FinFET TR 30 and the fourth FinFET TR 40. A second S / D contact layer is disposed on the second S / D region 320 such that the first S / D region and the second S / D region are physically separated by the separator 60 and electrically connected by the first via pin 910.The region B has a substantially similar structure to the region A except for the following configuration. In the region B, only one of the two S / D contact layers adjacent to each other in the Y direction is connected to the power supply line formed by the metal line 100 via the first via pin 910.The region C has a substantially similar structure to the region A except for the following configuration.The region D has a substantially similar structure to the region A except for the following configuration. In the region D disposed in a standard cell, two S / D contact layers adjacent to each other in the Y direction are respectively connected to two metal lines 100 via two first via pins 910.FIGS. 11A to 15D show various stages of an exemplary sequential manufacturing process for a structure corresponding to region B of FIG. 10, according to an embodiment of the present invention. The materials, configurations, structures, and / or processes used in FIGS. 1A to 8D may be used in the following embodiment, and the details are omitted. The order of the steps / processes may be interchanged.FIGS. 11A to 11D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 11A is a plan view, FIG. 11B is a sectional view taken along the line X 1-X 1 of FIG. 11A, FIG. 11C is a sectional view taken along the line Y 1-Y 1 of FIG. 11A, and FIG. 11D is a sectional view taken along the line X 2-X 2 of FIG. 11A. In FIG. 11A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.After the structure of FIGS. 3A to 3C is formed, a mask layer 70, for example, a photoresist layer or a hard mask layer having an opening 75A, is formed over the structure shown in FIGS. 3A to 3C. The opening 75A overlaps one of the S / D regions (e.g., 25B, see FIG. 4A ) and a portion of the separator 60, as shown in FIG. 11A.FIGS. 12A to 12D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 12A is a plan view, FIG. 12B is a sectional view taken along the line X 1-X 1 of FIG. 12A, FIG. 12C is a sectional view taken along the line Y 1-Y 1 of FIG. 12A, and FIG. 12D is a sectional view taken along the line X 2-X 2 of FIG. 12A. In FIG. 12A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.Using the mask layer 70 as an etching mask, the first ILD layer 50 is partially etched to expose the S / D region 25B, as shown in FIGS. 12A and 12C.FIGS. 13A to 13D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 13A is a plan view, FIG. 13B is a sectional view taken along the line X 1-X 1 of FIG. 13A, FIG. 13C is a sectional view taken along the line Y 1-Y 1 of FIG. 13A, and FIG. 13D is a sectional view taken along the line X 2-X 2 of FIG. 13A. In FIG. 13A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.After the S / D opening 26B is formed, a conductive material is deposited in the opening 26B to obtain an S / D contact layer 80A.FIGS. 14A to 14D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 14A is a plan view, FIG. 14B is a sectional view taken along the line X 1-X 1 of FIG. 14A, FIG. 14C is a sectional view taken along the line Y 1-Y 1 of FIG. 14A, and FIG. 14D is a sectional view taken along the line X 2-X 2 of FIG. 14A. In FIG. 14A, the substrate 10, the dielectric separation layer 30, the first ILD layer 50, and a second ILD layer 85 are not illustrated.After the S / D contact layer 80A is formed, a second ILD layer 85 and a first via pin 90 are formed, as shown in FIGS. 14A-14D. In contrast to the embodiment shown in FIGS. 7A and 7C, in which the first via pin 90 is connected to two S / D contact layers 80, in this embodiment the first via pin 90 is connected only to one S / D contact layer 80A.FIGS. 15A to 15D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 15A is a plan view, FIG. 15B is a sectional view taken along the line X 1-X 1 of FIG. 15A, FIG. 15C is a sectional view taken along the line Y 1-Y 1 of FIG. 15A, and FIG. 15D is a sectional view taken along the line X 2-X 2 of FIG. 15A. In FIG. 15A, the substrate 10, the dielectric separation layer 30, the first ILD layer 50, the second ILD layer 85, and a third ILD layer 95 are not illustrated.In this embodiment, a third ILD layer 95 and a first metal line 100 are sequentially formed over the structure of FIGS. 14A to 14D, as shown in FIGS. 15A to 15D.In contrast to the structures shown in FIGS. 8A to 8D, in the embodiment of FIGS. 15A to 15D, only one (e.g., 25B) of the two S / D contact layers is connected to the metal line 100 via the first via pin 90.FIGS. 16A through 20D illustrate various stages of an exemplary sequential fabrication process for a structure corresponding to region C of FIG. 10, in accordance with an embodiment of the present invention. The materials, configurations, structures, and / or processes used in FIGS. 1A to 8D may be used in the following embodiment, and the details are omitted. The order of the steps / processes may be interchanged.FIGS. 16A to 16D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 16A is a plan view, FIG. 16B is a sectional view taken along the line X 1-X 1 of FIG. 16A, FIG. 16C is a sectional view taken along the line Y 1-Y 1 of FIG. 16A, and FIG. 16D is a sectional view taken along the line X 2-X 2 of FIG. 16A. In FIG. 16A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.After the structure of FIGS. 3A-3C is formed, a mask layer 70, for example, a photoresist layer or a hard mask layer having an opening 75B, is formed over the structure shown in FIGS. 3A-3C. The opening 75B overlaps one of the S / D regions (e.g., 25B, see FIG. 4A ), but does not overlap the separator 60, as shown in FIG. 16A.FIGS. 17A to 17D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 17A is a plan view, FIG. 17B is a sectional view taken along the line X 1-X 1 of FIG. 17A, FIG. 17C is a sectional view taken along the line Y 1-Y 1 of FIG. 17A, and FIG. 17D is a sectional view taken along the line X 2-X 2 of FIG. 17A. In FIG. 17A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.Using the mask layer 70 as an etching mask, the first ILD layer 50 is partially etched to form the opening 26B exposing the S / D region 25B, as shown in FIGS. 17A and 17C.FIGS. 18A to 18D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 18A is a plan view, FIG. 18B is a sectional view taken along the line X 1-X 1 of FIG. 18A, FIG. 18C is a sectional view taken along the line Y 1-Y 1 of FIG. 18A, and FIG. 18D is a sectional view taken along the line X 2-X 2 of FIG. 18A. In FIG. 18A, the substrate 10, the dielectric separation layer 30, and the first ILD layer 50 are not illustrated.After the S / D opening 26B is formed, a conductive material is deposited in the opening 26B to obtain an S / D contact layer 80B.FIGS. 19A to 19D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 19A is a plan view, FIG. 19B is a sectional view taken along the line X 1-X 1 of FIG. 19A, FIG. 19C is a sectional view taken along the line Y 1-Y 1 of FIG. 19A, and FIG. 19D is a sectional view taken along the line X 2-X 2 of FIG. 19A. In FIG. 19A, the substrate 10, the dielectric separation layer 30, the first ILD layer 50, and a second ILD layer 85 are not illustrated.After the S / D contact layer 80B is formed, a second ILD layer 85 is formed, as shown in FIGS. 19A to 19D. In this embodiment, a first via pin 90 is not disposed on the S / D contact layer 80B.FIGS. 20A to 20D show a stage of a sequential manufacturing process for a semiconductor device according to an embodiment of the present invention. FIG. 20A is a plan view, FIG. 20B is a sectional view taken along the line X 1-X 1 of FIG. 20A, FIG. 20C is a sectional view taken along the line Y 1-Y 1 of FIG. 20A, and FIG. 20D is a sectional view taken along the line X 2-X 2 of FIG. 20A. In FIG. 20A, the substrate 10, the dielectric separation layer 30, the first ILD layer 50, the second ILD layer 85, and a third ILD layer 95 are not illustrated.A third ILD layer 95 and a first metal line 100 are sequentially formed over the structure of FIGS. 19A through 19D, as shown in FIGS. 20A through 20D.FIGS. 21A to 21D show an exemplary structure of a semiconductor device according to an embodiment of the present invention. The structure and the manufacturing method, which will be explained below with reference to FIGS. 21A to 21D, correspond to the enclosed area D in FIG. 10.As shown in FIGS. 21A-21D, a first fin structure 20A and a second fin structure 20B separated from the first fin structure 20A by a dielectric separation layer 30 are disposed over a substrate 10. A first fin field effect transistor (FinFET) TR 1 and a second FinFET TR 2 (see FIG. 4A ) are formed over the first fin structure 20A, and a third FinFET TR 3 and a fourth FinFET TR 4 (see FIG. 4A ) are formed over the second fin structure 20B. The first FinFET TR 1 includes a first gate electrode 40A, the second FinFET TR 2 includes a second gate electrode 40B, the third FinFET TR 3 includes a third gate electrode 40C, and the fourth FinFET TR 4 includes a fourth gate electrode 40D. A first S / D region 25A (see FIG. 4A ) is shared by and disposed between the first FinFET TR 1 and the second FinFET TR 2, and a first S / D region 25B (see FIG. 4A ) is shared by and disposed between the third FinFET TR 3 and the fourth FinFET TR 4. An ILD layer 50 is disposed over the first through fourth fin structures, the first through fourth FinFETs, and the first and second S / D regions. A first S / D contact layer 80C is disposed on the first S / D region 25A and extends to the second fin structure such that a portion of the first S / D contact layer 80C is over the isolation dielectric layer 30. A second S / D contact layer 80D is disposed on the second S / D region 25B and extends to the first fin structure such that a portion of the second S / D contact layer 80C is over the isolation dielectric layer 30. A first via pin 90C is disposed on the first S / D contact layer 80C, and a second via pin 90D is disposed on the second S / D contact layer 80D. A first metal line layer 100C is disposed on the first via pin 90C, and a second metal line layer 100D is disposed on the second via pin 90D. An end of the first S / D contact layer 80C is in contact with a separator 60, and an end of the second S / D contact layer 80D is in contact with a separator 60.The various embodiments or examples described herein provide several advantages over the prior art. For example, in the present invention, an S / D contact layer 80 is formed self-aligned using the gate dicing process and the separator 60. This allows the circuit size, particularly the size of standard cells, to be reduced. Further, it is possible to suppress the generation of round shapes of the ends of the S / D contact layers, thereby suppressing a short circuit between the S / D contact layer and a gate electrode.According to an aspect of the present invention, in a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed over a portion of a first fin structure and a portion of a second fin structure that are disposed over a substrate, extend in a first direction, are disposed parallel to each other in a second direction intersecting the first direction, and protrude from a dielectric separation layer. The first and second gate structures extend in the second direction and are arranged parallel to each other in the first direction. An interlayer dielectric layer is formed over the first and second gate structures and the first and second fin structures. A first mask layer having a first opening is formed over the interlayer dielectric layer. The first opening is over the first and second gate structures. The first and second gate structures are separated by the first opening, and the dielectric separation layer and the interlayer dielectric layer disposed between the first gate structure and the second gate structure are etched by the first opening to form a first recess. An insulating layer is formed in the first recess. A second mask layer having a second opening is formed to expose a portion of the insulating layer in the first recess and a portion of the interlayer dielectric layer. The second opening is over the first fin structure. The exposed portion of the interlayer dielectric layer is etched through the second opening to form at least a second recess over the first fin structure. A conductive material is deposited in the one second recess to form a first S / D contact layer.According to another aspect of the present invention, a semiconductor device includes: a first fin structure and a second fin structure; a first fin field effect transistor (FinFET) and a second FinFET; a first source / drain region; an interlayer dielectric layer; a first source / drain contact layer; and a separation isolation insulating layer. The second fin structure is separated from the first fin structure by a dielectric separation layer. The first and second fin structures extend in a first direction. The first FinFET and the second FinFET are formed over the first fin structure. The first FinFET includes a first gate electrode and the second FinFET includes a second gate electrode. The first and second gate electrodes extend in a second direction intersecting the first direction. The first source / drain region is shared by and is disposed between the first FinFET and the second FinFET. The interlayer dielectric layer is disposed over the first and second fin structures, the first and second FinFETs, and the first source / drain regions. The first source / drain contact layer is disposed on the first source / drain region and extends to the second fin structure such that a portion of the first source / drain contact layer is over the isolation dielectric layer. The isolation insulating layer is disposed adjacent to the first source / drain contact layer. One end of the first source / drain contact layer is in contact with the isolation insulating layer. The separation insulating layer is made of an insulating material different from the dielectric separation layer and the dielectric intermediate layer.

Claims

A method of manufacturing a semiconductor device, comprising the steps of: forming a first gate structure (40) and a second gate structure over a portion of a first fin structure (20A, 210) and a portion of a second fin structure (20B, 220) disposed over a substrate (10), extending in a first direction, being disposed parallel to each other in a second direction intersecting the first direction, and protruding from an insulating separation layer (30), the first and second gate structures extending in the second direction and being disposed parallel to each other in the first direction; forming an insulating interlayer (50) over the first and second gate structures (40) and the first and second fin structures (20B, 220); forming a first mask layer having a first opening over the interlayer insulating layer (50), the first opening being over the first and second gate structures (40); dicing the first and second gate structures (40) through the first opening and etching the isolation isolation layer (30) and the interlayer insulating layer (50) disposed between the first gate structure and the second gate structure through the first opening to form a first recess; forming an isolation layer in the first recess; forming a second mask layer having a second opening to expose a portion of the isolation layer in the first recess and a portion of the interlayer insulating layer (50), the second opening being over the first fin structure (20A, 210); etching the exposed portion of the interlayer insulating layer (50) through the second opening to form at least one second recess over the first fin structure (20A, 210); and depositing a conductive material in the at least one second recess to form a first source / drain contact layer (80, 810).The method of claim 1, wherein the insulating layer comprises SiN.The method according to claim 1 or 2, wherein the conductive material comprises at least one selected from the group consisting of W, Co, Ni, Ti and Ta, its silicide or its nitride.The method of any preceding claim, further comprising forming a first contact pin (910) in contact with the first source / drain contact layer (80, 810), the first contact pin (910) comprising at least one of W, Cu, Co and Ni or silicide thereof.The method of claim 4, further comprising forming a first conductive pattern in contact with the first contact pin (910), wherein the first conductive pattern is a power supply line.The method of any preceding claim, wherein the second opening is also over the second fin structure (20B, 220), wherein etching the exposed portion of the intermediate insulating layer (50) through the second opening creates a further second recess over the second fin structure (20B, 220), and the conductive material is deposited in the further second recess to obtain a second source / drain contact layer (80, 810).The method of claim 6, further comprising forming a first contact pin (910) in contact with the first source / drain contact layer (80, 810), the first contact pin (910) in contact with the second source / drain contact layer (80, 810).The method of claim 6, further comprising: forming a first contact pin (910) in contact with the first source / drain contact layer (80, 810); and forming a second contact pin (910) in contact with the second source / drain contact layer (80, 810), wherein the first contact pin (910) and the second contact pin are physically separated by an insulating material.The method of any of claims 6 to 8, wherein the second mask layer has a third opening to expose a portion of the insulating layer outside the first recess and the one second recess and the further second recess, wherein when the exposed portion of the interlayer insulating layer (50) is etched through the second opening, the portion of the insulating layer is etched through the third opening to form a third recess, and wherein when the conductive material is deposited in the one second recess and in the further second recess, the conductive material is also deposited in the third recess.A semiconductor device comprising: a first fin structure (20A, 210) and a second fin structure (20B, 220) separated from the first fin structure by an insulating separation layer (30), the first and second fin structures (20B, 220) extending in a first direction; a first fin field effect transistor (FinFET) and a second FinFET both fabricated over the first fin structure (20A, 210), the first FinFET including a first gate electrode (40A, 410), the second FinFET including a second gate electrode (40B, 420), and the first and second gate electrodes extending in a second direction intersecting the first direction; a first source / drain region shared by and disposed between the first FinFET and the second FinFET; an intermediate insulating layer (50) disposed over the first and second fin structures (20B, 220), the first and second FinFETs, and the first source / drain region; a first source / drain contact layer (80, 810) disposed on the first source / drain region and extending toward the second fin structure (20B, 220) such that a portion of the first source / drain contact layer is disposed over the isolation isolation layer (30); and a separation insulating layer (60) disposed adjacent to the first source / drain contact layer (80, 810) and extending through the interlayer insulating layer (50) into the separation insulating layer (30), wherein an end of the first source / drain contact layer (80, 810) is in contact with the separation insulating layer (60), and the separation insulating layer (60) is made of an insulating material different from the separation insulating layer (30) and the interlayer insulating layer (50).The semiconductor device of claim 10, wherein the first source / drain contact layer (80, 810) comprises at least one selected from the group consisting of W, Co, Ni, Ti and Ta, a silicide thereof, and a nitride thereof.The semiconductor device according to claim 10 or 11, wherein the insulating material of the isolation insulating layer (60) is SiN.The semiconductor device of any of claims 10 to 12, further comprising: a third FinFET and a fourth FinFET both fabricated over the second fin structure (20B, 220), the third FinFET comprising a third gate electrode (40C, 430), and the fourth FinFET comprising a fourth gate electrode (40D, 440); a second source / drain region shared by and disposed between the third FinFET and the fourth FinFET; and a second source / drain contact layer (80, 810) disposed on the second source / drain region and extending toward the first fin structure (20A, 210) such that a portion of the second source / drain contact layer is over the isolation isolation layer (30), wherein an end of the second source / drain contact layer (80, 810) is in contact with the isolation isolation layer (60), and the second source / drain contact layer (80, 810) is physically separated from the first source / drain contact layer by the isolation isolation layer (60).The semiconductor device of claim 13, further comprising a first contact pin (910) in contact with the first source / drain contact layer (80, 810), the first contact pin (910) in contact with the second source / drain contact layer (80, 810) and the isolation insulating layer (60).The semiconductor device of claim 13, further comprising: a first contact pin (910) in contact with the first source / drain contact layer (80, 810); and a second contact pin (910) in contact with the second source / drain contact layer (80, 810).The semiconductor device of any of claims 10 to 15, further comprising: a third fin structure (20); a fifth FinFET and a sixth FinFET both fabricated over the third fin structure (20), the fifth FinFET comprising a fifth gate electrode (40) and the sixth FinFET comprising a sixth gate electrode; a third source / drain region shared by and disposed between the fifth FinFET and the sixth FinFET; and a third source / drain contact layer (80, 810) disposed on the third source / drain region, the third source / drain contact layer (80, 810) not electrically connected to a source / drain region adjacent in the second direction.

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