Semiconductor circuit which has a flip-flop

Abstract

Semiconductor circuit comprising: a first circuit (100) which determines a logic level of a second node (NET 2) and a logic level of a third node (NET 0) based on a logic level of input data (D), a logic level of a clock signal (CLK), and a logic level of a first node (NET 1); and a second circuit (200, 210, 220, 230, 240) which determines the logic level of the first node (NET 1) based on the logic level of the clock signal (CLK), the logic level of the second node (NET 2) and the logic level of the third node (NET 0), wherein the first circuit (100) comprises: a subcircuit (120, 122) which determines the logic level of the second node (NET 2) based on the logic level of the input data (D) and the logic level of the first node (NET 1); a first transistor (NE1) connected to the logic level of the clock signal (CLK) to connect the third node (NET 0) to the second node (NET 2); a second transistor (PE3) connected to the inverted value of the logic level of the third node (NET 0) to pull up a fourth node (NET 3); and a third transistor (NE2) connected to the logic level of the third node (NET 0) to pull down the fourth node (NET 3).

Description

BACKGROUND 1. Technical field

[0001] The present disclosure relates to a semiconductor circuit having a flip-flop. 2. Description of the state of the art

[0002] US 2005 / 0 151 560 A1 discloses a flip-flop circuit with a scan structure consisting of an input section of a dynamic circuit and an output section of a static circuit, wherein data acquisition occurs within an interval with a pulse width short compared to a clock cycle. In the dynamic circuit of the input section, the number of series-connected MOS transistors to which a data signal is input is smaller than the number of series-connected MOS transistors to which a test input signal is input. With this structure, the operating speed at the time of data storage for a data signal input is increased and the number of MOS transistors is reduced.

[0003] Multiple logic circuits are integrated on a single chip due to the miniaturization of the process. Therefore, the size of a chip's unit cell area directly influences the chip's integration. Similarly, since the performance of a flip-flop for transferring data dependent on a clock signal within a digital system is directly related to the system's performance, obtaining a high-speed flip-flop for achieving a high-speed system has become increasingly important.

[0004] However, when the high-speed flip-flop is achieved, there is a problem of an increase in an area of ​​the flip-flop from the viewpoint of layout. SUMMARY

[0005] An object of the present disclosure is to provide a semiconductor circuit having a high-speed flip-flop in which the reliability of the product is increased and a unit cell area is reduced.

[0006] However, aspects of the present disclosure are not limited to those discussed herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure belongs by reference to the detailed description of the present disclosure provided below.

[0007] The above-mentioned object is achieved, for example, by a semiconductor circuit comprising a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node based on a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node based on the logic level of the clock signal, the logic level of the second node, and the logic level of the third node. The first circuit comprises a subcircuit and a first transistor. The first circuit determines the logic level of the second node based on the logic level of the input data and the logic level of the first node. The first transistor is connected to the logic level of the clock signal to connect the third node to the second node.A second transistor is tied to the inverted value of the logic level of the third node to pull up a fourth node and a third transistor is tied to the logic level of the third node to pull down the fourth node.

[0008] According to another aspect of the present disclosure, a semiconductor circuit is provided, comprising a first circuit, a second circuit, and a latch circuit. The first circuit determines a logic level of a second node and a logic level of a third node based on a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node based on the logic level of the clock signal, the logic level of the second node, and the logic level of the third node. The latch circuit determines a logic level of an output terminal based on the logic level of the clock signal and the logic level of the third node.The latch circuit includes a first latch transistor connected to the inverted value of the logic level of the third node to pull up a fifth node, a second latch transistor connected to a power source at one end and connected to the logic level of the fifth node, a third latch transistor connected in series with the second latch transistor at one end, connected to the fifth node at the other end and connected to the inverted value of the logic level of the clock signal, and an inverter that inverts the logic level of the fifth node and transmits it to the output terminal.

[0009] When the logic level of the clock signal is a first logic level, the logic level of the second node is transmitted to the third node and the logic level of the third node is transmitted to the output terminal.

[0010] According to yet another aspect of the present disclosure, a semiconductor circuit is provided, including a first circuit, a second circuit, and a latch circuit. The first circuit determines a logic level of a second node and a logic level of a third node based on a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node based on the logic level of the clock signal, the logic level of the second node, and the logic level of the third node. The latch circuit determines a logic level of an output terminal based on the logic level of the clock signal and the logic level of the third node. When the logic level of the clock signal or the logic level of the third node is the first logic level, the first node is precharged.If the logic level of the clock signal or the logic level of the second node is a second logic level different from the first logic level, the first node is discharged. If the logic level of the clock signal or the logic level of the first node is the first logic level, the third node is precharged. If all of the logic level of the clock signal, the logic level of the input data, and the logic level of the first node are the second logic level, the third node is discharged.

[0011] The invention is defined in the appended independent claims. Further developments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram illustrating a semiconductor circuit according to an embodiment of the present disclosure; Fig. 2 is a block diagram illustrating a semiconductor circuit according to an embodiment of the present disclosure; Fig. 3 is a circuit diagram illustrating a second subcircuit included in a first circuit of the Fig. 1 is included; Fig. 4 to 7 are timing charts for explaining the operation of the semiconductor circuit according to an embodiment of the present disclosure; Fig. 8 is a circuit diagram illustrating a semiconductor circuit according to another embodiment of the present disclosure; Fig. 9 is a circuit diagram illustrating a semiconductor circuit according to still another embodiment of the present disclosure; Fig. 10 and Fig. 11 are timing diagrams for explaining the operation of the semiconductor circuit according to some embodiments of the present disclosure; Fig. 12 is a circuit diagram illustrating a semiconductor circuit according to still another embodiment of the present disclosure; Fig. 13 is a circuit diagram illustrating a semiconductor circuit according to still another embodiment of the present disclosure; Fig. 14 is a flowchart for explaining the operation of the semiconductor circuit according to some embodiments of the present disclosure; Fig. 15 is a block diagram of a SoC system including the semiconductor circuit according to embodiments of the present disclosure; and Fig. 16 is a block diagram of an electronic system including the semiconductor circuit according to embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PRESENT DISCLOSURE

[0013] Advantages and features of the present disclosure and methods for achieving the same can be more readily understood by reference to the following detailed description of preferred embodiments and the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be considered limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the disclosure to those skilled in the art, and the present disclosure will be defined only by the appended claims. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

[0014] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it may be directly on or connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, no intervening elements or layers are present. Like numbers refer to like elements throughout. When used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0015] Spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe a relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were inverted, elements described as being "below" or "below" other elements or features would then be oriented "above" the other elements or features. Accordingly, the exemplary term "below" can encompass both an above and below orientation.The device may be oriented differently (rotated 90 degrees or under other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] The use of the terms "a" and "an" and similar references in the context of describing the disclosure (particularly in the context of the present claims) should be considered to encompass both the singular and plural, unless otherwise indicated herein or clearly contradicted by the context. The terms "comprising," "having," "including," and "containing" should be considered open-ended terms (i.e., meaning "including, but not limited to") unless otherwise noted.

[0017] It will be understood that although the terms "first," "second," etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, a first element, first component, or first section discussed above could be referred to as a second element, second component, or second section without departing from the teachings of the present disclosure.

[0018] The present disclosure will be described with reference to perspective views, cross-sectional views, and / or plan views, in which preferred embodiments of the disclosure are shown. Accordingly, the profile of an exemplary view may be modified according to manufacturing techniques and / or tolerances. That is, the embodiments of the disclosure are not intended to limit the scope of the present disclosure, but include all changes and modifications that may be caused due to a change in the manufacturing process. Accordingly, portions shown in the drawings are illustrated in schematic form, and the shapes of the portions are presented simply by way of illustration and not as a limitation.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure belongs. It is understood that the use of any and all examples or exemplary terms provided herein is intended only to further clarify the disclosure and is not a limitation on the scope of the disclosure unless otherwise specified. Furthermore, unless otherwise defined, any terms defined in commonly used dictionaries should not be unduly interpreted.

[0020] Fig. 1 is a circuit diagram illustrating a semiconductor circuit according to an embodiment of the present disclosure. Fig. 2 is a block diagram illustrating a semiconductor circuit according to an embodiment of the present disclosure. Fig. Figure 3 is a circuit diagram illustrating a second subcircuit included in the first circuit of the Fig. 1 is included.

[0021] With reference to the Fig. 1 and Fig. 2, a semiconductor circuit according to an embodiment of the present disclosure includes a first circuit 100, a second circuit 200, and a latch circuit 300.

[0022] The first circuit 100 may determine a logic level of a node NET 2 and a logic level of a node NET 0 based on a logic level of input data D, a logic level of a clock signal CLK, and a logic level of a node NET 1.

[0023] The second circuit 200 may determine the logic level of a node NET 1 based on the logic level of the clock signal CLK, the logic level of the node NET 2, and the logic level of the node NET 0.

[0024] The latch circuit can determine a logic level of an output terminal OUT based on the logic level of the clock signal CLK and the logic level of the node NET 0.

[0025] At this time, a portion of the output of the first circuit 100 can be used as an input of the second circuit 200, and a portion of the output of the second circuit 200 can be used as an output of the first circuit 100. The first circuit 100, the second circuit 200, and the latch circuit 300 can operate as a flip-flop. However, the present disclosure is not limited thereto.

[0026] In some embodiments of the present disclosure, the first circuit 100 and the second circuit 200 may include a gate of an Or-And-Inverter (OAI) structure, respectively. However, the present disclosure is limited thereto, and the detailed description thereof will be provided below.

[0027] In particular, the first circuit 100 has a first subcircuit 110 and a second subcircuit 120.

[0028] The first subcircuit 110 includes a transistor PE1 connected to an inverted value of the logic level of the node NET 1 to pull up the node NET 0, a transistor PE2 connected in parallel with the transistor PE1 and connected to an inverted value of the logic level of the clock signal CLK to pull up the node NET 0, and a transistor NE1 connected to the logic level of the clock signal CLK to connect the node NET 0 and the node NET 2.

[0029] At this time, the transistor NE1 may be placed between the node NET0 and the node NET2, and may transfer the logic level of the node NET0 to the node NET2 when it is turned on. However, the present disclosure is not limited thereto.

[0030] In this embodiment, as illustrated, one side of some of the transistors PE1, PE2 may be connected to the power supply voltage VDD, but the present disclosure is not limited thereto. Likewise, some of the transistors PE1, PE2 may be constructed from, for example, a PMOS transistor, and the remaining transistor NE1 may be constructed from, for example, an NMOS transistor, but the present disclosure is not limited thereto.

[0031] Furthermore, the first subcircuit 110 may further comprise a transistor PE3 connected to the inverted value of the logic level of the node NET 0 to pull up the node NET 3, and a transistor NE2 connected to the logic level of the node NET 0 to pull down the node NET 3. Here, the transistor PE3 and the transistor NE2 may be used as an inverter (corresponding to G1 in Fig. 2). Therefore, the node NET 0 and the node NET 3 can have logic levels that are opposite to each other. The inverter G3 and the NAND gate G2 within the Fig. 2 correspond to transistors NE1 and PE2 within Fig. 1. And the NAND gate G6 within Fig. 2 corresponds to transistors N1, N2 and N3 within Fig. 1.

[0032] In this embodiment, as illustrated, transistors PE3, NE2 may be connected in series between a power supply voltage VDD and a ground voltage, but the present disclosure is not limited thereto. Likewise, for example, transistor PE3 may be constructed from a PMOS transistor, and the remaining transistor NE2 may be constructed from an NMOS transistor, for example, but the present disclosure is not limited thereto.

[0033] The second subcircuit 120 includes a gate G5 that performs an OR operation of the logic level of the input data D and the logic level of the node NET 3, and a gate G4 that performs a NAND operation of the logic level of the output of the gate G5 and the logic level of the node NET 1 to transmit an output value to the node NET 2. That is, the second subcircuit 120 may be an OAI circuit that transmits the output values ​​to the node NET 2 based on the logic level of the input data D, the logic level of the node NET 3, and the logic level of the node NET 1. However, the present disclosure is not limited thereto. The output value transmitted to the node NET 2 may be supplied to the second circuit 100 as an input and may be connected to one end of the transistor NE1, but the present disclosure is not limited thereto.

[0034] More precisely, with reference to the Fig. 1 and Fig. 3, the second subcircuit 120 may include a subtransistor PG2 connected to the inverted value of the logic level of the node NET 3 to provide a power supply voltage VDD, a subtransistor PG3 connected in series with the subtransistor PG2 and connected to the inverted value of the logic level of the input data D, and a subtransistor PG1 connected in parallel with the subtransistor PG2 and the subtransistor PG3, which are connected in series with each other, and which is connected to the inverted value of the logic level of the node NET 1 to pull up the node NET 2.

[0035] Furthermore, the second subcircuit 120 may include a subtransistor NG3 connected to the logic level of the node NET 1 to transmit a ground voltage to the node NET 2, a subtransistor NG1 connected between the subtransistor NG3 and the node NET 2 and connected to the logic level of the input data D, and a subtransistor NG2 connected in parallel with the subtransistor NG1 and connected to the logic level of the node NET 3.

[0036] At this time, the node NET 2 can be precharged when the transistor PG1 is turned on or when the transistor PG2 and the transistor PG3 are turned on. This means that the node NET 2 can have a logic high level (hereinafter referred to as high level H). In contrast, the node NET 2 can be discharged when the transistor NG1 or the transistor NG2 is turned on and the transistor NG3 is turned on at the same time. This means that the node NET 2 can have a logic low level (hereinafter referred to as low level L).

[0037] Here, the high level H indicates a logic level of a reference level or higher, and the low level L may indicate a logic level of the reference level or less. For example, the high level H indicates a case of having a value higher than 50% of the logic level, and the low level L may indicate a case of having a value lower than 50% of the logic level. However, the present disclosure is not limited to this, and the magnitude of the reference level may be variously changed. Hereinafter, the logic level of the semiconductor circuit will be described as a high level H and a low level L based on this.

[0038] In this embodiment, as illustrated, transistors PG1, PG2, PG3, NG1, NG2, NG3 may be connected in series or parallel between the power supply voltage VDD and the ground voltage, but the present disclosure is not limited thereto. Likewise, some of the transistors PG1, PG2, PG3 may be constructed from, for example, a PMOS transistor, and the remaining transistors NG1, NG2, NG3 may be constructed from, for example, an NMOS transistor, but the present disclosure is not limited thereto.

[0039] Furthermore, in this embodiment, the configuration of the second subcircuit 120 is as shown in Fig. 3 illustrates the configuration using transistors PG1, PG2, PG3 and transistors NG1, NG2, NG3, but the present disclosure is not limited to this configuration. As long as a circuit performs the OR operation of the logic level of the input data D and the logic level of the NET 3 node and performs the NAND operation of the logic level of the output of the OR operation and the logic level of the NET 1 node to transfer the output values ​​to the NET 2 node, its detailed configuration can be variously modified as needed.

[0040] The second circuit 100 may include a transistor P1 connected to the inverted value of the logic level of the clock signal CLK to pull up the node NET 1, a transistor P2 connected in parallel to the transistor P1 and connected to the inverted value of the logic level of the node NET 0 to pull up the node NET 1, a transistor N1 connected to the logic level of the node NET 0 to transmit the logic level of the node NET 1, a transistor N2 connected in series to the transistor N1 and connected to the logic level of the node NET 2, and a transistor N3 connected in series to the transistor N2 and connected to the logic level of the clock signal CLK to transmit the ground voltage.

[0041] At this time, node NET 1 can be precharged when transistor P1 is turned on or transistor P2 is turned off. This means that node NET 1 can have a high logic level (a logic value of "1"). Conversely, node NET 1 can be discharged when all transistors N1 to N3 are turned on. This means that node NET 2 can have a low logic level (a logic value of "0").

[0042] For example, when the logic level of the clock signal CLK is a low level L or the logic level of the node NET 0 is a low level L, the node NET 1 may be precharged. Meanwhile, when the logic level of the clock signal CLK is a high level H, the logic level of the node NET 0 is a high level H, and the logic level of the node NET 2 is a high level H, the node NET 1 may be discharged. However, the present disclosure is not limited thereto.

[0043] In this embodiment, as illustrated, the transistors P1, P2, N1, N2, N3 may be connected in series or parallel between the power supply voltage VDD and the ground voltage, but the present disclosure is not limited thereto. Likewise, some of the transistors P1, P2 are constructed, for example, from PMOS transistors, and the remaining transistors N1, N2, N3 may be constructed, for example, from NMOS transistors. However, the present disclosure is not limited thereto, and some other embodiments of the second circuit 100 will be described below.

[0044] The latch circuit 300 includes a latch transistor PL1 connected to the inverted value of the logic level of the node NET 0 to pull up the node NET 4, a latch transistor PL2 connected to the power source VDD on one side and connected to the logic level of the node NET 4, a latch transistor PL3 connected in series with the latch transistor PL2 on one side, connected to the node NET 4 on the other side, and connected to the inverted value of the logic level of the clock signal CLK, and an inverter I1 that inverts the logic level of the node NET 4 and transmits it to the output terminal OUT.

[0045] Furthermore, the latch circuit 300 may further include a latch transistor NL1 connected between the node NET 3 and the node NET 4 and tied to the logic level of the clock signal CLK, and a latch transistor NL2 connected in parallel to the latch transistor NL1 and tied to the inverted value, which is inverted by the inverter I2, of the logic level of the node NET 4.

[0046] In this embodiment, the transistors PL1, PL2, PL3, NL1, NL2 may be connected in series or parallel between the power supply voltage VDD and the node NET3, but the present disclosure is not limited thereto. Likewise, some of the transistors PL1, PL2, PL3 may be constructed from, for example, a PMOS transistor, and the remaining transistors NL1, NL2 may be constructed from, for example, an NMOS transistor, but the present disclosure is not limited thereto.

[0047] Furthermore, in this embodiment, the configuration of the latch circuit 300 is as shown in Fig. 1 illustrates the circuit configured using the transistors PL1, PL2, PL3 and the transistors NL1, NL2, however, the present disclosure is not limited to such a configuration, and as long as the circuit is configured so that each time the clock signal CLK rises (for example, a positive edge), the logic level of the node NET 0 is transferred to the output terminal OUT, and the circuit value is maintained in the output circuit OUT in a section in which the clock signal CLK does not rise, its detailed configuration can be variously modified as needed.

[0048] The present disclosure is configured such that the first circuit 100 is used to operate the flip-flop, some of the transistors included in the second subcircuit 120 are shared by directly connecting the node NET 2 of the second subcircuit 120, which serves as an output terminal included in the first circuit 100, to the first subcircuit 110, and a discharge path is integrated.

[0049] Thus, in the semiconductor circuit according to some embodiments of the present disclosure, the number of transistors to be used can be reduced, and the area required to form the circuit can be reduced. Thus, the manufacturing cost of the semiconductor circuit is reduced, and the efficiency of the usage area can be increased. In addition, it is possible to achieve low power consumption while maintaining the performance of the flip-flop.

[0050] The Fig. 4 to 7 are timing charts for explaining the operation of the semiconductor circuit according to an embodiment of the present disclosure.

[0051] In the semiconductor circuit according to an embodiment of the present disclosure, the inverted value of the logic level of the input data D may be transmitted to the output terminal OUT each time the clock signal CLK increases. That is, the logic level of the output terminal OUT may be varied at a positive edge of the clock signal CLK. The value of the logic level of the output terminal OUT may be maintained at a section other than the positive edge of the clock signal CLK. Accordingly, when the clock signal CLK is at the high level H, the logic level of the output terminal OUT may have a value opposite to the logic level of the input data D. However, the present disclosure is not limited to this.

[0052] Fig. 4 is a timing chart for explaining the operation of the semiconductor circuit based on the case where the logic level of the input data D is the low level L.

[0053] In particular, the operation of the circuit at a time ta1 is described with reference to the Fig. 1 and Fig. 4. The logic level of the input data D is the low level L and the logic level of the clock signal CLK is the low level L.

[0054] In the first subcircuit 110, since the logic level of the clock signal CLK is the low level L, the transistor PE2, which is connected to the inverted value of the logic level of the clock signal CLK, is turned on to precharge the node NET0. At this time, the logic level of the node NET0 may be at a high level H.

[0055] Accordingly, transistor NE2, which is connected to the logic level of node NET 0, is turned on to discharge node NET 3. At this time, the logic level of node NET 3 can become a low level L.

[0056] In the second circuit 100, since the logic level of the clock signal CLK is the low level L, the transistor P1, which is connected to the inverted value of the logic level of the clock signal CLK, is turned on to precharge the node NET 1. At this time, the logic level of the node NET 1 can become a high level H.

[0057] In the second subcircuit 120, the gate G5 performs the OR operation of the logic level of the input data D (low level L) and the logic level (low level L) of the node NET 3 and transmits the low level L to the gate G4.

[0058] Gate G4 performs the NAND operation of the logic level (low level L) of the output of gate G5 and the logic level (high level H) of node NET 1 and transmits an output value (high level H) to node NET 2.

[0059] That is, in a state where the logic level of the clock signal CLK is the low level, both the node NET 0 and the node NET 1 are precharged, and the node NET 3 is discharged. The value of the node NET 2 becomes a high level H. The node NET 4 of the latch circuit 300 is precharged, and the logic level of the output terminal OUT is maintained at a low level L.

[0060] Subsequently, at a time ta2, the logic level of the clock signal CLK increases from the low level L to the high level H. Accordingly, the transistor NE1 is turned on, and the logic level of the node NET 2 can be transferred to the node NET 0. In other words, the logic levels of the node NET 2 and the node NET 0 can be the same.

[0061] Therefore, when transistor P1 of the second circuit 100 is turned off and transistors N1, N2, N3 are turned on, node NET1 can be discharged. That is, node NET1 is discharged when the logic level of clock signal CLK is high H, and it can be low L.

[0062] In the latch circuit 300, when the logic level of the clock signal CLK becomes a high level H, the transistor NL1 is turned on, and the logic level (low level L) of the node NET 3 is transferred to the node NET 4. Accordingly, the logic level of the output terminal OUT is determined to be the high level H, which is the inverted value of the logic level of the node NET 4.

[0063] Subsequently, at time ta3, the logic level of the clock signal CLK is converted from the high level H to the low level L. Accordingly, the node NET 1 is again precharged. However, regardless of the precharge of the node NET 1, the constant value of the node NET 0 is maintained, and the logic level of the output terminal OUT maintains the same value.

[0064] Subsequently, since there are no changes in the signal at a time ta4, the constant value is maintained and each node can have the same value as the time ta1.

[0065] Subsequently, the semiconductor circuit can be operated at a time ta5 in the same manner as in the time ta2, and the semiconductor circuit can be operated at a time ta6 in the same manner as in the time ta3.

[0066] Accordingly, in the semiconductor circuit of the present disclosure, each time the clock signal CLK increases (for example, when it changes from the low level L to the high level H), the logic level of the node NET 2 becomes the same as the logic level of the node NET 0, and the logic level of the node NET 0 can be transmitted to the output terminal OUT. Furthermore, in a section where the clock signal CLK does not increase, the value of the output terminal OUT can be maintained.

[0067] Furthermore, the logic level of the input data D has a value different from the logic level of the node NET 2. In a section in which the clock signal CLK is at a high level H, the logic level of the node NET 1 has a value different from the logic level of the node NET 0. However, the present disclosure is not limited thereto.

[0068] Fig. Fig. 5 is a timing chart for explaining the operation of the semiconductor circuit based on a case where the logic level of the input data D is the high level H. For convenience of description, the repeated description of the same matters as the contents described with reference to Fig. 4 will be omitted, and the differences will be mainly described.

[0069] Referring to the Fig. 1 and Fig. 5, at a time tb1, the logic level of the input data is the high level H and the logic level of the clock signal CLK is the low level L.

[0070] In the first subcircuit 110, since the logic level of the clock signal CLK is the low level L, the transistor PE2, which is connected to the inverted value of the logic level of the clock signal CLK, is turned on to precharge the node NET 0. Similarly, the transistor P1, which is connected to the inverted value of the logic level of the clock signal CLK, is turned on to precharge the node NET 1. At this time, all of the logic levels of the node NET 0 and the node NET 1 can become a high level H.

[0071] Accordingly, transistor NE2, which is connected to the logic level of node NET 0, is turned on to discharge node NET 3. At this time, the logic level of node NET 3 can become a low level L.

[0072] At this time, in the second subcircuit 120, gate G5 performs the OR operation of the logic level (high level H) of the input data D and the logic level (low level L) of the node NET 3, and transmits the high level H to gate G4. Gate G4 performs the NAND operation on the logic level (high level H) of the output of gate G5 and the logic level (high level H) of the node NET 1, and transmits the output value (low level L) to node NET 2.

[0073] That is, when the logic level of the input data D is the high level H, the logic level of the node NET 2 has a value opposite to the logic level of the node NET 1.

[0074] Subsequently, at a time tb2, the logic level of the clock signal CLK increases from the low level L to the high level H. Accordingly, the transistor NE1 is turned on and the logic level (low level L) of the node NET 2 can be transferred to the node NET 0.

[0075] At this time, in the second subcircuit 120, the transistor NG1 connected to the logic level of the input data D and the transistor NG3 connected to the node NET 1 are turned on, and the node NET 2 can be discharged.

[0076] Accordingly, the logic level of node NET 0 is discharged by the second subcircuit 120 and may become a low level L. Node NET 1 may be maintained at the high level H by turning on transistor P1.

[0077] In the latch circuit 300, when the logic level of the clock signal CLK becomes a high level H, the transistor NL1 is turned on, and the logic level (high level H) of the node NET 3 is transferred to the node NET 4. Accordingly, the logic level of the output terminal OUT is determined to be a low level L, which is an inverted value of the logic level of the node NET 4.

[0078] Subsequently, at time tb3, the logic level of clock signal CLK is converted from high H to low L. Accordingly, transistor PE1 is turned on, transistor NE1 is turned off, and node NET0 is again precharged. The logic level of the output terminal OUT is maintained at the same value.

[0079] Subsequently, since there is no change in the signal at time tb4, the constant value is maintained and each node can have the same value as time tb1.

[0080] Subsequently, the semiconductor circuit can be operated at time tb5 in the same manner as at time tb2, and the semiconductor circuit can be operated at time tb6 in the same manner as at time tb3.

[0081] Fig. 6 is a timing chart for explaining the operation of the semiconductor circuit based on a case where the logic level of the input data D increases from the low level L to the high level H. For convenience of explanation, the same matters as the contents described above will not be described hereinafter, and the differences will be mainly described.

[0082] Referring to the Fig. 1 and Fig. 6, the operation of the semiconductor circuit at times tc1, tc2, tc3 may be substantially the same as the operation at times ta1, ta2, ta3 described with reference to Fig. 4 are described.

[0083] That is, at time tc2, the logic level of the clock signal CLK rises from the low level L to the high level H. The transistor NE1 is turned on, and the logic level of the node NET 2 can be transferred to the node NET 0. In other words, the logic levels of the node NET 2 and the node NET 0 become identical to each other.

[0084] Accordingly, when transistor P1 of the second circuit 100 is turned off and transistors N1, N2, N3 are turned on, node NET1 may be discharged. That is, node NET1 may be discharged while the logic level of clock signal CLK is high (H), and it may be low (L).

[0085] In the latch circuit 300, when the logic level of the clock signal CLK becomes a high level H, the transistor NL1 is turned on, and the logic level (low level L) of the node NET 3 is transferred to the node NET 4. Accordingly, the logic level of the output terminal OUT is determined to be the high level H, which is the inverted value of the logic level of the node NET 4.

[0086] Subsequently, at time tc3, the logic level of the clock signal CLK is converted from the high level H to the low level L. Consequently, the transistor P1 is turned on, the transistor N3 is turned off, and the node NET1 is again precharged.

[0087] However, at time tc4, the logic level of the input data D can be converted from the low level L to the high level H.

[0088] At this time, transistor NE2, which is connected to the logic level of node NET 0, is turned on to discharge node NET 3. At this time, the logic level of node NET 3 becomes a low level L.

[0089] At this time, in the second subcircuit 120, the gate G5 performs the OR operation of the logic level (high level H) of the input data D and the logic level (low level L) of the node NET 3, and transmits the high level H to the gate G4. The gate G4 performs the NAND operation of the logic level (high level H) of the output of the gate G5 and the logic level (high level H) of the node NET 1, and transmits the output value (low level L) to the node NET 2. That is, when the logic level of the input data D is converted to the high level H, the logic level of the node NET 2 is converted to the low level L. However, since the logic level of the clock signal CLK does not change, the logic level of the node NET 2 is not transmitted to the output terminal OUT.

[0090] Subsequently, at time tc5, when the logic level of the clock signal CLK increases from the low level L to the high level H, the transistor NE1 is turned on and the logic level (low level L) of the node NET 2 can be transferred to the node NET 0.

[0091] At this time, in the second subcircuit 120, the transistor NG1, which is connected to the logic level of the input data D, and the transistor NG3, which is connected to the node NET 1, are turned on and the node NET 2 can be discharged.

[0092] Accordingly, the logic level of node NET 0 is discharged by the second subcircuit 120 and may become a low level L. Node NET 1 may be maintained at a high level H by turning on transistor P1.

[0093] In the latch circuit 300, when the logic level of the clock signal CLK becomes a high level H, the transistor NL is turned on, and the logic level (high level H) of the node NET 3 is transferred to the node NET 4. Accordingly, the logic level of the output terminal OUT is determined to be the low level L, which is the inverted value of the logic level of the node NET 4.

[0094] Subsequently, at time tc6, the logic level of clock signal CLK is converted from high H to low L. Accordingly, transistor PE1 is turned on, transistor NE1 is turned off, and node NET0 is again precharged. The logic level of the output terminal OUT is maintained at the same value.

[0095] Fig. 7 is a timing chart for explaining the operation of the semiconductor circuit based on the case where the logic level of the input data D is converted from the high level H to the low level L. For convenience of explanation, hereinafter, the repeated description of the same matter as the contents described above will not be described, and the differences will be mainly described.

[0096] Referring to the Fig. 1 and Fig. 7, the operation of the semiconductor circuit at times td1, td2, td3 is substantially the same as the operation at times tb1, tb2, tb3 described with reference to Fig. 5 are described.

[0097] That is, at time td2, when the logic level of the clock signal CLK increases from the low level L to the high level H, the transistor NE1 is turned on and the logic level (low level L) of the node NET 2 can be transferred to the node NET 0.

[0098] At this time, in the second subcircuit 120, the transistor NG1 connected to the logic level of the input data D and the transistor NG3 connected to the node NET 1 are turned on, and the node NET 2 can be discharged.

[0099] Accordingly, the logic level of node NET 0 is discharged by the second subcircuit 120 and may become a low level L. Node NET 1 may be maintained at a high level H by turning on transistor P1.

[0100] In the latch circuit 300, when the logic level of the clock signal CLK becomes a high level H, the transistor NL1 is turned on, and the logic level (high level H) of the node NET 3 is transferred to the node NET 4. Accordingly, the logic level of the output terminal OUT is determined to be the low level L, which is an inverted value of the logic level of the node NET 4.

[0101] Subsequently, at time td3, the logic level of clock signal CLK is converted from high H to low L. Accordingly, transistor PE1 is turned on, transistor NE1 is turned off, and node NET0 is again precharged. The logic level of the output terminal OUT is maintained at the same value.

[0102] However, at time td4, the logic level of the input data D can be converted from the high level H to the low level L.

[0103] Transistor NE2, which is connected to the logic level of node NET 0, is turned on to discharge node NET 3. At this time, the logic level of node NET 3 becomes a low level L.

[0104] Next, in the second subcircuit 120, gate G5 performs the OR operation of the logic level (low level L) of the input data D and the logic level (low level L) of the node NET 3, and transmits the low level L to gate G4. Gate G4 performs the NAND operation of the logic level (low level L) of the output of gate G5 and the logic level (high level H) of the node NET 1, and transmits the output value (high level H) to node NET 2. That is, when the logic level of the input data D is converted to the low level L, the logic level of the node NET 2 is converted to the high level H. However, since the logic level of the clock signal CLK does not change, the logic level of the node NET 2 is not transmitted to the output terminal OUT.

[0105] Subsequently, at time td5, the logic level of the clock signal CLK increases from the low level L to the high level H. The transistor NE1 is turned on, and the logic level of the node NET 2 can be transferred to the node NET 0. In other words, the logic levels of the node NET 2 and the node NET 0 become identical to each other.

[0106] Accordingly, when transistor P1 of the second circuit 100 is turned off and transistors N1, N2, N3 are turned on, node NET1 may be discharged. That is, node NET1 may be discharged while the logic level of clock signal CLK is high (H), and it may be low (L).

[0107] In the latch circuit 300, when the logic level of the clock signal CLK becomes a high level H, the transistor NL1 is turned on, and the logic level (low level L) of the node NET 3 is transferred to the node NET 4. Accordingly, the logic level of the output terminal OUT is determined to be the high level H, which is the inverted value of the logic level of the node NET 4.

[0108] Subsequently, at time td6, the logic level of the clock signal CLK is converted from the high level H to the low level L. Consequently, the transistor P1 is turned on, the transistor N1 is turned off, and the node NET1 is again precharged.

[0109] Fig. 8 is a circuit diagram illustrating a semiconductor circuit according to another embodiment of the present disclosure. For convenience of explanation, the same matters as the contents described above will not be described hereinafter, and the differences will be mainly described.

[0110] Referring to Fig. 8, a semiconductor circuit according to another embodiment of the present disclosure includes a first circuit 100, a second circuit 210, and a latch circuit 300. The first circuit 100 includes a first subcircuit 110 and a second subcircuit 122. The semiconductor circuit according to another embodiment of the present disclosure may have substantially the same structure as the semiconductor circuit described above with reference to FIG. Fig. 1 to 3.

[0111] However, as in the semiconductor circuit according to another embodiment of the present disclosure, the second subcircuit 122 and the second circuit 210 further comprise a transistor to which a scan enable signal SE and a scan input signal SIN are additionally supplied.

[0112] In particular, the second subcircuit 122 may include gate G5 and gate G4. Gate G5 may perform the OR operation of the logic level of the input data D, the logic level of the NET 3 node, and the logic level of the scan enable signal SE. Gate G4 performs the NAND operation of the logic level of the output of gate G5 and the logic level of the NET 1 node and may transmit the output values ​​to the NET 2 node.

[0113] The second circuit 210 may include a transistor P3 connected in series with the transistor P1 and tied to the inverted value of the logic level of the scan enable signal SE, and a transistor P4 connected in parallel with the transistor P3 and tied to the inverted value of the logic level of the scan input signal SIN.

[0114] Furthermore, the second circuit 210 may further comprise a transistor N4 connected to one end M1 of the transistor N1 and tied to the logic level of the scan enable signal SE, and a transistor N5 connected in series to the transistor N4 and tied to the logic level of the scan input signal SIN.

[0115] Fig. Fig. 9 is a circuit diagram illustrating a semiconductor circuit according to yet another embodiment of the present disclosure. For convenience of explanation, the same matters as the contents described above with reference to Fig. 8 are not described, and mainly the differences will be described.

[0116] Referring to Fig. 9, a semiconductor circuit according to yet another embodiment of the present disclosure includes a first circuit 100, a second circuit 220, and a latch circuit 300. The first circuit 100 includes a first subcircuit 110 and a second subcircuit 122. The semiconductor circuit according to yet another embodiment of the present disclosure may have substantially the same structure as the semiconductor circuit described above with reference to Fig. 8 is described.

[0117] However, the second circuit 220 of the semiconductor circuit according to yet another embodiment of the present disclosure may include a transistor N6 rather than the transistor N1.

[0118] In particular, the second circuit 220 may further include a transistor N6 connected to the node NET 1 at one end and tied to the logic level of the node NET 0, a transistor N4 connected in series to the transistor N6 and tied to the logic level of the scan enable signal SE, and a transistor N5 connected in series to the transistor N4 and tied to the logic level of the scan input signal SIN.

[0119] The semiconductor circuit according to some embodiments of the present disclosure, which is described with reference to the Fig. 8 and Fig. 9 is configured such that the first circuit 100 is used to operate the flip-flop, and by directly connecting the node NET2 serving as the output terminal of the second subcircuit 122 included in the circuit 100 to the first subcircuit 110, some transistors included in the second subcircuits 120 are shared, and the discharge path is integrated. Thus, in the semiconductor circuit according to some embodiments of the present disclosure, the number of transistors used is reduced and the area required to form the circuit can be reduced. Thus, the manufacturing cost of the semiconductor circuit is reduced and the area utilization efficiency can be increased. In addition, it is possible to achieve low power consumption while maintaining the performance of the flip-flop.

[0120] The Fig. 10 and Fig. 11 are timing diagrams for explaining the operation of the semiconductor circuit according to some embodiments of the present disclosure. Hereinafter, the same matters as in the embodiments described above will not be described, and differences will be mainly described.

[0121] The semiconductor circuit according to some embodiments of the present disclosure may be implemented in substantially the same manner as the semiconductor circuit described with reference to the Fig. 4 to 7 when the scan enable signal SE is not enabled (low level L).

[0122] However, when the scan enable signal SE is enabled (high level H), in the semiconductor circuit, the logic level of the output terminal OUT may change by the scan input signal SIN instead of the input data D.

[0123] Fig. 10 is a timing chart for explaining the operation of the semiconductor circuit based on the case where the logic level of the scan input signal SIN is the high level H.

[0124] In particular, he may, with reference to Fig. 10, in the case of times te1, te2, te3 will be substantially the same as the operation of the semiconductor circuit at times tb1, tb2, tb3 described with reference to Fig. 5 is described.

[0125] However, at time te4, the logic level of the scan enable signal SE is high. At this time, the node NET1 can be precharged when all transistors P1 and P4 are turned on. That is, the node NET1 is only precharged when all the logic levels of the scan input signal SIN and the logic level of the clock signal CLK are low.

[0126] That is, when the logic level of the scan enable signal SE is high level H, the node NET 1 is precharged when all of the logic levels of the scan input signal SIN and the logic level of the clock signal CLK are low level L. Moreover, when the logic level of the scan enable signal SE is low level L, regardless of the logic level of the scan input signal SIN, the node NET 1 is precharged when the logic level of the clock signal CLK is low level L.

[0127] In the second subcircuit, since gate G5 performs the OR operation of the logic level (high level H) of the scan enable signal SE, the logic level of the input signal D, and the logic level of the NET 3 node, it transfers the high level H to gate G4. Gate G4 performs the NAND operation of the logic level (high level H) of the output of gate G5 and the logic level of the NET 1 node and transfers the output values ​​to the NET 2 node. That is, the logic level of the NET 2 node becomes opposite to the logic level of the NET 1 node.

[0128] When transistor P4, which is connected by the inverted value of the logic level of the scan input signal SIN, is not activated, node NET 1 is not precharged, and when transistors N1, N4, and N5 are turned on, node NET 1 is discharged. Therefore, node NET 1 has a low logic level (L), and node NET 2 has a high logic level (H). However, since the logic level of the clock signal CLK does not change, the logic level of node NET 2 is not transmitted to the output terminal OUT.

[0129] Subsequently, at time te5, when the logic level of the clock signal CLK increases from the low level L to the high level H, the transistor NE1 is turned on, the logic level (high level H) of the node NET 2 can be transferred to the node NET 0. In addition, the logic level of the node NET 3 becomes a low level L, which is the inverted value of the logic level of the node NET 0.

[0130] In the latch circuit 300, when the logic level of the clock signal CLK becomes a high level H, the transistor NL1 is turned on, the logic level (low level L) of the node NET 3 is transferred to the node NET 4. Accordingly, the logic level of the output terminal OUT is determined to be the high level H, which is the inverted value of the logic level of the node NET 4.

[0131] Subsequently, at time te6, the logic level of the clock signal CLK is converted from the high level H to the low level L. At this time, the logic level of the output terminal OUT is maintained at the same value.

[0132] Fig. 11 is a timing chart for explaining the operation of the semiconductor circuit based on the case where the logic level of the scan input signal SIN is the low level L.

[0133] In particular, with reference to Fig. 11, in the case of times tf1, tf2, tf3, this may be substantially the same as the operation of the semiconductor circuit at times ta1, ta2 and ta3, which are described with reference to Fig. 4 are described.

[0134] However, at time tf4, the logic level of the scan enable signal SE is the high level H. At this time, the node NET 1 can be precharged when the transistors P1 and P4 are turned on.

[0135] In the second subcircuit 122, since gate G5 performs the OR operation of the logic level (high level H) of the scan enable signal SE, the logic level of the input data D, and the logic level of the NET node, it transfers the high level H to gate G4. Gate G4 performs the NAND operation of the logic level (high level H) of the output of gate G5 and the logic level of the NET 1 node and transfers the output value to node NET 2. That is, the logic level of node NET 2 becomes opposite to the logic level of node NET 1.

[0136] Since transistor P1, which is connected by the inverted value of the logic level of the clock signal CLK, is activated, the node NET 1 is precharged. Therefore, the node NET 1 has a high logic level (H), and the node NET 2 has a low logic level (L). However, since the logic level of the clock signal CLK does not change, the logic level of the node NET 2 is not transmitted to the output terminal OUT.

[0137] Subsequently, at time tf5, when the logic level of the clock signal CLK increases from the low level L to the high level H, the transistor NE1 is turned on, and the logic level (low level L) of the node NET 2 can be transferred to the node NET 0. In addition, the logic level of the node NET 3 becomes a high level H, which is the inverted value of the logic level of the node NET 0.

[0138] In the latch circuit 300, when the logic level of the clock signal CLK becomes a high level H, the transistor NL1 is turned on, and the logic level (high level H) of the node 3 is transferred to the node NET 4. Accordingly, the logic level of the output terminal OUT is determined to be the low level L, which is the inverted value of the logic level of the node NET 4.

[0139] Subsequently, at time tf6, the logic level of the clock signal CLK is converted from the high level H to the low level L. At this time, the logic level of the output signal OUT is maintained at the same value.

[0140] Accordingly, in another semiconductor circuit of the present embodiment, each time the clock signal CLK increases (for example, when it changes from the low level L to the high level H), the logic level of the node NET 2 becomes the same as the logic level of the node NET 0, and the logic level of the node NET 0 can be transferred to the output terminal OUT. Furthermore, in a section where the clock signal CLK does not increase, the value of the output terminal OUT can be maintained.

[0141] However, when the scan enable signal SE is enabled, the semiconductor circuit may be operated in a test mode for the scan operation, and the output value of the output terminal OUT may change based on the scan input signal SIN instead of the input data D. For example, when the scan input signal SIN is at a low level (L), the logic level of the output terminal OUT may be converted from the high level to the low level (L) upon a positive edge of the clock signal CLK. However, the present disclosure is not limited to this, and when the scan enable signal SIN is at a low level (L), the logic level of the output terminal OUT may be converted from the low level (L) to the high level (H) upon a positive edge of the clock signal CLK.

[0142] Fig. 12 is a circuit diagram illustrating a semiconductor circuit according to yet another embodiment of the present disclosure. For convenience of explanation, the same matters as the contents described above with reference to Fig. 8 are not described, and mainly the differences will be described.

[0143] Referring to Fig. 12, the semiconductor circuit according to yet another embodiment of the present disclosure includes a first circuit 100, a second circuit 230, and a latch circuit 310. The first circuit 100 includes a first subcircuit 110 and a second subcircuit 122. The semiconductor circuit according to yet another embodiment of the present disclosure may have substantially the same structure as the semiconductor circuit described above with reference to Fig. 8 is described.

[0144] However, in the semiconductor circuit according to another embodiment of the present disclosure, the second circuit 230 and the latch circuit 310 further include a transistor to which a reset signal R is additionally supplied.

[0145] In particular, the second circuit 230 may further comprise a reset transistor R1 connected between the transistor P1 and the node NET 1 and tied to the inverted value of the logic level of the reset signal R, and a reset transistor R2 connected between the node NET 1 and ground and tied to the logic level of the reset signal R.

[0146] Furthermore, the latch circuit 310 may further include a reset transistor R3 connected between the power source VDD and the latch transistor PL2 and tied to the inverted value of the logic level of the reset signal R, and a reset transistor R4 connected in parallel to the latch transistor NL1 and tied to the logic level of the reset signal R to discharge the node NET4.

[0147] Fig. 13 is a circuit diagram illustrating a semiconductor circuit according to yet another embodiment of the present disclosure. For convenience of explanation, the same matters as in the embodiments described above with reference to Fig. 9 are not described, and mainly the differences will be described.

[0148] Referring to Fig. 13, a semiconductor circuit according to yet another embodiment of the present disclosure includes a first circuit 100, a second circuit 240, and a latch circuit 310. The semiconductor circuit according to yet another embodiment of the present disclosure may have substantially the same structure as the semiconductor circuit described with reference to Fig. 9.

[0149] However, in the semiconductor circuit according to yet another embodiment of the present disclosure, the second circuit 230 and the latch circuit 310 further include a transistor to which a reset signal R is additionally supplied.

[0150] In particular, the second circuit 240 may further include a reset transistor R1 connected between the transistor P1 and the node NET 1 and tied to the inverted value of the logic level of the reset signal R, and a reset transistor R2 connected between the node NET 1 and ground and tied to the logic level of the reset signal R.

[0151] Furthermore, the latch circuit 310 may further include a reset transistor R3 connected between the power source VDD and the latch transistor PL2 and tied to the inverted value of the logic level of the reset signal R, and a reset transistor R4 connected in parallel to the latch transistor NL1 and tied to the logic level of the reset signal R to discharge the node NET4.

[0152] Fig. 14 is a flowchart for explaining the operation of the semiconductor circuit according to some embodiments of the present disclosure. Hereinafter, the same matters as the embodiments described above will not be described, and the differences will be mainly described.

[0153] The semiconductor circuit according to some embodiments of the present disclosure may be implemented in substantially the same manner as the semiconductor circuit described above with reference to the Fig. 4 to 7 when the reset signal R is not activated (low level L).

[0154] However, when the reset signal R is activated (high level H), the logic level of the output terminal OUT of the semiconductor circuit can immediately become a high level H regardless of whether the clock signal CLK increases.

[0155] Fig. 14 is a timing chart for explaining the operation of the semiconductor circuit based on a case where the logic level of the input data D is the high level H. However, the present disclosure is not limited thereto.

[0156] In particular with reference to Fig. 14, in the case of times tg1, tg2, tg3, it may be substantially the same as the operation of the semiconductor circuit at times tb1, tb2, tb3, which are described with reference to Fig. 5 are described.

[0157] However, at time tg4, the logic level of the reset signal R is the high level H. At this time, the node NET 1 is discharged by turning on the reset transistor R2.

[0158] In the second subcircuit 122, since gate G5 performs the OR operation of the logic level of the scan enable signal SE, the logic level (high level H) of the input data D, and the logic level of the NET 3 node, it transfers the high level H4 to gate G4. Gate G4 performs the NAND operation of the logic level (high level H) of the output of gate G5 and the logic level of the NET 1 node and transfers the output value to the NET 2 node. That is, the logic level of the NET 2 node becomes opposite to the logic level of the NET 1 node.

[0159] The NET 1 node is discharged when the reset signal R is activated. Accordingly, the NET 1 node has a low logic level (L) and the NET 2 node has a high logic level (H).

[0160] Node NET 0 is precharged by transistor PE1, which is connected to the logic level (low level L) of node NET 1. Accordingly, the logic level of node NET 3 is low level L.

[0161] In the latch circuit 310, when the logic level of the reset signal R becomes a high level H, the reset transistor R4 is turned on, and the logic level (low level L) of the node NET 3 is transferred to the node NET 4. Accordingly, the logic level of the output terminal OUT is determined to be the high level H, which is the inverted value of the logic level of the node NET 4.

[0162] Subsequently, at time tg5 and time tg6, since the logic level of the reset signal R is maintained at the high level H, the logic level of the output terminal OUT is maintained at the high level H regardless of the logic level of the clock signal CLK.

[0163] Fig. 15 is a block diagram of a SoC system including the semiconductor circuit according to embodiments of the present disclosure.

[0164] Referring to Fig. 15, a SoC system 1000 includes an application processor 1001 and a DRAM 1060.

[0165] The application processor 1001 may include a central processing unit 1010, a multimedia system 1020, a bus 1030, a memory system 1040, and a peripheral circuit 1050.

[0166] The central processing unit 1010 may perform the operations required to operate the SoC system 1000. In some embodiments of the present disclosure, the central processing unit 1010 may be formed by a multi-core environment having multiple cores.

[0167] The multimedia system 1020 may be used to perform various multimedia functions in the SoC system 1000. The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like.

[0168] Bus 1030 may be used for data communication among central processing unit 1010, multimedia system 1020, storage system 1040, and peripheral circuitry 1050. In some embodiments of the present disclosure, bus 1030 may have a multilayer structure. In particular, bus 1030 may be, but is not limited to, a multilayer advanced high-performance bus (AHB) or a multilayer advanced extensible interface (AXI).

[0169] The memory system 1040 may provide an environment necessary for the application processor 1001 to connect to external memory (e.g., DRAM 1060) and operate at high speed. In some embodiments of the present disclosure, the memory system 1040 may include a separate controller (e.g., a DRAM controller) necessary to control the external memory (e.g., DRAM 1060).

[0170] Peripheral circuitry 1050 may provide an environment necessary for SoC system 1000 to smoothly connect to an external device (e.g., a motherboard). Accordingly, peripheral circuitry 1050 may include various interfaces that enable the external device connected to SoC system 1000 to be compatible with SoC system 1000.

[0171] DRAM 1060 may function as operational memory required for the operation of application processor 1001. In some embodiments of the present disclosure, DRAM 1060 may be located external to application processor 1001, as illustrated. Specifically, DRAM 1060 may be packaged with application processor 1001 in a package-on-package (PoP) configuration.

[0172] The SOC system 1000 may include at least one of the semiconductor circuits according to the above-mentioned embodiments of the present disclosure.

[0173] Furthermore, the above-mentioned SoC system 1000 can be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, and a memory card, or any type of electronic products capable of transmitting or receiving information in a wireless environment.

[0174] Fig. 16 is a block diagram illustrating an electronic system including the semiconductor circuit according to embodiments of the present disclosure.

[0175] Referring to Fig.16, an electronic system 1100 according to the embodiment of the present disclosure may include a controller 1110, an input / output (I / O) device 1120, a storage device 1130, an interface 1140, and a bus 1150. The controller 1110, the I / O device 1120, the storage device 1130, and / or the interface 1140 may be connected to each other by bus 1150. The bus 1150 corresponds to a path over which the data is moved.

[0176] Controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing similar functions to the elements. I / O device 1120 may include a keypad, a keyboard, and a display device. Memory device 1130 may store data and / or instructions. Interface 1140 may be used to transmit data or receive data from a communications network. Interface 1140 may be a wired or wireless interface. For example, interface 1140 may include an antenna or a wired or wireless transceiver.

[0177] Although not shown in the drawing, the electronic system 1100 may have an operating memory for enhancing the operation of the controller 1110 and may further include a high-speed DRAM or SRAM.

[0178] The electronic system 1100 may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless telephone, a mobile phone, a digital music player and a memory card, or any type of electronic product capable of transmitting or receiving information in a wireless environment.

[0179] At least one of the semiconductor circuits according to the embodiments of the present disclosure may be used as at least one of the components of the electronic system 1100.

[0180] As is traditional in the art, embodiments may be described and illustrated in units of blocks that perform a described function or functions. These blocks, which may be referred to herein as units or modules or the like, are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, and the like, and may optionally be operated by firmware and / or software. The circuits may, for example, be embodied in one or more semiconductor chips or on substrate supports such as printed circuit boards and the like.The circuits comprising a block may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the disclosure. Similarly, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the disclosure.

[0181] While the present disclosure has been particularly illustrated and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims. The exemplary embodiments should be considered in a descriptive sense only and not for purposes of limitation.

Claims

[1] Semiconductor circuit comprising: a first circuit (100) which determines a logic level of a second node (NET 2) and a logic level of a third node (NET 0) based on a logic level of input data (D), a logic level of a clock signal (CLK), and a logic level of a first node (NET 1); and a second circuit (200, 210, 220, 230, 240) which determines the logic level of the first node (NET 1) based on the logic level of the clock signal (CLK), the logic level of the second node (NET 2) and the logic level of the third node (NET 0), wherein the first circuit (100) comprises: a subcircuit (120, 122) which determines the logic level of the second node (NET 2) based on the logic level of the input data (D) and the logic level of the first node (NET 1); a first transistor (NE1) connected to the logic level of the clock signal (CLK) to connect the third node (NET 0) to the second node (NET 2); a second transistor (PE3) connected to the inverted value of the logic level of the third node (NET 0) to pull up a fourth node (NET 3); and a third transistor (NE2) connected to the logic level of the third node (NET 0) to pull down the fourth node (NET 3). [2] A semiconductor circuit according to claim 1, wherein the first circuit (100) further comprises: a fourth transistor (PE1) connected to an inverted value of the logic level of the first node (NET 1) to pull up the third node (NET 0); and a fifth transistor (PE2) connected in parallel with the fourth (PE1) and tied to the inverted value of the logic level of the clock signal (CLK) to pull up the third node (NET 0). [3] A semiconductor circuit according to claim 1, wherein the subcircuit (122) comprises: a first gate (G5) which performs an OR operation of the logic level of the input data (D), the logic level of the fourth node (NET 3) and a logic level of a scan enable signal (SE); and a second gate (G4) which performs a NAND operation of the logic level of the output of the first gate (G5) and the logic level of the first node (NET 1) and transmits the output value to the second node (NET 2). [4] A semiconductor circuit according to claim 1, wherein the subcircuit (120) comprises: a first sub-transistor (PG2) connected to the inverted value of the logic level of the fourth node (NET 3) to provide a power supply voltage (VDD); a second sub-transistor (PG3) connected in series with the first sub-transistor (PG2) and tied to the inverted value of the logic level of the input data (D); a third sub-transistor (PG1) connected in parallel to the first sub-transistor (PG2) and the second sub-transistor (PG3) connected in series, and connected to the inverted value of the logic level of the first node (NET 1) to pull up the second node (NET 2); a fourth sub-transistor (NG3) connected to the logic level of the first node (NET 1) and transmitting a ground voltage to the second node (NET 2); a fifth sub-transistor (NG1) connected between the fourth sub-transistor (NG3) and the second node (NET 2) and connected to the logic level of the input data (D); and a sixth sub-transistor (NG2) connected in parallel with the fifth sub-transistor (NG1) and tied to the logic level of the fourth node (NET 3). [5] The semiconductor circuit according to claim 1, further comprising a latch circuit (300, 310) which determines a logic level of an output terminal (OUT) based on the logic level of the clock signal (CLK) and the logic level of the third node (NET 0). [6] A semiconductor circuit according to claim 5, wherein the latch circuit (300) comprises: a first latch transistor (PL1) connected to the inverted value of the logic level of the third node (NET 0) to pull up a fifth (NET 4) node; a second latch transistor (PL2) connected to a power source (VDD) on one side and tied to the logic level of the fifth node (NET 4); a third latch transistor (PL3) connected in series with the second latch transistor (PL2) at one end, connected to the fifth node (NET4) at the other end, and tied to the inverted value of the logic level of the clock signal (CLK); and an inverter (I1) which inverts the logic level of the fifth node (NET 4) and transmits it to the output terminal (OUT). [7] A semiconductor circuit according to claim 1, wherein the second circuit (210, 230) comprises: a sixth transistor (P1) connected to the inverted value of the logic level of the clock signal (CLK) to pull up the first node (NET 1); a seventh transistor (P2) connected to the inverted value of the logic level of the third node (NET 0) to pull up the first node (NET 1); an eighth transistor (N1) connected to the logic level of the third node (NET 0) to transmit the logic level of the first node (NET 1); a ninth transistor (N2) connected in series with the eighth transistor (N1) and connected to the logic level of the second node (NET 2); and a tenth transistor (N3) connected in series with the ninth transistor (N2) and connected to the logic level of the clock signal (CLK) to transmit a ground voltage. [8] A semiconductor circuit according to claim 1, wherein the second circuit (220, 240) comprises: a sixth transistor (P1) connected to the inverted value of the logic level of the clock signal (CLK) to pull up the first node (NET 1); a seventh transistor (P2) connected to the inverted value of the logic level of the third node (NET 0) to pull up the first node (NET 1); an eighth transistor (N2) connected to the logic level of the second node (NET 2) to transmit the logic level of the first node (NET 1); and a ninth transistor (N3) connected in series with the eighth transistor (N2) and connected to the logic level of the clock signal (CLK) to transmit a ground voltage. [9] A semiconductor circuit according to claim 8, wherein the second circuit (220, 240) further comprises: a tenth transistor (N6) connected to the first node (NET 1) at one end and tied to the logic level of the third node (NET 0); an eleventh transistor (N4) connected in series with the tenth transistor (N6) and connected to the logic level of a scan enable signal (SE); and a twelfth transistor (N5) connected in series with the eleventh transistor (N4) and tied to the logic level of a scan input signal (SIN). [10] A semiconductor circuit according to claim 8, wherein the second circuit (240) comprises: a first reset transistor (R1) connected between the sixth transistor (P1) and the first node (NET 1) and connected to the inverted value of the logic level of a reset signal (R); and a second reset transistor (R2) connected between the first node (NET 1) and the ground voltage and connected to a logic level of the reset signal (R). [11] Semiconductor circuit comprising: a first circuit (100) which determines a logic level of a second node (NET 2) and a logic level of a third node (NET 0) based on a logic level of input data (D), a logic level of a clock signal (CLK) and a logic level of a first node (NET 1); a second circuit (210, 220, 230, 240) which determines the logic level of the first node (NET 1) based on the logic level of the clock signal (CLK), the logic level of the second node (NET 2) and the logic level of the third node (NET 0); and a latch circuit (300, 310) which determines a logic level of an output terminal (OUT) based on the logic level of the clock signal (CLK) and the logic level of the third node (NET 0), wherein the latch circuit (300, 310) comprises: a first latch transistor (PL1) connected to the inverted value of the logic level of the third node (NET 0) to pull up a fifth (NET 4) node; a second latch transistor (PL2) connected to a power source (VDD) on one side and tied to the logic level of the fifth node (NET 4); a third latch transistor (PL3) connected in series with the second latch transistor (PL2) at one end, connected to the fifth node (NET4) at the other end, and tied to the inverted value of the logic level of the clock signal (CLK); and an inverter (I1) which inverts the logic level of the fifth node (NET 4) and transmits it to the output terminal (OUT), wherein when the logic level of the clock signal (CLK) is a first logic level, the logic level of the second node (NET 2) is transferred to the third node (NET 0), and the logic level of the third node (NET 0) is transferred to the output terminal (OUT). [12] A semiconductor circuit according to claim 11, wherein the logic level of the input data (D) has a logic level which is different from the logic level of the second node (NET 2). [13] A semiconductor circuit according to claim 11, wherein the logic level of the first node (NET 1) or the third node (NET 0) is discharged at a positive edge of the clock signal (CLK). [14] A semiconductor circuit according to claim 11, wherein, when the logic level of the clock signal (CLK) is a second logic level different from the first logic level, the first circuit (100) precharges the third node (NET 0) and the second circuit (210, 220, 230, 240) precharges the first node (NET 1). [15] A semiconductor circuit according to claim 11, wherein, when the logic level of the input data (D) is a second logic level different from the first logic level, the logic level of the second node (NET 2) has the first logic level. [16] A semiconductor circuit according to claim 11, wherein, when the logic level of the input data (D) is the first logic level, the logic level of the second node (NET 2) has a second logic level. [17] Semiconductor circuit comprising: a first circuit (100) which determines a logic level of a second node (NET 2) and a logic level of a third node (NET 0) based on a logic level of input data (D), a logic level of a clock signal (CLK) and a logic level of a first node (NET 1); a second circuit (200, 210, 220, 230, 240) which determines the logic level of the first node based on the logic level of the clock signal (CLK), the logic level of the second node (NET 1) and the logic level of the third node (NET 0); and a latch circuit (300) which determines a logic level of an output terminal (OUT) based on the logic level of the first clock signal (CLK) and the logic level of the third node (NET 0), wherein: if the logic level of the clock signal (CLK) or the logic level of the third node (NET 0) is a first logic level, the first node (NET 1) is pre-charged, if the logic level of the clock signal (CLK) or the logic level of the second node (NET 2) is a second logic level different from the first logic level, the first node (NET 1) is discharged, if the logic level of the clock signal (CLK) or the logic level of the first node (NET 1) is the first logic level, the third node (NET 0) is pre-charged, and when all of the logic level of the clock signal (CLK), the logic level of the input data (D) and the logic level of the first node (NET 1) are the second level, the third node (NET 0) is discharged. [18] A semiconductor circuit according to claim 17, wherein the logic level of the output terminal (OUT) is the same as the logic level of the third node (NET 0) when the logic level of the clock signal (CLK) is the second logic level. [19] A semiconductor circuit according to claim 17, wherein the logic level of the input data (D) is the same as the logic level of the first node (NET 1) when the logic level of the clock signal (CLK) is the second logic level.

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