Semiconductor Device and Method

Abstract

A method for manufacturing a semiconductor device, the method comprising: Forming multiple gate electrodes (106) over a first region (102) of a semiconductor substrate (101), wherein the multiple gate electrodes extend in a first direction (111); Forming a first metal layer (109) over the multiple gate electrodes in the first region, wherein a single conductor in the first metal layer extends within the first region in a second direction (113) perpendicular to the first direction, wherein the first metal layer (109) is free of fuses; Forming a second metal layer (201) over the first metal layer (109) in the first region (102), wherein each individual conductor in the second metal layer extends within the first region in the first direction, wherein the second metal layer is free of fuses; Forming a third metal layer (301) over the second metal layer (201) in the first region (102), wherein each individual conductor in the third metal layer extends within the first region (111) in the second direction (113), wherein the third metal layer includes fuses (307 - 311); and wherein the formation of the second metal layer (201) forms the second metal layer with a first thickness, and wherein the formation of the third metal layer (301) forms the third metal layer with a second thickness that is different from the first thickness; wherein the second thickness is less than the first thickness.

Description

GENERAL STATE OF THE ART

[0001] As the size of semiconductor devices decreases, the size of each individual component within the device should also be reduced, or there is a risk that they will become a bottleneck for further reduction of the overall device. For example, as the size of transistors or active devices is reduced, the size of other parts of the semiconductor device, such as the dielectric layers and metallization layers that provide interconnectivity for the active devices, should also be reduced. Otherwise, the overall device size can remain the same.

[0002] However, reducing the dielectric and metallization layers presents its own set of problems. For example, if the metallization layers themselves are reduced in size, any devices formed within them, such as passive components including capacitors, resistors, fuses, etc., will also be reduced in size. However, miniaturizing these types of devices can modify their properties beyond a desired performance range. Therefore, new methods for forming and utilizing the metallization layers and the devices within them are desirable to further miniaturize these components.

[0003] US 2007 / 0280012A1 relates to a semiconductor device with a plurality of metallic interconnect layers comprising an internal circuit with a transistor element formed and connected using interconnects in the plurality of interconnect layers, and at least one fuse circuit with a fuse element.

[0004] US 5,825,203 A relates to an integrated circuit device with variable logic comprising a plurality of variable logic blocks whose logic functions can be variably set, and a plurality of variable wiring circuits whose wiring connections can be variably made.

[0005] US 2012 / 0306048A1 concerns electrically programmable metal fuses with narrow metal strips between wider end sections and a length-to-width ratio greater than 5, to localize heat and induce controlled electromigration during programming.

[0006] The present invention is defined by independent claims 1, 6 and 11. Specific embodiments are defined by dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be clarified that, in accordance with standard industry practice, various features are not shown to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased. Fig. 1A to 1B represent a formation of active devices and a first metal layer according to some embodiments. Fig. 2A to 2B represent the formation of a second metal layer according to some embodiments. Fig. 3A to 3B represent the formation of a third metal layer according to some embodiments. Fig. 4A to 4B represent the formation of a fourth metal layer according to some embodiments. Fig. 5A to 5B represent the formation of a fifth metal layer according to some embodiments. DETAILED DESCRIPTION

[0008] The invention is defined according to the independent claims. The dependent claims relate to corresponding further developments. The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, purely examples and are not intended to be limiting. For example, the formation of a first feature above or on top of a second feature, as described below, may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features are not in direct contact.Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not itself prescribe any relationship between the various embodiments and / or configurations described.

[0009] Furthermore, spatial terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to facilitate description of the relationship of one element or feature to another element(s) or feature(s) illustrated in the figures. The spatial expressions are intended to encompass orientations of the device in use or in operation beyond those shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial descriptors used herein may be interpreted accordingly.

[0010] With reference to Fig. 1A to 1B, wherein Fig. 1B a top view of Fig. 1A along line BB' in Fig. Figure 1A depicts a section of a semiconductor device 100 comprising a semiconductor substrate 101, active devices 103, an interlayer dielectric (ILD) 105, a first dielectric layer 107, and a second metal layer 109 (M1) within the first dielectric layer 107. The semiconductor substrate 101 can comprise doped or undoped bulk silicon or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or hybrid alignment substrates.

[0011] The semiconductor substrate 101 can incorporate active devices 103. As a person skilled in the art will recognize, many different active and passive devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to create the desired structural and functional requirements of the design for the first semiconductor device 100. The active devices 103 can be formed using any suitable method.

[0012] In a particular embodiment, the active devices 103 can contain a gate dielectric (in Fig. 1A not shown separately), a gate electrode 106, spacer 108, which is located over a channel region (in Fig. The gate dielectric and the gate electrode 106 comprise source / drain regions (also not shown separately in Figure 1A) located on each side of the gate electrode 106. The gate dielectric and the gate electrode 106 can be formed and structured on the semiconductor substrate 101 by any suitable process known in the art. The gate dielectric can be a high-k dielectric material such as silicon dioxide, silicon oxynitride, silicon nitride, an oxide, a nitrogen-containing oxide, aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, a combination thereof, or the like. Preferably, the gate dielectric has a relative permittivity value greater than about 4.

[0013] In one embodiment, where the gate dielectric comprises an oxide layer, the gate dielectric can be formed by any oxide process, such as thermal wet or dry oxidation in an environment containing H₂O, NO, or a combination thereof, or by chemical vapor deposition (CVD) techniques using tetraethyl orthosilicate (TEOS) and oxygen as precursors. In one embodiment, the gate dielectric has a thickness of between about 0.8 nm and about 5 nm, such as a thickness of about 1.6 nm.

[0014] The gate electrode 106 comprises a conductive material such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), doped polycrystalline silicon, other conductive materials, or a combination thereof. In one example, amorphous silicon is deposited and recrystallized to produce polycrystalline silicon (polysilicon). In an embodiment where the gate electrode 106 is polysilicon, the gate electrode 106 can be formed by depositing doped or undoped polysilicon by low-pressure chemical vapor deposition (LPCVD) to a thickness in the range of about 10 nm to about 250 nm, such as about 150 nm.

[0015] The spacers 108 are formed on the sidewalls of the gate dielectric and the gate electrode 106. The spacers 108 are typically formed by the full-surface deposition of a spacer layer (not shown) onto the previously formed structure. The spacer layer comprises SiN, SiC, SiON, oxide, and the like, and is formed by commonly used methods such as chemical vapor deposition (CVD), plasma-enhanced CVD, sputtering, and other methods known in the art. The spacer layer is then patterned, for example, by anisotropic etching to remove the spacer layer from the horizontal surfaces of the structure in order to form the spacers 108.

[0016] Source / drain regions are formed in the semiconductor substrate 101 on opposite sides of the gate dielectric. In an embodiment where the semiconductor substrate 101 is an n-type substrate, the source / drain regions are formed by implanting suitable p-type dopants such as boron, gallium, indium, or the like. Alternatively, in an embodiment where the semiconductor substrate is a p-type substrate, the source / drain regions can be formed by implanting suitable n-type dopants such as phosphorus, arsenic, or the like. These source / drain regions are implanted using the gate dielectric, the gate electrode 106, and the spacer 108 as masks.

[0017] It should be clarified that a person skilled in the art will recognize that many other processes, steps, or the like can be applied to form these source / drain regions. For example, a person skilled in the art can realize that several implants can be designed using different combinations of spacers and liners to form source / drain regions with a specific shape or property suitable for a particular purpose. Any one of these processes can be applied to form the source / drain regions, and the above description is not intended to limit the present embodiments to the steps presented above.

[0018] Considering Fig. 1B can the gate electrode 106 of each of the active devices 103 within a first region (in Fig. 1B (shown by the dashed box with reference marks 102) are formed in one embodiment such that they extend in the same direction to each other, and in one particular embodiment the first region 102 can be a fuse bit cell region. In one embodiment the first region 102 can be a region of the semiconductor substrate 101 having fuses embedded in a third metal layer 301 (in Fig. 1B is not shown, but is shown below in relation to Fig. 3 are shown and explained). Thus, although the first region 102 can comprise the entire semiconductor substrate 101, it can also comprise a subsection of the semiconductor substrate 101, such as a region with a first width W1 of approximately 200 µm to approximately 400 µm (e.g., 300 µm) and a first length L1 of approximately 100 µm to approximately 300 µm (e.g., 200 µm). However, any suitable dimension can be used.

[0019] Furthermore, the top view shows... Fig. 1B in the first region 102 at least some of the active devices 103 are arranged. The active devices 103, which are arranged in the first region 102 (in this top view), each have a gate electrode 106 with a first longitudinal axis (in Fig. 1B (represented by the dashed line with reference numeral 108) which is parallel to the other gate electrode 106 in the first region 102. Furthermore, the first longitudinal axis of each gate electrode 106 in the first region 102 extends along a first direction (in Fig. 1B represented by the arrow with reference mark 111).

[0020] With renewed reference to Fig. In 1A, the ILD layer 105 is formed over the active devices 103 to protect and insulate them. In one embodiment, the ILD layer 105 can comprise a material such as boron-phosphorus silicate glass (BPSG), although any suitable dielectrics can be used for each layer. The ILD layer 105 can be formed by applying a process such as PECVD, although alternatively, other processes such as LPCVD can be applied. The ILD layer 105 can be formed to a thickness ranging from about 10 nm to about 300 nm.

[0021] After the formation of the ILD layer 105, contact plugs 104 can be formed through the ILD layer 105 to electrically connect the active devices 103 to the overlying first metal layer 109. In another embodiment, the formation of the contact plugs 104 can first be initiated by forming contact plug openings through the ILD layer 105 to expose the two source / drain regions or, alternatively, the gate electrodes 106 of the active devices 103. In one embodiment, the contact plug openings can be formed by means of a suitable photolithographic masking and etching process.

[0022] After the contact plug openings are formed, a first adhesive layer can form (in Fig. 1A not shown separately). In one embodiment, the first adhesive layer is used to support the adhesion of the remaining contact connectors 104 to the underlying structure and can be, for example, tungsten, titanium nitride, tantalum nitride, or the like, and can be formed by a process such as CVD, plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like.

[0023] After the first adhesive layer is formed, the remainder of the contact connectors 104 is formed in contact with the adhesive layer. In one embodiment, the material of the contact connectors 104 is tungsten (W), although alternatively any other suitable material such as aluminum, copper, combinations thereof, or the like may be used. The material of the contact connectors 104 can be formed by a process such as CVD, although any suitable process such as PECVD, physical vapor deposition (PVD), atomic layer deposition (ALD), and the like may be used.

[0024] After filling, the contact plugs 104 are planarized so that the material of the contact plugs 104 that lies outside the ILD layer 105 is removed, so that the contact plugs 104 (one of which is in Fig. (as shown in Figure 1A). In one embodiment, the planarization process is a chemical-mechanical polishing (CMP) process in which a combination of etching materials and abrasive materials is brought into contact with the material of the contact plugs 104 and an abrasive pad (not shown separately) is used to grind away the material of the contact plugs 104 until all the material of the contact plugs 104 above the first dielectric layer 105 has been removed.

[0025] The first dielectric layer 107 can be formed over the ILD layer 105. The first dielectric layer 107 can be made from one or more suitable dielectric materials, such as low-k dielectrics like carbon-doped oxides, low-k dielectrics with extremely low dielectric constants like porous carbon-doped silicon dioxide, silicon dioxide, silicon nitride, a polymer like polyimide, combinations of these, or the like. The first dielectric layer 107 can be formed by a process such as spin deposition or chemical vapor deposition (CVD), although any suitable process can be used, and can have a first thickness T1 of between about 40 nm and about 100 nm, such as about 60 nm.

[0026] Fig. Figures 1A to 1B also represent the formation of the first metal layer 109 within the first dielectric layer 107. In one embodiment, the first metal layer 109 can be formed by, for example, a Damascene process, whereby an opening is first created in the first dielectric layer 107. In another embodiment, the opening can first be formed by applying and structuring a photoresist material over the first dielectric layer 107. After applying and structuring the photoresist material, a dry etching process such as reactive ion etching can be applied to transfer the structure from the structured photoresist to the underlying first dielectric layer 107.

[0027] After transferring the desired structure, the opening can be filled with a conductive material to form the first metal layer 109 within the first dielectric layer 107. In one embodiment, the formation of the conductive material can first be initiated by depositing a barrier layer (in Fig. (1A to 1B not shown separately) are initiated. The barrier layer can be a barrier material such as titanium nitride or tantalum nitride, which can be deposited by a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. However, any suitable material or deposition method can be used to form the barrier layer.

[0028] After the formation of the barrier layer, a conductive material can be deposited to fill and / or overfill the openings in the first dielectric layer 107. In one embodiment, the conductive material can be a material such as copper, aluminum, or tungsten, which can be formed, for example, by means of a seed layer (not shown) and a plating process such as electrochemical plating, although alternatively, depending on the desired materials, other formation processes such as sputtering, evaporation, or a PECVD process can be used. After filling the openings for the first metal layer 109 with conductive material, excess conductive material outside the openings for the first metal layer 109 can be removed, and the first metal layer 109 and the first dielectric layer 107 can be planarized using, for example, a chemical-mechanical polishing process.Furthermore, due to the fact that all excess conductive material outside the openings is removed, the first metal layer 109 also has the same thickness as the first dielectric layer 107, such as the first thickness T1.

[0029] With renewed reference to Fig. 1B The first metal layer 109 is used to connect the various active devices 103 (via the contact connectors 104), with the connections being routed as required to meet the functional requirements for the semiconductor device 100. Furthermore, each of the individual conductive lines within the first metal layer 109 has a second longitudinal axis (in Fig. 1B (shown by the dashed line with reference numeral 110) which is parallel to the other conductive lines within the first metal layer 109 within the first region 102. Furthermore, the second longitudinal axis 110 extends in a second direction (in Fig. 1B (represented by the arrow with reference numeral 113), which is perpendicular to the first direction 111. Accordingly, the first metal layer 109 is oriented perpendicular to the gate electrodes 106 of the active devices 103.

[0030] Fig. 2A to 2B represent a cross-sectional view and a top view respectively, wherein Fig. 2B a top view of Fig. Figure 2A shows the formation of a second dielectric layer 203 along line BB' of the semiconductor device 100 after the formation of a second metal layer 201 (M2). In one embodiment, the second dielectric layer 203 can initially be formed prior to the second metal layer 201, and the second dielectric layer 203 can be formed as described above with respect to the first dielectric layer 107. For example, the second dielectric layer 203 can be a low-k dielectric material formed by a spin-deposition process. However, in this process, the second dielectric layer 203 can be formed with a thickness T2 of between approximately 100 nm and approximately 200 nm, such as approximately 130 nm.

[0031] After forming the second dielectric layer 201, the second metal layer 201 can be formed within the second dielectric layer 203. In one embodiment, the second metal layer 201 can, for example, first be formed by creating openings for the second metal layer 201 within the second dielectric layer 203 using, for example, a dual-damascene process, in which two photolithographic masks and two etching processes are used to form both a lower via section and an upper trench section. In another embodiment, the openings for the second metal layer 201 can be initiated using a first mask together with a first etching process to form the shape of the lower via section of the second metal layer 201 (which is defined by the upper section of the second metal layer 201 in the second dielectric layer 203). Fig. 2A is separated by the dashed line 205).

[0032] In one embodiment, the first mask can be a photoresist arranged using, for example, a spin-on process. After arrangement, the photoresist can then be exposed to a structured light source and developed to form a structured photoresist with the desired structure for the lower via-connected section of the second metal layer 201. However, as an alternative, the first mask can be a hard mask such as silicon nitride. Alternatively, any suitable marking material and any process for structuring the masking material can be used.

[0033] After arranging and structuring the first mask, its structure can be transferred to the second dielectric layer 203. In one embodiment, a directional etching process, such as reactive ion etching, can be used to remove the material of the second dielectric layer 203, while the first mask serves as a mask during the etching process. Accordingly, only exposed and unprotected material is removed, thus transferring the structure of the first mask to the second dielectric layer 203.

[0034] After transferring the structure of the first mask to the second dielectric layer 203, the first mask can be removed. In an embodiment where the first mask is a photoresist, the first mask can be removed using, for example, an ashing process, which increases the temperature of the first mask until thermal decomposition occurs, thereby removing the photoresist. However, alternatively, any other removal method, such as a wet etching process, can be used.

[0035] After forming openings for the lower via sections of the second metal layer 201, the openings for the lower via sections can be extended simultaneously with the formation of upper trench sections within the second dielectric layer 203. In one embodiment, after forming the lower sections of the second metal layer 201 by the first mask and etching, a second mask and a second etching process can be used to extend the openings for the second metal layer 201 onto the first metal layer 109 and to form the upper trench section of the second metal layer 201, the second metal layer 201 being used to conduct electrical signals, power, and ground connections.

[0036] The second mask can be similar to the first, as explained above. For example, the second mask can be a photoresist structured into the desired pattern for the upper trench sections of the second metal layer 201 by exposing and developing a layer of a photoresist composition (not shown separately). However, as an alternative, the second mask can be a hard mask such as silicon nitride. Alternatively, any suitable marking material and any process for structuring the masking material can be used.

[0037] After arranging and structuring the second mask, its structure can be transferred to the second dielectric layer 203. In one embodiment, a directional etching process, such as reactive ion etching, can be used to remove the material of the second dielectric layer 203, with the second mask acting as a mask during the etching process. Accordingly, only exposed and unprotected material is removed, allowing the structure of the second mask to be transferred to the second dielectric layer 203. This process forms the widened upper trench sections of the second metal layer 201 and also extends the shape of the lower sections of the second metal layer 201 through the second dielectric layer 203 to expose the first metal layer 109.

[0038] Once complete, the second mask can be removed and the openings filled to form the second metal layer 201. In an embodiment where the second mask is a photoresist, the second mask can be removed using, for example, an ashing process, which raises the temperature of the second mask until the material thermally decomposes and can be removed. However, alternatively, any suitable removal process, such as etching or the application of a suitable solvent, can be used.

[0039] After removing the second mask, the second metal layer 201 can be formed within both the lower and upper vias using a first seed layer (not shown) and a plating process such as electrochemical plating, although alternative formation processes such as sputtering, evaporation, or PECVD can be used. The second metal layer 201 can comprise copper, but alternative materials such as aluminum or tungsten can be used. After filling the openings for the second metal layer 201 with conductive material, excess conductive material outside the openings for the second metal layer 201 can be removed, and the second metal layer 201 and the second dielectric layer 203 can be planarized using, for example, a chemical-mechanical polishing process.

[0040] In one embodiment, the lower via-hole section of the second metal layer 201 can be formed with a third thickness T3 of between approximately 40 nm and approximately 80 nm, such as approximately 50 nm. Furthermore, the upper via-hole section of the second metal layer 201 can be formed with a fourth thickness T4, which is greater than the first thickness T1, such as between approximately 60 nm and approximately 120 nm, such as approximately 80 nm. However, any suitable thickness can be used to form the second metal layer 201.

[0041] Fig. 2B, which shows a top view of the structure from Fig. Figure 2A illustrates that the individual conduits of the second metal layer 201 (e.g., the upper trench section) within the first area 102 of the second metal layer 201 have third longitudinal axes (which are in Fig. 2B (shown by the dashed line with reference numeral 207) exhibits that are parallel to each other. Furthermore, these third longitudinal axes 207 are aligned in the first direction 111. Accordingly, the individual conductors of the second metal layer 201 are aligned in the same direction as the gate electrodes 106 of the active devices 103.

[0042] Fig. 3A to 3B represent the formation of a third metal layer 301 (M3) and a third dielectric layer 303 over the second metal layer 201, wherein Fig. 3B a top view from Fig. 3A along line BB'. In one embodiment, the third dielectric layer 303 can be formed using similar methods and materials as described above with reference to the second dielectric layer 203. For example, the third dielectric layer 303 can be a low-k dielectric material formed by a spin-deposition process. However, any suitable process can be used to form the third dielectric layer 303. The third dielectric layer 303 can be formed with a fifth thickness T5 of between about 80 nm and about 140 nm, such as about 110 nm.

[0043] After forming the third dielectric layer 303, the third metal layer 301 can be formed within the third dielectric layer 303. In one embodiment, the third metal layer 301 can be formed using similar methods and materials as described above with reference to the second metal layer 201. For example, a two-stage dual-damascene process can be used to first form a first opening in the third dielectric layer 303 and then to enlarge the first opening through the third dielectric layer 303 to form a bottom via opening, while simultaneously forming a second opening in, but not through, the third dielectric layer 303 for a top trench opening.After the openings are formed, a conductive material such as copper can be deposited to fill and / or overfill the openings, and excess conductive material outside the openings can be removed using a planarization process. However, any suitable fabrication method can be used to form the third metal layer 301.

[0044] In one embodiment, the upper groove sections of the third metal layer 301 have a sixth thickness T6 that is less than the fourth thickness T4 (of the second metal layer 201), which is, for example, between about 40 nm and about 100 nm, such as about 60 nm. Furthermore, the lower via sections of the third metal layer 301 can be formed with a seventh thickness T7 of between about 40 nm and about 80 nm, such as about 50 nm. However, any suitable thickness can be used.

[0045] By forming the upper trench sections of the third metal layer 301 with a sixth thickness T6 that is less than the fourth thickness T4, the overall resistance present during fuse programming can be reduced. In particular, in an embodiment where the second metal layer 201 is thicker than the third metal layer 301, the lower resistance of the second metal layer 201 leads to an increase in the fuse connection current that can be supplied to the fuses within the third metal layer 301 (e.g., the first fuse 307, the second fuse 309, and the third fuse 311) from the connections of the second metal layer 201.

[0046] Fig. 3B, which shows a top view of the structure Fig. Figure 3A illustrates that the individual conductors within the first area 102 of the third metal layer 301 third longitudinal axes (which are in Fig. 2B (shown by the dashed line with reference numeral 305) exhibits the third longitudinal axes 305 being parallel to each other. Furthermore, the third longitudinal axes 305 are also aligned in the second direction 113. Accordingly, the third metal layer 301 is aligned with the first metal layer 109 and also perpendicular to the gate electrodes 106 of the active devices 103, as well as perpendicular to the second metal layer 201 and the gate electrodes 106 of the active devices 103. By forming the third longitudinal axes 305 perpendicular to the gate electrodes, the structure is suitable for lithopgraphy.

[0047] Fig. 3B further describes the formation of fuses (e.g., a first fuse 307, a second fuse 309, and a third fuse 311) within the third metal layer 301. In one embodiment, the first fuse 307, the second fuse 309, and the third fuse 311 are formed in the third metal layer 301 by adjusting the thickness of sections of the individual conductors of the third metal layer 301 using, for example, masking and etching processes during the formation of the openings for the third metal layer 301.For example, in a particular embodiment, the first fuse 307, in which the individual conductors of the third metal layer 301 within the first region 102 have a second width W2 of between approximately 35 nm and approximately 55 nm, such as approximately 45 nm, can be formed with a third width W3 that is smaller than that of the second fuse 309 and the third fuse 311, and is, for example, between approximately 20 nm and approximately 40 nm, such as approximately 30 nm. Furthermore, the second fuse 309 can be formed with a fourth width W4 that is larger than that of the first fuse 307 and smaller than that of the third fuse 311, such as between approximately 25 nm and approximately 45 nm, such as approximately 35 nm. Finally, the third fuse 311 can be formed with a fifth width W5 that is larger than that of both the first fuse 307 and the second fuse 309, such as between approximately 30 nm and approximately 50 nm, such as approximately 40 nm.However, any suitable dimension can be used.

[0048] Although there are only three fuses in Fig. Figure 3B is intended to represent the embodiments and not to limit them. Rather, any suitable number of fuses (greater than, equal to, or less than the number shown) may be used, and all such numbers shall be fully included within the scope of protection of the embodiments.

[0049] By forming the fuses (e.g., the first fuse 307, the second fuse 309, and the third fuse 311) within the third metal layer 301 without additional conductors, and by not forming the fuses within the first metal layer 109, not within the second metal layer 201 (which has routing), or within the overlying metal layers (described below), the first region 102 containing the fuses can be reduced in size, since the routing that may be required in the second metal layer 201 (in addition to the fuses) can be eliminated. For example, the size of the first region 102 (in a top view) can be reduced to a range of approximately 20,000 µm. 2 and approximately 120,000 µm 2 such as 60000 µm 2 The size of the first area 102, which includes the fuses, can be reduced. By reducing the size of the first area 102, which includes the fuses, the overall size of the semiconductor device 100 can also be reduced.

[0050] Fig. Figures 4A to 4B represent the formation of a fourth metal layer 401 (M4) within a fourth dielectric layer 403. In one embodiment, the fourth dielectric layer 403 can be formed using similar methods and materials as described above with reference to the second dielectric layer 203. For example, the fourth dielectric layer 403 can be a low-k dielectric material deposited using a spin-depositing process to an eighth thickness Ts of between about 100 nm and about 200 nm, such as about 130 nm. can be formed. However, any suitable processes and any suitable thicknesses can be used to form the fourth dielectric layer 403.

[0051] After forming the fourth dielectric layer 403, the fourth metal layer 401 can be formed within the fourth dielectric layer 403. In one embodiment, the fourth metal layer 401 can be formed using similar methods and materials as described above with reference to the second metal layer 201. For example, a two-stage dual-damascene process can be used to first form a first opening for a lower via section in the fourth dielectric layer 403 and then to enlarge the first opening through the fourth dielectric layer 403 while simultaneously forming a second opening in, but not through, the fourth dielectric layer 403 for an upper trench opening of the fourth metal layer 401.After the openings are formed, a conductive material such as copper can be deposited to fill and / or overfill the openings, and excess conductive material outside the openings can be removed using a planarization process. However, any suitable fabrication method can be used to form the fourth metal layer 401.

[0052] In one embodiment, the upper trench section of the fourth metal layer 401 can be formed with a ninth thickness T9 of between approximately 60 nm and approximately 120 nm, such as approximately 80 nm. Furthermore, the lower via section can have a tenth thickness T 10 The thickness may range from approximately 40 nm to approximately 80 nm, or approximately 50 nm. However, any suitable thickness can be used to form the upper trench section of the fourth metal layer 401 and the lower via section of the fourth metal layer 401.

[0053] Fig. 4B, which shows a top view of the structure Fig. 4A along line BB' (where the active devices 103 are also represented by the dashed lines for simplicity) illustrates that the individual conductors of the fourth metal layer 401 (e.g., the upper trench sections of the fourth metal layer 401) within the fourth metal layer 401 fifth longitudinal axes (which in Fig. 4B (shown by the dashed line with reference numeral 405) exhibits that are aligned with each other. Furthermore, the fifth longitudinal axes 405 are also aligned in the first direction 111. Accordingly, the fourth metal layer 401 is aligned parallel to the second metal layer 201 and the gate electrodes 106 of the active devices 103. Additionally, the fourth metal layer 401 is perpendicular to the third metal layer 301 and the first metal layer 109.

[0054] Fig. 5A to 5B represent a formation of a fifth metal layer 501 (M3) within a fifth dielectric layer 503, wherein Fig. 5B a top view from Fig. 5A along line BB'. In one embodiment, the fifth dielectric layer 503 can be formed using similar methods and materials as described above with reference to the second dielectric layer 203. For example, the fifth dielectric layer 503 can be a dielectric low-k material formed to an eleventh thickness T using a spin-on process. 11 The fifth dielectric layer 503 can be formed from a size between approximately 200 nm and approximately 400 nm, such as approximately 300 nm. However, any suitable process can be used to form the fifth dielectric layer 503.

[0055] After forming the fifth dielectric layer 503, the fifth metal layer 501 can be formed within the fifth dielectric layer 503. In one embodiment, the fifth metal layer 501 can be formed using similar processes and materials as described above with reference to the second metal layer 201. For example, a two-stage dual-damascene process can be used to first form a first opening in the fifth dielectric layer 503 for the lower via section of the fifth dielectric layer 501, and then to enlarge the first opening through the fifth dielectric layer 503 while simultaneously forming a second opening in, but not through, the fifth dielectric layer 503 for the upper trench section of the fifth metal layer 501.After the openings are formed, a conductive material such as copper can be deposited to fill and / or overfill the openings, and excess conductive material outside the openings can be removed using a planarization process. However, any suitable fabrication method can be used to form the fifth metal layer 501.

[0056] Fig. 5B, which shows a top view of the structure Fig. 5A (where the active devices 103 are also represented by the dashed lines for the sake of simplicity) illustrates that the individual conductors of the fifth metal layer 501 (e.g., the upper trench sections of the fifth metal layer 501) within the first area 102 of the fifth metal layer 501 sixth longitudinal axes (which in Fig.5B (shown by the dashed line with reference numeral 505) exhibit that are aligned with each other. Furthermore, the sixth longitudinal axes 505 are also aligned in the second direction 113. Accordingly, the fifth metal layer 501 is aligned perpendicular to the second metal layer 201 and the gate electrodes 106 of the active devices 103. Additionally, the fifth metal layer 501 is parallel to the third metal layer 301 and the first metal layer 109.

[0057] After forming the fifth metal layer 501, the semiconductor device 100 can be completed by forming contact pads, passivation layers, and external connectors that link the semiconductor device 100 to external devices (all of which are not shown separately in the figures). The semiconductor device 100 can also be singulated from the wafer from which it was formed. Furthermore, any suitable additional structures, packages, or other external devices can be used and connected to the semiconductor device 100 to manufacture the semiconductor device 100 for use by the end user.

[0058] Furthermore, once the semiconductor device 100 is ready for use, it can be programmed to trigger specific fuses (e.g., the first fuse 307, the second fuse 309, and the third fuse 311) for programming purposes. In one embodiment, the first fuse 307, the second fuse 309, and the third fuse 311 can be triggered sequentially, e.g., by means of an EFUSE process, although any suitable process can be used. For example, in one embodiment where an EFUSE process is used, a voltage of between about 1.6 V and about 2.0 V (e.g., about 1.8 V) is applied to the third metal layer 301 (e.g., through the second metal layer 201) for a period of between about 2 µs and about 10 µs (e.g., about 6 µs).When this voltage is applied to the third metal layer 301 with the dimensions described above, it successively trips the first fuse 307 (with the smallest width), then the second fuse 309 (with the medium width), and finally the third fuse 311. Accordingly, by controlling the voltage and the duration during which the programming current is applied to the fuses, a controlled programming process that trips the fuses sequentially can be used to trip one fuse (e.g., the first fuse 307), two fuses (e.g., the first fuse 307 and the second fuse 309), or all three fuses (e.g., the first fuse 307, the second fuse 309, and the third fuse 311). Therefore, the semiconductor device 100 can be programmed as desired.

[0059] However, the total programming current used to program the fuses in the third metal layer 301 can be increased by manufacturing the metal layers and fuses as described herein, due to the reduced resistance resulting from the increased thickness of the second metal layer 201, which conducts the programming current to the third metal layer 301. Accordingly, the programming current applied to the third metal layer 301 can range from approximately 20 µA to approximately 100 µA, such as approximately 60 µA. However, any suitable programming current can be applied.

Claims

[1] Method for manufacturing a semiconductor device, the method comprising: Forming multiple gate electrodes (106) over a first region (102) of a semiconductor substrate (101), wherein the multiple gate electrodes extend in a first direction (111); Forming a first metal layer (109) over the multiple gate electrodes in the first region, wherein a single conductor in the first metal layer extends within the first region in a second direction (113) perpendicular to the first direction, wherein the first metal layer (109) is free of fuses; Forming a second metal layer (201) over the first metal layer (109) in the first region (102), wherein each individual conductor in the second metal layer extends within the first region in the first direction, wherein the second metal layer is free of fuses; Forming a third metal layer (301) over the second metal layer (201) in the first region (102), wherein each individual conductor in the third metal layer extends within the first region (111) in the second direction (113), wherein the third metal layer includes fuses (307 - 311); and wherein the formation of the second metal layer (201) forms the second metal layer with a first thickness, and wherein the formation of the third metal layer (301) forms the third metal layer with a second thickness that is different from the first thickness; wherein the second thickness is less than the first thickness. [2] Method according to claim 1, further comprising forming a fourth metal layer (401) over the third metal layer (301) in the first region (102), wherein each individual conductor in the fourth metal layer (501) extends within the first region in the first direction (111). [3] Method according to claim 2, further comprising forming a fifth metal layer (501) over the fourth metal layer (401) in the first region (102), wherein each individual conductor in the fifth metal layer extends within the first region in the second direction (113). [4] Method according to any of the preceding claims, wherein the formation of the third metal layer (301) comprises at least partially a dual damascene process. [5] Method according to any of the preceding claims, further comprising programming the fuses (307 - 311). [6] Method for manufacturing a semiconductor device, the method comprising: Forming a series of active devices (103) on a semiconductor substrate (101); Deposition of a first metal layer (109) over the series of active devices (103), wherein the first metal layer is arranged in a top view perpendicular to the series of active devices; Deposition of a second metal layer (201) over the first metal layer (109), wherein the second metal layer is arranged perpendicular to the first metal layer in the top view; Depositing a series of fuses (307 - 311) in a third metal layer (301) over the second metal layer (201), wherein the third metal layer is arranged perpendicular to the second metal layer in plan view; and wherein the depositing of the series of fuses (307 - 311) forms the series of fuses with a first thickness, and wherein the depositing of the second metal layer forms the second metal layer with a second thickness that is different from the first thickness, the first thickness being less than the second thickness. [7] Method according to claim 6, further comprising the deposition of a fourth metal layer (401) over the third metal layer (301), wherein the fourth metal layer is arranged perpendicular to the third metal layer in the top view. [8] Method according to claim 7, further comprising the deposition of a fifth metal layer (501) over the fourth metal layer (401), wherein the fifth metal layer is arranged perpendicular to the fourth metal layer in the top view. [9] Method according to any one of claims 6 to 8, wherein the second metal layer (201) is free of fuses. [10] Method according to any one of claims 6 to 9, wherein the deposition of the third metal layer (301) further comprises a dual damascene process. [11] Semiconductor device comprising: several active devices (103) in a first region (102) of a semiconductor substrate (101), wherein the several active devices extend in a first direction (111); a first metal layer (109) over the multiple active devices (103), wherein the first metal layer comprises multiple first metal conductors in the first region arranged in a second direction (113) perpendicular to the first direction; a second metal layer (201) over the first metal layer (109), wherein the second metal layer comprises several second metal conductors in the first region arranged in the first direction; and a third metal layer (301) over the second metal layer (201), wherein the third metal layer comprises several third metal conductors and several fuses (307 - 311), the several third metal conductors being arranged in the second direction; and wherein the several third metal conductors have a first thickness, the second metal layer (201) has a second thickness, and the first thickness is less than the second thickness. [12] Semiconductor device according to claim 11, further comprising a fourth metal layer (401) above the third metal layer (301), wherein the fourth metal layer comprises several fourth metal conductors arranged in the first direction. [13] Semiconductor device according to claim 12, further comprising a fifth metal layer (501) over the fourth metal layer (401), wherein the fifth metal layer comprises several fifth metal conductors arranged in the second direction. [14] Semiconductor device according to claim 13, wherein the first metal layer (109) and the second metal layer (201) are the only metallization layers between the active devices (103) and the third metal layer (301). [15] Semiconductor device according to any one of claims 11 to 14, wherein the third metal layer (301) is embedded in a dielectric high-k material.

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