Switch device and method

Abstract

Switch device comprising: a switch (10; 20; 40; 71) comprising a control terminal, a first load terminal and a second load terminal, a switch driver (16; 26; 48; 70) coupled to the control terminal of the switch (10; 20; 40; 71), an inverse current detector (15; 62; 710) configured to detect an inverse current condition at the first and second load terminals of the switch, and a voltage driver (14; 60, 61; 74, 77) configured to drive a node (OUT_R) associated with the switch driver (16; 26; 48; 70) to a predetermined voltage in response to the detection of an inverse current condition by the inverse current detector (15; 62; 710), wherein the switch driver (16; 26; 48; 70) comprises a semiconductor structure comprising a parasitic bipolar transistor (515; 516), wherein the voltage driver (14; 60, 61; 74, 77) is configured to prevent the parasitic bipolar transistor (515, 516) from pulling the node to a potential that prevents closure of the switch (10; 20; 40; 71) during an inverse current state.

Description

TECHNICAL FIELDThe present application relates to switching devices and methods for operating switching devices.BACKGROUNDPower switches are conventionally used to couple a load to a supply voltage. In recent years, "smart" circuit breaker devices have been developed that are equipped with one or more diagnostic capabilities and protection features, for example, against overload and short circuit events. In some implementations, a MOS transistor may be used as a power switch in a power switch device that selectively couples a load to a supply voltage. Such circuit breakers are used, for example, in modern automotive and industrial systems in place of conventional fuses and electromechanical switches for low voltage medium to high current applications. In such applications, a first load terminal (also referred to as an input terminal) of the power switch device is coupled to a supply voltage, and a second load terminal (also referred to as an output terminal) of the power switch device is coupled to a load to be supplied with current. In such arrangements, a so-called inverse current state may occur in which the voltage at the second load terminal (output terminal) is higher than the voltage at the first load terminal (input terminal). Due to parasitic bipolar transistors that become conductive in such a situation, it may be impossible to turn on the power switch device, which may be desirable for some applications, however.In this connection, a conventional circuit breaker device is disclosed in DE 196 06 100 A1.US 2006 / 0 250 737 A1 discloses a device in which a state is detected in which an input terminal of a switched-mode power supply is short-circuited and a current flow in a reverse direction thereby occurs. In this case, a transistor is turned off to block a discharge current.DE 195 34 159 A1 discloses a circuit arrangement with a circuit breaker in which a circuit breaker is permanently switched on when polarity reversal is detected.U.S. Pat. No. 2016 / 0 033 983 A1 and JP 2005-198 375 A disclose further devices in which a transistor is permanently switched off under certain conditions.Further switching devices are known from US 2010 / 0 073 082 A1, DE 10 2004 055 057 A1, US 2008 / 0 036 443 A1, US 2009 / 0 085 540 A1, US 2016 / 0 322 902 A1 or US 2008 / 0 278 129 A1.Thus, it is an object to provide power switch devices and corresponding methods in which the power switch device can be reliably turned on even in the case of an inverse current state.SUMMARYThere is provided a switch device as defined in claim 1 and a method as defined in claim 14. The dependent claims define further embodiments.According to one embodiment, a switch device is provided comprising:a switch comprising a control terminal, a first load terminal, and a second load terminal;a switch driver coupled to the control terminal of the switch,an inverse current detector configured to detect an inverse current state at the first or second load terminal of the switch, anda voltage driver configured to drive a node associated with the switch driver to a predetermined voltage in response to the detection of an inverse current state by the inverse current detector,wherein the switch driver comprises a semiconductor structure comprising a parasitic bipolar transistor, wherein the voltage driver is configured to prevent the parasitic bipolar transistor from pulling the node to a potential that prevents closing of the switch during an inverse current state.According to another embodiment, there is provided a method comprising:detecting an inverse current state at a switch; anddriving a node associated with a switch driver driving the switch and comprising a semiconductor structure comprising a parasitic bipolar transistor to a predetermined voltage in response to detecting an inverse current state at the switch to prevent the parasitic bipolar transistor from pulling the node to a potential that prevents closure of the switch during an inverse current state.The summary set forth above is only for a brief review of some aspects of some embodiments and is not to be interpreted as limiting. In particular, further embodiments may include features, components or elements other than those discussed above.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a diagram illustrating a switch device according to an embodiment. FIG. 2 illustrates an example environment power switch device in which embodiments may be implemented. FIGS. 3A to 3D are explanatory diagrams for illustrating various states of a power switch device. FIG. 4 is a diagram showing the effects of an inverse current state. FIG. 5 is a cross-sectional view of a semiconductor structure illustrating the effects of an inverse current state. FIG. 6 is a circuit diagram illustrating a switch device according to an embodiment. FIG. 7 is a circuit diagram illustrating a switch device according to another embodiment. FIG. 8 is a diagram illustrating a test arrangement for switch devices. FIG. 9 is a diagram illustrating test results for a particular embodiment of a switch device. FIG. 10 shows a flow chart for illustrating a method according to an embodiment. FIG. 11 is a circuit diagram illustrating a switch device according to another embodiment.DETAILED DESCRIPTIONVarious embodiments will be described in detail below with reference to the accompanying drawings. It should be noted that these embodiments are provided solely as illustrative examples and should not be construed as limiting the scope of the present application. For example, while an embodiment may be described as including a plurality of features or elements, this is for illustrative purposes only, and in other embodiments, some of these features or elements may be missing and / or replaced with alternative features or elements. Additionally, in some embodiments, features or elements in addition to those described herein or illustrated in the drawings may be provided, such as features or elements conventionally used in circuit breakers, without departing from the scope of the present application. Features or elements of different embodiments may be combined with one another to form further embodiments. Variations or modifications described with reference to one of the embodiments may also be applied to other embodiments.Direct electrical connections or terminals illustrated in the drawings or described herein, i.e., connections or terminals without intervening elements, may also be implemented as indirect connections or terminals, i.e., connections or terminals with one or more additional intervening elements, and vice versa, as long as the general function of the connection or terminal, such as transmission of a particular information or signal or provision of a particular controller, is substantially maintained. Connections or terminals may be implemented as wire-based connections or wireless connections or terminals, or as a mixture of the two forms.In general, switches such as circuit breakers in the context of the present application may be described as comprising one or more control terminals and two or more load terminals. Opening and closing of the power switch may be controlled by applying one or more signals to at least one of the one or more control terminals. If the power switch is closed (also referred to as "switched on" or "in switched on state"), it provides a low-impedance connection between at least two of its load terminals, so that current can flow between the load terminals. When the switch is open (also referred to as "off" or "in off state"), the power switch has a blocking behavior between its load terminals, i.e. it is high-ohmic, so that substantially no current can flow between the load terminals (apart from undesirable effects such as leakage current etc., which can occur in actual devices). When used as a power switch, for example, one load terminal may be coupled to a load and another load terminal to a supply voltage such as a battery voltage to selectively couple the load to the supply voltage via the power switch. A power switch that selectively couples a load to a positive supply voltage is also referred to as a high side switch, while a power switch that couples a load to a negative supply voltage or ground is also referred to as a low side switch.In some embodiments, such a switch may be implemented using a field effect transistor (FET) such as a MOS (metal oxide semiconductor) transistor. in this case, the load terminals correspond to source and drain terminals of the MOS transistor, and a control terminal used to open and close the switch corresponds to a gate terminal. In other embodiments, a switch may be implemented using a bipolar transistor. In such a case, the load terminals correspond to emitter and collector terminals, and a control terminal used for opening and closing the switch corresponds to a base terminal. In other embodiments, insulated gate bipolar transistors (IGBT) may be used. In such a case, the load terminals correspond to emitter and collector terminals, and a control terminal used for opening and closing the switch may correspond to a base terminal. In some of a circuit breaker, in addition to a control terminal used for opening and closing the switch and the above-mentioned load terminals, other terminals including control terminals may be provided for diagnostic functions.In some embodiments, an inverse current state may be detected in a switch device and a node associated with a driver circuit controlling the switch device may be driven to a predetermined voltage, e.g., a supply voltage, in response to the detection of the inverse current state. In some embodiments, this may ensure that the switch device may be reliably turned on (i.e., brought into the closed state) even when there is an inverse current state.Referring to the figures, FIG. 1 shows a simplified block diagram for illustrating a switch device according to an embodiment.The switch device of FIG. 1 includes a switch 10. A first load terminal of the switch 10 is coupled to a first terminal 11 and a second load terminal of the switch 10 is coupled to a second terminal 12. In operation, the first terminal 11 may be coupled to a supply voltage, such as a battery voltage, and the second terminal 12 to a load, for example. By controlling a control terminal 13 of the switch 10 via a switch driver 16, the first and second terminals 11, 12 can be selectively electrically coupled to and decoupled from each other. In this way, a load can be selectively coupled to a supply voltage, for example.The switch device of FIG. 1 also includes an inverse current detector 15 coupled to the first terminal 11 and the second terminal 12. The inverse current detector 15 detects an inverse current detecting state. For example, an inverse current condition may be detected by the inverse current detector 15 when a voltage at terminal 12 exceeds a voltage at terminal 11, such as a supply voltage coupled to terminal 11.When the inverse current detector 15 detects an inverse current state, it controls a voltage driver 14 to drive a node associated with the switch driver 16 to a predetermined voltage. For example, in this case, the voltage driver 14 may couple a supply voltage also coupled to the first terminal 11 to a node supplying the switch driver 16. This node may be a node that would otherwise be raised or pulled to a voltage at the second terminal 12 and / or maintained in the floating state. In this way, in some embodiments, as will be described in more detail below, a parasitic bipolar transistor formed in some implementations of the switch driver 16 may be prevented from becoming conductive, which in turn allows the switch driver 16 to turn on the switch 10, even in the case of an inverse current condition.Concepts using an inverse current detector as explained with reference to FIG. 1 may be part of smart power switch devices, for example. FIG. 2 shows a smart power switch device serving as an example environment for implementing techniques disclosed with reference to FIG. 1 or below with reference to FIGS. 3-9.The power switch device of FIG. 2 includes a MOSFET 20 that functions as a power switch to selectively couple a supply voltage, in this case a battery voltage VBat, to a load. This load is represented in Figure 2 by a bulb 27, although any other type of load may be used. The battery voltage VBat is an example of a supply voltage for which an under voltage can be detected as explained with reference to FIG. 1. A gate terminal of the power MOSFET 20 is coupled to an output of a gate driver and level converter 26. Through the gate driver and level converter 26, the switch can be selectively turned on or off using an on-off signal, the on state corresponding to a state in which the power MOSFET 20 is closed and an off state corresponding to an open state, as explained above. The on-off signal is an example of a signal at a control input connection, such as control input connection 13 in Fig. 1, which may be used to supply a storage element for storing information relating to a detected under voltage condition.In the embodiment of Fig. 2, the gate driver and level converter 26 additionally receive a signal from a temperature sensor, which in the example of Fig. 2 is formed by a transistor 21 and a current source 22. The transistor 21 may be a bipolar transistor whose pn junctions change their behavior with a change in temperature. In other embodiments, any other conventional configuration of a temperature sensor may be used.In addition, the power switch device of FIG. 2 includes a current limiter 23. the current limiter 23 receives a measurement quantity of a current flowing through the load terminals of a power MOSFET 20 by measuring a voltage drop across a sense resistor 24, and may control the gate terminal of the power MOSFET 22 to prevent an overcurrent. Other circuit elements may also be provided, such as shunt resistors for current limiting. In addition, a zener diode clamping circuit 25 is provided as overvoltage protection. It should be noted that the illustrated power switch devices are for illustrative purposes only; for example, in other power switch devices, only some of the features or elements illustrated in FIG. 2 and / or alternative features or elements may be provided.Inverse currents and problems associated therewith will be further explained below with reference to FIGS. 3 to 5.FIGS. 3A to 3D show various shifting situations. Each of FIGS. 3A to 3D shows a certain switching situation, and shows an example of a control signal IN controlling a switch, a current I L and a state of the switch "DMOS state". A DMOS (Double Diffused Metal Oxide Semiconductor Field Effect Transistor) transistor is an example of a switch that can be used in some embodiments.FIG. 3A shows a case where the control input IN is always at a level to turn on the switch, and the state of the switch is always "on" accordingly. This on state remains, regardless of whether the current changes from a normal current to an inverse current or vice versa.FIG. 3B shows a similar situation to FIG. 3A, wherein the control signal IN has a voltage level indicating an off state and the switch is thus in the off state all the time. In this case, the switched-off state also remains independent of normal current or inverse current.FIG. 3C shows a case of particular interest for some embodiments discussed herein. In this case, the control signal IN first indicates a turned-off state, and after some time, the switch is to be turned on. However, in the situation shown in FIG. 3C, the switching from the off state to the on state takes place during an inverse current state. Ideally, the switch should be turned on as indicated by the DMOS state. However, in some conventional solutions this cannot be reliably ensured due to parasitic transistor effects. Embodiments discussed herein, such as the embodiment of FIG. 1, may ensure that the switch is reliably turned on in such a situation by driving a node associated with a switch driver to a predetermined voltage.FIG. 3D shows the situation reversed with respect to FIG. 3C, in which a switch is initially switched on by a corresponding control signal IN and then switched off during an inverse current state. This case is generally less problematic than turning on the switch as shown in FIG. 3C.FIG. 4 is a circuit diagram further illustrating the effect of an inverse current in a switch device. FIG. 4 shows a switch device using a MOS transistor 40, such as a DMOS transistor, as a switch.The transistor 40 comprises a substrate diode 41. the transistor 40 is provided to selectively couple a supply voltage VSat a terminal 43 to an output terminal 44, which may in turn be coupled to a load, for example. A current source 42 represents an external inverse current.A gate driver 48 is coupled to a gate terminal of the transistor 40 to control the turn-off of the transistor 40. A node out_r associated with the gate driver 48 is coupled to the output terminal 44 via a resistor 47. Reference numeral 49 denotes a current source illustrating a current provided from a charge pump circuit 412 to the gate terminal of the transistor 40. The inverse current is also indicated by arrow 45 in FIG. 4. Just to give a numerical example, in the inverse current state in FIG. 4, VSmay be 13.5 V, while the voltage at the output terminal 44 may be 14.5 V, which also results in a voltage of 14.5 V at the node OUT_R.Reference numeral 410 denotes a parasitic transistor formed by semiconductor structures that, in some examples, implement the gate driver 48, as will be explained in more detail below with reference to FIG. 5.In an inverse current state, which is indicated by a dashed arrow 46 through the resistor 47, the parasitic transistor 410 is triggered, i.e. switched on. As indicated by arrow 411, this pulls gate voltage Vgate to the potential of VS(parasitic transistor 410 is in saturation: VCEat<=0.1 V). In a normal ON state of the power transistor 40, the gate voltage Vgateis defined by the output voltage of the charge pump. In this case, the power pump potential is always much higher than VS (maximum allowable Vgs voltage of the power transistor 40 is defined by technology, e.g., 3.6 V; vchp=vs+3.6 v). However, since the voltage at the node OUT is higher than VS in an inverse current state, this means that the transistor 40 cannot be turned on in such a case because the parasitic bipolar transistor 410 is activated and the gate-source voltage of the power transistor 40 is approximately 0 V.The presence of a parasitic bipolar transistor such as 410 may be better understood with reference to FIG. 5, which illustrates a cross-sectional view of an example of a semiconductor structure for implementing a switch device. The semiconductor structure of FIG. 5 is formed in an n+substrate 50. A DMOS transistor as a switch is formed by a p-type substrate region 54 having an n+ contact region 55 and a gate electrode 52 for providing a channel 53 for the drain. Reference numerals 517 denote substrate diodes formed by the DMOS transistor structure shown in Fig. 5. Gate driver structures are formed in a p-well 57 formed in the n+substrate 50. The gate driver structure comprises in particular an NMOS transistor controlled by a gate terminal 513 and a PMOS transistor controlled by a gate terminal 514. A source terminal (also denoted S) of the NMOS transistor is formed by an n+ doped region 58 coupled to node OUT_R as indicated in FIG. 5. A drain terminal (also referred to as D) is formed by an n+ region 59. The PMOS transistor is composed of p+ regions 511 (serving as a drain) and p+ regions 512 (serving as a source) formed in an n-well 510. The n-well 510 is also coupled to node OUT_R, which in turn is coupled to the output of the DMOS via resistor 56. Resistor 56 corresponds to resistor 47 of FIG. 4 and the drains of the above-discussed NMOS and PMOS transistors are coupled to the gate of the DMOS via connection 51, as shown. By controlling the gates 513, 514, accordingly, either the source of the NMOS transistor or the source of the PMOS transistor can be coupled to the gate, which can be used to open and close the DMOS transistor.As can be seen, parasitic bipolar transistors 515, 516 are formed. In the example structure of FIG. 5, the parasitic bipolar transistor 515 is comprised of the n+ region 59, the p-well 57, and the n+ substrate 50, and the parasitic bipolar transistor 516 is comprised of the n-well 510, the p-well 57, and the n+ substrate 50.FIG. 6 shows a switch device according to an embodiment which is based on the switch device already explained with reference to FIG. 4. To avoid repetition, the elements in FIG. 6 already described with reference to FIG. 4 have the same reference numerals and will not be discussed in detail again.In addition to the elements explained with reference to FIG. 4, the embodiment of FIG. 6 comprises an inverse current detector formed by a comparator 62 comparing the voltage at the output terminal 44 with a voltage derived from VS, for example, by an additional voltage offset element 63, thereby providing a certain margin, for example, between -20 and -50 mV, such as on the order of -40 mV (in other words, the voltage at terminal 44 may be compared with VS plus the margin to prevent activation of the mechanism in very minor inverse current / counter voltage states or in a difference of 0 V caused by a switched-off state). In other embodiments, instead of or in addition to the voltage offset element 63, the comparator 63 may have an offset, e.g., between -20 and -50 mV, for example on the order of -40 mV, to provide such margin. The comparator 62 controls two switches 60, 61. In normal operation, i.e. when no inverse current state is detected, the switch 60 is closed and the switch 61 is opened, resulting in normal operation of the switch device. However, if an inverse current state is detected, the switch 60 is opened, as a result of which the connection 44 is decoupled from the node OUT_R. The comparator 62, in some embodiments, may include a small hysteresis, for example, in the range of about 10 mV, to prevent switching of the detection of the inverse current state. In addition, switch 61 is closed, thereby driving node OUT_R to VS. This prevents the parasitic bipolar transistor 410 from being switched on and thus prevents the voltage Vgate from being brought to the voltage at the output terminal 44. For this reason, the transistor 40 in the embodiment in FIG. 6 can still be reliably turned on even in an inverse current state.FIG. 7 shows a further embodiment of a switch device.The switch device of FIG. 7 comprises a switch transistor 71, which may be, for example, a MOSFET transistor, such as a DMOS, comprising a substrate diode 72. The switch transistor 71 is controlled by a gate driver 70 to selectively couple a supply voltage VSat 73 to an output 79. To this end, the gate driver 70 is coupled between a gate terminal of the switch transistor 71 and a node OUT_R.The node OUT_R is coupled to the output terminal 79 via a first switch 77 implemented by an NMOS transistor (which may correspond to switch 60, for example). In addition, node OUT_R is coupled to supply voltage 73 via a second switch 74 embodied by a PMOS transistor (which may correspond to switch 61, for example).For detecting an inverse current state, the switch device from FIG. 7 comprises a comparator 710. A first input of the comparator 710 is coupled to the source terminal of the switch transistor 71 as shown in FIG. 7. A second input of comparator 710 is coupled to a reference potential generated by supply voltage VS 73 plus a margin Vref 712. An output of the comparator 710 controls the second switch 74 and via a level converter 78 the first switch 77. the comparator 710 is supplied by VS and a floating supply line gndfl generated by a floating supply regulator 715. The comparator output may directly drive the PMOS transistor 74 in the embodiment of FIG. 7. The operation of the comparator 710 and the first and second switches 77, 74 substantially corresponds to that of the comparator 62 and the switches 60, 61 in FIG. 6 In particular, in the embodiment of FIG. 7, in normal operation, when no inverse current state is detected by the comparator 710, the switch 77 is closed (turned on) and the switch 74 is open (turned off). If there is an inverse current detection, i.e. the voltage at the output terminal 79 is higher than voltage VS at 73 plus the margin Vref 712, the switch 77 is opened, decoupling the node OUT_R from the output terminal 79, and the second switch 74 is closed, coupling the node OUT_R to the supply voltage at 73 and driving OUT_R to VS. As explained above, in the embodiments, this can ensure that the switch transistor 71 can be turned on even when an inverse current state exists.In addition, the switch device of FIG. 7 comprises a depletion transistor 75 and a third switch 76, which is embodied as a MOS transistor. The depletion transistor 75 and the third switch 76 and the first switch 77 have substrate terminals coupled to a substrate node 711. Through the depletion transistor 75 and the third switch 76, the substrate node 711 is selectively coupled to either the output terminal 79 or OUT_R. In particular, when an inverse current state exists, depletion transistor 75, which operates as a current source (e.g., provides a current of about 5 μA), pulls the common substrate to the potential of OUT_R, and fourth switch 76 is turned off, while under normal operating conditions (without inverse current), third switch 76 is turned on and overdrives the current emanating from depletion transistor 75. In some implementations, this may further contribute to a correct switching behavior of the first switch 77, although the depletion transistor 75 and the third switches 76 may be absent in other embodiments (such as shown in FIG. 6 ).Instead of the depletion transistor 75, in other embodiments, a common current source or a high-resistance resistor (e.g., having a resistance value of 100 kOhm or more) may be used. These elements (including depletion transistor 75) may also be referred to as current source elements because they act like a current source.FIGS. 8 and 9 show testing and test results of a device similar to the device of the embodiment of FIG. 7. FIG. 8 shows a circuit diagram of a test system for testing a device under test (DUT) 84, in particular a switch device as illustrated above. The test system of FIG. 8 includes a power supply 80 for providing a supply voltage VSto the one device under test 84, which may correspond to the supply voltage VSat 73 in FIG. 7, for example. In addition, the test system comprises a control signal generator 81 for generating a control signal for the tested switch device 84, which is supplied to the input terminal 82. This corresponds to an input signal supplied to the gate driver, such as the gate driver 70 in FIG. 7, such as a signal for controlling transistors of gate drivers, such as at the gate terminals 513, 514 in FIG. 5, Finally, the test system of FIG. 8 comprises an inverse current generator 83 for inducing an inverse current state between an output terminal 85 and the supply voltage VS. With this system, the device under test 84 can be tested in different switching states and normal and inverse current states, respectively. The situations illustrated in FIGS. 3A to 3D may be evaluated using such a test system, for example.FIG. 9 shows test results for an example embodiment similar to the embodiment of FIG. 7. In FIG. 9, various curves are shown which show voltages and current intensities over time.A curve 91 shows a supply voltage VS. Curve 92 shows a control voltage used to control the switch, which changes between on and off states as shown. A curve 94 shows a current state, wherein negative values indicate an inverse current state. A curve 90 shows an output voltage. Curve 93 shows a voltage at an additional diagnostic output, which may be provided in some implementations. A curve 90 shows the voltage at the node OUT.In the situation shown in FIG. 9, it can be seen that the control voltage 92 is HIGH at the beginning (time=10 ms), whereby the switch is switched on. At a time of approximately 11.3 ms, the control voltage changes to LOW, as a result of which the switch is switched off. An output voltage 90 at this time is then higher than a supply voltage VS (curve 91), which corresponds to an inverse current state. At a time of about 11.6 seconds, the control signal 92 again becomes HIGH, thereby turning the switch on again. The fact that the output voltage 90 again approaches the curve 91 (supply voltage) shows that the switch has actually been turned on during the inverse state, i.e. the techniques applied in this particular embodiment allow the switch to be turned on even in an inverse current state. At a time of approximately 12.2 ms, the control signal 92 changes back to LOW, whereby the switch is switched off again.FIG. 10 is a flow diagram illustrating a method according to an embodiment. The method of FIG. 10 may be applied to, but is not limited to, the switching devices and systems discussed above with reference to FIGS. 1-9. Nevertheless, for ease of illustration, reference is made to Figures 1 through 9 in describing the method of Figure 10.At 100, the method of FIG. 10 includes detecting an inverse current condition at a switch. For example, for this detection, one or both load terminals of the switch can be coupled to inputs of a comparator, as shown in FIGS. 6 and 7. At 101, the method includes driving a node associated with a switch driver, thereby driving the switch to a predetermined voltage when an inverse current condition has been detected at 100. The switch driver may be coupled between the node and a control input of the switch, for example, as shown in FIGS. 6 and 7. Driving the node in particular implementations may include coupling the node to a predetermined voltage, such as a supply voltage, by closing a switch. In addition, as shown in FIGS. 6 to 7, the node may be decoupled from an output terminal of the switch (for example, by opening the switch 60 of FIG. 6 or the switch 77 of FIG. 7 ).Fig. 11 is a circuit diagram of a switch device illustrating another embodiment. The circuit of FIG. 11 includes a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 111 having a substrate diode as a switch to selectively couple a load 112 to a supply voltage Vbb. Reference numeral 113 denotes a generator capable of inducing an inverse current state at the MOSFET 111.A gate terminal of the MOSFET 111 is controlled by a charge pump 117. The charge pump 117 is part of an integrated control circuit 114 for controlling the MOSFET 111. The control circuit 114 further comprises a comparator 121 whose input terminals 123, 124 are coupled to Vbb and a source terminal of the MOSFET 11, respectively, for detecting an inverse current state. An output of the comparator 121 at node 125 controls a first NMOS switch 120 (depletion mode transistor) whose function is similar to that of the first switch 60 in FIG. 6. In addition, the output of the comparator 121 controls, via a level converter 131, which places the comparator output in a floating supply domain, a PMOS switch 130, the function of which corresponds to that of the second switch 61 from FIG. 6. The level converter 131 is supplied with a voltage gndfl through a floating supply regulator 132.The circuit of FIG. 11 further includes a parasitic diode 1109, which may be formed in a semiconductor structure when the circuit of FIG. 11 is executed. Another diode 110 is provided in an anti-serial connection with diode 1109. Thereby, the flow of current through the diode 1109 in the case of an inverse current state can be prevented. A diode 119 serves to determine an operating point of the NMOS switch 120. Reference numeral 118 denotes a protection diode.Note that in the above-explained switch device, various elements may be monolithically integrated on a single chip. The inverse current detection can be monolithically integrated with the switch transistor itself (and possibly also other elements, e.g. as illustrated in FIG. 2 ), for example together with the first and second switches (e.g. 60, 61 of FIG. 6 ). In other embodiments, one or more components may be provided separately from the switch itself.In addition, at least some of the switches explained above are formed as high-side switches and are used as such, wherein a first load terminal (e.g. drain terminal) of the switch is coupled to a supply voltage and a second load terminal (e.g. a source terminal) of the switch is coupled to a load. An inverse current state can then be detected based on the supply voltage and a voltage at the second load terminal, e.g. using a comparator as explained. In applications of switch devices other than high side switches, an inverse current state may be detected based on a voltage at the first load terminal (which in the case of high side switches corresponds to the supply voltage) and a voltage at the second load terminal. This may be done, for example, using a comparator, possibly together with a voltage offset element, in substantially the same manner as described above, wherein only the supply voltage is replaced by the voltage at the first load terminal.As will be apparent from the above explanations of modifications and variations, the embodiments listed are only for examples and should not be interpreted as restrictive.In accordance with some embodiments, the following examples are provided:Example 1. a switch device comprising:a switch (10; 20; 40; 71) comprising a control terminal, a first load terminal and a second load terminal,a switch driver (16; 26; 48; 70) coupled to the control terminal of the switch (10; 20; 40; 71),an inverse current detector (15; 62; 710) configured to detect an inverse current state at the first and second load terminals of the switch, anda voltage driver (14; 60, 61; 74, 77) configured to drive a node (OUT_R) associated with the switch driver (16; 26; 48; 70) to a predetermined voltage in response to detection of an inverse current state by the inverse current detector (15; 62; 710).Example 2. the switch device of example 1, wherein the switch driver (16; 26; 48; 70) is coupled between the node (OUT_R) and the control terminal of the switch (10; 20; 40; 71).Example 3. The switch device of example 1, wherein the inverse current detector (15; 62; 710) comprises a comparator (62, 710).Example 4. the switch device of example 3, wherein the first load terminal of the switch is configured to be coupled to a supply voltage terminal, wherein a first input terminal of the comparator (710) is coupled to the second load terminal of the switch (71), and wherein a second input terminal of the comparator (710) is coupled to the supply voltage terminal.Example 5. the switch device of example 4, wherein the comparator includes an offset.Example 6. the switch device of example 4, further comprising a voltage offset element (63) coupled between the second input terminal of the comparator (62) and the supply voltage terminal.Example 7. the switch device of example 1, wherein the voltage driver comprises a first switch (61; 74) configured to couple the node to the predetermined voltage when the inverse current detector (15; 62; 710) detects an inverse current state.Example 8. The switch device of example 7, wherein the voltage driver further comprises a second switch (60; 77) configured to disconnect the node (OUT_R) from the second load terminal of the switch (10; 20; 40; 71) when the inverse current detector (15; 62; 710) detects an inverse current state.Example 9. the switch device of example 8, further comprising a current source element (75) coupled between a substrate terminal of the second switch and the node (OUT_R), and a third switch (76) coupled between the substrate terminal of the second switch (77) and the second load terminal of the switch (70).Example 10. The switch device of example 9, wherein at least one of the current source element (75) and the third switch (76) is configured to be controlled by the inverse current detector (710).Example 11. The switch device of example 9, wherein the current source element comprises at least one of a depletion transistor (75), a current source, and a resistor.Example 12. The switch device of example 11, wherein the first load terminal of the switch (10; 20; 40; 71) is configured to be coupled to a supply voltage (VS) and the second load terminal of the switch (10; 20; 40; 71) is configured to be coupled to a load (27).Example 13. the switch device of example 12, wherein the predetermined voltage is the supply voltage.Example 14. The switch device of example 1, wherein the switch driver (16; 26; 48; 70) comprises a semiconductor structure comprising a parasitic bipolar transistor (515; 516), wherein the voltage driver (14; 60, 61; 74, 77) is configured to prevent the parasitic bipolar transistor (515, 516) from pulling the node to a potential that prevents closure of the switch (10; 20; 40; 71) during an inverse current state.Example 15. A method comprising:detecting an inverse current state at a switch (10; 20; 40; 71); anddriving a node associated with a switch driver (16; 26; 48; 70) driving the switch to a predetermined voltage in response to detecting an inverse current state at the switch.Example 16. The method of example 15, wherein driving the node comprises coupling the node to a supply voltage.Example 17. the method of example 15, wherein driving the node further comprises decoupling the node from a second load terminal of the switch, the second load terminal coupled to a load.Example 18. The method of example 17, further comprising selectively coupling a substrate terminal of a switch (75, 76) to decouple the node from the second load terminal of the switch to the node or the second load terminal, in response to detecting an inverse current condition.Example 19. The method of example 15, wherein a first load terminal of the switch (10; 20; 40; 71) is coupled to a supply voltage, the predetermined voltage corresponding to the supply voltage.Example 20, the method of example 15, wherein detecting the inverse current state comprises comparing a voltage at the second load terminal of the switch to at least one of a supply voltage and a voltage at the first load terminal of the switch.

Claims

A switch device comprising: a switch (10; 20; 40; 71) comprising a control terminal, a first load terminal and a second load terminal; a switch driver (16; 26; 48; 70) coupled to the control terminal of the switch (10; 20; 40; 71); an inverse current detector (15; 62; 710) configured to detect an inverse current state at the first and second load terminals of the switch; and a voltage driver (14; 60, 61; 74, 77) configured to drive a node (OUT_R) associated with the switch driver (16; 26; 48; 70) to a predetermined voltage in response to the inverse current detector (15; 62; 710) detecting an inverse current state, wherein the switch driver (16; 26; 48; 70) a semiconductor structure comprising a parasitic bipolar transistor (515; 516), wherein the voltage driver (14; 60, 61; 74, 77) is configured to prevent the parasitic bipolar transistor (515, 516) from pulling the node to a potential that prevents closing of the switch (10; 20; 40; 71) during an inverse current state.The switch device of claim 1, wherein the switch driver (16; 26; 48; 70) is coupled between the node (OUT_R) and the control terminal of the switch (10; 20; 40; 71).The switch device according to claim 1 or 2, wherein the inverse current detector (15; 62; 710) comprises a comparator (62, 710).The switch device of claim 3, wherein the first load terminal of the switch is configured to be coupled to a supply voltage terminal, wherein a first input terminal of the comparator (710) is coupled to the second load terminal of the switch (71), and wherein a second input terminal of the comparator (710) is coupled to the supply voltage terminal.The switch device of claim 4, wherein the comparator has an offset.The switch device of claim 4, further comprising a voltage offset element (63) coupled between the second input terminal of the comparator (62) and the supply voltage terminal.The switch device according to any one of claims 1 to 6, wherein the voltage driver comprises a first switch (61; 74) configured to couple the node to the predetermined voltage when the inverse current detector (15; 62; 710) detects an inverse current state.The switch device according to claim 7, wherein the voltage driver further comprises a second switch (60; 77) configured to disconnect the node (OUT_R) from the second load terminal of the switch (10; 20; 40; 71) when the inverse current detector (15; 62; 710) detects an inverse current state.The switch device of claim 8, further comprising a current source element (75) coupled between a substrate terminal of the second switch and the node (OUT_R), and a third switch (76) coupled between the substrate terminal of the second switch (77) and the second load terminal of the switch (70).The switch device according to claim 9, wherein at least one of the current source element (75) and the third switch (76) is configured to be controlled by the inverse current detector (710).The switch device according to claim 9 or 10, wherein the current source element comprises at least one of a depletion transistor (75), a current source, and a resistor.The switch device according to any one of claims 1 to 11, wherein the first load terminal of the switch (10; 20; 40; 71) is configured to be coupled to a supply voltage (VS), and the second load terminal of the switch (10; 20; 40; 71) is configured to be coupled to a load (27).The switch device of claim 12, wherein the predetermined voltage is the supply voltage.A method comprising: detecting an inverse current state at a switch (10; 20; 40; 71); and driving a node associated with a switch driver (16; 26; 48; 70) driving the switch and comprising a semiconductor structure comprising a parasitic bipolar transistor (515; 516) to a predetermined voltage in response to detecting an inverse current state at the switch to prevent the parasitic bipolar transistor (515, 516) from pulling the node to a potential that prevents closure of the switch (10; 20; 40; 71) during an inverse current state.The method of claim 14, wherein driving the node comprises coupling the node to a supply voltage.The method of claim 14, wherein driving the node further comprises decoupling the node from a second load terminal of the switch, the second load terminal coupled to a load.The method of claim 16, further comprising selectively coupling a substrate terminal of a switch (75, 76) for decoupling the node from the second load terminal of the switch to the node or the second load terminal in response to detection of an inverse current condition.The method of any of claims 14 to 16, wherein a first load terminal of the switch (10; 20; 40; 71) is coupled to a supply voltage, the predetermined voltage corresponding to the supply voltage.The method of any of claims 14 to 18, wherein detecting the inverse current state comprises comparing a voltage at the second load terminal of the switch to at least one of a supply voltage and a voltage at the first load terminal of the switch.

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