Semiconductor module

Abstract

Semiconductor module (110), comprising: a laminate substrate (10) comprising an insulating plate (14), a printed circuit board (16) provided on a first surface (20) of the insulating plate (14), and a metal plate (18) provided on a second surface (22) opposite the first surface (20), wherein the laminate substrate (10) comprises at least one semiconductor device (30); and a bonding substrate (50) opposite the laminate substrate (10), wherein the bonding substrate comprises a metal layer (54), wherein the insulating plate (14) extends further outwards than an outer edge section (26) of the circuit board (16), and the metal layer (54) has a region which overlaps with the outer edge section (26) of the printed circuit board (16) in a top view and extends further outwards than the outer edge section (26) of the printed circuit board (16), wherein the bonding substrate (50) further comprises one or more metal projections (60) which project from the metal layer (54) towards the laminate substrate (10), the metal projections (60) comprise a metal projection of which at least one section is positioned further outwards than the outer edge section of the printed circuit board (16), the metal protrusion has a region that overlaps with the outer edge section (26) of the circuit board (16), and the at least one semiconductor device (30) and the metal layer (54) are electrically connected to each other in such a way that the metal layer (54) and the at least one semiconductor device (30) have the same potential when the semiconductor module (110) is supplied with current.

Description

BACKGROUND Technical area

[0001] The present invention relates to a semiconductor module. Related technology

[0002] In a semiconductor module capable of handling high voltage, a semiconductor device is mounted on a laminate substrate. The laminate substrate comprises an insulating plate made of ceramic or the like, a printed circuit board (PCB) mounted on the front surface of the insulating plate, and a metal plate mounted on the back surface of the insulating plate. The semiconductor device is mounted on the PCB. When a high voltage is applied to the semiconductor device, a high voltage is also applied to the PCB. In particular, the edge regions of the PCB are exposed to a higher electric field strength than the other regions of the PCB.To reduce the electric field strength at the edges of the printed circuit board, conventional techniques have made the gap between the edges of the ceramic layer and the edges of the printed circuit board smaller than the gap between the edges of the ceramic layer and the edges of the metal plate (see, for example, Japanese Patent Publication JP 2002 - 270 730 A).

[0003] DE 101 19 813 A1 discloses a control substrate covered with an electromagnetic shielding component. The electromagnetic shielding component is connected to a conductive base plate on which a power insulating substrate is positioned. A conductive connecting component, through which the electromagnetic shielding component and the conductive base plate are electrically connected, is inserted into a housing. The control substrate and the electromagnetic shielding component are supported by the conductive connecting component.

[0004] JP 2005-235929A discloses a power converter comprising a main power conversion circuit containing a switching device, a freewheeling diode, or similar; a control circuit containing low-power components, such as an electronic component for generating a signal to control the switching device; a housing for accommodating the main circuit and the control circuit; and a shielding element designed to divide the housing into a storage compartment for the main circuit and a storage compartment for the control circuit. The shielding element comprises an element capable of shielding the heat generated by the main circuit and an element capable of shielding the electromagnetic noise generated by the main circuit, which are integrated and shaped in a thin film.

[0005] The present invention uses a novel approach to reduce the electric field strength to a level that is lower at the circuit board on which the semiconductor device in the semiconductor module, to which a high voltage can be applied, is placed than in conventional technology. SUMMARY

[0006] The technical problem is solved by means of the features of the independent claim. The dependent claims relate to particular embodiments. The following are aspects that serve to better understand the invention. A first aspect can comprise a semiconductor module comprising a laminate substrate, which includes an insulating plate, a printed circuit board provided on a first surface of the insulating plate, a metal plate provided on a second surface opposite the first surface, and a compound substrate provided such that it is opposite the laminate substrate and comprises a metal layer.The insulating plate extends further outwards than an outer edge section of the circuit board, and the metal layer has a region that overlaps with the outer edge section of the circuit board and extends further outwards than the outer edge section of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] They show: Fig. 1 A schematic cross-sectional view of a semiconductor module 100 in a first embodiment. Fig. 2A to 2C the principle of reducing the electric field strength in the first embodiment. Fig. 3 a schematic cross-sectional view of a semiconductor module 110 in a second embodiment. Fig. 4A to 4B describe the principle of reducing the electric field strength in the second embodiment. Fig. 5 a schematic cross-sectional view of a semiconductor module 120 in a third embodiment. Fig. Figure 6 shows a top view showing a laminate substrate 10, a laminate substrate 12 and a laminate substrate 13. Fig. 7A and Fig. 7B a semiconductor module 130 in the powered-on state and the OFF state. Fig. 8A and Fig. 8B enlarged views showing the semiconductor module 130 in the powered-on state. Fig. 9A to 9D the relationship between the extension of the outer edge section of the metal layer 54 and the distribution of the potentials. Fig. 10 a graph showing the relationship between the extension of the outer boundary section and the proportion of the electric field strength at the corner section. Fig. 11A to 11C the relationship between the protruding length of the metal projection 60 and the distribution of potentials at the outer edge section. Fig. 12 a graph showing the relationship between the protruding length of the metal projection 60 and the proportion of the electric field strength at the corner section of the outer edge section. Fig. 13A to 13C the relationship between the protruding length of the metal protrusion 60 and the distribution of potentials at the inner edge section. Fig. 14 a graph showing the relationship between the protruding length of the metal projection 60 and the proportion of the electric field strength at the corner section of the inner edge section. Fig. 15A to 15C the proportion of the electric field strength at the corner section, measured for a case where a metal plate 18 is not divided, and for a case where the metal plate 18 is divided. DESCRIPTION OF THE EXAMPLES OF EXECUTION

[0008] Some embodiments of the present invention are described below. These embodiments do not limit the invention according to the claims, and all combinations of the features described in the embodiments are not necessarily essential to the means provided by the aspects of the invention.

[0009] Fig. Figure 1 is a schematic cross-sectional view of a semiconductor module 100 in a first embodiment. The semiconductor module 100 of the present embodiment comprises a laminate substrate 10, a laminate substrate 13, and a compound substrate 50, which is provided to face the laminate substrate 10 and the laminate substrate 13. The semiconductor module 100 includes a resin 90 for sealing the laminate substrates 10 and 13 and the compound substrate 50 therein. The resin 90 is, for example, an epoxy-based resin.

[0010] The laminate substrate 10 comprises an insulating board 14, a printed circuit board 16, and a metal plate 18. The insulating board 14 is shaped like a flat plate and has a first surface 20, which is the main surface, and a second surface 22, which is located opposite the first surface 20. The printed circuit board 16 is placed on the first surface 20 of the insulating board 14, and the metal plate 18 is placed on the second surface 22. The printed circuit board 16 and the metal plates 18 are made, for example, of copper (Cu) or aluminum (Al).

[0011] The insulating plate 14, for example, consists of a sintered product made of silicon nitride (SiN₂). x ), Aluminum nitride (A1N x) or aluminum oxide (A12O3). An outer edge section 24 of the insulating plate 14 is positioned further outwards than an outer edge section 26 of the printed circuit board 16. It should be noted that, as the term is used here, “an outer edge section” refers to the edge section of a component that is positioned closer to the outer periphery of the semiconductor module 100 than the rest of the component.

[0012] In the present embodiment, the laminate substrates 10 and 13 each have separate insulating plates 14. In other words, the insulating plate 14 for the laminate substrate 10 is separate from the insulating plate 14 for the laminate substrate 13. It should be noted that the laminate substrates 10 and 13 may not have separate insulating plates 14. In other words, the laminate substrates 10 and 13 may share a common insulating plate 14. In this case, an opening can be provided at the boundary between the laminate substrate 10 and the laminate substrate 13.

[0013] The printed circuit board 16 is a metal layer containing circuit structures. The circuit structures in the printed circuit board 16 are designed to electrically connect a variety of external terminals 40, a variety of electrically conductive adhesive layers 32, and a variety of electrically conductive support pins 34.

[0014] The metal plate 18 has rectangular front and rear surfaces. The front surface of the metal plate 18 is in contact with the second surface 22 of the insulating plate 14. The rear surface of the metal plate 18 is not covered with resin 90 and is exposed externally to the outside of the semiconductor module 100. The metal plate 18 is configured to dissipate the heat generated by a semiconductor device 30 to the outside of the semiconductor module 100.

[0015] The printed circuit board 16 has a plurality of semiconductor devices 30 mounted on it, with a plurality of electrically conductive adhesive layers 32 provided between them. The plurality of semiconductor devices 30 comprises a first semiconductor device 30-1, which has a switching capacitor, and a second semiconductor device 30-2, which has a rectifying capacitor.

[0016] The first semiconductor device 30-1 is, for example, an insulated-gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect power transistor (MOSFET). In this device, an IGBT and a power MOSFET are formed in a substrate of silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). The first semiconductor device 30-1 is, for example, a power MOSFET formed in a SiC substrate.

[0017] The second semiconductor device 30-2 is a diode, for example a PN diode or a Schottky diode (SBD). In the present embodiment, the second semiconductor device 30-2 is an SBD.

[0018] The laminate substrate 10 has a plurality of semiconductor devices 30 mounted on it. Each plurality of semiconductor devices 30 has an electrode (for example, a drain or cathode electrode) on its back surface, which is electrically connected to an external terminal 40-1 via the circuit board 16. Furthermore, each plurality of semiconductor devices 30 has another electrode (for example, a source, gate, or anode electrode) on its front surface, which is electrically connected to the connecting substrate 50 via the plurality of electrically conductive support pins 34.

[0019] The laminate substrate 13 has no semiconductor devices 30 mounted on it. The printed circuit board 16 of the laminate substrate 13 provides interconnections within the semiconductor module 100. In the present embodiment, the printed circuit board 16 of the laminate substrate 13 provides, for example, source interconnections. The printed circuit board 16 of the laminate substrate 13 is electrically connected to a metal layer 54 by means of a plurality of electrically conductive support pins 34. In addition, the printed circuit board 16 of the laminate substrate 13 is electrically connected to an external terminal 40-2.

[0020] The external terminals 40 extend through the resin 90 to the outside. The external terminals 40 pass through the holes provided in the bonding substrate 50. The external terminals 40 are not electrically connected to the bonding substrate 50. In other words, the external terminals 40 are not electrically connected to either the metal layer 54 or the metal layer 58 in the bonding substrate 50.

[0021] When the semiconductor module 100 is powered on (in the ON state), the external terminal 40-1, which is connected to the circuit board 16 of the laminate substrate 10, serves as the drain terminal of the semiconductor module 100. In contrast, the external terminal 40-2, which is connected to the circuit board 16 of the laminate substrate 13, serves as the source terminal of the semiconductor module 100. Thus, although the semiconductor module 100 is operational, a higher voltage is applied to external terminal 40-1 than to external terminal 40-2.

[0022] When the semiconductor module 100 is powered on (in the ON state), current flows between the plurality of external terminals 40. For example, current flows through external terminal 40-1, the circuit board 16 of the laminate substrate 10, the electrically conductive adhesive layers 32, the semiconductor devices 30, the electrically conductive support pins 34 on the laminate substrate 10, the metal layer 54 of the interconnect substrate 50, the electrically conductive support pins 34 on the laminate substrate 13, the circuit board 16 of the laminate substrate 13, and external terminal 40-2 in the order shown. It should be noted that the metal plate 18 always has a low potential, even while the semiconductor module 100 is powered on. In the present embodiment, the metal plate 18 has a ground potential (0 V).

[0023] The interconnecting substrate 50 is, for example, a circuit board. In the present embodiment, the interconnecting substrate 50 has a base section 52, a metal layer 54, and a metal layer 58. The metal layer 54 is provided on the surface of the base section 52 that faces the laminate substrates 10 and 13. Additionally, the metal layer 58 is provided on the surface of the base section 52 that faces away from the metal layer 54. The interconnecting substrate 50 has a plurality of holes through which the external terminals 40 pass. The metal layers 54 and 58 can have a plurality of holes to allow the external terminals 40 to pass through them, or they can be provided in such a way that they do not block the plurality of holes.

[0024] The base section 52 is insulating. Metal layers 54 and 58 are metal layers containing circuit structures. Metal layer 54 provides the source interconnections within the semiconductor module 100 and is connected to the printed circuit board 16 of the laminate substrate 13 via electrically conductive support pins 34. Metal layer 58 provides the gate interconnections within the semiconductor module 100 and is connected to an external terminal 40 for a gate electrode (not shown). Metal layer 54 is also connected to the source electrode on the front surface of the first semiconductor device 30-1 and the anode electrode on the front surface of the second semiconductor device 30-2 via electrically conductive support pins 34. Additionally, metal layer 58 is connected to the gate electrode on the front surface of the first semiconductor device 30-1 via electrically conductive support pins 34.

[0025] As in Fig. As shown in Figure 1, the metal layer 54 in the present embodiment has a region that overlaps with the outer edge section 26 of the circuit board 16 and extends further outwards than the outer edge section 26 of the circuit board 16.

[0026] According to the printed circuit board 16 and the metal layer 54 of the present embodiment, the equipotential curves between the outer edge section 24 of the insulating plate 14 and the outer edge section 26 of the printed circuit board 16 are less dense than in conventional technology. Therefore, the electric field strength at the outer edge section 26 of the printed circuit board 16 can be reduced.

[0027] In the present embodiment, the laminate substrates 10 and 13 each have separate metal plates 18. As a result, the equipotential curves between the inner edge section 25 of the insulating plate 14 and the inner edge section 27 of the printed circuit board 16 are less dense than if the laminate substrates 10 and 13 shared a common metal plate 18. Therefore, the electric field strength at the inner edge section 27 of the printed circuit board 16 can be reduced.

[0028] Fig. 2A to 2C illustrate the principle of reducing the electric field strength in the first embodiment. Fig. Figures 2A to 2C are partially enlarged views of the outer edge section 26 of the printed circuit board 16 of the laminate substrate 10. Fig. 1. It should be noted that the in Fig. The equipotential curves shown in Figures 2A to 2C are only presented to give a general impression of the actual equipotential curves.

[0029] Fig. Figure 2A shows the equipotential curves that can be observed when the compound substrate 50 is not provided in the first embodiment. Fig. Figure 2B shows the equipotential curves that can be observed when the bonding substrate 50 is provided and the outer edge section 56 of the metal layer 54 of the bonding substrate 50 is positioned such that it coincides with the outer edge section 26 of the printed circuit board 16 in the first embodiment. Fig. Figure 2C shows the equipotential curves that can be observed when the first embodiment is implemented as previously described.

[0030] A high voltage is applied to the circuit board 16 of the laminate substrate 10, both when the semiconductor module 100 is powered (in the ON state) and when the semiconductor module 100 is not powered (in the OFF state). In the present embodiment, it is assumed that a voltage of approximately 3.3 kV is applied to the circuit board 16. Here, the letter "k" denotes the cube of 10. In contrast, the metal plate 18 is grounded, and the potential of the metal plate 18 is therefore 0 V. It should be noted that the circuit board 16 has an equipotential across its entire surface. Likewise, the circuit board 18 has an equipotential across its entire surface.

[0031] In the insulating plate 14, the potential varies continuously from approximately 3.3 kV at the first surface 20 to 0 V at the second surface 22. In the present embodiment, 5 equipotential curves between 3.3 kV and 0 V are shown schematically in intervals of 550 V.

[0032] As in Fig. As can be seen in Figure 2A when the connecting substrate 50 is not provided, the equipotential curves surround the outer edge section 26 of the printed circuit board 16. The equipotential curves extending outwards between the outer edge section 26 of the printed circuit board 16 and the outer edge section 24 of the insulating board 14 rise sharply in a substantially parallel direction to the outer edge section 26. The steeply rising equipotential curves wrap around the printed circuit board 16 to appear on the front surface of the printed circuit board 16.

[0033] The electric field strength increases when the intervals between adjacent equipotential curves decrease. As in Fig. As can be seen in diagram 2A, the equipotential curves are closest at the lower corner section 36 of the outer edge section 26 of the circuit board 16. Therefore, the electric field strength is locally high at the corner section 36 of the circuit board 16.

[0034] If the electric field strength of corner section 36 of the circuit board 16 increases, a partial discharge from corner section 36 can occur. This partial discharge can damage the insulating plate 14, which is in contact with corner section 36. Therefore, the insulating plate 14 may fail. If this happens, the semiconductor module 100 will no longer perform its intended functions. Accordingly, it is important to reliably maintain the insulating properties of the insulating plate 14. To reliably maintain the insulating properties of the insulating plate 14, it is important to reduce the electric field strength at corner section 36 of the circuit board 16.

[0035] In the Fig. In the case shown in 2B, the electric field strength at corner section 36 is compared with that in Fig. The case shown in 2A is reduced because it prevents the equipotential curves from going around circuit board 16 to appear on the front side of circuit board 16. As in the case shown in Fig. In the case shown in 2A, however, the equipotential curves rise in an essentially parallel direction to the outer boundary section 26, in which in Fig. Case 2B shown. Therefore, the concentration of electric fields at corner section 36 cannot be completely attenuated.

[0036] On the other hand, as in Fig. As can be seen in 2C, when the outer edge section 56 of the metal layer 54 is positioned further out than the outer edge section 26 of the circuit board 16, the equipotential curves avoid the metal layer 54 and are directed outwards. Thus, the electric field strength at the corner section 36 of the circuit board 16 is lower compared to that in Fig. In the case shown in Figure 2B, the electric field strength is further reduced, and partial discharge from corner section 36 can be prevented. It should be noted that the electric field strength can also be similarly reduced at the corner section of the inner edge section 27 of the printed circuit board 16. It is understood that the term "an inner edge section," as used here, refers to the corner section of the laminate substrates 10 and 13 that is positioned further inward from the semiconductor module 100 than the rest of the laminate substrates 10 and 13.

[0037] Fig. Figure 3 shows a schematic cross-sectional view of a semiconductor module 110 in a second embodiment. The semiconductor module 110 of the present embodiment has at least one metal projection 60 in the compound substrate 50. In this respect, the second embodiment differs from the first embodiment. With this exception, the second embodiment is the same as the first embodiment.

[0038] The metal protrusion 60 projects from the metal layer 54 towards the laminate substrate 10. At least one section of the metal protrusion 60 is positioned further out than the outer edge section 26 of the printed circuit board 16. The interconnect substrate 50 can have multiple metal protrusions 60.

[0039] The metal projection 60 can have an area that overlaps with the outer edge section 26 of the printed circuit board 16. Viewed in the direction perpendicular to the plane of the insulating plate 14, the outer edge section 66 of the metal projection 60 can be positioned such that it coincides with the position of the outer edge section 24 of the insulating plate 14. This can be seen from the dashed lines in Fig. 3. For example, the metal layer 54 and the metal projections 60 can be formed as a single piece by bending the outermost section of the metal layer 54.

[0040] As in Fig. As shown in Figure 3, additional metal protrusions 60 can be provided further inward than the inner edge section 27 of the printed circuit board 16. In other words, the additional metal protrusions 60 can be provided further inward than the printed circuit board 16. Thus, the electric field strength at the corner section of the inner edge section 27 of the printed circuit board 16 is reduced.

[0041] In the semiconductor module 110 of the present embodiment, the printed circuit board 16 of the laminate substrate 10 and the printed circuit board 16 of the laminate substrate 13 are separated from each other, and different voltages are applied to them during operation. More precisely, the voltage applied to the printed circuit board 16 of the laminate substrate 10 is higher than the voltage applied to the printed circuit board 16 of the laminate substrate 13. In this case, the metal protrusion 60 can only be provided on the metal layer 54, which is positioned such that it faces the printed circuit board 16 of the laminate substrate 10 to which a higher voltage is applied. Thus, the electric field strength at the corner section of the printed circuit board 16 to which a higher voltage is applied can be reduced, and the effort of manufacturing the metal protrusion 60 can be eliminated.

[0042] Fig. Figures 4A to 4B illustrate the principle of reducing the electric field strength in the second embodiment. Fig. Figures 4A to 4B are partially enlarged views of the outer edge section 26 of the circuit board 16 of the Fig. 3 laminate substrates shown 10.

[0043] Fig. Figure 4A shows the equipotential curves near the outer edge section 26 of the circuit board 16 in the first embodiment, in which the metal projection 60 is not provided. Fig. Figure 4B shows the equipotential curves near the outer edge section 26 of the circuit board 16 in the second embodiment. As in Fig. As can be seen in 4B, the metal protrusion 60 can be compared to the equipotential curves in the equipotential curves. Fig. Position the component shown in case 4A further outwards. This further reduces the electric field strength at corner section 36 of the outer edge section 26. The electric field strength is similarly reduced at the corner section of the inner edge section 27 of the circuit board 16.

[0044] Fig. Figure 5 shows a schematic cross-sectional view of a semiconductor module 120 in a third embodiment. The semiconductor module 120 of the present invention comprises an insulating plate 14, which is shaped like a flat plate, and the insulating plate 14 is not divided, has no openings, and is provided as a single piece. In this respect, the third embodiment differs from the second embodiment. With this exception, the third embodiment is the same as the second embodiment.

[0045] In the present embodiment, the laminate substrate 10 comprises a plurality of printed circuit boards 16-1 and 16-2, to which different voltages are applied during operation and which are separated from one another. The laminate substrate 10 comprises a plurality of metal plates 18-1 and 18-2, corresponding to the printed circuit boards 16-1 and 16-2. In other words, the metal plate 18 has an opening 19 formed therein in the region opposite the inner edge sections 27 of the printed circuit boards 16-1 and 16-2.

[0046] The third embodiment produces the same effects as the first and second embodiments. More precisely, the electric field strength at the outer edge sections 26 of the circuit boards 16-1 and 16-2 can be reduced. Furthermore, the electric field strength at the inner edge sections 27 of the circuit boards 16-1 and 16-2 can also be reduced.

[0047] Fig. Figure 6 shows a top view showing a laminate substrate 10, a laminate substrate 12, and a laminate substrate 13. The laminate substrates 10 and 13 correspond to the laminate substrates 10 and 13 with reference to the first to third embodiments. In this embodiment, the laminate substrate 12 is added. The laminate substrate 12 does not have any semiconductor devices 30 mounted on it. In the present embodiment, the circuit board 16 of the laminate substrate 12 provides gate interconnections and additional source interconnections.

[0048] In Fig. 6. Similar symbols denote similar terminals, electrodes, devices, or the like. Thus, the reference symbols do not apply to all of the symbols in Fig. 6 assigned.

[0049] The semiconductor devices 30, which are provided on the laminate substrate 10, comprise a first semiconductor device 30-1 having a switching capacitance, and a second semiconductor device 30-2 having a rectifying capacitance.

[0050] The external terminals 40 are indicated by the double circles. The electrically conductive support pins 34 are indicated by the smaller circles than the external terminals 40. The electrically conductive support pins 34 are also provided on the first and second semiconductor devices 30-1 and 30-2.

[0051] Fig. 7A and Fig. Figure 7B shows a semiconductor module 130, which is provided as a model to simulate a distribution of potentials. The drawings according to the Fig. 7A and Fig. Figure 7B shows potential distributions at the edge sections of the printed circuit boards 16 of the laminate substrates 10, 12, and 13. It should be noted that the semiconductor devices 30, the electrically conductive support pins 34, the external terminals 40, the base section 52, and the metal layer 58 of the interconnect substrate 50, and the like, are not used in the simulations. In other words, the effects of these components are not considered in the simulations. It should be noted that the metal protrusion 60 is not shown in the drawings. Fig. 11A to 11C to Fig. The simulations shown in the 14 images are used.

[0052] When the laminate substrate 12 is added, one of the edge sections of the printed circuit board 16 of the laminate substrate 10 that is closer to the laminate substrate 12 is designated as the first edge section 28, and one of the edge sections of the printed circuit board 16 of the laminate substrate 10 that is closer to the laminate substrate 13 is designated as the second edge section 29.

[0053] Fig. Figure 7A shows the semiconductor module 130 in the powered-on state (the ON state). In the present embodiment, the printed circuit board 16 of the laminate substrate 13 provides the source interconnects, and the printed circuit board 16 of the laminate substrate 10 provides the drain interconnects. The printed circuit board 16 of the laminate substrate 12 provides additional source interconnects. The gate interconnects on the laminate substrate 12 are neither shown nor explained. When the semiconductor module 130 is in the ON state, a voltage of 3300 V is applied to both the source interconnects of the laminate substrate 13 and the additional source interconnects of the laminate substrate 12. A voltage of 3300 V is also applied to the metal layer 54 of the interconnect substrate 50, which serves as a source interconnect. 3303 V are applied to the drain interconnections of the laminate substrate 10.Metal plate 18 is grounded, and therefore 0 V is applied to it.

[0054] Fig. Figure 7B shows the semiconductor module 130 in the off-state (the OFF state). In the present embodiment, when the semiconductor module 130 is in the OFF state, a voltage of 3 V is applied to the source interconnects of the laminate substrate 13 and the additional source interconnects 12. A voltage of 3 V is also applied to the metal layer 54 of the interconnect substrate 50. In contrast, a voltage of 3303 V is applied to the drain interconnects of the laminate substrate 10, as in the case where the semiconductor module 130 is in the ON state. 0 V is applied to the metal plate 18 when the semiconductor module 130 is in the OFF state.

[0055] For the simulations, both the printed circuit board 16 and the metal plate 18 were copper plates with a thickness of 1 mm. Additionally, a copper foil with a thickness of 0.2 mm was used as the metal layer 54 of the bonding substrate 50. The insulating plate 14 of each laminate substrate was formed to have a thickness of 0.635 mm and consisted of aluminum nitride. An epoxy resin was used as resin 90. The resin 90 was formed to have a thickness of 0.8 mm and to cover the respective components.

[0056] The insulating plate 14 of the laminate substrate 10 was separated from the insulating plate 14 of the laminate substrate 12 by a distance of 3 mm. Likewise, the insulating plate 14 of the laminate substrate 10 was separated from the insulating plate 14 of the laminate substrate 13 by a distance of 3 mm. The edge section of the insulating plate 14 of each laminate substrate was positioned 1 mm outside the edge section of the corresponding printed circuit board 16 and 1 mm outside the edge section of the corresponding metal plate 18. The insulating plate 16 of each of the laminate substrates was separated from the metal plate 54 of the interconnect substrate 50 by a distance of 1.55 mm.

[0057] Fig. 8A and Fig. Figure 8B shows distributions of potentials that can be observed when the semiconductor module 130 is in the ON state. Fig. 8A is an enlarged view showing the proximity of the outer edge section 26 of the in Fig. 7A shows the laminate substrate 13. Fig. 8B is an enlarged view showing the space between the laminate substrate 13 and the in Fig. Figure 7A shows the laminate substrate 10. It should be noted that the equipotential curves within the insulating board 14 are between Fig. 8A and Fig. Continue to 8B. Fig. 8A and Fig. 8B does not show the laminate substrate 12.

[0058] In Fig. In 8A, the metal layer 54 has an area that overlaps with the outer edge section 26 of the circuit board 16. However, the metal layer 54 does not have an area that is positioned further outwards than the outer edge section 26 of the circuit board 16.

[0059] Fig. Figures 9A to 9D show the relationship between the distribution of the potentials and the length of the extension outwards of the outer edge section 56 of the metal layer 54, seen in the direction that is perpendicular to the first surface 20 of the insulating plate 14. Fig. Figures 9A to 9D are enlarged views showing the potential distributions observed near the edge of the laminate substrate 13 when the semiconductor module 130 is in the ON state. The length of the outward extension of the outer edge 56 of the metal layer 54 was varied compared to the outer edge 26 of the printed circuit board 16. The length of the outward extension was adjusted for the Fig. Case 9A shown at 0 mm, for Fig. 9B to 1 mm, for Fig. 9C on 2 mm and for Fig. 9D set to 2.3 mm. It should be noted that the in Fig. Case 9A shown in Fig. This corresponds to the case shown in 8B.

[0060] Fig. Figures 9A to 9D clearly indicate that as the outward extension of the outer edge section 56 of the metal layer 54 increases compared to the outer edge section 26 of the printed circuit board 16, the equipotential curves are deflected further outwards. This reduces the electric field strength at the corner section 36 of the outer edge section 26 of the printed circuit board 16.

[0061] Fig. Figure 10 is a graph showing the relationship between the length of the extension of the outer edge section 56 of the metal layer 54 and the proportion of the electric field strength at the corner section 36. Fig. 10 presents the in Fig. The results shown in 9A to 9D are quantitative. The case where the extension length is 0 mm corresponds to that in Fig. Case 9A shows the difference in electric field strength. The proportion of the electric field strength is determined in comparison to the electric field strength observed when the extension length is 0 mm, which is considered to be 100%.

[0062] When the extension length was 1 mm, the electric field strength at corner section 36 was 94.25% of the electric field strength observed when the extension length was 0 mm. When the extension length was 2 mm, the electric field strength at corner section 36 was 86.21% of the electric field strength observed when the extension length was 0 mm. When the extension length was 2.3 mm, the electric field strength at corner section 36 was 85.06% of the electric field strength observed when the extension length was 0 mm. These results clearly indicate that the electric field strength at corner section 36 was reduced by positioning the outer edge section 56 of the metal layer 54 further outward than the outer edge section 26 of the printed circuit board 16.It should be noted that the compound substrate 50 is considerably larger than the laminate substrate 13 when the length of the metal layer extension 54 is 2 mm or more. Therefore, the influence of the compound substrate 50 on the size of the semiconductor module 100 is too large to be ignored. Thus, it is particularly preferred to set the length of the metal layer extension 54 to 2 mm or less, because this prevents the semiconductor module 100 from becoming unnecessarily large.

[0063] Fig. Figures 11A to 11C show the relationship between the protruding length of the metal projection 60 and the potential distributions at the outer edge section 26. Fig. Figures 11A to 11C are enlarged views showing the potential distributions observed near the edge of the laminate substrate 13 when the semiconductor module 130 is in the ON state. The metal layer 54 extends 2 mm outwards compared to the outer edge 26 of the printed circuit board 16. Fig. Figure 11A shows the results that can be observed when the metal protrusion 60 is not provided. Fig. Figure 11B shows the results that can be observed when the metal projection 60 protrudes by 0.5 mm in the direction towards the laminate substrate 13. Fig. Figure 11C shows the results that can be observed when the metal projection 60 protrudes by 0.7 mm in the direction of the laminate substrate 13. The in Fig. The case shown in 11A corresponds to the one in Fig. Case shown in 9C.

[0064] Fig. Figure 12 is a graph showing the relationship between the protruding length of the metal projection 60 and the proportion of the electric field strength at the corner section 36 of the outer edge section 26. Fig. 12 shows the in Fig. The results shown in Figures 11A to 11C are quantitative. The case where the protruding length of the metal projection is 600 mm corresponds to that shown in Figures 11A to 11C. Fig. Case 11A shows the electric field strength. The proportion of the electric field strength is determined in comparison to the electric field strength observed when the preceding length is 0 mm, which is considered to be 100%.

[0065] When the projecting length was 0.5 mm, the electric field strength at corner section 36 was essentially equal to the electric field strength observed when the projecting length was 0 mm (= 100%). However, when the projecting length was 0.7 mm, the electric field strength at corner section 36 was 96% of the electric field strength observed when the projecting length was 0 mm. This had the effect that increasing the projecting length of the metal projection 60 reduced the electric field strength at corner section 36 of the outer edge section 26. The electric field strength at corner section 36 can be effectively reduced if the projecting length of the metal projection 60 is 0.5 mm or more.

[0066] Fig. Figures 13A to 13C show the relationship between the protruding length of the metal projection 60 and the potential distributions at the inner edge section 27 of the printed circuit board 16 of the laminate substrate 13. Fig. Figures 13A to 13C are enlarged views showing the potential distributions near the region between the second boundary section 29 of the laminate substrate 10 and the inner boundary section 27 of the laminate substrate 13. It should be noted that Fig. 13A to 13C show the results that can be observed when the semiconductor module 130 is in the ON state. Fig. Figure 13A shows the results that can be observed when the metal protrusion 60 is not provided. Fig. Figure 13B shows the results that can be observed when the metal protrusion 60 extends 0.5 mm from the metal layer 54 towards the laminate substrate 13 between the laminate substrate 13 and the laminate substrate 10. Fig. Figure 13C shows the results that can be observed when the metal projection 60 protrudes by 0.7 mm in the direction towards the laminate substrate 13.

[0067] Fig. Figure 14 is a graph showing the relationship between the protruding length of the metal projection 60 and the proportion of the electric field strength at the corner section 36 of the inner edge section 27 of the circuit board 16 of the laminate substrate 13. Fig. 14 shows the in Fig. The results shown in sections 13A to 13C are quantitative. The fraction of the electric field strength is determined in comparison to the electric field strength observed when the preceding length is 0 mm, as shown in Fig. 13A is shown and is considered to be 100%.

[0068] When the projecting length was 0.5 mm, the electric field strength at corner section 36 was 97.40% of the electric field strength observed when the projecting length was 0 mm. When the projecting length was 0.7 mm, the electric field strength at corner section 36 was 83.12% of the electric field strength observed when the projecting length was 0 mm. These results showed that as the projecting length of the metal projection 60 increases, the electric field strength at corner section 36 of the inner edge section 27 is also effectively reduced.

[0069] Fig. Figure 15A shows a case where the metal plate 18 is not divided, and Fig. Figure 15B shows a case where the metal plate 18 is split. Fig. Figure 15C shows the fraction of the electric field strength at corner section 36, which can be observed when the metal plate 18 is undivided and when the metal plate 18 is divided. The fraction of the electric field strength at corner section 36 of the inner edge section 27 of the printed circuit board 16 of the laminate substrate 13 is compared to the electric field strength that is observed for the Fig. The case shown in 15A, which is considered to be 100%, is determined. The proportion of the electric field strength at corner section 36, which is used for the in Fig. The percentage observed in the case shown in 15B was 72.64%.

[0070] At the in Fig. In the case shown in 15A, the equipotential curves cannot penetrate the metal plate 18. In the case shown in Fig.In contrast, in the case shown in Figure 15B, the equipotential curves can be deflected through the region between the divided regions of the metal plate 18. If the equipotential curves protrude through the regions between the divided regions of the metal plate 18, the equipotential curves at corner section 36 are less densely packed. This can consequently reduce the electric field strength at corner section 36. REFERENCE MARK LIST 10 laminate substrate 12 laminate substrate 13 Laminate substrate 14 Insulation board 16 circuit board 18 metal plates 19 Opening 20 First surface 22 Second surface 24 Outer edge section 25 Inner marginal section 26 Outer edge section 27 Inner marginal section 28 First marginal section 29 Second marginal section 30 Semiconductor device 32 Electrically conductive adhesive layer 34 Electrically conductive support pin 36 Corner section 40 External terminal 50 compound substrate 52 Basic section 54 Metal layer 56 Outer edge section 58 Metal layer 60 Metal protrusion 66 Outer edge section 90 Harz 100 semiconductor modules 110 semiconductor module 120 semiconductor module 130 semiconductor module

Claims

[1] Semiconductor module (110), comprising: a laminate substrate (10) comprising an insulating plate (14), a printed circuit board (16) provided on a first surface (20) of the insulating plate (14), and a metal plate (18) provided on a second surface (22) opposite the first surface (20), wherein the laminate substrate (10) comprises at least one semiconductor device (30); and a bonding substrate (50) opposite the laminate substrate (10), wherein the bonding substrate comprises a metal layer (54), wherein the insulating plate (14) extends further outwards than an outer edge section (26) of the circuit board (16), and the metal layer (54) has a region that overlaps with the outer edge section (26) of the printed circuit board (16) in a top view and extends further outwards than the outer edge section (26) of the printed circuit board (16), wherein the bonding substrate (50) further comprises one or more metal projections (60) which project from the metal layer (54) towards the laminate substrate (10), the metal projections (60) comprise a metal projection of which at least one section is positioned further outwards than the outer edge section of the printed circuit board (16), the metal protrusion has a region that overlaps with the outer edge section (26) of the circuit board (16), and the at least one semiconductor device (30) and the metal layer (54) are electrically connected to each other in such a way that the metal layer (54) and the at least one semiconductor device (30) have the same potential when the semiconductor module (110) is supplied with current. [2] Semiconductor module (110) according to claim 1, wherein the length of the extension to the outside of the metal layer (54) is 2 mm or less compared to the outer edge section (26) of the printed circuit board (16). [3] Semiconductor module (110) according to claim 1 or 2, wherein the semiconductor module comprises a plurality of printed circuit boards (16) which are separated from each other, and the metal projections (60) comprise a metal projection of which at least one section is positioned further inwards than the inner edge sections (27) of a printed circuit board (16) of the plurality of printed circuit boards in the top view. [4] Semiconductor module (110) according to any one of claims 1 to 3, wherein the semiconductor module comprises a plurality of printed circuit boards (16) which are separated from each other and to which different voltages are applied, and the metal protrusion (60) is positioned on the metal layer (54) to face one of the circuit boards (16) to which a higher voltage is applied. [5] Semiconductor module (120) according to any one of claims 1 to 4, wherein the semiconductor module comprises a plurality of printed circuit boards (16) which are separated from each other and to which different voltages are applied, and in the metal plate (18) an opening (19) is formed in a region opposite the inner edge sections (27) of the respective circuit boards (16-1, 16-2). [6] Semiconductor module (120) according to claim 5, wherein a plurality of the metal plates (18) is provided such that it corresponds to the plurality of printed circuit boards (16). [7] Semiconductor module (120) according to one of claims 5 and 6, wherein the insulating plate (14) is formed as a flat plate and is provided as a single piece and is not divided or has no openings.

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