Planar Field Effect Transistor

Abstract

Planar field-effect transistor (100) which features: a drain extension area (102) between a channel area (104) and a drain connection (D) on a first surface (106) of a semiconductor body (112); a first electrode part (108) and a second electrode part (110) which are laterally spaced apart from each other, wherein the first electrode part (108) is arranged as a gate electrode above the channel area (104) and the second electrode part (110) is arranged above the drain expansion area (102) and is electrically separated from the first electrode part (108); a gate dielectric (1141) between the first electrode part (108) and the channel region (104); and a further dielectric (1142) between the first electrode part (108) and the drain expansion region (102), wherein the thickness of the further dielectric (1142) is greater than the thickness of the gate dielectric (1141) and the gate dielectric (1141) borders the further dielectric in the direction of the drain terminal (D), and wherein the further dielectric (1142) comprises a first dielectric, as well as a planar dielectric (1147) between the first dielectric and the gate dielectric (1141), wherein the planar dielectric (1147) is thicker than the gate dielectric (1141) and borders a top surface (106) of a part of the drain expansion region (102), and the first dielectric is a LOCOS dielectric or a beveled dielectric, and the further dielectric (1142) is located under the second electrode part (110) is thicker than the planar dielectric (1147) under the first electrode part (108).

Description

TECHNICAL AREA

[0001] The application concerns a planar field-effect transistor. BACKGROUND

[0002] In semiconductor devices with field-effect transistors, a large number of field-effect transistor cells are typically connected in parallel to achieve a desired current-carrying capacity in a power semiconductor device. Examples of such semiconductor devices are described in US Publication 2017 / 0047442A1. In circuit applications such as DC-DC converters, the transistors are optimized to minimize losses occurring in each switching cycle. Each cycle involves various switching states, with different loss components occurring in each switching phase. These losses can be increased or decreased by specific transistor parameters. For example, at high load currents, the transistor resistance in the on-state (Rdson) is a dominant parameter in the circuit application, while in the medium and low current ranges, switching losses due to capacitance become more significant.

[0003] It is desirable to reduce the switching losses of planar field-effect transistors in order to improve the efficiency of a circuit arrangement implemented with the field-effect transistors. SUMMARY

[0004] The aforementioned problem is solved by the subject matter of claim 1. Further embodiments are described in the dependent claims.

[0005] The present invention relates to a planar field-effect transistor. The planar field-effect transistor has a drain expansion region between a channel region and a drain terminal on a first surface of a semiconductor body. Furthermore, the planar field-effect transistor has a first electrode region and a second electrode region, which are laterally spaced apart from each other. The first electrode region is arranged as a gate electrode above the channel region, and the second electrode region is arranged above the drain expansion region and is electrically isolated from the first electrode region. The electrical isolation between the first and second electrode regions allows for a reduction of the gate capacitance Cg by designing the second electrode region as a field plate and, for example, electrically connecting it to a reference potential.The gate capacitance Cg comprises a gate-to-drain capacitance Cgd as well as a gate-to-source capacitance Cgs. The first and second electrode parts are, for example, spaced-apart sections of the same wiring plane, from which laterally spaced parts such as conductor tracks or electrodes are obtained through structuring, e.g., lithographic structuring. The planar field-effect transistor includes an additional dielectric between the first electrode part and the drain extension region, the thickness of which is greater than the thickness of the gate dielectric, and the gate dielectric borders the additional dielectric in the direction of the drain terminal.The secondary dielectric comprises a first dielectric and a planar dielectric between the first dielectric and the gate dielectric. The planar dielectric is thicker than the gate dielectric and abuts a top surface of a portion of the drain expansion region at the first surface. The first dielectric is either a LOCOS dielectric or a beveled dielectric. The increased dielectric thickness further reduces the electric fields at the first surface, resulting in a further improvement in the breakdown performance of the planar field-effect transistor.

[0006] According to one embodiment, the second electrode part is electrically connected to a source terminal and therefore does not contribute to the gate capacitance Cg.

[0007] According to one embodiment, the planar field-effect transistor is a lateral power semiconductor device in which a body region and a source region are electrically short-circuited. In this lateral power semiconductor device, a channel region forms in a portion of the body region on the first surface, which overlaps with a gate dielectric and the first electrode portion acting as the gate electrode. The conductivity of this channel region can be controlled by applying a suitable voltage to the first electrode portion. A channel current flowing in a lateral direction parallel to the first surface can thus be controlled along this channel region. In a self-blocking n-channel FET, i.e., an enhancement-type n-channel FET, for example, a conducting channel is created if a positive voltage between the gate terminal G and the source terminal S exceeds a threshold voltage Vth.In this case, the channel returns to a blocking state if the gate voltage falls below the threshold voltage, e.g., at a gate voltage of 0V.

[0008] According to one embodiment, the drain expansion region is suitable for blocking a drain-to-source voltage in a range of 5V to 200V. The desired voltage blocking range can be set by appropriately dimensioning and doping the drain expansion region. Thus, the planar field-effect transistor can be used, for example, in circuit applications such as DC-DC converters. To achieve a desired current-carrying capacity, the planar field-effect transistor can be constructed from a large number of planar field-effect transistor cells connected in parallel. These parallel-connected planar field-effect transistor cells can, for example, be arranged in the form of a strip or a strip segment. Of course, the field-effect transistor cells can also have any other shape, e.g., circular, elliptical, polygonal, or octahedral.

[0009] According to one embodiment, the first electrode part and the second electrode part are distinct parts of a structured electrode layer. The electrode layer can be a conductive layer such as a metal layer, a metal silicide layer, a metal alloy, or a highly doped semiconductor layer, or a combination of these materials. The electrode layer can, for example, be a wiring layer that, after structuring, can function as a conductor or electrode in other component areas. Naturally, the electrode layer can also be an electrode layer located between a first wiring layer and the first semiconductor surface.

[0010] According to one embodiment, the planar field-effect transistor also has a deep body region that is electrically connected to the source terminal and extends laterally below the drain expansion region, wherein the extent of the deep body region and the extent of the drain expansion region overlap at least partially in a first lateral direction. The first lateral direction is, for example, a channel length direction of the channel region perpendicular to a channel width direction. The channel length direction runs, for example, along a direction from the source to the drain terminal of the planar field-effect transistor. Due to the compensation principle or RESURF (REduced SURface Field) principle, the partial overlap has a positive effect on the blocking capability of the planar field-effect transistor.The extension of the deep body region in the first lateral direction and the extension of the first electrode part acting as a gate electrode in the first lateral direction can, for example, overlap.

[0011] According to one embodiment, the extension of the deep body region in the first lateral direction and the extension of the second electrode part in the first lateral direction overlap at least partially.

[0012] According to one embodiment, the deep body region has laterally adjacent first and second body regions, and the dopant dose in the first body region, which is laterally closer to the drain terminal, is smaller than in the second body region. This allows for a further improvement in the on-resistance Rdson as well as the drain-to-source breakover voltage, i.e., the drain-to-source breakdown voltage.

[0013] According to another embodiment, a bottom surface of the planar dielectric transitions seamlessly into a bottom surface of the gate dielectric, and the top surface of the gate dielectric transitions via a step directed towards the first surface into a top surface of the gate dielectric. This further reduces the electric fields at the first surface, resulting in a further improvement in the breakdown behavior of the planar field-effect transistor.

[0014] According to another embodiment, the thickness of the additional dielectric increases towards the drain terminal. A lower side of the additional dielectric runs parallel to the first surface, and the second electrode portion is arranged on an upper side of the additional dielectric that is inclined relative to the first surface. This also further reduces the electric fields at the first surface, resulting in a further improvement in the breakdown behavior of the planar field-effect transistor.

[0015] According to a further embodiment, the second electrode part is electrically connected via a contact to a field plate arranged above the second electrode part, and the field plate extends laterally further towards the drain terminal than the second electrode part. This allows the electric field profile in the drift region to be further improved and a higher drain-to-source blocking strength to be achieved. The field plate can, for example, be part of a first structured metallization layer.

[0016] According to one embodiment, the planar field-effect transistor also has a third electrode section above the drain expansion region, wherein the second electrode section is arranged laterally between the third electrode section and the first electrode section, and the third electrode section is electrically connected to the second electrode section via the field plate. The lateral separation of the drain-side field plates allows for a further improvement of the electric field profile in the drift region and thus improves the drain-to-source blocking strength.

[0017] According to one embodiment, the drain expansion region has laterally adjacent first and second drain expansion subregions, and the dopant dose in the first drain expansion subregion, which is laterally closer to the drain terminal, is greater than in the second drain expansion subregion. This allows for a further improvement in the on-resistance Rdson as well as the drain-to-source breakover voltage, i.e., the drain-to-source breakdown voltage.

[0018] The semiconductor device can be used in a variety of applications. For example, according to one embodiment, a DC-DC converter incorporates one of the embodiments of the semiconductor device described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings serve to illustrate exemplary embodiments of the invention, are incorporated into the disclosure, and form part thereof. The drawings merely depict exemplary embodiments and, together with the description, serve to explain them. Further exemplary embodiments and many of the intended advantages will become apparent from the detailed description below. The elements and structures shown in the drawings are not necessarily drawn to scale. Identical reference numerals refer to identical or corresponding elements and structures. Fig. Figure 1 is a schematic cross-sectional view of a planar field-effect transistor with a first electrode part acting as a gate electrode and a second electrode part acting as a field plate, as well as a drain expansion region. Fig. 2 is a schematic cross-sectional view of a [structure] as shown in Fig. 1 planar field-effect transistor shown, in which an STI (Shallow Trench Isolation) region is arranged between the first and second electrode parts and the drain extension region. Fig. Figure 3 is a schematic cross-sectional view of a structure as shown in Fig. 1 planar field-effect transistor shown, in which a LOCOS (Local Oxidation of Silicon) region is arranged between the first and second electrode parts and the drain extension region. Fig. Figure 4 is a schematic cross-sectional view of a structure as shown in Figure 4. Fig. 1 planar field-effect transistor shown, in which a planar dielectric is arranged between the first and second electrode parts and the drain expansion region. Fig. Figure 5 is a schematic cross-sectional view of a structure as shown in Figure 5. Fig. 1 planar field-effect transistor shown, in which a triangular or beveled dielectric is arranged between the first and second electrode parts and the drain expansion region. Fig. 6 is a schematic cross-sectional view of a [structure] as shown in Fig. 1 planar field-effect transistor shown, in which a field plate effect is realized both by the second electrode part and by a contact surface formed above the second electrode part. Fig. 7 is a schematic cross-sectional view of a [structure] as shown in Fig. 1 shown planar field-effect transistor, in which the drain expansion region is divided into differently doped subregions. Fig. Figure 8 is a schematic cross-sectional view of a structure as shown in Figure 8. Fig. 1 shown planar field-effect transistor, in which a buried body region is divided into differently doped subregions. Fig. Figure 9 is a schematic cross-sectional view of a structure as shown in Fig. 1 planar field-effect transistor shown, in which the second electrode part as well as a laterally spaced third electrode part act as a field plate. Fig. Figure 10 is a graph showing the time course of gate and drain voltage for various planar field-effect transistors. Fig. Figure 11 shows a schematic circuit diagram of a DC-DC converter with field-effect transistors, which, according to the embodiments of the Fig. They can be designed from 1 to 9. DETAILED DESCRIPTION

[0020] The following detailed description refers to the accompanying drawings, which form part of the disclosure and show specific embodiments for illustrative purposes. In this context, directional terminology such as "top," "bottom," "front," "back," "front," "back," etc., refers to the orientation of the figures just described. Since the components of the embodiments can be positioned in different orientations, this directional terminology serves only for explanation and is in no way to be considered limiting.

[0021] It goes without saying that further embodiments exist and that structural or logical modifications can be made to these embodiments without deviating from what is defined by the claims. The description of the embodiments is not limiting in this respect. In particular, elements of the embodiments described below can be combined with elements of other described embodiments, unless the context indicates otherwise.

[0022] The terms "have," "contain," "comprise," "exhibit," and the like are, in the following, open terms that indicate the presence of the aforementioned elements or characteristics, but do not exclude the presence of further elements or characteristics. The indefinite and definite articles include both the plural and the singular, unless the context clearly indicates otherwise.

[0023] The terms "have," "contain," "comprise," "exhibit," and similar terms are open-ended, indicating the presence of the identified structures, elements, or features without excluding additional elements or features. Indefinite and definite articles should encompass both the plural and singular unless the context clearly indicates otherwise.

[0024] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more intermediate elements suitable for signal transmission may be present between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0025] In Fig. Figure 1 shows a schematic cross-sectional view of a planar field-effect transistor 100. The planar field-effect transistor 100 has a drain expansion region 102 between a channel region 104 and a drain terminal D on a first surface 106 of a semiconductor body 112. The planar field-effect transistor also has a first electrode part 108 and a second electrode part 110. The first electrode part 108 is laterally spaced from the second electrode part 110, with the first electrode part 108 being arranged as a gate electrode above the channel region 104 and the second electrode part 110 being arranged above the drain expansion region 102 and electrically separated from the first electrode part 108. The second electrode part 110 acts as a field plate and is electrically connected to a reference terminal R, e.g., the source terminal S.

[0026] A planar field-effect transistor is a field-effect transistor in which a gate dielectric and a gate electrode are manufactured using planar technology, so that they are positioned on a semiconductor substrate and, unlike in trench-gate structures, are not located in a trench extending into the semiconductor substrate.

[0027] Thus, the planar field-effect transistor 100 exhibits in Fig. Figure 1 describes a semiconductor body 112 on which an insulating structure 114 is formed on the first surface 106. The insulating structure 114 comprises a gate dielectric 1141, which is positioned above the channel region 104 between the first electrode part 108, which acts as the gate electrode, and the channel region 104. The insulating structure 114 can, for example, have further parts in the direction of the drain terminal D that differ from the gate dielectric 1141 with respect to material composition or geometric dimensions such as thickness. Examples of such further parts of the insulating structure 114 are described below. The gate dielectric 1141 can, for example, be an insulating material such as an oxide, e.g., SiO2, a nitride, e.g., Si3N4, a high-k dielectric, or a low-k dielectric, or any combination thereof. For example, the gate dielectric 1141 is configured as a thermal oxide.The first electrode part 108, which acts as a gate electrode, is placed on the gate dielectric 1141 and is electrically connected to a gate terminal G.

[0028] The semiconductor body 112 can be based on various semiconductor materials, such as silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), silicon-germanium, germanium, gallium arsenide, silicon carbide, gallium nitride, or other composite semiconductor materials. The semiconductor body can be based on a semiconductor substrate, such as a semiconductor wafer, and may comprise one or more epitaxial layers deposited on it, or it may be back-thinned. A conductivity type of the drain expansion region 102 corresponds to a portion of the semiconductor body 112 surrounding the drain expansion region 102. However, for example, the doping concentration in the drain expansion region 102 may be comparatively higher.

[0029] The planar field-effect transistor 100, for example, can be constructed from field-effect transistor cells arranged in the form of a strip or a strip segment. Of course, the field-effect transistor cells can also have any other shape, e.g., circular, elliptical, polygonal, or octahedral.

[0030] The second electrode part 110, acting as a field plate, is electrically connected to a reference potential, such as a source terminal S. The source terminal S is, for example, a conductive structure that may include electrically connected conductive components such as contact plugs, metallization tracks, and connection pads. These conductive components, in turn, consist of conductive material such as a metal, a metal silicide, a metal alloy, a highly doped semiconductor, or a combination thereof. The specifications for the drain terminal D regarding material and structure are the same as those given for the source terminal S.

[0031] The source terminal S is electrically connected to a source region 118 of a first conductivity type and to a body region 120 of a second conductivity type. The first conductivity type corresponds to the conductivity type of the drain extension region 102. The electrical connection between the body region 120 and the source terminal S is in Fig. Figure 1 is simplified and can be implemented in various ways in practice. For example, the source terminal S can include a trench contact that extends into the semiconductor body 112 and electrically contacts the body region 120 via the bottom of the trench contact and part of the side wall. Similarly, the electrical contacting of the body region 120 can be achieved, for example, by connecting the source region 118 and the body region 120 along a plane perpendicular to the plane of the drawing. Fig. 1. Directed in one direction, e.g., along a strip in the case of strip-shaped transistor cells of the planar field-effect transistor 100, the transistors are alternately directed to the first surface 106 and are in electrical contact there with the source terminal S. For this purpose, the source region 118 is guided along a direction perpendicular to the plane of the drawing by Fig. The body region 120 is formed in a direction of expansion in the form of spaced-apart segments, between which the contact area for the body region 120 is located. The body region 120 and the source region 118 can also laterally adjoin each other on the first surface 109 and each be in electrical contact with the source terminal S.

[0032] The planar field-effect transistor 100, for example, can be implemented monolithically using a hybrid technology. Such hybrid technologies allow for the integration of, for instance, analog blocks on a single chip using bipolar components for interfaces to digital systems, digital blocks using CMOS (complementary metal-oxide-semiconductor) components for signal processing, and high-voltage or power blocks using field-effect transistors. These hybrid technologies are known, for example, as bipolar-CMOS-DMOS, BCD, or smart power technologies (SPT) and are used in a wide variety of applications, including lighting, motor control, automotive electronics, power management for mobile devices, audio amplifiers, power supplies, hard drives, and printers.

[0033] The drain extension region 102 is a semiconductor region of the first conductivity type that conducts the channel current exiting the end of the channel region 104 to the drain terminal D. Similar to how a drift zone in a vertical power semiconductor device serves to conduct the channel current vertically to the drain terminal, the drain extension region 102 acts as a drift zone in which a load current is conducted laterally to the drain terminal D. Like the drift zone in vertical power semiconductor devices, the drain extension region 102 in the planar field-effect transistor also contributes significantly to the blocking capability of these devices, i.e., the maximum drain-to-source voltage during operation, which is typically specified in the device's datasheet. This blocking capability can be influenced and appropriately adjusted, for example, by suitable dimensioning and doping of the drain extension region 102.In one embodiment, the drain extension area 102 is suitable to block a drain-to-source voltage in a range of 5 V to 200 V.

[0034] In one example, the gate dielectric 1141 is formed as part of the insulating structure 114 between the channel region 104 and the first electrode part 108. The insulating structure 104 also includes a further dielectric 1142, which is formed, among other places, between the first electrode part 108 and the drain extension region 102, wherein the thickness d2 of the further dielectric 1142 is greater than the thickness d1 of the gate dielectric 1141. The gate dielectric 1141 borders the further dielectric 1142 in the direction of the drain terminal D. The further dielectric 1142 can, for example, consist of or include a combination of the dielectrics STI (Shallow Trench Insulation), LOCOS (Local Oxidation of Silicon), planar dielectric, or beveled dielectric.

[0035] For example, the insulating structure can be produced using different dielectrics manufactured in a mixed technology, and these or some of these dielectrics can be combined to form the insulating structure 114.

[0036] One example refers to the one in Fig. 1 planar field-effect transistor shown, in which the reference terminal R of the second electrode part 110 is electrically connected to the source terminal.

[0037] In the Fig. Figure 2, a cross-sectional view of a planar field-effect transistor 100, illustrates an example in which the body region 120 has first, second, and third body subregions 1201, 1202, and 1203 of the second conductivity type. The first body subregion 1201 borders the gate dielectric 1141 and thus serves to form a conductive channel when a suitable voltage is applied to the first electrode part 108, which acts as the gate electrode. The second body subregion 1202 serves as a vertical connection area for a buried third body subregion 1203, which extends laterally as a deep body subregion below the drain expansion region 102, with the extension of the deep body subregion 1203 and the extension of the drain expansion region 102 in a first lateral direction x1 overlapping at least partially. The partial overlap has an effect due to the compensation principle, or rather...The RESURF (REduced SURface Field) principle has a positive effect on the blocking capability of the planar field-effect transistor 100. The extent of the third body sub-region 1203 in the first lateral direction x1 and an extent of the first electrode part 108 in the first lateral direction x1 partially overlap.

[0038] Depending on whether the doping of the second body subregion 1202 on the first surface 106 is suitable for forming an ohmic contact, a highly doped body termination region 1204 of the second conductivity type can be formed on the first surface 106 to electrically connect the first to third body subregions 1201, 1202, 1203 to the source termination S. In addition to body region 120, source region 118 is also electrically connected to the source termination S. The electrical connection of body region 120 and source region 118 to the first surface 106 can be achieved in various ways. Reference is made to the explanations above in this context.

[0039] The source terminal S has a first contact surface 1221, e.g., part of a wiring plane such as a metallization plane, and a first electrical contact 1222, wherein the first electrical contact 1221 extends through an intermediate dielectric 124 to the body region 120 or the source region 118 and electrically contacts it. The gate terminal has a second contact surface 1231, e.g., part of a wiring plane such as a metallization plane, and a second electrical contact 1232, wherein the second electrical contact 1231 extends through the intermediate dielectric 124 to the first electrode part 108 and electrically contacts it. A reference electrode R has a third contact surface 1241, e.g.,The electrode consists of a portion of a wiring plane, such as a metallization plane, and a third electrical contact 1241, wherein the third electrical contact 1241 extends through the intermediate dielectric 124 to the second electrode portion 110, which acts as a field plate, and makes electrical contact with it. The source terminal S and the reference electrode R can, for example, be short-circuited. The drain terminal D has a fourth contact surface 1251, e.g., a portion of a wiring plane, such as a metallization plane, and a fourth electrical contact 1252, wherein the fourth electrical contact 1252 extends through the intermediate dielectric 124 to the body region 120 or the drain terminal region 1025 and makes electrical contact with them. The first to fourth contact surfaces 1222, 1232, 1242, 1252 can, for example, be generated from the same wiring plane by lithographic structuring into the different contact surfaces.Likewise, the first to fourth electrical contacts 1221, 1231, 1241, 1251 can, for example, be processed together as contact plugs or contact rows.

[0040] The first electrode part 108, acting as a gate electrode, extends along the first lateral direction x1 beyond the termination of the first body subregion 1201 and overlaps with the drain extension region 102. Between the drain extension region 102 and the first electrode part 108, an STI region 1143 is formed as part of the insulating structure 114. The STI region 1143 is also formed between the second electrode part 110 and the drain extension region 102. The second electrode part 110, which is electrically isolated from the gate terminal G, acts as a field plate and enhances the blocking capability of the planar field-effect transistor 100. The drain extension region 102 is electrically connected to the drain terminal D via the drain terminal region 1025, e.g., a highly doped region of the first conductivity type.

[0041] In the Fig. In the example shown, the gate dielectric 1141 extends laterally across the channel region 114 towards the drain connection D and then transitions below the first electrode part 108 into the STI region 1143 of the insulating structure 114.

[0042] The in Fig. The example shown in Figure 2 enables a reduction of the gate capacitance and thus a reduction of the switching losses in the medium and low current range of circuit applications of the planar field-effect transistor 100 by separating the second electrode part 110, which acts as a field plate, from the gate terminal G and by designing the insulating structure 114.

[0043] In Fig. Figure 3 shows another example of the planar field-effect transistor 100 in a cross-sectional view. Features of this example, which are similar to those of the one in Fig. Examples shown in section 2, which are identical or similar to them, are marked with matching reference identifiers. The example shown in Fig. The third example shown differs from the example in Fig. 2. This is achieved by the fact that the insulating structure 114, for reducing the electric field at the first surface, has a LOCOS region 1144 instead of the STI region 1143, which, due to the processing of this oxide, extends both into the semiconductor body 112 and is formed above it. Thus, the first electrode part 108 also runs obliquely in the transition region from the gate dielectric 1141 to the LOCOS region 1144.

[0044] In Fig. Figure 4 shows another example of the planar field-effect transistor 100 in a cross-sectional view. Features of this example, which are similar to those of the one in Fig. Examples 2 shown are identical or similar to them and are marked with matching reference identifiers. The example shown in Fig. The example shown in section 4 differs from the example in Fig. 2 by the fact that the insulating structure 114, to reduce the electric field at the first surface 106, instead of the STI region 1143, has a planar dielectric 1145 such as a planar oxide, the top of which transitions via a step 128 directed towards the first surface 106 into a top of the gate dielectric 1141.

[0045] In Fig. Figure 5 shows another example of the planar field-effect transistor 100 in a cross-sectional view. Features of this example, which are similar to those of the one in Fig. Examples 2 shown are identical or similar to them and are marked with matching reference identifiers. The example shown in Fig. The example shown in point 5 differs from the example in Fig. 2 by the insulating structure 114 having a triangular dielectric 1146 instead of the STI region 1143 to reduce the electric field at the first surface, wherein a thickness of the triangular dielectric 1146 increases in the direction of the drain terminal D, a bottom side of the triangular dielectric 1146 runs parallel to the first surface 106, and the second electrode part 110 is arranged on a top side region of the triangular dielectric 1146 inclined to the first surface 106.

[0046] In Fig. Figure 6 shows another example of the planar field-effect transistor 100 in a cross-sectional view. Features of this example, which are similar to those of the one in Fig. Examples 2 shown are identical or similar to them and are marked with matching reference identifiers. The example shown in Fig. The example shown in section 6 differs from the example in Fig. 2 by further improving the barrier strength between drain and source, the field plate is not only extended by the second electrode part 110, which, compared to the embodiment of Fig. The gate dielectric 1141 is not only shortened laterally, but is also formed by the third contact surface 1241. Furthermore, another planar dielectric 1147 is formed between the STI region 1143 and the gate dielectric 1141, which is thicker than the gate dielectric 1141 and thus contributes to a further reduction of the gate capacitance.

[0047] In Fig. Figure 7 shows another example of the planar field-effect transistor 100 in a cross-sectional view. Features of this example, which are similar to those of the one in Fig. Examples 6 shown are identical or similar to them and are marked with matching reference identifiers. The example shown in Fig. The example shown in point 7 differs from the example in Fig. 6. This is achieved by the fact that the drain expansion area has laterally adjacent first and second drain expansion sub-areas 1021, 1022, and the dopant dose in the first drain expansion sub-area 1021, which is laterally closer to the drain connection D, is greater than in the second drain expansion sub-area 1022. This allows for a further improvement in the on-resistance and the drain-source blocking resistance.

[0048] In Fig. Figure 8 shows another example of the planar field-effect transistor 100 in a cross-sectional view. Features of this example, which are similar to those of the one in Fig. Examples 7 shown are identical or similar to them and are marked with matching reference identifiers. The example shown in Fig. The example shown in point 8 differs from the example in Fig. 7. This is achieved by the fact that the third body subregion 1203 has adjacent first and second body subregions 1205, 1206, and the dopant dose in the first body subregion 1205, which is laterally closer to the drain connection D, is smaller than in the second body subregion 1206. This allows for a further improvement in the on-resistance and the drain-source blocking resistance.

[0049] In Fig. Figure 9 shows another example of the planar field-effect transistor 100 in a cross-sectional view. Features of this example, which are similar to those of the one in Fig. Examples 7 shown are identical or similar to them and are marked with matching reference identifiers. The example shown in Fig. The example shown in 9 differs from the example in Fig. 7 by a third electrode part 111 above the drain expansion area 102, wherein the second electrode part 110 is arranged laterally between the third electrode part 111 and the first electrode part 108. The third electrode part 111 is electrically connected to the second electrode part 110 via a fifth electrical contact 1262, the third contact surface 1241 and the third electrical contact 1242. This allows for a further improvement in the on-resistance and the drain-source blocking resistance.

[0050] In Fig. Figure 10 shows a schematic graph where the left y-axis represents a gate voltage and the right y-axis represents a drain voltage. The curves shown represent the simulated time course of these voltages at a constant gate current. A planar field-effect transistor serves as the reference, which does not have a [missing information - likely a specific feature or characteristic] as described in [missing information - likely a diagram]. Fig. The second electrode part shown in Figure 1 has its gate dielectric laterally connected to an STI region. The curves cgref and cdref show the time course of the gate and drain voltages. The curves cg1 and cd1 show the time course of the gate and drain voltages of a device as shown in Figure 1. Fig. In the example shown, in addition to the first electrode part 108 acting as a gate electrode, a second field electrode part 110 acting as a field electrode is present. Comparing the curves cg1 and cd1 with the curves cgref and cdref reveals the advantageous reduction in the charge duration of the gate-drain capacitance. A further improvement can be achieved by placing a [missing information] between the gate dielectric 1141 and the STI region 1143 of the example from [missing information]. Fig. 2. A further planar dielectric, thicker than the gate dielectric 1141, is placed, cf. for example the further planar dielectric 1147 in the example of Fig. 6. This further improvement can be seen when comparing the curves cg2 and cd2 with the curves cg1 and cd1.

[0051] In the schematic diagram of the Fig. Figure 11 shows an application example in the form of a DC-DC converter 200, in which the planar field-effect transistor 100 can be implemented. The DC-DC converter 200 also has a driver stage Tr and converts an input voltage Vin into an output voltage Vout by means of the planar field-effect transistor 100 and a downstream filter comprising an inductor L and a capacitor C. The elements contained within the dashed area 201 can, for example, be implemented as an integrated circuit.

Claims

[1] Planar field-effect transistor (100) which features: a drain extension area (102) between a channel area (104) and a drain connection (D) on a first surface (106) of a semiconductor body (112); a first electrode part (108) and a second electrode part (110) which are laterally spaced apart from each other, wherein the first electrode part (108) is arranged as a gate electrode above the channel area (104) and the second electrode part (110) is arranged above the drain expansion area (102) and is electrically separated from the first electrode part (108); a gate dielectric (1141) between the first electrode part (108) and the channel region (104); and a further dielectric (1142) between the first electrode part (108) and the drain expansion region (102), wherein the thickness of the further dielectric (1142) is greater than the thickness of the gate dielectric (1141) and the gate dielectric (1141) borders the further dielectric in the direction of the drain terminal (D), and wherein the further dielectric (1142) comprises a first dielectric, as well as a planar dielectric (1147) between the first dielectric and the gate dielectric (1141), wherein the planar dielectric (1147) is thicker than the gate dielectric (1141) and borders a top surface (106) of a part of the drain expansion region (102), and the first dielectric is a LOCOS dielectric or a beveled dielectric, and the further dielectric (1142) is located under the second electrode part (110) is thicker than the planar dielectric (1147) under the first electrode part (108). [2] Planar field-effect transistor (100) according to claim 1, wherein the second electrode part (110) is electrically connected to a source terminal (S). [3] Planar field-effect transistor (100) according to any of the preceding claims, wherein the planar field-effect transistor (100) is a lateral power semiconductor device in which a body region (120) and a source region (118) are electrically short-circuited. [4] Planar field-effect transistor (100) according to one of the preceding claims, wherein the drain extension region (102) is suitable to block a drain-to-source voltage in a range of 5V to 200V. [5] Planar field-effect transistor (100) according to one of the preceding claims, wherein the first electrode part (108) and the second electrode part (110) are different parts of a structured electrode layer. [6] Planar field-effect transistor (100) according to any one of the preceding claims, which furthermore comprises: a deep body region (1203) that is electrically connected (S) to the source port and extends laterally below the drain extension region (102), wherein an extension of the deep body region (1203) in a first lateral direction (x1) and an extension of the drain extension region (102) in the first lateral direction (x1) overlap at least partially. [7] Planar field-effect transistor (100) according to claim 6, wherein the extension of the deep body region (1203) in the first lateral direction (x1) and an extension of the second electrode part (110) in the first lateral direction (x1) overlap at least partially. [8] Planar field-effect transistor (100) according to claim 6 or 7, wherein the deep body region (1203) has laterally adjacent first and second body part regions (1205, 1206), and a doping dose in the first body part region (1205) located laterally closer to the drain terminal (D) is smaller than in the second body part region (1206). [9] Planar field-effect transistor (100) according to claim 1, wherein a bottom surface of the planar dielectric (1147) transitions steplessly into a bottom surface of the gate dielectric (1141), and a top surface of the planar dielectric (1147) transitions via a step (128) directed towards the first surface (106) into a top surface of the gate dielectric (1141). [10] Planar field-effect transistor (100) according to claim 1, wherein the thickness of the further dielectric increases in the direction of the drain terminal (D), a bottom side of the further dielectric runs parallel to the first surface (106), and the second electrode part (110) is arranged on a top side region of the further dielectric inclined to the first surface (106). [11] Planar field-effect transistor (100) according to one of the preceding claims, wherein the second electrode part (110) is electrically connected via a contact (1242) to a field plate (1241) arranged above the second electrode part, and the field plate (1241) extends further in a lateral direction towards the drain terminal (D) than the second electrode part (110). [12] Planar field-effect transistor (100) according to one of the preceding claims, which furthermore has a third electrode part (111) above the drain expansion region (102), wherein the second electrode part (110) is arranged laterally between the third electrode part (111) and the first electrode part (108), and the third electrode part (111) is electrically connected to the second electrode part (110) via the field plate (1241). [13] Planar field-effect transistor (100) according to one of the preceding claims, wherein the drain enlargement region (102) has laterally adjacent first and second drain enlargement subregions (1021, 1022), and a dopant dose in the first drain enlargement subregion (1021) located laterally closer to the drain terminal is greater than in the second drain enlargement subregion (1022). [14] DC-DC converter (200) comprising the planar field-effect transistor (100) according to any one of the preceding claims.

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