Carrier arrangement and method for processing a carrier

Abstract

A method (100) for processing a carrier (202), the method comprising: Generating a crack structure (208) by forming an array of defects (206) in the carrier (202), wherein a surface region (204f) of the carrier (202) is arranged above the array of defects (206) on a first surface (202f) of the carrier (202), and wherein the crack structure (208) extends from the array of defects (206) into the surface region (204f) and has a plurality of cracks with a width of less than 500 nm; after generating the crack structure (208), partially removing the carrier (202) and thereby removing the arrangement of defects (206); subsequently, after partially removing the carrier (202), forming a metallization structure (310, 310p) on an exposed second surface (204b) of the surface region (204f), and subsequently Separating the surface region (204f) of the carrier (202) into a plurality of surface region sections (204p) along the crack structure (208).

Description

FIELD OF INVENTION

[0001] Various embodiments generally relate to a carrier, a carrier assembly, and a method for processing a carrier. General state of the art

[0002] In general, various techniques can be used for processing a wafer or any other carrier. Processing the wafer may involve singulating the wafer into multiple dies. The singulated dies may also be referred to as chips, bare chips, or unencapsulated dies, and the process of singulating the dies from the wafer may also be referred to as dicing or chipping. Various techniques can be used to separate a wafer into multiple dies, such as, for example, mechanical dicing, laser ablation dicing, dicing by grinding, plasma dicing, and the like. During wafer-level processing, i.e., before singulating the wafer into multiple dies, so-called trench regions may be provided that surround active die regions of the wafer.Accordingly, any material loss due to the dicing process performed at a later stage can already be accounted for during wafer processing. After dicing the wafer into multiple dies, an encapsulation process can be used to house the dies. The dies can be individually encapsulated, and more than one die can be provided in a so-called multi-chip package. However, there may be processes that include an encapsulation process or part of an encapsulation process at the wafer level.

[0003] JP 2017-34 129 A and US 2012 / 0 100 694 A1 each describe a method for processing a workpiece having a plurality of circuits, wherein dicing lines are defined between the circuits, and wherein the workpiece is irradiated from a rear side with a pulsed laser to produce a modified layer along the dicing lines, wherein the workpiece is subsequently fractured along the dicing lines. US 2015 / 0 279 740 A1 describes a method for metallizing a rear side of a semiconductor, wherein a carrier is attached to a substrate by means of an adhesive, a trench is subsequently formed in the carrier such that a portion of the adhesive is exposed, and after etching the exposed adhesive, a surface of the semiconductor is metallized.US 2010 / 0 012 632 A1 describes a method for dicing an object using a laser, wherein a modified layer is created in a silicon wafer of the object using the laser, wherein a crack propagates from this modified layer toward a surface of the object, and wherein the object is diced along the created cracks. JP 2015-037 172 A discloses a wafer processing method comprising a holding step, a modified layer forming step, a deformation reducing step, and a grinding step. The holding step holds a wafer W on a support table. The modified layer forming step forms a division starting point for a modified layer along a predetermined division line on the surface inside the wafer after the holding step.The distortion-reducing dividing step divides the wafer before or during the modified layer formation step and reduces the distortion caused by the formation of the modified layer with the division starting point. The grinding step forms a plurality of chips with a finishing thickness by grinding the wafer from a starting point of at least the division starting point of the modified layer to achieve the finishing thickness at which the wafer can be divided, and removing the modified starting point layer after the modified layer formation step and the distortion-reducing dividing step. Brief description of the invention

[0004] A method for processing a carrier according to claim 1 and a carrier assembly according to claim 15 are provided. Further embodiments are described in the dependent claims.

[0005] According to various embodiments, a method for processing a carrier may include, among other things: forming an array of defects in the carrier, wherein a surface region of the carrier is arranged over the array of defects on a first surface of the carrier, wherein the array of defects is configured to generate a crack structure extending from the array of defects into the surface region; partially removing the carrier to remove the array of defects; and separating the surface region of the carrier into a plurality of surface region sections along the crack structure. Short description of the drawings

[0006] In the drawings, like reference characters generally refer to the same parts throughout the several views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings. In the drawings: Fig. 1 shows a schematic flow diagram of a method for processing a carrier according to various embodiments; Fig. 2A shows a carrier in a schematic cross-sectional view in a first stage during processing of the carrier according to various embodiments; Fig. 2B shows a carrier in a schematic plan view in a first stage during processing of the carrier according to various embodiments; Fig. 2C shows a surface area of ​​a carrier in a schematic cross-sectional view in a second stage during processing of the carrier according to various embodiments; Fig. 2D separate surface area sections of a carrier in a schematic cross-sectional view in a third stage during processing of the carrier according to various embodiments; Fig. 3A and Fig. 3B shows a surface area of ​​a carrier in a schematic cross-sectional view at various stages during processing of the carrier according to various embodiments; Fig. 4A to 4C show a surface area of ​​a carrier in a schematic cross-sectional view at different stages during processing of the carrier according to various embodiments; Fig. 5 shows a carrier in a schematic cross-sectional view in a first stage during processing of the carrier according to various embodiments; Fig. 6 shows a carrier in a schematic cross-sectional view in a first stage during processing of the carrier according to various embodiments; Fig. 7A and Fig. 7B shows a carrier in a schematic cross-sectional view at various stages during processing of the carrier according to various embodiments; Fig. 7C shows a surface area of ​​a carrier in a schematic cross-sectional view during processing of the carrier according to various embodiments; and Fig. 8 a scanning electron micrograph of a carrier section separated from the carrier according to various embodiments. Description

[0007] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily exclusive of one another, as some embodiments may be combined with one or more other embodiments to form new embodiments. Various embodiments are described in connection with methods, and various embodiments are described in connection with devices.It is to be understood, however, that embodiments described in connection with methods may apply analogously to devices and vice versa.

[0008] The terms “at least one” and “one or more” may be understood to include any integer greater than or equal to one, i.e., one, two, three, four, [...], etc. The term “several” may be understood to include any integer greater than or equal to two, i.e., two, three, four, five, [...], etc.

[0009] The phrase "at least one of" with respect to a group of elements may be used herein to refer to at least one element from the group consisting of the elements. For example, the phrase "at least one of" with respect to a group of elements may be used herein to refer to a selection of the following: one of the listed elements, multiples of one of the listed elements, multiples of individual listed elements, or multiples of a multiple of the listed elements.

[0010] The word "over", used herein to describe forming a feature, e.g., a region, "over" a side or surface, may be used to denote that the feature, e.g., the region, may be formed "directly on", e.g., in direct contact with, the implied side or surface. The word "over", used herein to describe forming a feature, e.g., a region, "over" a side or surface, may be used to denote that the feature, e.g., the region, may be formed "indirectly on" the implied side or surface, with one or more additional regions disposed between the implied side or surface and the formed region.

[0011] In the same way, the word "cover", used herein to describe a feature disposed over another feature, e.g., an area "covering" a side or surface, can be used to mean that the feature, e.g., the area, can be disposed over and in direct contact with the implied side or surface. The word "cover", used herein to describe a feature disposed over another feature, e.g., an area "covering" a side or surface, can be used to mean that the feature, e.g., the area, can be disposed over and in indirect contact with the implied side or surface, with one or more additional areas disposed between the implied side or surface and the covering area.

[0012] The term "lateral", used with reference to the "lateral" extension of a structure (or structural element) provided on or in a carrier (e.g., a region, a substrate, a wafer, or a semiconductor workpiece), may be used herein to refer to an extension or positional relationship along a surface of the carrier. This means that a surface of a carrier (e.g., a surface of a substrate, a surface of a wafer, or a surface of a workpiece) may serve as a reference, typically referred to as the main processing surface. Furthermore, the term "width", used with reference to a "width" of a structure (or structural element), may be used herein to refer to the lateral extension of a structure.Furthermore, the term "height," used with reference to a height of a structure (or structural element), may be used herein to refer to an extension of a structure along a direction perpendicular to the surface of a support (e.g., perpendicular to the main machining surface of a support). The term "thickness," used with reference to a "thickness" of a region, may be used herein to refer to the spatial extension of the region perpendicular to the surface of the support (material or material structure) on which the region is deposited. If a surface of the support is parallel to the surface of the support (e.g., parallel to the main machining surface), the "thickness" of the region deposited on the surface of the support may be the same as the height of the region.

[0013] The term "region," as used herein to refer to a "doped region," a "surface region," a "support region," a "body region," and the like, may be used to refer to a continuous region.

[0014] According to various embodiments, a semiconductor region (e.g., a semiconductor substrate, a semiconductor wafer, a deposited semiconductor region, an epitaxial semiconductor region, and the like) may be made of silicon or include silicon. However, other semiconductor materials of various types may be used in a similar manner, e.g., germanium, Group III to V (e.g., SiC), or other types, including, for example, polymers. In one embodiment, the semiconductor region is a wafer made of silicon (e.g., p-doped or n-doped). In an alternative embodiment, the semiconductor region is a silicon-on-insulator (SOI) wafer.

[0015] In various embodiments, a method for processing ultrathin dies (or ultrathin chips) is provided herein. The dies may have a thickness of less than about 50 µm. The dies may optionally include a backside metal. Furthermore, the dies may optionally include a highly doped surface layer (e.g., a highly doped epitaxial layer) on the frontside.

[0016] The processing may, according to various embodiments, provide a cost-effective dicing concept for such ultra-thin dies. Furthermore, the dicing concept described herein allows for the patterning of a backside metallization on a planar surface at the wafer level. Illustratively, the dicing concept described herein allows for the formation of a backside metallization prior to separating the dies from the wafer. According to various embodiments, a backside metallization may include one or more electrically conductive layers (e.g., metal layers). The one or more metal layers of the backside metallization may be based on copper or a copper alloy, aluminum or an aluminum alloy, or any other suitable electrically conductive material. The backside metallization may also include a thick metal layer, e.g., with a thickness above about 2 µm, e.g., above about 5 µm.In this case, the backside metallization can also be configured to mechanically stabilize the ultra-thin die.

[0017] According to various embodiments, the dies may also include a front-side metallization. According to various embodiments, a front-side metallization may include one or more metal layers, as desired, to contact the respective electronic structures of the die. The front-side metallization may also include a thick metal layer, e.g., with a thickness above about 5 µm, e.g., based on copper or a copper alloy, aluminum or an aluminum alloy, or any other suitable electrically conductive material. In this case, the front-side metallization may also be configured to mechanically stabilize the ultra-thin die.

[0018] According to various embodiments, an ultra-thin die as described herein may be used to fabricate a vertical device, e.g., a vertical power device, such as, for example, a vertical diode, a vertical transistor, and / or a vertical thyristor. A vertical device may be configured to provide substantially vertical current flow through the die, e.g., from a front side of the die to a back side of the die. Furthermore, the lateral edges of the die may be configured to avoid electrical shorting between the front side and the back side.

[0019] According to various embodiments, a stealth dicing process may be used to singulate multiple carrier sections from a carrier, e.g., for singulating multiple dies from a wafer. During the stealth dicing process, the carrier (e.g., a wafer) may be supported by a glass carrier or any other suitable auxiliary carrier. Furthermore, a backside metal patterning process may be performed before and / or during the singulation of the carrier.

[0020] In general, competing conventional dicing concepts for singulating ultrathin dies may have one or more disadvantages. During mechanical dicing, a die sidewall may be damaged by the dicing blades. A laser ablation process may reduce die strength and may lead to metal contamination of a die sidewall. Standard Dicing By Grinding (DBG) concepts may be poorly compatible with process flows using dies with backside metallization. Plasma dicing concepts may involve a complicated process flow to avoid backside metal covering the die sidewalls, and topological steps on the backside may complicate backside patterning.

[0021] According to various embodiments, an efficient dicing concept can be provided that avoids metal contamination of the respective sidewalls of the die.

[0022] Fig. 1 illustrates a schematic process flow of a method 100 for processing a carrier. The method includes, among other things: at 110, forming an array of defects in the carrier configured to generate a crack structure extending from the array of defects into a surface region of the carrier; at 120, partially removing the carrier to remove the array of defects; and at 130, separating the surface region of the carrier into a plurality of surface region sections along the crack structure. The surface region of the carrier is arranged above the array of defects on a first surface of the carrier. Without loss of generality, the first surface may be a front surface on a front side of the carrier, e.g., a so-called main processing surface of the carrier.According to various embodiments, partially removing the carrier may include exposing a second surface of the surface region to the first surface. The method 100 may further include forming a metallization structure on the exposed second surface of the surface region. The method 100 may further include bonding the carrier to an auxiliary carrier, wherein the surface region of the carrier faces the auxiliary carrier and wherein a backside of the carrier is exposed.

[0023] The Fig. 2A to 2D show a carrier in a schematic cross-sectional view at various stages during processing, e.g., while performing the method 100, according to various embodiments.

[0024] Fig. 2A shows the carrier in a schematic cross-sectional view in a first processing stage, e.g., after the process 110 of the method 100 is performed, according to various embodiments. The carrier 202 may include or consist of a semiconductor material, e.g., silicon or any other suitable semiconductor material, e.g., silicon carbide, germanium, GaAs, and the like. The carrier 202 may be a wafer, e.g., having a diameter or a width (e.g., an extension in the lateral direction 101 and / or 103, illustrated in the figures) in the range of about 10 cm to about 50 cm, or even above 50 cm.

[0025] The carrier 202 includes an array of defects 206. Illustratively, an array of defective portions of the carrier 202 may be generated in the carrier 202. The array of defects 206 may be formed in a body region 204b (also referred to as a support region) of the carrier 202. The body region may be disposed beneath a surface region 204f of the carrier 202. The surface region 204f may include a first surface 202f on a first side of the carrier 202. According to various embodiments, the first surface 202f may be a main processing surface of the carrier 202 at a front side of the carrier 202. The carrier 202 may include a second surface 202b on a second side of the carrier 202 opposite the first side. According to various embodiments, the second surface 202b may be a backside surface of the carrier 202 on a backside of the carrier 202.

[0026] According to various embodiments, the carrier 202 may include one or more electronic structures arranged above and / or in the surface region 204f of the carrier 202. The one or more electronic structures may include one or more vertical electronic structures, such as, for example, one or more vertical diode structures, one or more vertical transistor structures, and / or one or more vertical thyristor structures. According to various embodiments, the one or more electronic structures may be configured to provide substantially a current flow vertically through the carrier 202, e.g., from a front side 202f of the carrier 202 to a back side 202b of the carrier 202.

[0027] According to various embodiments, the surface region 204f may be an active region of the carrier 202 for fabricating electronic components, e.g., logic circuits, memory circuits, sensor circuits, micromechanical or microelectromechanical structures, etc. The surface region 204f may have a thickness 205 (e.g., an extension along a thickness or vertical direction 105) in the range of approximately several micrometers to approximately several dozen micrometers, e.g., in the range of approximately 5 µm to approximately 50 µm. According to various embodiments, at least the surface region 204f may contain or consist of a semiconductor material. The body region 204b may contain any other suitable material, e.g., a support material. However, in the case that the carrier 202 is a semiconductor wafer, the carrier 202, e.g., the surface region 204f and the body region 204b, may consist essentially of semiconductor material.

[0028] According to various embodiments, the surface region 204f may include or be an epitaxial layer. The epitaxial layer may include the same semiconductor material as the rest of the carrier 202 or as the body region 204b. As an example, the body region 204b of the carrier 202 may be provided by a semiconductor wafer (e.g., a silicon wafer), and the surface region 204f may be an epitaxial semiconductor layer (e.g., a silicon epitaxial layer) deposited over the semiconductor wafer.

[0029] According to various embodiments, the semiconductor material (e.g., silicon) of the surface region 204f may be doped with at least one dopant. The surface region 204f may be p-doped or n-doped. The dopant concentration of the at least one dopant of the surface region 204f of the carrier 202 may be above approximately 10 16 cm -3 be, e.g. above about 10 17 cm-3 , e.g. over about 10 18 cm -3 . In other words, the surface region 204f may contain a highly doped semiconductor material (e.g., highly doped silicon). In this case, the surface region 204f may not be sufficiently transparent to infrared light to perform stealth dicing through the surface region 204f. The material (e.g., the semiconductor material) of the body region 204f may be selected to be sufficiently transparent to infrared light to perform stealth dicing from the backside, e.g., through the body region 204b. If the body region 204b contains, for example, silicon, the body region 204b may therefore be undoped or lightly doped, e.g., with a dopant concentration below about 10 16 cm -3 , e.g. below about 10 15 cm -3 , e.g. below about 10 14 cm -3 .

[0030] According to various embodiments, the arrangement of defects 206 is configured to generate a crack structure 208 extending from the arrangement of defects 206 into the surface region 204f of the carrier 202. According to various embodiments, the cracks of the crack structure 208 may extend (e.g., substantially vertically) up to the first surface 202f of the carrier 202. As shown in Fig. 2A, the surface region 204f may be free of the arrangement of defects 206, or in other words, the arrangement of defects 206 may be generated only in the body region 204b of the carrier 202. The body region 204b of the carrier 202 is also referred to herein as a support region, since the body region 204b may be substantially removed during processing, see, for example, Fig. 2C.

[0031] For example, in Fig. 2A, the arrangement of defects 206 may include a plurality of defects 206d arranged in a suitable pattern to generate the desired crack structure 208. The plurality of defects 206d may be arranged in one or more arrangement levels 205h. According to various embodiments, planar arrangement levels 205h may be arranged parallel to the first surface 202f of the carrier 202. The respectively adjacent defects 206d may be spaced from one another, e.g., by a distance in the range of about 1 µm to about 100 µm, e.g., in the range of about 10 µm to about 80 µm, e.g., in the range of about 20 µm to about 60 µm.

[0032] According to various embodiments, each defect 206d of the array of defects 206 may contain modified (e.g., amorphized) material of the carrier 202 (e.g., of the body region 204b), surrounded by (mono- or poly-)crystalline material of the carrier 202 (e.g., of the body region 204b). However, the defects 206d may also be porous regions or otherwise distorted regions of the carrier 202. The defects 206d may be formed by stealth dicing using a focused infrared laser beam. In this case, the defects 206d may also be referred to as candlesticks or modification sites.

[0033] Fig. 2B shows the carrier 202 in a schematic top view in a first processing stage, e.g., after the process 110 of the method 100 has been carried out, according to various embodiments. The carrier 202 may include a plurality of surface region sections 204p to be separated, or, in other words, to be singulated or sawn. The surface region sections 204p may be device regions of the carrier 202. The respective adjacent surface region sections 204p to be separated from one another may be spaced apart from one another. A separation region 220 may be provided between each of the respective adjacent surface region sections 204p to be separated from one another in order to compensate for material loss during the separation process. According to various embodiments, the carrier 202 may include one or more separation regions 220 along which the surface region 204f of the carrier 202 is to be separated into a plurality of surface region sections 204p.Illustratively, the surface region portions 204p may be chip or die regions of a wafer that are separated from each other by one or more scribe line regions.

[0034] According to various embodiments, the defect arrangement 206 may have a predefined pattern defining a plurality of separation lines 111, 113 for separating the surface region of the carrier into the plurality of surface region sections. The crack structure 208 may extend substantially along the separation lines 111, 113. In other words, the crack structure 208 may be formed between the respective adjacent surface region sections 204p to be separated, i.e., within the one or more separation regions 220. The surface region sections 204p may also be referred to herein as carrier sections 204p.

[0035] Fig. 2C shows the surface region 204f of the carrier 202 in a schematic cross-sectional view in a second processing stage, e.g., after the process 110 and the process 120 of the method 100 have been performed, according to various embodiments. The arrangement of defects 206 may be completely removed. Removing the arrangement of defects 206 may allow the surface region portions 204 of the surface region 204f to be provided with a sufficiently high mechanical stability.

[0036] To remove the arrangement of defects 206, the carrier 202 may be partially removed, e.g., the body region 204b of the carrier 202 may be partially or completely removed. According to various embodiments, the arrangement of defects 206 may be removed by thinning the carrier 202 from the back side 202b. The thinning may be performed via grinding, also referred to as polishing, e.g., chemical mechanical polishing. According to various embodiments, the carrier 202 may be reduced in thickness or, in other words, may be partially removed. The thickness of the carrier 202, or in other words, the thickness of the surface region 204f, may be below about 50 µm after performing the process 120 of the method 100.

[0037] According to various embodiments, the partial removal of the carrier may include exposing a second surface 204b of the surface layer 204 to the first surface 202f. A remaining portion of the carrier 202 may be the surface region 204f. Illustratively, the surface region 204f may be an ultra-thin carrier 202t that has already been pre-cracked or cracked into chips or dies. As shown in Fig. 2C, the ultra-thin carrier 202t may have a front surface 202f (which may be the same surfaces as the front surface 202f of the carrier 202 prior to thinning) and an exposed back surface 204b opposite the front surface 202f.

[0038] The cracks of the crack structure 208 may be very thin, e.g., in the range of approximately several nanometers. e.g., the cracks may have a width (e.g., an extension in the lateral direction 101 or the lateral direction 103, as illustrated in the figures) of less than approximately 500 nm, e.g., less than approximately 200 nm, e.g., less than approximately 100 nm, e.g., less than approximately 50 nm, e.g., less than approximately 10 nm. The second surface 204b of the surface layer 204 may be substantially smooth and dense, allowing the formation of a metallization layer on the second surface 204b of the surface layer 204 without metal of the metallization layer penetrating into the cracks of the crack structure 208. Therefore, the sidewalls of the surface region portions 204p (extending from the front side to the back side of the surface region 204f) may remain free of metal contamination.In the case that the surface region 204f may contain an epitaxial layer, the thinning may be performed such that only the epitaxial layer remains.

[0039] Fig. 2D shows a plurality of separated surface region sections 204p in a schematic cross-sectional view in a second processing stage, e.g., after the process 110, the process 120, and the process 130 of the method 100 have been performed, according to various embodiments. The surface region 204f of the carrier 202 may be separated into a plurality of surface region sections 204p along the crack structure 208. The separation of the surface region sections 204p may include providing a gap 111g between respectively adjacent surface region sections 204p.

[0040] Fig. 3A shows a surface region 204f of the carrier 202 in a schematic cross-sectional view in a second processing stage, e.g., before the process 130 of the method 100 is carried out, according to various embodiments. Fig. 3A can be similarly described above, e.g., with reference to the Fig. 2A to 2D. Prior to separating the surface region 204f into a plurality of surface region portions 204p, a metallization structure 310 may be formed (e.g., in a process 120a, which may optionally be included in the method 100) on the exposed second surface 204b of the surface region 204f. Illustratively, a backside metallization structure of the backside of the surface region 204f may be formed. Due to crack formation based on the arrangement of defects 206, electrically conductive material from the metallization structure 310 may not enter the cracks and may not cover the sidewalls of the surface region portions 204p.

[0041] According to various embodiments, the metallization structure 310 may include one or more electrically conductive layers (e.g., one or more contacting layers, one or more routing layers, etc.) forming a wiring structure, wherein the wiring structure may be at least partially embedded in dielectric material. According to various embodiments, the metallization structure 310 may be a single metal layer, e.g., a copper layer, a copper alloy layer, an aluminum layer, or an aluminum alloy layer. Forming the metallization structure 310 may, for example, include one or more layer formation processes (e.g., chemical or physical vapor deposition processes) and one or more patterning processes (e.g., including one or more lithographic processes and one or more etching processes, e.g., reactive ion etching).

[0042] The surface region 204f and the metallization structure 310 may be separated into a plurality of surface region sections 204f, wherein each of the surface region sections 204f includes a metallization structure section 310p, as shown in Fig. 3B in a schematic cross-sectional view, according to various embodiments. The metallization structure 310 may be configured to break according to the surface region portions 204f into the metallization structure portions 310p during the separation of the surface region portions 204f.

[0043] Fig. 4A shows a surface region 204f of the carrier 202 in a schematic cross-sectional view in a second processing stage, e.g., before the process 130 of the method 100 is carried out, according to various embodiments. Fig. 4A may be formed as described herein, e.g., with reference to the Fig. 2A to 2D, e.g. similar Fig. 3A, can be processed.

[0044] If the metallization structure 310 may be thick, e.g., having a thickness above about 1 µm, the metallization structure 310 may be patterned to support breaking of the metallization structure 310 into the metallization structure portions 310p during the separation of the surface region portions 204f, as shown in Fig. 4B.

[0045] The metallization structure 310 may be patterned according to the crack structure 208. Therefore, the metallization structure 310 may be partially removed to expose one or more of the surface portions 402b of the second surface 204b of the surface region 204f at the crack structure 208. The patterning process (e.g., a process 120b that may optionally be included in the method 100) may include forming a patterned mask layer exposing the regions of the metallization structure 310 to be removed and an etching process, e.g., reactive ion etching, to remove the exposed regions of the metallization structure 310. Illustratively, the crack structure may be exposed on the second surface 204b of the surface region 204f.

[0046] The surface region 204f and the metallization structure 310 may be separated into a plurality of surface region sections 204f, wherein each of the surface region sections 204f includes a metallization structure section 310p, as shown in Fig. 4C in a schematic cross-sectional view, according to various embodiments. The metallization structure 310 may be separated into a plurality of metallization structure sections 310p before the surface region 204f is separated into a plurality of surface region sections 204f.

[0047] Fig. 5 shows the carrier 202 in a schematic cross-sectional view in a first processing stage, e.g., after the process 110 of the method 100 has been performed, according to various embodiments. According to various embodiments, the arrangement of defects 206 can be generated via a focused laser beam as described above. This process can also be referred to as stealth dicing.

[0048] According to various embodiments, a focus region 502f of the focused laser beam 502b may be scanned within the carrier 202, e.g., within the body region 204b of the carrier 202 and, for example, not within the surface region 204f of the carrier 202. The focus region 502f of the focused laser beam 502b may be scanned along one or more two-dimensional planes 205h, 505a, 505b (see Fig. 2A). The laser 502 can be operated in a pulsed mode so that multiple defects 206d (e.g., modification sites) can be generated in the carrier 202 in the desired pattern to provide the arrangement of defects 206 and the crack structure 208.

[0049] To generate the array of defects 206 within the carrier 202, i.e., beneath the surface region 204f, the position of a smallest waist (also referred to as the focus region 502f) of the focused laser beam 502b can be measured, adjusted, and guided accordingly. A laser 502, or in other words, a laser array, can be used to generate the focused laser beam 502b. The laser 502 can include optical elements (e.g., at least one lens or at least one mirror) to provide a focus region 502f of the focused laser beam 502b at a desired z-position along a z-direction and at a desired position within the xy-plane. Furthermore, a movable stage may be used to position the carrier 202 relative to the focus area 502f of the focused laser beam 502b and to move the carrier 202 within the xy plane (and optionally also in the z direction) perpendicular to the z direction.The position of the carrier 202 relative to the position of the focus region 502f of the focused laser beam 502b may be controlled such that the focused laser beam 502b is provided within the carrier 202 to form the array of defects 206 between the surface region 204f and the second surface 202b of the carrier 202.

[0050] The focused laser beam 502b may be provided such that energies above the damage threshold of the respective carrier material (e.g., silicon) may be introduced into the carrier 202. This may cause a localized shell of damaged crystal in the carrier 202, e.g., a localized amorphous region. The locally damaged carrier material may provide the array of defects 206. The locally damaged carrier material (e.g., the array of defects 206) may have a refractive index that is different from the refractive index of the undamaged carrier material.Therefore, the arrangement of defects 206 may be generated by forming a plurality of defects in a first arrangement level 505a and generating a plurality of defects in a second arrangement level 505b different from the first arrangement level 505a, and the like, wherein a first distance between the first arrangement level 505a and the first surface 202f of the carrier 202 is smaller than a second distance between the second arrangement level 505b and the first surface 202f of the carrier 202. In order to avoid distortions due to the different refractive index of the damaged material, the plurality of defects in the second arrangement level 505b are formed after forming the plurality of defects in the first arrangement level 505a.

[0051] The position of the carrier 202 relative to the position of the focus region 502f of the focused laser beam 502b can be controlled such that the focused laser beam 502b is moved within the carrier 202 to provide the arrangement of defects 206 according to a predefined pattern.

[0052] As an example, a pulsed and tightly focused laser beam may be used to generate the defects 206d of the array of defects 206, as described herein. The laser pulses may have a duration below about 1 ns, a power density above the damage threshold of the material (e.g., for silicon, above 1 E10 W / cm 2 , e.g. in the range of about 1 E10 W / cm 2 up to about 1 E15 W / cm 2 ), a Rayleigh length below about 10 µm and a smallest waist below about 10 µm for precise localization and generation of the defects 206d.

[0053] Since surface effects are to be avoided during the generation of defects 206, a wavelength in a range where the carrier material is substantially transparent to laser beam 502b can be selected for the focused laser beam 502b. For example, if carrier 202 consists essentially of silicon, the wavelength can be in the infrared range, e.g., above approximately 800 nm, e.g., in the range from approximately 800 nm to approximately 1500 nm, e.g., in the range from approximately 1000 nm to approximately 1100 nm.

[0054] Fig. 6 shows the carrier 202 in a schematic cross-sectional view in a first processing stage, e.g., after the process 110 of the method 100 has been performed, according to various embodiments. The carrier 202 may include a doped layer 604e. The doped layer 604e may be an epitaxial layer, i.e., the doped layer 604e may be epitaxially grown on the underlying surface 604f, e.g., using a chemical vapor deposition process, e.g., plasma-enhanced chemical vapor deposition.

[0055] Since the doped layer 604e may be less transparent than an undoped layer or non-transparent (illustratively not suitably transparent) for the laser beam 502 having a wavelength in the infrared range, the array of defects 206 may be generated via the laser beam 502b from the backside 202b of the carrier 202, as shown, for example, in Fig. 5 shown.

[0056] The doped layer 604e may be the surface region 204f of the carrier 202 or part of the surface region 204f of the carrier 202. According to various embodiments, the surface region 204f or the doped layer 604e of the surface region 204f may be readily processed, e.g., with one or more electronic structural elements. According to various embodiments, the carrier 202 may also include a front-side metallization arranged on and / or above the first surface 202f of the carrier 202.

[0057] Fig. 7A shows the carrier 202 in a schematic cross-sectional view in a first processing stage, e.g., during or after the process 110 of the method 100 is performed, according to various embodiments. The carrier 202 may be bonded to an auxiliary carrier 702, e.g., to a glass carrier or any other suitable auxiliary carrier. The surface region 204f of the carrier 202 may face the auxiliary carrier 702. In this case, the backside 202b of the carrier 202 is exposed for the processing of the backside 202b. The carrier 202 may also be bonded to the auxiliary carrier 702 during other processes of the method 100, e.g., during the process 120 or during the formation of the backside metallization structure 310, as in Fig. 7B in a schematic cross-sectional view. Via the auxiliary carrier 702, thinning of the carrier 202 can be performed from the rear side, as described above, e.g., for removing the array of defects 206.

[0058] Forming the array of defects 206 via a focused laser beam may be more efficient in the case where the carrier 202 has a thickness of less than about 300 µm. Therefore, according to various embodiments, the carrier 202 may be thinned to a thickness of less than about 300 µm, e.g., a thickness in the range of about 70 µm to about 300 µm, before the array of defects 206 is formed in the carrier 202. This may be achieved by thinning the carrier 202 from the backside 202b via grinding or any other suitable process.

[0059] Fig. 7C shows the surface region 204f of the carrier 202 in a schematic cross-sectional view during a separation process according to various embodiments. Separating the surface region 204f of the carrier 202 may include mounting (e.g., adhering with tape) the surface region to a swelling tape 710 and expanding the swelling tape 710 to laterally separate the plurality of surface region portions 204p from each other along the crack structure 208.

[0060] The swelling tape 710 may be mounted on an outer frame 714, expanded, and mounted on an inner frame 712. After the swelling tape 710 is expanded, a tape cutter 716 may be used to cut the swelling tape 710. The swelling tape 710 may also be referred to as a dicing tape. However, any other suitable process for separating the surface region portions 204p from each other may also be used. As an example, the swelling tape 710 may be radially expanded and then clamped between two outer frames.

[0061] As an example, a surface region portion 204p (e.g., each individual ultrathin chip) of a plurality of surface region portions 204p (e.g., of the plurality of ultrathin chips) may be removed separately from the pre-processed surface region 204f (e.g., of the ultrathin carrier or wafer) via a so-called Pick, Crack & Place™ process.

[0062] According to various embodiments, after separating the surface region portions 204p from each other, the separated surface region portions 204p may be further processed, e.g., an encapsulation process may be performed. Furthermore, according to various embodiments, the surface region portions 204p may be at least partially covered with an encapsulation material before being separated from each other, e.g., illustratively at the wafer level.

[0063] Fig. 8 shows a scanning electron micrograph of a 15 µm thick die (i.e., surface region portion) 204p after separation, e.g., after the process 130 of the method 100 is performed. Using the separation process described herein, smooth edges 804e may be generated on the fractured surface 704f (e.g., the sidewalls) of the surface region portion 204p according to various embodiments. Furthermore, the fractured surface 704f may be free of electrically conductive material, e.g., a metal, whereas the metallization structure 310 may be formed over the backside 204b of the surface region 204f.

[0064] The arrangement of defects 206 may be configured to provide a predefined fracture structure 208 such that the surface area 204f breaks into pieces 204p, whereas the pieces 204p have smooth edges or a smooth fractured surface (the sidewalls of the pieces 204p), as in Fig. 8 shown.

[0065] According to various embodiments, the surface region 204f, or in other words, the ultrathin wafer 202t, may be decomposed by forming the arrangement of defects 206 in the carrier 202 before thinning the carrier 202 and then thinning the carrier 202 to a target thickness below 50 µm, thus providing the ultrathin wafer 202t. The arrangement of defects 206 may cause mechanical stress and / or deformation in the carrier 202, such that the crack structure is formed through the surface region 204f.

[0066] According to various embodiments, the carrier 202 may be processed as follows: mounting the carrier 202 with a front side to a glass carrier, grinding the carrier 202 to a first thickness, e.g., in the range of about 70 µm to about 300 µm, then forming the defects 206 via stealth dicing, e.g., using two or more scans, and grinding the carrier 202 to a target thickness, e.g., below about 50 µm.

[0067] According to various embodiments, in case the carrier 202 includes an epitaxial layer as the surface region 204f, the target thickness may be equal to the thickness of the epitaxial layer.

[0068] According to various embodiments, grinding the carrier 202 to the target thickness may completely eliminate stealth dicing damage.

[0069] According to various embodiments, stealth laser dicing may be performed from the backside 202b of the carrier 202 to cause trim cracks through the carrier 202, including the surface region 204f. The surface region 204f may include or be a highly doped epitaxial layer. The highly doped epitaxial layer may not allow penetration of the laser beam from the front side of the carrier 202 due to infrared light absorption.

[0070] The separated dies (i.e., the surface region portions 204p) can be formed on the glass carrier, and the sidewalls may not be damaged even at a die thickness below about 50 µm. The carrier 202 can be mounted to the auxiliary carrier 702 (e.g., a glass carrier) via an adhesive or mounting tape.

[0071] According to various embodiments, the thinned carrier 202t or the surface region 204f mounted on the auxiliary carrier 702 may be subjected to backside processing after the carrier 202 is thinned to the target thickness. Therefore, a flat surface 204b is provided for backside processing. The backside processing may include metal deposition and a lithographic process for patterning the deposited metal and the like. The separation distance (e.g., the cracks of the crack structure 208) 111g between the dies 204p may be very small (e.g., in the nanometer range), so that the backside processing processes (e.g., wet etching, plasma etching, lithography, sputter deposition, etc.) may not be affected (or negligibly affected) by the small cracks.

[0072] To separate the dies 204p from each other, as in Fig.8, the thinned carrier 202t (or in other words, the surface region 204f) may be mounted on a source tape 710 (e.g., the tape may be laminated to the backside metallization 310, 310p of the thinned carrier 202t). The source tape 710 may be fixed to the outer frame 714. The auxiliary carrier 702 (e.g., the glass carrier) may be detached from the front side (e.g., via ashing of the adhesive through the glass carrier via a laser beam). In an expansion process, a gap is generated between the dies 204p, and the inner frame 712 may be fixed to the source tape 710. Thereafter, the source tape 710 may be cured via ultraviolet light, and the source tape 710 with the attached dies 204p may be ready for shipping and receiving.

[0073] According to various embodiments, the dies 204 formed with the process flow described herein may have high fracture toughness due to the removal of the laser damage 206. The process flow described herein may be compatible with backside metal deposition and backside metal patterning. The process flow described herein may provide a topological step-free backside patterning process. The process flow described herein may easily prevent metal deposition on the die sidewalls during backside processing. The process flow described herein may not cause edge cracks to propagate into the wafer (or in other words, into the carrier). The process flow described herein may provide ultra-thin scribe lines, for example, with a width of less than about 20 µm.

[0074] According to various embodiments, the dies 204p may include any suitable structure for a desired application. The dies 204p may be configured as ultra-thin MOSFETs, e.g., with a copper backside metal. The dies 204p may be configured as an RF-ID device for RF-ID applications, tagging, etc. The identification chips may be laminated into documents, papers, messages, etc. (e.g., without backside metallization). The dies 204p may be configured as ultra-thin IGBTs, e.g., with a copper backside metal.

[0075] According to various embodiments, in case the surface region 204f of the carrier 202 is not highly doped, or in other words, sufficiently transparent to infrared light, a similar process flow may be realized by stealth dicing from the front side (e.g., down to 150 µm) before the carrier 202 is mounted on a subcarrier 710. In this case, only a grinding process may be used for removing the laser damage.

[0076] Various examples are provided below with reference to the figures described above.

[0077] Example 1 is a method 100 for processing a carrier 202, the method including: forming an array of defects 206 in the carrier 202, wherein a surface region 204f of the carrier 202 is disposed over the array of defects 206 at a first surface 202f of the carrier 202, wherein the array of defects 206 is configured to generate a crack structure 208 extending from the array of defects 206 into the surface region 204f; partially removing the carrier 202 to remove the array of defects 206; and (e.g., thereafter) separating the surface region 204f of the carrier 202 into a plurality of surface region sections 204p along the crack structure 208. The surface region 204f of the carrier 202 (after partially removing the carrier 202 to remove the array of defects 206) may be considered as a thin or ultra-thin carrier 202t, e.g.,with a thickness less than the carrier 202 before the array of defects 206 is removed, e.g., less than about 50 µm. The thin or ultra-thin carrier 202t includes the plurality of surface region portions 204p, wherein the cracks of the crack structure 208 are arranged between respective adjacent surface region portions 204p. In case the carrier 202 is a wafer, the surface region 204f of the carrier 202 (after partially removing the carrier 202 to remove the array of defects 206) may be considered a thin or ultra-thin wafer 202t, e.g., with a thickness less than the carrier 202 before the array of defects 206 is removed, e.g., less than about 50 µm. In this case, the surface region portions 204p may typically be considered chips or dies.Illustratively, the method 100 may be considered a separation process (also referred to as a dicing process) for separating the surface region portions 204p from each other (or in other words, singulating the surface region portions 204p or for decomposing the surface region 204f into the surface region portions 204p).

[0078] In Example 2, the method of Example 1 may optionally include that the carrier 202 contains or consists of semiconductor material.

[0079] In Example 3, the method of Example 1 or 2 may optionally include that the surface region 204f contains or consists of semiconductor material.

[0080] In Example 4, the method of Example 3 may optionally include that the surface region 204f includes or consists of an epitaxial layer of semiconductor material.

[0081] In Example 5, the method of Example 3 or 4 may optionally include the semiconductor material of the surface region 204f having a dopant concentration above 10 16 cm -3 (dopant atoms per cubic centimeter).

[0082] In Example 6, the method of any one of Examples 2 to 5 may optionally include the semiconductor material comprising or consisting of silicon.

[0083] In Example 7, the method of any of Examples 1 to 6 may optionally include forming an array of defects 206 comprising generating a plurality of defects 206d in the carrier 202 via a focused laser beam 502b. The plurality of defects 206d may be generated via stealth dicing.

[0084] In Example 8, the method of any of Examples 1 to 7 may optionally include forming an array of defects 206 comprising generating a plurality of defects 206d in a first array level 505a and generating a plurality of defects in a second array level 505b different from the first array level 505a. The plurality of defects 206d may be generated via stealth dicing.

[0085] In Example 9, the method of Example 8 can optionally include a first distance between the first arrangement level 505a and the first surface 202f of the carrier 202 being smaller than a second distance between the second arrangement level 505b and the first surface 202f of the carrier 202, and the plurality of defects 206d being formed in the second arrangement level 505b after forming the plurality of defects 206d in the first arrangement level 505a.

[0086] In Example 10, the method of any of Examples 1 to 9 may optionally include each defect 206d of the array of defects 206 comprising amorphized material (e.g., amorphous silicon) of the carrier 202, surrounded by crystalline material (e.g., crystalline silicon) of the carrier 202. According to various embodiments, the carrier 202 may be a single-crystalline carrier, such that the array of defects 206 comprises amorphized material (e.g., amorphous silicon) of the carrier 202, surrounded by single-crystalline material (e.g., single-crystalline silicon) of the carrier 202.

[0087] In Example 11, the method of any of Examples 1 to 10 may optionally include the arrangement of defects 206 having a predefined pattern defining a plurality of separation lines 111, 113 for separating the surface region 204f of the carrier 202 into the plurality of surface region sections 204p. The separation lines 111, 113 may also be referred to as scribe lines.

[0088] In Example 12, the method of any of Examples 1 to 11 can optionally include that partially removing the carrier 202 includes exposing a second surface 204b of the surface region 204f to the first surface 202f.

[0089] In Example 13, the method of Example 12 (e.g., prior to separating the surface region 204f into a plurality of surface region portions 204p) further includes forming a metallization structure 310, 310p on the exposed second surface 204b of the surface region 204f.

[0090] In Example 14, the method of Example 13 may optionally include forming a metallization structure 310, 310p including forming at least one metallization layer 310 and patterning the at least one metallization layer 310p according to the crack structure 208.

[0091] In Example 15, the method of Example 14 may optionally include wherein patterning the metallization layer 310p according to the crack structure 208 comprises partially removing the metallization layer 310 to expose one or more surface portions 402b of the second surface 204b of the surface region 204f at the crack structure 208.

[0092] In Example 16, the method of any of Examples 1 to 15 may optionally further include adhering the carrier 202 to an auxiliary carrier 702, wherein the surface region 204f of the carrier 202 faces the auxiliary carrier 710 and wherein a backside 202b of the carrier 202 is exposed.

[0093] In Example 17, the method of Example 16 can optionally include wherein partially removing the carrier 202 includes thinning the carrier 202 from the backside 202b.

[0094] In Example 18, the method of Example 17 may optionally include thinning the carrier 202 including grinding the carrier 202. Grinding the carrier 202 may be performed via polishing, e.g., chemical mechanical polishing or any other suitable grinding process. The carrier 202 may be thinned from the backside 202b of the carrier 202. According to various embodiments, the front side 202f of the carrier 202 and / or the surface region 204f may be readily processed, e.g., including one or more electronic structures.

[0095] In Example 19, the method of Example 17 or 18 can optionally include wherein thinning the carrier 202 includes reducing a thickness of the carrier 202 to below 50 µm.

[0096] In Example 20, the method of any of Examples 1 to 19 may optionally further include, prior to forming an array of defects 206 in the carrier 202, thinning the carrier to a thickness of less than 300 µm.

[0097] In Example 21, the method of any of Examples 1 to 20 can optionally include wherein separating the surface region 204f of the carrier comprises attaching the surface region 204f to a source tape 710 and expanding the source tape 710 to laterally separate the plurality of surface region portions 204p from each other.

[0098] Example 22 is a method 100 for processing a carrier 202, the method including: forming an array of defects 206 in a support region 204b of the carrier 202, wherein the array of defects 206 is configured to generate a crack structure 208 extending into a surface region 204f of the carrier 202 disposed on a front side 202f of the carrier 202 above the support region 204b, wherein the crack structure 208 defines a plurality of separation lines 111, 113 for separating the surface region 204f of the carrier 202 into a plurality of surface region portions 204p; thinning the carrier 202 from a back side 202b of the carrier 202 opposite the front side 202f to remove the array of defects 206; and separating the plurality of surface region sections 204p of the surface region 204f from each other along the separation lines 111, 113.

[0099] Example 23 is a carrier 202 including: a support region 204b and a surface region 204f disposed above the support region 204b, the surface region 204f providing a top surface 202f of the carrier 202; an array of defects 206 disposed in the support region 204b of the carrier 202; and a crack structure 208 extending from the array of defects 206 into the surface region 204f.

[0100] In Example 24, the carrier 202 of Example 23 can optionally include the surface region 204f having a thickness of less than 50 µm.

[0101] In Example 25, the carrier 202 of Example 23 or 24 may optionally include that the surface region 204f contains doped semiconductor material. The semiconductor material may contain or be silicon.

[0102] In Example 26, the carrier 202 of any of Examples 23 to 25 can optionally include that the arrangement of defects 206 comprises a plurality of defects 206d arranged in a first arrangement level 505a and in a second arrangement level 505b different from the first arrangement level 505a.

[0103] In Example 27, the carrier 202 of Example 26 can optionally include a first distance between the first arrangement level 505a and the surface 202f of the carrier 202 being smaller than a second distance between the second arrangement level 505b and the surface 202f of the carrier 202.

[0104] In Example 28, the carrier 202 of Example 26 or 27 may optionally include that the defects 206d of the array of defects 206 are arranged in a predefined pattern defining a plurality of separation lines 111, 113 for separating the surface region 204f of the carrier 202 into the plurality of surface region portions 204p.

[0105] In Example 29, the carrier 202 of any one of Examples 23 to 28 can optionally include each defect 206d of the array of defects 206 comprising amorphous material of the body region 204b of the carrier 202 surrounded by a single-crystalline material of the body region 204b of the carrier 202.

[0106] Example 30 is a carrier assembly including a subcarrier 702 and a carrier 202 of any one of Examples 23 to 29 mounted on the subcarrier 702.

[0107] Example 31 is a method 100 for processing a carrier 202, the method including, among other things: forming an array of defects 206 in a support layer 204b of the carrier 202, wherein a surface layer 204f of the carrier 202 is disposed over the support layer 204b, the array of defects 206 configured to generate a crack structure 208 extending from the support layer 204b into the surface layer 204f of the carrier 202; removing the support layer 204b to remove the array of defects 206 and expose the surface layer 204f; and separating the surface layer 204f of the carrier 202 into a plurality of surface layer portions 204p along the crack structure 208.

[0108] Example 32 is a method 100 for processing a carrier 202, the method including: forming an array of defects 206 in a support region 204b of the carrier 202, wherein a surface region 204f of the carrier 202 is disposed over the support region 204b, the array of defects 206 configured to generate a crack structure 208 extending from the support region 204b into the surface region 204a of the carrier 202; removing the support region 204b to remove the array of defects 206; and separating the surface region 204f of the carrier 202 into a plurality of surface region portions 204p along the crack structure 208.

[0109] Example 33 is a carrier 202t including: a crack structure 208 extending from a front side 202f of the carrier 202t through the carrier 202t to a back side 204b of the carrier 202t, wherein the crack structure 208 separates a plurality of sections 204p of the carrier 202t from each other; wherein the carrier 202t has a thickness of less than 50 µm and includes a metallization structure 310, 310p arranged on the back side 204b of the carrier 202t.

[0110] Example 34 is a carrier arrangement including: a source tape 710; a carrier 202t arranged on the source tape 710, wherein the carrier 202t has a thickness below 50 µm, wherein the carrier 202t includes a crack structure 208 extending from a front side 202f of the carrier 202t through the carrier 202t to a back side 204b of the carrier 202t, wherein the crack structure 208 separates a plurality of carrier sections 204p of the carrier 202t from one another; and wherein the carrier 202t comprises a metallization structure 310, 310p arranged on the back side 204b of the carrier 202t.

Claims

[1] A method (100) for processing a carrier (202), the method comprising: Generating a crack structure (208) by forming an array of defects (206) in the carrier (202), wherein a surface region (204f) of the carrier (202) is arranged above the array of defects (206) on a first surface (202f) of the carrier (202), and wherein the crack structure (208) extends from the array of defects (206) into the surface region (204f) and has a plurality of cracks with a width of less than 500 nm; after generating the crack structure (208), partially removing the carrier (202) and thereby removing the arrangement of defects (206); subsequently, after partially removing the carrier (202), forming a metallization structure (310, 310p) on an exposed second surface (204b) of the surface region (204f), and subsequently Separating the surface region (204f) of the carrier (202) into a plurality of surface region sections (204p) along the crack structure (208). [2] The method of claim 1, wherein the surface region (204f) comprises semiconductor material. [3] The method of claim 2, wherein the semiconductor material having a dopant concentration greater than 10 16 cm -3 is endowed. [4] The method of any one of claims 1 to 3, wherein forming an array of defects (206) comprises generating a plurality of defects (206d) in the carrier (202) via a focused laser beam (502b). [5] The method of any one of claims 1 to 4, wherein forming an array of defects (206) comprises generating a plurality of defects (206d) in a first array level (505a) and generating a plurality of defects (206d) in a second array level (505b) different from the first array level (505a). [6] The method of claim 5, wherein a first distance between the first arrangement level (505a) and the first surface (202f) of the carrier (202) is smaller than a second distance between the second arrangement level (505b) and the first surface (202f) of the carrier (202), wherein the plurality of defects (206d) are formed in the second arrangement level (505b) after forming the plurality of defects (206d) in the first arrangement level (505a). [7] The method of any one of claims 1 to 6, wherein each defect (206d) of the array of defects (206) comprises amorphized material of the carrier (202) surrounded by crystalline material of the carrier (202). [8] The method of any one of claims 1 to 7, wherein partially removing the carrier (202) comprises exposing a second surface (204b) of the surface region (204f) to the first surface (202f). [9] The method of claim 1, wherein forming a metallization structure (310, 310p) comprises forming at least one metallization layer (310) and patterning the at least one metallization layer (310p) according to the crack structure (208). [10] Method according to one of claims 1 to 9, further comprising: Bonding the carrier (202) to an auxiliary carrier (702), wherein the surface region (204f) of the carrier (202) faces the auxiliary carrier (702) and wherein a back side (202b) of the carrier (202) is exposed. [11] The method of claim 10, wherein partially removing the carrier (202) comprises thinning the carrier (202) from the back side (202b). [12] The method of claim 11, wherein thinning the carrier (202) comprises reducing a thickness of the carrier (202) to below 50 µm. [13] Method according to one of claims 1 to 12, further comprising: before forming an array of defects (206) in the carrier (202), thinning the carrier (202) to a thickness below 300 µm. [14] The method of any one of claims 1 to 13, wherein separating the surface region (204f) of the carrier (202) comprises attaching the surface region (204f) to a source tape (710) and expanding the source tape (710) to separate the plurality of surface region portions (204p) from one another. [15] Carrier arrangement, comprising: a source tape (710); a thinned carrier (202t) arranged on the source belt (710), wherein the thinned carrier (202t) has a thickness of less than 50 µm, wherein the thinned carrier (202t) has a crack structure (208) extending from a front side (202f) of the thinned carrier (202t) through the thinned carrier (202t) to a back side (204b) of the thinned carrier (202t), wherein the crack structure (208) has a plurality of cracks from the front side (202f) to the back side (204b) of the thinned carrier (202t) with a width of less than 500 nm, wherein the crack structure (208) separates a plurality of sections (204p) of the thinned carrier (202t) from one another; and wherein the thinned carrier (202t) has a metallization structure (310, 310p) arranged on the back side (204b) of the thinned carrier (202t).

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