Protection against gate contact bridging through reduced contact dimensions in FinFET SRAM

Abstract

Semiconductor device, comprising: a first elongated gate structure (121) extending in a first direction, wherein the first elongated gate structure (121) has a first end section (121A), a second end section (121B) and a third section (121C) arranged between the first end section (121A) and the second end section (121B); a second elongated gate structure (122) extending in the first direction and separated from the first elongated gate structure (121) by a gap (201); a first conductive contact (132) extending in the first direction, wherein the first conductive contact (132) is arranged adjacent to the third section (121C) of the first elongated gate structure (121), wherein the first conductive contact (132) has a first dimension (160) measured in the first direction and a second dimension (161) measured in a second direction perpendicular to the first direction; a second conductive contact (133) extending in the first direction, wherein the second conductive contact (133) is located adjacent to the first end section (121A) of the first elongated gate structure (121) and a section (133A) of the second conductive contact (133) overlaps with the gap (201) in the first direction, wherein the second conductive contact (133) has a third dimension (170) measured in the first direction and a fourth dimension (171) measured in the second direction, wherein the first dimension (160) is smaller than the third dimension (170) and wherein the second dimension (161) is larger than the fourth dimension (171); a first fin structure (113) that intersects the first elongated gate structure (121) and the first conductive contact (132) in a top view; and a second fin structure (114) that intersects the first elongated gate structure (121) and the second conductive contact (133) in a top view, wherein the first fin structure (113) and the second fin structure (114) each extend in the second direction and wherein the first fin structure (113) is separated from the second fin structure (114) in the first direction, wherein the first conductive contact (132) comprises a Vcc contact or a BL contact of a static random access memory (SRAM) cell and the second conductive contact (133) comprises a Vss contact or a node contact of the SRAM cell.

Description

BACKGROUND

[0001] In integrated circuit technology far below the micrometer scale, embedded static random-access memory (SRAM) has become a popular storage unit for high-speed data transmission, image processing, and system-on-a-chip (SoC) applications. The amount of embedded SRAM in microprocessors and SoCs increases to meet the performance demands of each new technology generation. As silicon technology continues to scale from one generation to the next, changes in the intrinsic threshold voltage (Vt) of planar bulk transistors reduce the static signal-to-noise ratio (SNM) of complementary metal-oxide-semiconductor (CMOS) SRAM cells. This reduction in SNM, caused by increasingly smaller transistor geometries, is undesirable. SNM is further reduced when Vcc is scaled down to a lower voltage.

[0002] To address SRAM challenges and increase cell miniaturization possibilities, fin field-effect transistor (FinFET) devices are frequently employed in certain applications. A FinFET offers both speed and device stability. A FinFET features a channel (referred to as the fin channel) associated with the top surface and opposing sidewalls. Benefits can be derived from the additional sidewall width (ion power) as well as improved subthreshold leakage control. Therefore, FinFETs should exhibit advantages in gate length scaling and intrinsic voltage fluctuations. However, existing FinFET-RAM devices still have shortcomings, such as those related to undesirable fluctuations in gate end positions, which can compromise gate / contact isolation and adversely affect FinFET-SRAM performance and / or reliability.

[0003] SRAM devices with FinFETs are known, for example, from US 2011 / 0 317 477 A1 and US 2014 / 0 151 812 A1. US 8,247,846 B2 describes elongated interconnect structures between elements in different layers of a semiconductor chip.

[0004] Although the existing FinFET SRAM devices were generally adequate for their intended purposes, they were not entirely satisfactory in every aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention provides a semiconductor device with the features of claim 1, an SRAM cell with the features of claim 9, and a method for revising a layout design for a circuit with the features of claim 17. Exemplary embodiments are specified in the dependent claims.

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with common practice in the industry, various elements are not drawn to scale. In fact, the dimensions of the various elements may be enlarged or reduced as desired for clarity of discussion. It is also emphasized that the accompanying drawings show only typical embodiments of this invention and are therefore not to be considered limiting, since the invention can be applied equally to other embodiments. Fig. Figure 1 is a perspective view of an example FinFET device. Fig. Figure 2 shows a circuit diagram for a 1-bit SRAM cell according to an embodiment of the present disclosure. Fig. Figure 3 shows a top view of the 1-bit SRAM cell according to an embodiment of the present disclosure. Fig. Figure 4 shows an example of an actually manufactured conductive contact of the SRAM cell according to an embodiment of the present disclosure. Fig. Figure 5 shows an original 1-bit SRAM cell layout design and a revised 1-bit SRAM cell layout design based on the conventional 1-bit SRAM cell layout design according to an embodiment of the present disclosure. Fig. Figure 6 is a flowchart showing a method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0008] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or device to other element(s) or device(s), as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here may be interpreted accordingly.

[0009] The present disclosure relates, without limitation, to a fin-like field-effect transistor (FinFET) device. The FinFET device can, for example, be a complementary metal-oxide-semiconductor (CMOS) device, such as a p-metal-oxide-semiconductor (PMOS) FinFET device and an n-metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure continues with one or more FinFET examples to describe various embodiments of the present disclosure. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.

[0010] The use of FinFET devices is becoming increasingly popular in the semiconductor industry. Referring to Fig. Figure 1 shows a perspective view of an exemplary FinFET device 50. The FinFET device 50 is a non-planar multi-gate transistor fabricated on a substrate (such as a bulk substrate). A thin silicon-containing “fin-like” structure (hereinafter referred to as the “fin”) forms the body of the FinFET device 50. The fin extends along a Fig. 1. X-direction shown. The fin has a fin width W. fin , measured along a Y-direction that is perpendicular to the X-direction. A gate 60 of the FinFET device 50 encloses this fin, for example around the upper surface and the opposite sidewall surfaces of the fin. Thus, a section of the gate 60 is arranged above the fin in a Z-direction that is perpendicular to both the X-direction and the Y-direction.

[0011] L Gdenotes a length (or width, depending on the perspective) of the gate 60, measured in the X direction. The gate 60 can comprise a gate electrode component 60A and a gate dielectric component 60B. The gate dielectric 60B has a thickness t ox , measured in the Y direction. A section of the gate 60 is located above a dielectric insulation structure, such as a shallow trench insulation (STI). A source 70 and a drain 80 of the FinFET device 50 are formed in extensions of the fin on opposite sides of the gate 60. A section of the fin enclosed by the gate 60 serves as a channel for the FinFET device 50. The effective channel length of the FinFET device 50 is determined by the dimensions of the fin.

[0012] FinFET devices offer several advantages over conventional metal-oxide-semiconductor field-effect transistor (MOSFET) devices (also known as planar transistor devices). These advantages can include improved chip area efficiency, enhanced carrier mobility, and a manufacturing process compatible with that of planar devices. Therefore, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for part or all of the IC chip.

[0013] However, conventional FinFET devices can still exhibit shortcomings. For example, further miniaturization of semiconductor feature sizes can alter the gate profile—particularly the gate end sections—and cause unintended bridging between the gate and nearby conductive contacts. In SRAM devices, this bridging can manifest as bridges between the gate and Vss or node contacts. According to various aspects of this disclosure, the dimensions of the Vss and node contacts are reduced to mitigate the bridging risk, as described in more detail below.

[0014] Fig. Figure 2 shows a circuit diagram for a single-port SRAM cell (e.g., a 1-bit SRAM cell) 90. The single-port SRAM cell 90 comprises pull-up transistors PU1, PU2; pull-down transistors PD1, PD2; and pass-gate transistors PG1, PG2. As shown in the circuit diagram, transistors PU1 and PU2 are p-type transistors, like the p-type FinFETs described above, and transistors PG1, PG2, PD1, and PD2 are the n-type FinFETs described above.

[0015] The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled to each other and to the drains of transistors PU1 and PD1 to form a first memory node SN1, and the gates of transistors PU1 and PD1 are coupled to each other and to the drains of transistors PU2 and PD2 to form a complementary first memory node SNB1. The sources of the pull-up transistors PU1 and PU2 are coupled to the supply voltage Vcc (also known as Vdd) and the sources of the pull-down transistors PD1 and PD2 are coupled to a voltage Vss, which in some embodiments may be an electrical ground.

[0016] The first memory node SN1 of the first data latch is connected to the bit line BL via the pass-gate transistor PG1, and the complementary first memory node SNB1 is coupled to the complementary bit line BLB via the pass-gate transistor PG2. The first memory node SN1 and the complementary first memory node SNB1 are complementary nodes that often operate at opposite logic levels (logic high or logic low). The gates of the pass-gate transistors PG1 and PG2 are coupled to a word line WL.

[0017] Fig. Figure 3 shows a fragmentary top view of SRAM cells according to an embodiment of the present disclosure. The SRAM cells comprise a plurality of cells, such as a 1-bit SRAM cell 100 (as an example), the circuit diagram of which is shown in Figure 3. Fig. 2 is shown as circuit diagram 90. The elements of the SRAM cell 100 are shown in the top view of Fig. 3 shown in a rectangle with dashed borders.

[0018] The SRAM cells comprise a plurality of fin lines 110-115 (also referred to as the active area or OD). As in Fig. As shown in Figure 3, four fin lines 111-114 are arranged within (or as part of) the SRAM cell 100 and each extends in the X direction (also in Fig. (1 shown). The fin lines 111-114 comprise a semiconductor material, for example silicon or silicon-germanium. In some embodiments, fin lines 111 and 114 are fin lines for the pull-down transistors and fin lines 112 and 113 are fin lines for the pull-up transistors.

[0019] The SRAM cells also include a plurality of elongated gate structures (also called gate lines) 120-127, each extending in the Y direction (also in Fig. 1 shown). The gate structures 120-127 each enclose one or more of the fin lines 110-115 in the above with reference to Fig. 1. Two continuous gate structures 121 and 124 are arranged entirely within the SRAM cell 100. The gate structures 120 and 125 also each extend partially within the SRAM cell 100. The gate structures 120, 121, 124, and 125 and the fin lines 111-114 together form at least six transistor devices, for example, the transistor devices PD1, PD2, PG1, PG2, PU1, and PU2 of the above with reference to Fig. 2 described SRAM cells.

[0020] A majority of conductive contacts 130-141 are also shown in the top view of Fig. Figure 3 shows that within (at least partially within) the SRAM cell 100 are arranged a bit line (BL) contact 131, a Vcc (or Vdd) contact 132, a Vss (or ground) contact 133, a node contact 135, a node contact 136, a Vss contact 138, a Vcc contact 139, and a BL contact 140. Fig. As shown in Figure 3, the BL contact 131 has a dimension 150 measured in the Y direction and a dimension 151 measured in the X direction, the Vcc contact 132 has a dimension 160 measured in the Y direction and a dimension 161 measured in the X direction, the Vss contact 133 has a dimension 170 measured in the Y direction and a dimension 171 measured in the X direction, the node contact 135 has a dimension 180 measured in the Y direction and a dimension 181 measured in the X direction, and the node contact 136 has a dimension 190 measured in the Y direction and a dimension 191 measured in the X direction.

[0021] In some embodiments, the dimension 150 of the BL contact 131 is smaller than approximately 100 nanometers (nm). The dimension 150 is also smaller than the dimension 170 of the Vss contact 133 and smaller than the dimension 180 of the node contact 135. In some embodiments, the ratio between the dimension 150 and the dimension 170 is less than approximately 0.5, and the ratio between the dimension 150 and the dimension 180 is less than approximately 0.7. These ratio ranges are optimized for SRAM cell design and performance.

[0022] In some embodiments, the dimension 160 of the Vcc contact 132 is smaller than approximately 40 nanometers (nm). The dimension 160 is also smaller than the dimension 170 of the Vss contact 133 and smaller than the dimension 180 of the node contact 135. In some embodiments, the ratio between the dimension 160 and the dimension 170 is less than approximately 0.4, and the ratio between the dimension 160 and the dimension 180 is less than approximately 0.6. These ratio ranges are optimized for SRAM cell design and performance.

[0023] In some embodiments, the dimension 151 of the BL contact 131 is larger than the dimension 171 of the Vss contact 133 and larger than the dimension 181 of the node contact 135. In some embodiments, the dimension 151 is at least approximately 0.5 nm larger than the dimension 171 and the dimension 151 is at least approximately 0.5 nm larger than the dimension 181. In some embodiments, the dimension 161 of the Vcc contact 132 is larger than the dimension 171 of the Vss contact 133 and larger than the dimension 181 of the node contact 135. In some embodiments, the dimension 161 is at least approximately 0.5 nm larger than the dimension 171 and the dimension 161 is at least approximately 0.5 nm larger than the dimension 181. The dimension 171 of the Vss contact Dimension 133 can also be smaller than dimension 181 of the node contact 135. In some embodiments, dimension 171 is at least approximately 0.1 nm smaller than dimension 181.As explained in more detail below, these dimensional ranges are specifically configured to reduce the risk of unwanted gate contact bridging.

[0024] As in Fig. As shown in Figure 3, gate lines 120, 121, and 122 are essentially aligned in the X-direction, and gate lines 123, 124, and 125 are also essentially aligned in the X-direction. Gate structures 120 and 121 are separated by a gap 200 in the Y-direction, gate structures 121 and 122 are separated by a gap 201 in the Y-direction, and gate structures 124 and 125 are separated by a gap 202 in the Y-direction.The gate structure 121 is separated from the Vcc contact 132 by a gap 210 in the X direction, the gate structure 121 is separated from the Vss contact 133 by a gap 220 in the X direction, the gate structure 120 is separated from the BL contact 131 by a gap 230 in the X direction, the gate structure 121 is separated from the node contact 135 by a gap 240 in the X direction, the gate structure 124 is separated from the node contact 135 by a gap 250 in the X direction, the gate structure 124 is separated from the node contact 136 by a gap 260 in the X direction, and the gate structure 121 is separated from the node contact 136 by a gap 270 in the X direction.

[0025] As described above, one aspect of the present disclosure involves reducing the probability of unwanted contact-gate bridging. Specifically, due to process control limitations, the dimensions of the gate structures 120-125 can vary. For example, the width (measured in the X-direction) of the gate structures 120-125 can vary from device to device. This gate width variation may be even greater or more significant at an end section of the gate structure. Using the gate structure 121 as an example, it has two opposing end sections 121A and 121B, which are connected by a non-end section 121C. In some embodiments, the end section 121A or 121B may each have a length (measured in the Y-direction, extending from an endpoint and inward to a center of the gate structure 121) that is approximately 0% to 2% of the total length of the gate structure 121.In other embodiments, the amount can range from approximately 0% to 10%. Due to process control limitations, the width deviations (in the X-direction) at the end sections 121A or 121B of the gate structure 121 can be more significant.

[0026] As in Fig. As shown in Figure 3, the end section 121A of the gate structure 121 is adjacent to a non-end section 133A of the Vss contact 133, and the end section 121B is adjacent to a non-end section 135A of the node contact 135. In some embodiments, the segment 133A can refer to any section of the Vss contact that is less than 40% of the total length (e.g., dimension 170) of the Vss contact 133 from a center point of the Vss contact 133 (on either side of the center point along the Y-direction). In some embodiments, the segment 135A can refer to any section of the node contact that is less than 40% of the total length (e.g., length 180) of the node contact 135 from a center point of the node contact 135 (on either side of the center point along the Y-direction). Segment 135A can overlap with gap 200 in the Y direction (without touching it, however).In other words, segment 135A is located adjacent to or near the end sections of gate structures 120-121. Put another way, segment 135A is located adjacent to gap 200.

[0027] As the width of the end sections 121A-121B of the gate structure 121 increases due to process control limits, the gate contact bridging risks increase, and these bridging risks are higher at locations in the SRAM cell where an end section of a gate structure is located close to or adjacent to a non-end section of a conductive contact. In other words, bridging is more likely in areas where gaps between adjacent gate structures overlap with a non-end section of a conductive contact, for example where gap 200 overlaps with a non-end section of node contact 135 in the Y direction (e.g., adjacent to it but not touching it), or where gap 201 overlaps with a non-end section of Vss contact 133 in the Y direction (e.g., adjacent to it but not touching it), or where gap 202 overlaps with a non-end section of node contact 136 in the Y direction (e.g.,adjacent to it, but without touching it) or where the gap 203 overlaps with a non-end section of the Vss contact 138 in the Y direction (e.g. adjacent to it, but without touching it).

[0028] In particular, there may be a bridging risk between the end section 121A and the middle segment 133A of the Vss contact 133, and a bridging risk between the end section 121B and the middle segment 135A of the node contact 135. Similarly, an end section of the gate structure 120 may potentially bridge with the node contact 135, an end section of the gate structure 122 may potentially bridge with the Vss contact 133, an end section of the gate structure 124 may potentially bridge with the Vss contact 138, and end sections of the gate structures 124 and 125 may potentially bridge with the node contact 136.

[0029] Gate contact bridging is undesirable because it can impair the performance and reliability of SRAM cells or even cause them to fail. Unfortunately, conventional SRAM cell designs and manufacturing have not adequately addressed this problem or found a satisfactory solution. However, according to the various aspects of this disclosure, the Vss contacts 133 / 138 and the node contacts 135 / 136 (where bridging is a risk) are reduced in size in the X direction to decrease the probability of bridging with the adjacent gate structure(s).

[0030] For example, the dimension 171 of the Vss contact 133 is reduced compared to the dimension 151 of the BL contact 131 or the dimension 161 of the Vcc contact 132. In some embodiments, the dimension 151 and the dimension 161 are each at least 0.5 nm larger than the dimension 171. As a result of the reduced dimension 171 of the Vss contact 133, the gap 220 between the Vss contact 133 and the gate structure 121 is also larger than the gap 210 between the Vcc contact 132 and the gate structure 121 (or larger than the gap 230 between the BL contact 131 and the gate structure 120). In some embodiments, the gap 220 is at least approximately 0.2 nm larger than the gap 210 or the gap 230.

[0031] The smaller dimension 171 (or conversely, the larger gap 220) allows for greater tolerance of the gate structure 121 to profile variations. Even if the end section 121A of the gate structure is enlarged due to imperfections in the process control, it still need not come into physical contact with the Vss contact 133, since the boundary of the reduced Vss contact 133 is ultimately "further away" from the end section 121A of the gate structure 121. Likewise, the reduced Vss contact 133 also has reduced bridging risks with the gate structure 122. It is understood that the Vss contact 138 is also reduced in a similar way to the Vss contact 133 and, as such, has a lower bridging risk with the gate structures 123 / 124.

[0032] Considering the node contacts 135 / 136, the dimensions 181 and 191 of their node contacts 135 and 136, respectively, are reduced compared to the dimension 151 of the BL contact 131 or the dimension 161 of the Vcc contact 132. In some embodiments, the dimension 151 and the dimension 161 are each at least 0.5 nm larger than the dimensions 181 or 191. As a result of the reduced dimension 181 of the node contact 135, the gap 240 between the Vss contact 135 and the gate structure 121 is also larger than the gap 210 between the Vcc contact 132 and the gate structure 121 (or larger than the gap 230 between the BL contact 131 and the gate structure 120). In some embodiments, the gap 240 is at least approximately 0.1 nm larger than the gap 210 or the gap 230.

[0033] With respect to the node contact 136, as a result of the reduced dimension 191 of the node contact 136, the gap 260 between the node contact 136 and the gate structure 124 is also larger than the gap 210 between the Vcc contact 132 and the gate structure 121 (or larger than the gap 230 between the BL contact 131 and the gate structure 120). In some embodiments, the gap 260 is at least approximately 0.1 nm larger than the gap 210 or the gap 230.

[0034] The smaller dimensions 181 and 191 (or conversely, the larger gaps 240 and 260) allow for a higher tolerance of the gate structures 120-121 and 124-125 to profile variations. Even if the end section 121B of the gate structure is enlarged due to imperfections in the process control, it still cannot come into physical contact with the node contact 135, since the boundary of the reduced node contact 135 is effectively "farther away" from the end section 121B of the gate structure 121. Likewise, the reduced node contact 135 also has reduced bridging risks with the gate structure 120. Similarly, the reduced node contact 136 also has reduced bridging risks with the gate structures 124-125 (e.g., their end sections).

[0035] In some embodiments, the node contacts 135-136 are misaligned in the X-direction. In other words, gap 240 is larger than gap 270, and gap 260 is larger than gap 250. This misalignment results from the fact that bridging problems for node contact 135 exist with respect to gate structures 120-121 (i.e., the gate structure end sections located near gaps 240 or 200), while bridging problems for node contact 136 exist with respect to gate structures 124-125 (i.e., the gate structure end sections located near gaps 260 or 220). In other words, while it may be advantageous for node contact 135 to be located further away from gate structures 120-121, it is not so important that node contact 135 is located further away from gate structure 124.As such, node contact 135 can be reduced in size from the "top" (the side facing gap 200), but not from the "bottom" (the side facing gate structure 124). Similarly, while it may be advantageous for node contact 136 to be located further away from gate structures 124-125, it is not so important that node contact 136 be located further away from gate structure 121. As such, node contact 136 can be reduced in size from the "bottom" (the side facing gap 202), but not from the "top" (the side facing gate structure 121). It is understood, however, that this is only one possible embodiment. In other embodiments, node contacts 135-136 can be reduced in size from both the "top" and the "bottom".

[0036] Compared to the node contacts 135-136, the Vss contacts 133 and 138 can be reduced in size from both the "top" and the "bottom" view. This is because the gate structures 126-127 – which resemble the gate structures 121-122 – are located "above" the Vss contact 133 in the top view. Fig. 3. In some embodiments, the SRAM cell located immediately "above" SRAM cell 100 is a "mirrored" version of SRAM cell 100. In other words, the SRAM cell located immediately "above" SRAM cell 100 is identical to SRAM cell 100, except that the components in this SRAM cell are "mirrored" by 180° in the X-direction compared to the components in SRAM cell 100. As such, the Vss contact 133 may also have bridging issues with the gate structures 126-127. Thus, according to the various aspects of the present disclosure, the Vss contact 133 may be separated from the gate structure 126 by a gap similar to the gap 220 (e.g., they are substantially the same size). To minimize the bridging risks between the Vss contact 133 and the gate structures 126-127, the dimension 171 of the Vss contact 133 is reduced from both the "top" and the "bottom" side.In other words, the gap 220 between the Vss contact 133 and the gate structure 126 is enlarged to avoid potential physical contact between the Vss contact 133 and the gate structures 126-127, even if the gate structures 126-127 have larger end sections due to imperfections in the process control. The same applies to the Vss contact 138 with respect to its neighboring gate structures.

[0037] Because the Vss contacts 133 and 138 are reduced in size from both the "top" and the "bottom," while the node contacts 135-136 only need to be reduced from one side (e.g., the "top") (e.g., the "top" for node contact 135 and the "bottom" for node contact 136), the dimension 171 (of the Vss contacts 133 or 138) is smaller than the dimension 181 (of node contact 135) and the dimension 191 (of node contact 136). In some embodiments, the dimension 181 is at least approximately 0.1 nm larger than 171, and the dimension 191 is at least approximately 0.1 nm larger than 171.

[0038] Compared to the Vss contacts 133 / 138 and the node contacts 135 / 136, the BL contacts 131 / 140 and the Vcc contacts 132 / 139 are not as prone or sensitive to gate contact bridging. This is because the BL contacts 131 / 140 and the Vcc contacts 132 / 139 are not adjacent to the end sections of any of the gate structures 120-125 in the SRAM cell 100. For example, no segment of the Vcc contact 132 overlaps with any of the gaps 200 or 201 in the Y direction. The same applies to Vcc contact 139 and BL contacts 131 and 140. As such, BL contacts 131 / 140 and Vcc contacts 132 / 139 have a larger window for gate contact bridging. Therefore, it is not necessary to reduce their dimensions 151 or 161.

[0039] In some embodiments, dimensions 151 or 161 may remain the same as in the original SRAM cell design. In other embodiments, dimensions 151 or 161 may actually be slightly increased compared to the original SRAM cell design. For example, while dimension 151 of the BL contact 131 is M nanometers according to the original SRAM cell design, the present disclosure can reconfigure the design and / or fabrication of the BL contact 131 such that dimension 151 is now M + N nanometers. In some embodiments, N may be in a range from about 0 nm to about 0.5 nm. The increased dimension 151 of the BL contact 131 may improve device performance, for example, by reducing contact resistance (due to the larger size).This can be particularly helpful if the dimension 150 of BL contact 131 is small (since small contacts have a higher contact resistance). For similar reasons, the dimension 161 of Vcc contact 132 can be reconfigured to be larger than the value specified by the original SRAM cell design.

[0040] It goes without saying that, although the elements in Fig. Figure 3 shows rectangles, but the actual manufactured devices do not necessarily have such perfect shapes. For example, the edges of the elements (e.g., the fins, contacts, or gate structures) do not have to be perfectly straight and may therefore exhibit roughness or nonlinearity. An example of this is shown in Figure 3. Fig. Figure 4 shows a top view of an actual manufactured Vss contact 133 according to one embodiment. As shown in Figure 4, Fig. As can be seen in Figure 4, the actually manufactured Vss contact 133 is not a perfect rectangle, but rather has a "T-shape" (or a "bone shape") in top view. This means that not only does the Vss contact have somewhat curved edges, but its middle section 133A is also narrower (in the X direction) than its end sections 133B or 133C.

[0041] In some embodiments, the narrower central section 133A is specifically configured to further reduce bridging problems. Referring to the two Fig. 3-4 The middle section 133A is the section of the Vss contact 133 that is adjacent to the gap 201 defined by the end sections of the gate structures 121-122. In other words, the middle section 133A is the section of the Vss contact 133 that is most at risk of bridging with the gate structures 121-122. Thus, by configuring the profile of the Vss contact 133 such that its middle section tapers inwards, the bridging risks between the Vss contact 133 and the gate structures 121-122 are further minimized. In the Fig. In the embodiment shown in Figure 4, dimension 171 is measured somewhere in the middle section 133A, for example at its narrowest point. However, it is understood that in other embodiments dimension 171 can be measured in the end sections 133B or 133C.

[0042] In some embodiments, the reduction in size of the Vss contacts 133 / 138 and the node contacts 135 / 136 is achieved by revising the original SRAM cell layout design. An example of this approach is shown in Fig. Figure 5 shows an original 1-bit SRAM cell layout design 300 and a revised 1-bit SRAM cell layout design 400. In some embodiments, the original SRAM cell layout design 300 comprises a computer file, such as a GDS (Graphical Database System) file, and the revised SRAM cell layout design 400 comprises a photomask design. For example, IC chip design and / or layout engineers may create the original SRAM cell layout design 300 and send the design to a semiconductor manufacturer, such as a foundry. The semiconductor manufacturer will then design and / or manufacture a photomask on which the original SRAM cell layout design 300 has been revised into the revised SRAM cell layout design 400. It is understood that in some embodiments additional elements such as OPC (optical proximity correction) features can be implemented on the photomask.

[0043] As in Fig. As shown in Figure 5, the original SRAM cell layout design 300 and the revised SRAM cell layout design 400 each comprise fin lines 311-314 and 411-414, respectively, which correspond to fin lines 111-114 of the SRAM cell 100, which are described above with reference to Fig. 3 were described. The original SRAM cell layout design 300 and the revised SRAM cell layout design 400 also include gate structures 320-325 and 420-425, respectively, which correspond to gate structures 120-125 of SRAM cell 100, described above with reference to Fig. 3 described. The original SRAM cell layout design 300 and the revised SRAM cell layout design 400 further include conductive contacts 331-340 and 431-440, respectively, which correspond to the conductive contacts 131-140 of SRAM cell 100 described above with reference to Fig. 3 were described.

[0044] As described above, to minimize gate contact bridging risks, the Vss contacts and node contacts are reduced in size in the X direction. Using the Vss contact as an example, the Vss contact 333 in the original SRAM cell layout design 300 has a dimension of 370, measured in the Y direction, and a dimension of 371, measured in the X direction. As part of the revision of the original SRAM cell layout design 300, the dimension of 371 is reduced to a dimension of 471 for the revised Vss contact 433. In the Fig. In the embodiment shown in Figure 5, the reduction of dimension 371 is carried out on both the "top" and the "bottom" of the Vss contact 333, as indicated by the arrows on the "top" and "bottom" of the Vss contact. In other embodiments, the reduction of dimension 371 can be carried out on one side (i.e., either the "top" or the "bottom"), but not the other. In some embodiments, dimension 371 is at least approximately 0.5 nm larger than dimension 471. At the same time, dimension 370 is kept the same size. In other words, the dimension 470 (measured in the Y direction) of the revised Vss contact 433 is essentially the same as dimension 370. It is understood that the Vss contact 338 of the original SRAM cell layout design 300 has been reduced to the Vss contact 438 of the revised SRAM cell layout design 400.

[0045] Furthermore, node contacts 335-336 are similarly reduced to node contacts 435-436, although node contacts 335-336 do not need to be reduced from both the "top" and the "bottom". For example, as explained in more detail in relation to Fig. As described in section 3, the bridging risk for node contact 335 from the "top side" (located opposite gate structures 320-321) is higher, and therefore node contact 335 only needs to be reduced in size from the "top side" to form the revised node contact 435. Similarly, the bridging risk for node contact 336 from the "bottom side" (located opposite gate structures 324-325) is higher, and therefore node contact 336 only needs to be reduced in size from the "bottom side" to form the revised node contact 436. However, it is understood that in some embodiments, node contacts 335-336 can each be reduced in size from both the "top side" and the "bottom side" to form the revised node contacts 435 and 436, respectively.

[0046] Fig.Figure 6 is a flowchart illustrating a method 900 according to an embodiment of the present disclosure. The method 900 comprises a step 910 in which a layout design for a circuit is received. The circuit comprises: an elongated gate structure extending in a first direction (Y-direction), a first conductive contact extending in the first direction, and a second conductive contact extending in the first direction. An end section of the elongated gate structure is located near the second conductive contact, but not near the first conductive contact.

[0047] Procedure 900 includes a step 920 in which the layout design is revised. The revision involves reducing the size of the second conductive contact in a second direction perpendicular to the first.

[0048] In some embodiments, revising the layout design includes generating a photomask design as the revised layout design.

[0049] In some embodiments, receiving the layout design includes receiving a layout design for a static random-access memory (SRAM) cell. In some embodiments, the first conductive contact comprises a Vcc contact or a BL contact. In some embodiments, the second conductive contact comprises a Vss contact or a node contact.

[0050] In some embodiments, the reduction is carried out without reducing the size of the second conductive contact in the first direction.

[0051] It is understood that additional operations may be performed before, during, or after steps 910-920 of procedure 900. For example, procedure 900 may include a step of fabricating an SRAM device according to the revised layout design. For the sake of simplicity, other additional steps are not described in detail here.

[0052] Based on the above description, it is evident that the present disclosure offers advantages over conventional FinFET SRAM devices. However, it is understood that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, nor is any particular advantage required for all embodiments. One advantage is that the present disclosure reduces the gate contact bridging risks. For example, in a conventional SRAM cell design, the Vss contact or the node contact can bridge with adjacent gate structures if the end sections of these gate structures have been enlarged due to process control limitations. The present disclosure reduces the dimensions of the Vss contact or the node contact, so that physical contact with the adjacent gate structures is unlikely, even if the footprint of the gate structures is enlarged.The reduced risk of bridging enables an improved SRAM device and better reliability. Further advantages include compatibility with existing FinFET SRAM designs and manufacturing, making the implementation of this disclosure simple and inexpensive.

[0053] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device comprises an elongated gate structure extending in a first direction. The elongated gate structure has a first end section, a second end section, and a third section located between the first and second end sections. The semiconductor device includes a first conductive contact extending in the first direction. The first conductive contact is located adjacent to the third section of the elongated gate structure. The first conductive contact has a first dimension measured in a first direction and a second dimension measured in a second direction perpendicular to the first direction. The semiconductor device includes a second conductive contact extending in the first direction.The second conductive contact is located adjacent to the first end section of the elongated gate structure. The second conductive contact has a third dimension, measured in the first direction, and a fourth dimension, measured in the second direction. The first dimension is smaller than the third dimension. The second dimension is larger than the fourth dimension. A first fin structure intersects the elongated gate structure and the first conductive contact in a top view. A second fin structure also intersects the elongated gate structure and the second conductive contact in a top view. Both the first and second fin structures extend in the second direction. The first fin structure is separated from the second fin structure in the first direction.

[0054] Another aspect of the present disclosure relates to a static random-access memory (SRAM) cell. The SRAM cell comprises a first gate and a second gate, each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is located adjacent to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

[0055] Another aspect of the present disclosure relates to a method. A layout design for a circuit is received. The circuit comprises: an elongated gate structure extending in a first direction (Y-direction), a first conductive contact extending in the first direction, and a second conductive contact extending in the first direction. An end section of the elongated gate structure is located near the second conductive contact, but not near the first conductive contact. The layout design is revised. The revision involves reducing the size of the second conductive contact in a second direction perpendicular to the first direction.

[0056] For example, different resistances can be achieved for the bit line conductor and the word line conductor by implementing different thicknesses. However, other techniques can also be used to modify the resistances of the metal conductors.

Claims

[1] Semiconductor device comprising: a first elongated gate structure (121) extending in a first direction, wherein the first elongated gate structure (121) has a first end section (121A), a second end section (121B) and a third section (121C) arranged between the first end section (121A) and the second end section (121B); a second elongated gate structure (122) extending in the first direction and separated from the first elongated gate structure (121) by a gap (201); a first conductive contact (132) extending in the first direction, wherein the first conductive contact (132) is located adjacent to the third section (121C) of the first elongated gate structure (121), wherein the first conductive contact (132) has a first dimension (160) measured in the first direction and a second dimension (161) measured in a second direction perpendicular to the first direction; a second conductive contact (133) extending in the first direction, wherein the second conductive contact (133) is located adjacent to the first end section (121A) of the first elongated gate structure (121) and a section (133A) of the second conductive contact (133) overlaps with the gap (201) in the first direction, wherein the second conductive contact (133) has a third dimension (170) measured in the first direction and a fourth dimension (171) measured in the second direction, wherein the first dimension (160) is smaller than the third dimension (170) and wherein the second dimension (161) is larger than the fourth dimension (171); a first fin structure (113) that intersects the first elongated gate structure (121) and the first conductive contact (132) in a top view; and a second fin structure (114) that intersects the first elongated gate structure (121) and the second conductive contact (133) in a top view, wherein the first fin structure (113) and the second fin structure (114) each extend in the second direction and wherein the first fin structure (113) is separated from the second fin structure (114) in the first direction, wherein the first conductive contact (132) comprises a Vcc contact or a BL contact of a static random access memory (SRAM) cell and the second conductive contact (133) comprises a Vss contact or a node contact of the SRAM cell. [2] Semiconductor device according to claim 1, wherein the section (133A) of the second conductive contact (133) which overlaps with the gap (201) in the first direction is a non-end section (133A) of the second conductive contact (133). [3] Semiconductor device according to claim 1 or 2, further comprising: a third conductive contact (135) extending in the first direction, wherein the third conductive contact (135) is arranged adjacent to the second end section (121B) of the first elongated gate structure (121), wherein the third conductive contact (135) has a fifth dimension (180) measured in the first direction and a sixth dimension (181) measured in the second direction, wherein the first dimension (160) is smaller than the fifth dimension (180) and wherein the second dimension (161) is larger than the sixth dimension (181). [4] Semiconductor device according to claim 3, wherein the fourth dimension (171) is smaller than the sixth dimension (181). [5] Semiconductor device according to claim 3 or 4, wherein: the first conductive contact (132) comprises a Vcc contact of a static random access memory (SRAM) cell; the second conductive contact (133) comprises a Vss contact of the SRAM cell; the third conductive contact (135) comprises a node contact of the SRAM cell; the node contact (135) is located on a first side of the first elongated gate structure (121); and the Vcc contact (132) and the Vss contact (133) are located on a second side of the first elongated gate structure (121) opposite the first side. [6] Semiconductor device according to any one of the preceding claims 3 to 5, wherein the semiconductor device further comprises: a third elongated gate structure (120) extending in the first direction, wherein the third elongated gate structure (120) is separated from the first elongated gate structure (121) by a gap (200); and a bit line (BL) contact (131) of the SRAM cell, which is located adjacent to the third elongated gate structure (120), but not to the first elongated gate structure (121); where: the BL contact (131) has a seventh dimension (150) which is measured in the first direction and an eighth dimension (151) which is measured in the second direction; the seventh dimension (150) is smaller than the third dimension (170) and the fifth dimension (180); and the eighth dimension (151) is larger than the fourth dimension (171) and the sixth dimension (181). [7] Semiconductor device according to one of the preceding claims, wherein the second dimension (161) is at least about 0.5 nanometers larger than the fourth dimension (171). [8] Semiconductor device according to one of the preceding claims, wherein the first elongated gate structure (121) encloses both the first fin structure (113) and the second fin structure (114). [9] Static random access memory (SRAM) cell, comprising: a first gate (121) and a second gate (122), each extending in a first direction, wherein a first gap (201) separates the first gate (121) from the second gate (122) in the first direction; a Vcc contact (132) extending in the first direction, wherein a second gap (210) separates the Vcc contact (132) and the first gate (121) in a second direction perpendicular to the first direction, and wherein no segment of the Vcc contact (132) overlaps with the first gap (201) in the first direction; and a Vss contact (133) extending in the first direction, wherein a third gap (220) separates the Vss contact (133) from the first gate (121) in the second direction, wherein a segment of the Vss contact (133) is located adjacent to the first gap (201) and overlaps with the first gap (201) in the first direction, wherein the Vss contact (133) is smaller than the Vcc contact (132) in the second direction. [10] SRAM cell according to claim 9, wherein a middle segment (133A) of the Vss contact (133) is separated from the first gap (201) in the second direction and overlaps with the first gap (201) in the first direction. [11] SRAM cell according to claim 9 or 10, further comprising: a node contact (135) extending in the first direction, wherein a fourth gap (240) separates the node contact (135) from the first gate (121), wherein the node contact (135) is smaller than the Vcc contact (132) in the second direction, and wherein the node contact (135) is arranged on a first side of the first gate (121), and the Vcc contact (132) and the Vss contact (133) are arranged on a second side of the first gate (121) opposite the first side. [12] SRAM cell according to claim 11, wherein the Vss contact (133) is smaller in the second direction than the node contact (135). [13] SRAM cell according to claim 11 or 12, further comprising a third gate (120) extending in the first direction, wherein a fifth gap (200) separates the third gate (120) from the first gate (121) in the first direction and wherein a non-end section (135A) of the node contact (135) is arranged adjacent to the fifth gap (200). [14] SRAM cell according to claim 13, further comprising: a bit line (BL) contact (131) extending in the first direction, wherein a sixth gap (230) separates the BL contact (131) from the third gate (120) in the second direction, wherein the BL contact (131) is larger than the Vss contact (133) and larger than the node contact (135) in the second direction, and wherein the BL contact (131) and the node contact (135) are arranged on opposite sides of the third gate (120). [15] SRAM cell according to any one of the preceding claims 9 to 14, wherein the Vss contact (133) is at least about 0.5 nanometers smaller than the Vcc contact (132) in the second direction. [16] SRAM cell according to any one of the preceding claims 9 to 15, further comprising a plurality of fins (114, 115) extending in the second direction, wherein the first gate (121) and the second gate (122) each enclose a corresponding fin. [17] Procedures, including: Receiving a layout design for a circuit comprising: a first elongated gate structure (121) extending in a first direction, a second elongated gate structure (120, 122) extending in the first direction and separated from the first elongated gate structure (121) by a gap (200, 201), a first conductive contact (131, 132) extending in the first direction, and a second conductive contact (133, 135) extending in the first direction, wherein an end section (121A, 121B) of the elongated gate structure (121) is located near the second conductive contact (133, 135) but not near the first conductive contact (131, 132), and wherein a section of the second conductive contact (133, 135) is connected to the gap (200, 201) in the first direction. overlaps; and Revision of the layout design, wherein the revision comprises reducing the size of the second conductive contact (133, 135) in a second direction perpendicular to the first direction, such that a dimension (171, 181) of the second conductive contact (133, 135) in the second direction is smaller than a dimension (151, 161) of the first conductive contact (131, 132) in the second direction, where: Receiving the layout design includes receiving a layout design for a static random access memory (SRAM) cell; the first conductive contact (131, 132) comprises a Vcc contact (132) or a BL contact (131); and the second conductive contact (133, 135) comprises a Vss contact (133) or a node contact (135). [18] Method according to claim 17, wherein revising the layout design comprises generating a photomask design as the revised layout design. [19] Method according to claim 17 or 18, wherein the reduction is carried out without reducing the size of the second conductive contact (133, 135) in the first direction.

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