Circuit and method for writing to a bit cell

Abstract

Circuit (100) comprising: a first bit line (BL); a power node having a first power voltage level (VDDM); a reference node with a reference voltage level (VSS); a first pass gate (121) coupled between the first bit line (BL) and the power node; and a first driver (123) coupled between the first bit line (BL) and the reference node; where: the first pass gate (121) is configured to receive a first signal (DTM), to couple the first bit line (BL) to the power node when the first signal (DTM) has the reference voltage level (VSS), and to decouple the first bit line (BL) from the power node when the first signal (DTM) has the first power voltage level (VDDM); the first driver (123) is configured to receive a second signal (WT) based on a control signal (WD), to couple the first bit line (BL) to the reference node when the second signal (WT) has a second power voltage level (VDD) between the reference voltage level (VSS) and the first power voltage level (VDDM), and to decouple the first bit line (BL) from the reference node when the second signal (WT) has the reference voltage level (VSS); and the circuit (100) further comprises an input circuit (130) configured to generate the first signal (DTM) independently of the control signal (WD).

Description

BACKGROUND

[0001] In some memory circuits, memory arrays operate at a power voltage level that is higher than the power voltage level at which other circuits operate. The higher voltage level of the memory array supports the reliable operation of memory cells, while the lower voltage level of the other circuits reduces power requirements.

[0002] By separately activating circuit performance features, circuits having multiple power domains are capable of achieving overall circuit performance that exceeds the performance levels of circuits having individual power domains.

[0003] US 2014 / 0269112 A1 describes a driver for a memory circuit, the driver comprising a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage range at a first node based on an input signal in a second range and in response to a mode selection signal being in a first mode, the first drive signal being at the same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage range at a second node based on the input signal and in response to the mode selection signal being in the first mode, the second drive signal being at a complementary logic level with respect to the input signal;and operating the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode;

[0004] US 8971133 B1 describes a memory device having an array of memory cells connected to a core voltage level and an access circuit used to perform a write operation to write data to a plurality of addressed memory cells. At least one bit line connected to at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level before performing the write operation. A word line driver circuit is configured to apply a word line signal at the core voltage level to the word line associated with the row of the array containing the addressed memory cells.A write multiplex driver circuit applies a mux control signal to the write multiplex circuit, which then couples the bit line of each addressed memory cell to the write driver circuit, depending on the mux control signal indicating which column contains the addressed memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is a schematic of a memory circuit according to some embodiments. Fig. 2 is a schematic of an input circuit according to some embodiments. Fig. 3 is a flowchart of a method for writing to a bit cell according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples of implementing various features of the provided subject matter. Specific examples of components, values, materials, arrangements, or the like are described below to simplify the present disclosure. Other components, values, acts, materials, arrangements, or the like are contemplated. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Furthermore, the present disclosure may repeat reference numerals and / or letters throughout the various examples. This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or arrangements discussed.

[0007] Furthermore, spatial terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as shown in the figures. The spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptors used herein may also be interpreted accordingly.

[0008] A memory circuit includes a bit line, a power node having a memory domain power voltage level, a reference node having a reference voltage level, a pass gate coupled between the bit line and the power node, and a driver coupled between the bit line and the reference node. The pass gate selectively couples the bit line to the power node in response to a first signal, and the driver selectively couples the bit line to the reference node in response to a second signal. The first signal is based on the memory domain power voltage level, and the second signal is based on a second power voltage level between the reference voltage level and the memory domain power voltage level.

[0009] Fig. 1 is a circuit diagram of a memory circuit 100 according to some embodiments. The memory circuit 100 includes a bit cell 110, a driver circuit 120, and an input circuit 130. The bit cell 110 and the driver circuit 120 are each electrically coupled to a first bit line BL and a second bit line BLB. Signal paths 131 to 134 connect the input circuit 130 to the driver circuit 120.

[0010] The bit cell 110 is a memory bit cell of the memory circuit 100. In some embodiments, the bit cell 110 is one of a plurality of bit cells (not shown), and one or more bit cells (not shown) in addition to the bit cell 110 are electrically coupled to the first bit line BL and the second bit line BLB.

[0011] In the embodiment shown in Fig. 1, bitcell 110 is a six-transistor bitcell configured as a memory cell of a static random access memory (SRAM) circuit. In some embodiments, bitcell 110 includes fewer or more than six transistors. In some embodiments, bitcell 110 is configured as a memory cell other than a memory cell of an SRAM circuit.

[0012] Bitcell 110 includes bitcell pass gates 111 and 112, p-type metal-oxide-semiconductor (PMOS) transistors 113 and 114, and n-type metal-oxide-semiconductor (NMOS) transistors 115 and 116. Pass gate 111 and the gate terminals of PMOS transistor 114 and NMOS transistor 115 are electrically coupled to a node N1. Pass gate 112 and the gate terminals of PMOS transistor 113 and NMOS transistor 116 are electrically coupled to a node N2. The gates of pass gates 111 and 112 are electrically coupled to a word line 117.

[0013] A source terminal of the respective PMOS transistors 113 and 114 is electrically coupled to a power node VDDM, and a source terminal of the respective NMOS transistors 115 and 116 is electrically coupled to a reference node VSSM. The power node VDDM has a power voltage level corresponding to a memory domain and is also referred to as a memory domain power node with a memory domain power voltage level. The reference node VSSM has a reference voltage level for the memory domain, which is also referred to as a memory domain reference node with a memory domain reference voltage level.

[0014] In some embodiments, the power node VDDM has a memory domain voltage level relative to the memory domain reference voltage level of 0.7 volts (V) to 1.0 V.

[0015] By configuring the PMOS transistors 113 and 114 and the NMOS transistors 115 and 116, the memory cell 100 is configured to store, in operation, one of the memory domain power voltage level or the memory domain reference voltage level at node N1 and the other of the memory domain power voltage level or the memory domain reference voltage level at node N2.

[0016] In operation, a first logic state or value corresponds to node N1 storing the memory domain power voltage level and node N2 storing the memory domain reference voltage level, and a second logic state or value corresponds to node N1 storing the memory domain reference voltage level and node N2 storing the memory domain power voltage level.

[0017] The pass gate 111 is configured to selectively electrically couple the node N1 to the bit line BL or electrically decouple the node N1 from the bit line BL in response to a signal WL on the word line 117. The pass gate 112 is configured to selectively electrically couple the node N2 to the bit line BLB or electrically decouple the node N2 from the bit line BLB in response to the signal WL on the word line 117.

[0018] In some embodiments, the WL signal has a first logic state corresponding to the WL signal at the memory domain power voltage level (which is the same voltage level as at the memory domain power node VDDM) and a second logic state corresponding to the WL signal at the memory domain reference voltage level (which is the same voltage level as at the memory domain reference voltage level VSSM). In some embodiments, the WL signal is thereby based on the memory domain power voltage level. In some embodiments, the WL signal has a different scheme instead of being based on the memory domain power voltage level.

[0019] Due to the configuration of pass gates 111 and 112, during a read operation, bit line BL is used to determine the voltage level of node N1, and bit line BLB is used to determine the voltage level of node N2. During a read operation, a logic state or value of bit cell 110 is determined using bit lines BL and BLB.

[0020] Due to the configuration of pass gates 111 and 112, during a write operation, bit line BL is used to detect a voltage level at node N1, and bit line BLB is used to detect a voltage level at node N2. During a write operation, a logic state or value is written to bit cell 110 via bit lines BL and BLB.

[0021] Driver circuit 120 includes bitline pass gates 121 and 122, drivers 123 and 124, and logic gates 125 and 126. Pass gate 121 is coupled between memory domain power node VDDM and bitline BL, and pass gate 122 is coupled between memory domain power node VDDM and bitline BLB. Driver 123 is coupled between bitline BL and a reference node VSS and between logic gate 125 and reference node VSS. Driver 124 is coupled between bitline BLB and reference node VSS and between logic gate 126 and reference node VSS. Logic gates 125 and 126 are each electrically coupled to a second power node VDD.

[0022] The second power node VDD has a second power voltage level corresponding to a domain separate from the memory domain. The reference node VSS has a second reference voltage level.

[0023] In some embodiments, the second power node VDD has a second power voltage level relative to the second reference voltage level of 0.3 V to 0.6 V. In some embodiments, the memory domain voltage level is 300 to 500 millivolts (mV) greater than the second power voltage level. In some embodiments, the memory domain voltage level is at least 350 mV greater than the second power voltage level.

[0024] In some embodiments, the second reference voltage level of the reference node VSS is the memory domain reference voltage level of the reference node VSSM. In some embodiments, the second reference voltage level of the reference node VSS has a value that is different from the memory domain reference voltage level of the reference node VSSM.

[0025] A drain terminal of pass gate 121 is electrically coupled to bit line BL, a source terminal of pass gate 121 is electrically coupled to memory domain power node VDDM, and a gate terminal of pass gate 121 is electrically coupled to signal line 132. Pass gate 121 is therefore configured to electrically couple bit line BL to memory domain power node VDDM in response to a signal DTM on signal path 132.

[0026] In operation, the DTM signal controls the pass gate 121 to selectively drive the bit line BL to the memory domain power voltage level. In some embodiments, the DTM signal has a first logic state corresponding to the DTM signal at the memory domain power voltage level and a second logic state corresponding to the DTM signal at the memory domain reference voltage level. In some embodiments, the DTM signal is thereby based on the memory domain power voltage level. In some embodiments, the DTM signal has a different scheme instead of being based on the memory domain power voltage level.

[0027] A drain terminal of pass gate 122 is electrically coupled to bit line BLB, a source terminal of pass gate 122 is electrically coupled to memory domain power node VDDM, and a gate terminal of pass gate 122 is electrically coupled to signal line 134. Pass gate 122 is therefore configured to electrically couple bit line BLB to memory domain power node VDDM in response to a signal DCM on signal path 134.

[0028] In operation, the DCM signal controls the pass gate 122 to selectively drive the bit line BLB to the memory domain power voltage level. In some embodiments, the DCM signal has a first logic state corresponding to the DCM signal at the memory domain power voltage level and a second logic state corresponding to the DCM signal at the memory domain reference voltage level. In some embodiments, the DCM signal is thereby based on the memory domain power voltage level. In some embodiments, the DCM signal has a different scheme instead of being based on the memory domain power voltage level. In some embodiments, the DCM signal corresponds to a data complement signal for a data bit written to the bit cell 110 during a write operation.

[0029] In the embodiment shown in Fig. 1, pass gates 121 and 122 each include a PMOS transistor. In some embodiments, pass gate 121 includes an NMOS transistor or other suitable switching device capable of selectively coupling bit line BL to memory domain power node VDDM in response to signal DTM. In some embodiments, pass gate 122 includes an NMOS transistor or other suitable switching device capable of selectively coupling bit line BLB to memory domain power node VDDM in response to signal DCM.

[0030] A drain terminal of driver 123 is electrically coupled to bit line BL, a source terminal of driver 123 is electrically coupled to reference node VSS, and a gate terminal of driver 123 is electrically coupled to an output terminal of logic gate 125. Driver 123 is therefore configured to electrically couple bit line BL to reference node VSS in response to a signal WT on the output terminal of logic gate 125.

[0031] In operation, the WT signal thereby controls the driver 123 to selectively drive the bit line BL to the second reference voltage level. In some embodiments, the WT signal has a first logic state corresponding to the WT signal having the second power voltage level and a second logic state corresponding to the WT signal having the second reference voltage level. In some embodiments, the DCM signal is thereby based on the second power voltage level. In some embodiments, the WT signal has a different scheme instead of being based on the second power voltage level.

[0032] A drain terminal of driver 124 is electrically coupled to bit line BLB, a source terminal of driver 124 is electrically coupled to reference node VSS, and a gate terminal of driver 124 is electrically coupled to an output terminal of logic gate 126. Driver 124 is therefore configured to electrically couple bit line BLB to reference node VSS in response to a signal WC on the output terminal of logic gate 126.

[0033] In operation, the WC signal thereby controls the driver 124 to selectively drive the BLB bit line to the second reference voltage level. In some embodiments, the WC signal has a first logic state corresponding to the WC signal having the second power voltage level and a second logic state corresponding to the WC signal having the second reference voltage level. In some embodiments, the WC signal is thereby based on the second power voltage level. In some embodiments, the WC signal has a different scheme instead of being based on the second power voltage level. In some embodiments, the WC signal corresponds to a write complement signal for a data bit written to the bit cell 110 during a write operation.

[0034] In the embodiment shown in Fig. 1, drivers 123 and 124 each include an NMOS transistor. In some embodiments, driver 123 includes a PMOS transistor or other suitable switching device capable of selectively coupling bit line BL to reference node VSS in response to signal WT. In some embodiments, driver 124 includes a PMOS transistor or other suitable switching device capable of selectively coupling bit line BLB to reference node VSS in response to signal WC.

[0035] Logic gate 125 includes a first input terminal electrically coupled to signal path 131 and a second input terminal configured to receive a signal WD generated by circuitry (not shown) separate from memory circuitry 100. In some embodiments, signal WD is a write decode signal generated by a write line decode circuit. In some embodiments, during a write operation, signal WD has a logic state indicating that bit cell 110 or another bit cell electrically coupled to bit lines BL and BLB is a target of the write operation.In some embodiments, during a write operation, the signal WD has a logic state indicating that the bit cell 110 or another bit cell electrically coupled to the bit lines BL and BLB is a target of the write operation based on decoding a multi-bit memory address.

[0036] Logic gate 125 is therefore configured to generate the WT signal on the output terminal, which has a logic state determined by the logic state of the DC signal on signal line 131 and the logic state of the WD signal. In operation, the DC and WD signals thereby control the WT control signal received by driver 123 as described above.

[0037] The DC and WD signals are each based on the second power voltage level. In some embodiments, the WD signal corresponds to a write decode signal for the bit cell 110 during a write operation during which the WD signal has a second reference voltage level.

[0038] Logic gate 126 includes a first input terminal electrically coupled to signal path 133 and a second input terminal configured to receive signal WD. Logic gate 126 is therefore configured to generate signal WC on the output terminal, which has a logic state determined by the logic state of signal DT on signal line 133 and the logic state of signal WD. In operation, signals DT and WC thereby control control signal WT, which is received by driver 124 as described above.

[0039] The DT signal is based on the second power voltage level.

[0040] In the embodiment shown in Fig. 1, logic gates 125 and 126 are each a NOR gate. In some embodiments, logic gate 125 includes one or more other types of logic gates suitable for generating the WT signal for controlling driver 123 in response to one or more input signals, such as the DC and WD signals. In some embodiments, logic gate 126 includes one or more other types of logic gates suitable for generating the WC signal for controlling driver 124 in response to one or more input signals, such as the DT and WD signals.

[0041] The input circuit 130 is a circuit such as the circuit 200 described below with reference to Fig. 2, which is configured to generate the signals DC, DTM, DT and DCM on the respective signal paths 131 to 134.

[0042] The input circuit 130 is configured to generate the signal DTM based on the signal DT and the signal DCM based on the signal DC. In some embodiments, the input circuit 130 is configured to generate the signal DTM with the memory domain reference voltage level synchronized with the signal DT with the second reference voltage level. In some embodiments, the input circuit 130 is configured to generate the signal DCM with the memory domain power voltage level synchronized with the signal DC with the second power voltage level.

[0043] In some embodiments, the input circuit 130 is configured to generate the signals DC and DTM as a complementary pair during a write operation such that the signals DC and DTM have logic states that are different from each other, and to generate the signals DT and DCM as a complementary pair such that the signals DC and DTM have logic states that are different from each other.

[0044] In some embodiments, during a write operation, the complementary pair of signals DC and DTM, in combination with a logic state of the signal WD corresponding to the write operation, cause the bit line BL to be electrically coupled to either the memory domain power node VDDM or the reference node VSS. In some embodiments, during a write operation, the complementary pair of signals DT and DTM, in combination with a logic state of the signal WD corresponding to the write operation, cause the bit line BLB to be electrically coupled to either the memory domain power node VDDM or the reference node VSS.

[0045] In some embodiments, the input circuit 130 is configured to generate the signals DT and DC as a complementary pair during a write operation, generate the signal DTM synchronized with the signal DT, and generate the signal DCM synchronized with the signal DC.

[0046] In some embodiments, during a write operation, the signals DT and DC, which are a complementary pair, the signal DTM synchronized with the signal DT and the signal DCM synchronized with the signal DC, cause either the bit line BL to be electrically coupled to the memory domain power node VDDM while the bit line BLB is electrically coupled to the reference node VSS, or the bit line BL to be electrically coupled to the reference node VSS while the bit line BLB is electrically coupled to the memory domain power node VDDM.

[0047] The memory circuit 100 is therefore configured to detect a first of the memory domain power voltage level or the second reference voltage level at node N1 during a write operation using the bit line BL, and to detect a second of the memory domain power voltage level or the second reference voltage level at node N2 using the bit line BLB. During a write operation, the memory circuit 100 thereby writes one of two possible logic states or values ​​to the bit cell 110 using the bit lines BL and BLB.

[0048] In one non-limiting example of a write operation, memory circuit 100 writes a logic value to bit cell 110 when signal WD is at the second reference voltage level and signal WL is at the memory domain power voltage level. During the write operation, signal WD having the second reference voltage level causes logic gate 125 to generate signal WT for driver 123 by inverting signal DC, and logic gate 126 to generate signal WC for driver 124 by inverting signal DT. Signals DT and DC, being a complementary pair, therefore cause one of bit lines BL or BLB to be driven to the memory domain power voltage level during the write operation, while the other of bit lines BL or BLB is driven to the second reference voltage level.

[0049] During the write operation, the WL signal at the memory domain power voltage level causes the bit line pass gate 111 to electrically couple the bit line BL to the node N1 and the bit line pass gate 112 to electrically couple the bit line BLB to the node N2. During the write operation, the node N1 is thereby driven to one of the memory domain power voltage level or the second reference voltage level, while the node N2 is driven to the other of the memory domain power voltage level or the second reference voltage level.

[0050] If the logic value written to bit cell 110 during the write operation causes bit line BL to drive node N1 to the memory domain power voltage level, transistor 114 is turned off, allowing node N2 to be driven to the second reference voltage level by bit line BLB. If the logic value written to bit cell 110 during the write operation causes bit line BLB to drive node N2 to the memory domain power voltage level, transistor 113 is turned off, allowing node N1 to be driven to the second reference voltage level by bit line BL.

[0051] The configuration of memory circuit 100 ensures that a write operation to bit cell 110 drives nodes N1 and N2 to a desired voltage level, respectively, by ensuring that the relevant one of transistors 113 or 114 is turned off during the write operation. Because the relevant transistor is turned off during a write operation, this ensures that a desired logic value is written to bit cell 110 during a write operation in which a transition in signal WL precedes a transition in signal WT or WC. During a write operation in which the relevant transistor is not turned off by driving it to the memory domain power voltage level, if the relevant driver is unable to drive the node coupled to the source of the transistor to the second reference voltage level, a write error may occur.

[0052] By driving one of the bit lines BL or BLB to the memory domain power voltage level and the other of the bit lines BL or BLB to the second reference voltage level during a write operation, a dummy read operation is not required to clear the bit lines BL and BLB before the write operation.

[0053] Compared to other approaches in which neither the bit line BL nor the bit line BLB is selectively coupled to the memory domain power node VDDM, the memory circuit 100 is configured to prevent write errors and dummy reads. Compared to other approaches in which the bit lines BL and BLB are driven using cross-latched PMOS transistors or NMOS drivers with enhanced drive capabilities, the memory circuit 100 also has a smaller area and low overall loss.

[0054] In some embodiments, the memory circuit 100 has a configuration that includes one or more pass gates, drivers, logic gates, and / or signals that are different than those described in Fig. 1, so that during a write operation, one of the bit lines BL or BLB is otherwise driven to the memory domain power voltage level, while the other of the bit lines BL or BLB is driven to the second reference voltage level, thereby achieving the advantages described above with reference to the embodiments shown in Fig. 1 illustrated embodiment.

[0055] The input circuit 130 is configured such that, during one or more operations outside of write operations as described above, the input circuit 130 generates the signals DT and DC, respectively, having the second power voltage level, while the signals DTM and DCM each have the memory domain power voltage level. The memory circuit 100 is therefore configured such that, during the one or more operations outside of write operations, the bit line BL is electrically decoupled from the memory domain power node VDDM by the pass gate 121 and from the reference node VSS by the driver 123, while the bit line BLB is electrically decoupled from the memory domain power node VDDM by the pass gate 122 and from the reference node VSS by the driver 124.

[0056] By being electrically decoupled from the memory domain power node VDDM and the reference node VSS during the one or more non-write operations, the bit lines BL and BLB are each capable of being electrically coupled to the second power node VDD by one or more circuits (not shown) and thereby driven or precharged to the second power voltage level. In some embodiments, the one or more non-write operations include a read operation or an idle or sleep state.

[0057] Fig. 2 is a circuit diagram of an input circuit 200 according to some embodiments. The input circuit 200 is usable as the input circuit 130 described above with reference to the memory circuit 100 and Fig. 1. The input circuit 200 includes an inverter 210, the NAND gates 220 to 240, and the conversion circuits 250 and 260. The inverter 210 and the NAND gates 220 to 240 are each configured to operate in a power domain 270 having the second power voltage level described above with reference to the memory circuit 100 and Fig. 1. The input circuit 200 is configured to receive the signals DLAT, BLAT, SCANLATENB, and CKP_WRITE from one or more circuits (not shown) external to the input circuit 200, and to generate the signals DC, DCM, DT, and DTM based on the signals DLAT, BLAT, SCANLATENB, and CKP_WRITE.

[0058] Inverter 210 is configured to receive the DLAT signal from an external source (not shown) at the input terminal and output a DLATB signal at the output terminal. In operation, inverter 210 inverts the DLAT signal to generate the DLATB signal.

[0059] NAND gate 220 is configured to receive the BLAT signal from an external source (not shown) at a first input terminal and the SCANLATENB signal from an external source (not shown) at a second input terminal, and to output a BLATN signal at the output terminal. In operation, NAND gate 220 performs a NAND operation on the BLAT and SCANLATENB signals to generate the BLATN signal.

[0060] NAND gate 230 is configured to receive the DLATB signal at a first input terminal, the BLATN signal at a second input terminal, and the CKP_WRITE signal from an external source (not shown) at a third input terminal, and to output the DC signal on signal line 231. In operation, NAND gate 230 performs a NAND operation on the DLATB, BLATN, and CKP_WRITE signals to generate the DC signal.

[0061] NAND gate 240 is configured to receive the DLAT signal at a first input terminal, the BLATN signal at a second input terminal, and the CKP_WRITE signal at a third input terminal, and to output the DT signal on signal line 241. In operation, NAND gate 240 performs a NAND operation on the DLAT, BLATN, and CKP_WRITE signals to generate the DT signal.

[0062] Since the inverter 210 and the NAND gates 220 to 240 are each configured to operate in the power domain 270, the signals DLAT, BLAT, SCANLATENB, DLATB, BLATN, CKP_WRITE, DC and DT are each based on the second power voltage level.

[0063] Conversion circuit 250 is configured to receive the DC signal on signal line 231 and generate the DCM signal on signal line 251. Conversion circuit 250 is electrically coupled to the memory domain power node VDDM and configured to generate the DCM signal based on the memory domain power voltage level.

[0064] Conversion circuit 250 is configured to generate the DCM signal synchronized with the DC signal. In some embodiments, the DCM signal synchronized with the DC signal includes the DCM signal having a delay introduced by conversion circuit 250, wherein the delay is insignificant relative to the timing of the operations of memory circuit 100.

[0065] Conversion circuit 250 is configured to generate the DCM signal based on the memory domain power voltage level. In some embodiments, conversion circuit 250 is configured to generate the DCM signal by shifting a voltage level input by the DC signal from the second power voltage level to the memory domain power voltage level.

[0066] In the embodiment shown in Fig. 2, conversion circuit 250 includes two inverters (not labeled) configured to generate the DCM signal based on the memory domain power voltage level and synchronized with the DC signal. In some embodiments, conversion circuit 250 includes one or more other circuit elements configured to generate the DCM signal based on the memory domain power voltage level and synchronized with the DC signal.

[0067] Conversion circuit 260 is configured to receive signal DT on signal line 241 and generate signal DTM on signal line 261. Conversion circuit 260 is electrically coupled to memory domain power node VDDM and configured to generate signal DTM based on the memory domain power voltage level.

[0068] Conversion circuit 260 is configured to generate signal DTM synchronized with signal DT. In some embodiments, signal DTM synchronized with signal DT includes signal DTM having a delay introduced by conversion circuit 260, wherein the delay is insignificant relative to the timing of operations of memory circuit 100.

[0069] Conversion circuit 260 is configured to generate signal DTM based on the memory domain power voltage level. In some embodiments, conversion circuit 260 is configured to generate signal DTM by shifting a voltage level input by signal DT from the second power voltage level to the memory domain power voltage level.

[0070] In the embodiment shown in Fig. 2, conversion circuit 260 includes two inverters (not labeled) configured to generate signal DTM based on the memory domain power voltage level and synchronized with signal DT. In some embodiments, conversion circuit 260 includes one or more other circuit elements configured to generate signal DTM based on the memory domain power voltage level and synchronized with signal DT.

[0071] By configuring input circuit 200, NAND gate 230 is configured to generate the DC signal as an inverted version of the DLATB signal, as enabled by the BLATN and CKP_WRITE signals. By configuring input circuit 200, NAND gate 240 is configured to generate the DT signal as a non-inverted version of the DLAT signal, as enabled by the BLATN and CKP_WRITE signals.

[0072] The input circuit 200 is therefore configured to generate the DC and DT signals as a complementary pair. Since the DCM signal is synchronized with the DC signal and the DTM signal is synchronized with the DT signal, the input circuit 200 is configured to generate the DCM and DTM signals as a complementary pair.

[0073] During a write operation, the signals BLAT, SCANLAT ENB, and CKP_WRITE therefore enable the generation of the signals DC, DCM, DT, and DTM, which are usable in the circuit 100, as described above with reference to Fig. 1 described.

[0074] In one or more operations other than write operations, as described above with respect to the memory circuit 100 and Fig. 1, the CKP_WRITE signal having the second reference voltage level causes the DC and DT signals to each have the second power voltage level, and the DCM and DTM signals to each have the memory domain power voltage level.

[0075] The input circuit 200 is therefore designed to be usable as input circuit 130 of the memory circuit 100, so that the advantages described above with reference to the memory circuit 100 and Fig. 1 can be achieved.

[0076] Fig. 3 is a flowchart of a method 300 for writing to a bit cell according to one or more embodiments. In some embodiments, the method 300 is implemented to write to a bit cell of an SRAM. In some embodiments, the method 300 is implemented to write to the bit cell 110 of the memory circuit 100 described above with reference to Fig. 1 is described.

[0077] In some embodiments, operations in addition to those described in Fig. 3 are carried out before, between and / or after the operations described in Fig. 3. In some embodiments, the operations described in Fig. 3 are carried out in a sequence that differs from that shown in Fig. 3 shown order.

[0078] At operation 310, a first bitline and a second bitline are driven to a first voltage level. The first voltage level corresponds to a domain of a memory circuit outside of a memory domain. In some embodiments, the first bitline is bitline BL, the second bitline is bitline BLB, and driving the first bitline and the second bitline to the first voltage level includes driving bitlines BL and BLB to the second power voltage level on the second power node VDD described above with reference to memory circuit 100 and Fig. 1 is described.

[0079] At operation 320, the bit cell is coupled to the first and second bit lines. The first bit line and the second bit line have the first voltage level. In some embodiments, coupling the bit cell to the first and second bit lines includes utilizing one or more bit cell pass gates. In some embodiments, coupling the bit cell to the first and second bit lines includes coupling bit cell 110 to bit line BL via bit cell pass gate 111 and coupling bit cell 110 to bit line BLB via bit cell pass gate 112, described above with reference to memory circuit 100 and Fig. 1 is described.

[0080] In some embodiments, coupling the bit cell to the first and second bit lines includes selectively coupling the bit cell to one or both of the first and second bit lines in response to a signal based on a memory domain power voltage level. In some embodiments, coupling the bit cell to the first and second bit lines includes coupling the bit cell 110 to the bit lines BL and BLB in response to the signal WL based on the memory domain power voltage level on the memory domain power node VDDM described above with reference to the memory circuit 100 and Fig. 1 is described.

[0081] At operation 330, a first one of the first bitline or the second bitline is driven to a second voltage level that is higher than the first voltage level. Driving the first one of the first bitline or the second bitline to the second voltage level includes driving the first one of the first or the second bitline to an operating voltage of the bitcell. In some embodiments, driving the first one of the first bitline or the second bitline to the second voltage level includes driving the first one of the first bitline or the second bitline to the memory domain power voltage level on the memory domain power node VDDM described above with reference to memory circuit 100 and Fig. 1 is described.

[0082] In some embodiments, driving the first of the first bitline or the second bitline to the second voltage level includes controlling a bitline pass gate to electrically couple the first of the first or the second bitline to a power node having the second voltage. In some embodiments, driving the first of the first bitline or the second bitline to the second voltage level includes controlling one of the bitline pass gates 121 or 122 to electrically couple one of the bitlines BL or BLB to the memory domain power node VDDM having the memory domain voltage level described above with reference to the memory circuit 100 and Fig. 1 is described.

[0083] In some embodiments, driving the first of the first bitline or the second bitline to the second voltage level includes controlling a bitline pass gate with a signal based on the second voltage level. In some embodiments, driving the first of the first bitline or the second bitline to the second voltage level includes controlling one of the bitline pass gates 121 or 122 with one of the signals DTM or DCM described above with reference to the memory circuit 100 and Fig. 1 is described.

[0084] In some embodiments, driving the first of the first bit line or the second bit line to the second voltage level includes controlling a bit line pass gate with a signal having a transition that lags behind a transition in a signal controlling pass gates in the bit cell. In some embodiments, driving the first of the first bit line or the second bit line to the second voltage level includes controlling one of the pass gates 121 or 122 with one of the signals WT or WC having a transition that lags behind a transition in a signal WL described above with reference to the memory circuit 100 and Fig. 1 is described.

[0085] In some embodiments, driving the first of the first bitline or the second bitline to the second voltage level includes generating the signal based on the second voltage level from a signal based on the first voltage level. In some embodiments, driving the first of the first bitline or the second bitline to the second voltage level includes generating one of the memory domain power voltage level-based signals DCM or DTM from a corresponding one of the second voltage level-based signals DC or DT described above with reference to memory circuit 200 and Fig. 2 is described.

[0086] At operation 340, in some embodiments, a bit cell transistor is turned off in response to driving the first of the first bit line or the second bit line to the second voltage level. In some embodiments, turning off a bit cell transistor in response to driving the first of the first bit line or the second bit line to the second voltage level includes turning off a PMOS transistor of an SRAM bit cell.

[0087] In some embodiments, turning off a bit cell transistor in response to driving the first of the first bit line or the second bit line to the second voltage level includes turning off one of the transistors 113 or 114 of the bit cell 110, which is described above with respect to the memory circuit 100 and Fig. 1 is described.

[0088] At operation 350, a second one of the first bitline or the second bitline is driven to a reference voltage level that is lower than the first voltage level. Driving the second one of the first bitline or the second bitline to the reference voltage level includes driving the second one of the first bitline or the second bitline to a domain reference voltage level of the memory circuit outside the memory domain. In some embodiments, the domain reference voltage level of the memory circuit outside the memory domain is the same as a domain reference voltage level of the memory domain.

[0089] In some embodiments, driving the second of the first bit line or the second bit line to the reference voltage level includes driving one of the bit lines BL or BLB to the second reference voltage level on the reference node VSS described above with respect to the memory circuit 100 and Fig. 1 is described.

[0090] In some embodiments, driving the second of the first bit line or the second bit line to the reference voltage level includes controlling a driver to electrically couple the second of the first bit line or the second bit line to a reference node having the reference voltage level. In some embodiments, driving the second of the first bit line or the second bit line to the reference voltage level includes controlling one of the drivers 123 or 124 to electrically couple one of the bit lines BL or BLB to the reference node VSS having the second reference voltage level, which is described above with respect to the memory circuit 100 and Fig. 1 is described.

[0091] In some embodiments, driving the second of the first bit line or the second bit line to the reference voltage level includes controlling a driver with a signal based on the first voltage level. In some embodiments, driving the second of the first bit line or the second bit line to the reference voltage level includes controlling one of the drivers 123 or 124 with one of the signals WT or WC described above with reference to the memory circuit 100 and Fig. 1 is described.

[0092] At operation 360, in some embodiments, the first bitline and the second bitline are returned to the first voltage level. In some embodiments, returning the first bitline and the second bitline to the first voltage level includes controlling pass gates to decouple the first bitline and the second bitline from a power node having the second voltage level. In some embodiments, returning the first bitline and the second bitline to the first voltage level includes controlling drivers to decouple the first bitline and the second bitline from a reference node having the reference voltage level.

[0093] In some embodiments, returning the first bit line and the second bit line to the first voltage level includes controlling pass gates 121 and 122 to decouple bit lines BL and BLB from the memory domain power node VDDM having the memory domain voltage level described above with respect to memory circuit 100 and Fig. 1. In some embodiments, returning the first bit line and the second bit line to the first voltage level includes controlling drivers 123 and 124 to decouple bit lines BL and BLB from reference node VSS having the second reference voltage level, which was described above with respect to memory circuit 100 and Fig. 1 is described.

[0094] In some embodiments, returning the first bit line and the second bit line to the first voltage level includes controlling pass gates and drivers based on a signal corresponding to operations other than write operations. In some embodiments, returning the first bit line and the second bit line to the first voltage level includes controlling pass gates 121 and 122 and drivers 123 and 124 based on the CKP_WRITE signal described above with reference to memory circuit 100 and Fig. 1 and the memory circuit 200 and Fig. 2 is described.

[0095] By driving a first one of a first bit line or a second bit line to a second voltage level higher than the first voltage level and driving a second one of the first bit line or the second bit line to a reference voltage level, the method 300 ensures that a desired logical value is written to a bit cell. The method 300 thus provides improved reliability and reduced loss compared to approaches in which a bit line is not driven to a second voltage level higher than a first voltage level, as described above with respect to the memory circuit 100.

[0096] In some embodiments, a circuit includes a bitline, a power node having a first power voltage level, a reference node having a reference voltage level, a pass gate coupled between the bitline and the power node, and a driver coupled between the bitline and the reference node. The pass gate is configured to couple the bitline to the power node in response to a first signal, the first signal based on the first power voltage level, and the driver is configured to couple the bitline to the reference node in response to a second signal, the second signal based on a second power voltage level between the reference voltage level and the first power voltage level.

[0097] In some embodiments, a memory circuit includes a reference node having a reference voltage level, a memory domain power node having a memory domain power voltage level, a first bit line, a second bit line, and a bit cell. The bit cell includes a first bit cell pass gate configured to selectively couple the bit cell to the first bit line and a second bit cell pass gate configured to selectively couple the bit cell to the second bit line. A driver circuit includes a first bit line pass gate, a second bit line pass gate, a first driver, and a second driver.The bit cell is configured to operate at the memory domain power level, the first bit line pass gate is configured to selectively couple the first bit line to the memory domain power node, the second bit line pass gate is configured to selectively couple the second bit line to the memory domain power node, the first driver is configured to selectively couple the first bit line to the reference node, and the second driver is configured to selectively couple the second bit line to the reference node.

[0098] In some embodiments, the method of writing to a bit cell comprises coupling the bit cell to a first bit line and to a second bit line, the first and second bit lines having a first voltage level, driving a first one of the first bit line or the second bit line to a second voltage level higher than the first voltage level, the second voltage level corresponding to an operating voltage of the bit cell, and driving a second one of the first bit line or the second bit line to a reference voltage level lower than the first voltage level.

[0099] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should recognize that they may readily use the present disclosure as a basis for constructing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein.

[0100] The invention is defined by the independent claims. The dependent claims describe preferred embodiments of the invention.

Claims

[1] Circuit (100) comprising: a first bit line (BL); a power node having a first power voltage level (VDDM); a reference node with a reference voltage level (VSS); a first pass gate (121) coupled between the first bit line (BL) and the power node; and a first driver (123) coupled between the first bit line (BL) and the reference node; where: the first pass gate (121) is configured to receive a first signal (DTM), to couple the first bit line (BL) to the power node when the first signal (DTM) has the reference voltage level (VSS), and to decouple the first bit line (BL) from the power node when the first signal (DTM) has the first power voltage level (VDDM); the first driver (123) is configured to receive a second signal (WT) based on a control signal (WD), to couple the first bit line (BL) to the reference node when the second signal (WT) has a second power voltage level (VDD) between the reference voltage level (VSS) and the first power voltage level (VDDM), and to decouple the first bit line (BL) from the reference node when the second signal (WT) has the reference voltage level (VSS); and the circuit (100) further comprises an input circuit (130) configured to generate the first signal (DTM) independently of the control signal (WD). [2] The circuit (100) of claim 1, wherein the input circuit (130) is configured to generate the first signal (DTM) from a sixth signal (DT), the sixth signal being based on the second power voltage level (VDD). [3] The circuit (100) of claim 2, wherein the input circuit (130) includes: a NAND gate (240) configured to generate the sixth signal (DT) based on three input signals. [4] Circuit (100) according to one of the preceding claims, wherein: the first power voltage level (VDDM) is a power voltage level of a memory domain of a memory circuit. [5] Circuit (100) according to one of the preceding claims, further comprising: a second bit line (BLB); a second pass gate (122) coupled between the second bit line (BLB) and the power node; and a second driver (124) coupled between the second bit line (BLB) and the reference node; where: the second pass gate (122) is configured to receive a third signal (DCM), to couple the second bit line (BLB) to the power node when the third signal (DCM) has the reference voltage level (VSS), and to decouple the second bit line (BLB) from the power node when the third signal (DCM) has the first power voltage level (VDDM); the second driver (124) is configured to receive a fourth signal (WC) based on the control signal (WD), to couple the second bit line (BLB) to the reference node when the fourth signal (WC) has the second power voltage level (VDD), and to decouple the second bit line (BLB) from the reference node when the fourth signal (WC) has the reference voltage level (VSS); and the input circuit (130) is designed to generate the third signal (DCM) independently of the control signal (WD). [6] The circuit (100) of claim 5, wherein the input circuit (130) is configured to generate the first signal (DTM) and the third signal (DCM) as a complementary pair during a write operation. [7] Circuit (100) according to claim 6, wherein: outside the write operation, the input circuit (130) is configured to generate the first signal (DTM) having a first logic state and the third signal (DCM) having the first logic state; the first pass gate (121) is configured to decouple the first bit line (BL) from the power node based on the first signal (DTM) having the first logic state; and the second pass gate (122) is configured to decouple the second bit line (BLB) from the power node based on the third signal (DCM) having the first logic state. [8] Circuit (100) according to one of the preceding claims 5 to 7, wherein the input circuit (130) is arranged to generate a fifth signal (DC) and a sixth signal (DT); wherein: the fifth and sixth signals are based on the second power voltage level (VDD); the first signal (DTM) and the fourth signal (WC) are based on the sixth signal (DT); and the second signal (WT) and the third signal (DCM) are based on the fifth signal (DC). [9] Circuit (100) according to one of the preceding claims, wherein: the first power voltage level (VDDM) is at least 350 millivolts (mV) greater than the second power voltage level (VDD). [10] Memory circuit (100), comprising: a reference node with a reference voltage level (VSS); a memory domain power node having a memory domain power voltage level (VDDM); a first bit line (BL); a second bit line (BLB); a bit cell (110), including: a first bit cell pass gate (111) configured to selectively couple the bit cell (110) to the first bit line (BL); and a second bit cell pass gate (112) configured to selectively couple the bit cell (110) to the second bit line (BLB); and a driver circuit (120) comprising a first bit line pass gate (121), a second bit line pass gate (122), a first driver (123) and a second driver (124); where: the bit cell (110) is configured to operate at the memory domain power voltage level (VDDM); the first bit line pass gate (121) is configured to receive a first signal (DTM), to couple the first bit line (BL) to the memory domain power node when the first signal (DTM) has the reference voltage level (VSS), and to decouple the first bit line (BL) from the memory domain power node when the first signal (DTM) has the memory domain power voltage level (VDDM); the second bit line pass gate (112) is configured to receive a third signal (DCM), to couple the second bit line (BLB) to the memory domain power node when the third signal (DCM) has the reference voltage level (VSS), and to decouple the second bit line (BLB) from the memory domain power node when the third signal (DCM) has the memory domain power voltage level (VDDM); the first driver (123) is configured to receive a second signal (WT) based on a control signal (WD), to couple the first bit line (BL) to the reference node when the second signal (WT) has a second power voltage level (VDD) between the reference voltage level (VSS) and the memory domain power voltage level (VDDM), and to decouple the first bit line (BL) from the reference node when the second signal (WT) has the reference voltage level (VSS); the second driver (124) is configured to receive a fourth signal (WC) based on the control signal (WD), to couple the second bit line (BLB) to the reference node when the fourth signal (WC) has the second power voltage level (VDD), and to decouple the second bit line (BLB) from the reference node when the fourth signal (WC) has the reference voltage level (VSS); and the memory circuit (100) further comprises an input circuit (130) configured to generate the first signal (DTM) and the third signal (DCM) independently of the control signal (WD). [11] Memory circuit (100) according to claim 10, wherein the input circuit (130) is arranged to during an operation for writing a first logical value to the bit cell (110), controlling the first bit line pass gate (121) to couple the first bit line (BL) to the memory domain power node and controlling the second driver (124) to couple the second bit line (BLB) to the reference node, and during an operation to write a second logic value to the bit cell (110), controlling the second bit line pass gate (122) to couple the second bit line (BLB) to the memory domain power node and controlling the first driver (123) to couple the first bit line (BL) to the reference node; where the second logical value is different from the first logical value. [12] Memory circuit (100) according to claim 11, wherein: the input circuit (130) is configured to control the first bit line pass gate (121) to decouple the first bit line (BL) from the memory domain power node and to control the second bit line pass gate (122) to decouple the second bit line (BLB) from the memory domain power node outside the operation for writing the first logic value and outside the operation for writing the second logic value. [13] The circuit (100) of any one of the preceding claims 10 to 12, wherein the first driver (123) and the second driver (124) are configured to operate in a power domain having the second power voltage level (VDD), and the second power voltage level is at least 350 millivolts (mV) lower than the memory domain power voltage level (VDDM). [14] A method for writing to a bit cell (110), comprising: coupling the bit cell (110) to a first bit line (BL) having a first voltage level (VDD); Receiving a first signal (DC) having a reference voltage level (VSS) and a control signal (WD) having the reference voltage level at a first logic gate (125); generating a second signal (WT) having the first voltage level (VDD) by the first logic gate (125) in response to the first signal (DC) and the control signal (WD) having the reference voltage level (VSS); Driving the first bit line (BL) to the reference voltage level (VSS) in response to the second signal (WT) having the first voltage level (VDD); Receiving a third signal (DTM) having a second voltage level (VDDM) higher than the first voltage level (VDD) at a first pass gate (121); and Decoupling the first bit line (BL) from a power voltage node having the second voltage level (VDDM) in response to the third signal (DTM) having the second voltage level, wherein the third signal (DTM) is independent of the control signal (WD). [15] The method of claim 14, wherein receiving the control signal (WD) having the reference voltage level (VSS) is in response to the bit cell (110) being the target of a write operation based on decoding a multi-bit memory address. [16] The method of claim 14 or 15, further comprising: coupling the bit cell (110) to a second bit line (BLB) having the first voltage level (VDD); Receiving a fourth signal (DT) having the first voltage level (VDD) and the control signal (WD) having the reference voltage level (VSS) at a second logic gate (126); generating a fifth signal (WC) having the reference voltage level (VSS) by the second logic gate (126) in response to the fourth signal (DT) having the first voltage level (VDD) and the control signal (WD) having the reference voltage level (VSS); Decoupling the second bit line (BLB) from a reference voltage node having the reference voltage level (VSS) in response to the fifth signal (WC) having the reference voltage level; Receiving a sixth signal (DCM) having the reference voltage level (VSS) at a second pass gate (122), the sixth signal (DCM) being independent of the control signal (WD); and Driving the second bit line (BLB) to the second voltage level (VDDM) in response to the sixth signal (DCM) having the reference voltage level (VSS). [17] The method of claim 16, further comprising: Generating the third signal (DTM) with the second voltage level (VDDM) synchronously with the fourth signal (DT) with the first voltage level (VDD), and Generating the sixth signal (DCM) with the reference voltage level (VSS) synchronously with the first signal (DC) with the reference voltage level (VSS). [18] The method of claim 16 or 17, wherein both the coupling of the bit cell (110) to the first bit line (BL) and the coupling of the bit cell (110) to the second bit line (BLB) are performed in response to a signal based on the second voltage level (VDDM). [19] The method of any one of claims 14 to 18, further comprising precharging the first bit line (BL) to the first voltage level (VDD), wherein precharging the first bit line to the first voltage level comprises: generating the second signal (WT) having the reference voltage level (VSS) by the first logic gate (125) in response to the control signal (WD) having the first voltage level (VDD); Decoupling the first bit line (BL) from a reference voltage node having the reference voltage level (VSS) in response to the second signal (WT) having the reference voltage level (VSS); and Decoupling the first bit line (BL) from the power voltage node in response to the third signal (DTM) having the second voltage level (VDDM).

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