DATA PROTOCOL FOR MANAGING PERIPHERAL DEVICES

Abstract

Device comprising: - a connection module (100) defining one or more communication bus cables (123) that communicatively couple one or more peripheral devices (114) installed on a backplane (122) to an information handling device (102), - a data module (235) that reads, via each of the one or more communication bus cables (123), a data packet associated with a peripheral device (114), each data packet including one or more data fields that define an identifier for a position at which the peripheral device (114) is installed on the backplane (122), and - a topology module (240) that determines a cable connection configuration for the one or more communication bus cables (123) and the one or more peripheral devices (114) based on the installation position identifier received from each of the data packets associated with the one or more peripheral devices (114); - wherein the data packet further comprises one or more fields containing data describing one or more properties of a Storage Enclosure Processor (SEP) (115) located on the backplane (122).

Description

FIELD OF THE INVENTION

[0001] The subject matter disclosed herein relates to peripheral computing devices and, more particularly, to a data protocol for managing peripheral devices. STATE OF THE ART

[0002] Computing devices may include peripheral devices coupled to the computing device using one or more communication buses. These communication buses may be communication bus cables that communicatively couple peripheral devices to an information-handling device. Conventional communication bus architectures and protocols may not be capable of managing multiple peripheral devices coupled to an information-handling device using communication bus cables.

[0003] Publication US 5 523 747 A describes a cable management system that enables the routing of wired services between service lines and user lines. Each service line enters the cabling system at a service termination unit circuit card, which also contains part of a crosspoint switching matrix. Each user line enters the system via a line termination unit circuit card. The service termination unit circuit cards are all mounted to connectors on a first side of a midplane, and the line termination unit circuit cards are mounted to connectors on the other side of the midplane. Pins extending through the midplane interconnect the connectors so that any service line can be connected to any user line. A system controller card mounted on the midplane communicates with the circuit cards via a midplane bus.Each of the peripheral devices connected to the user lines is equipped with an identification device that stores a unique identification code and information characterizing the device.

[0004] Publication US 2015 / 0331894 A1 discloses a system and method for uniquely identifying a storage device in a series of storage devices of a storage system. A shelf identifier of a storage device shelf in which the storage device is installed is determined. A stack identifier associated with a connection of the storage device is also determined. The storage system creates a device name for the storage device based on the shelf identifier and the stack identifier.

[0005] Publication US 9 026 687 B1 discloses a controller comprising a communication interface configured to communicatively connect a host to a computer expansion bus configured for enumerating and configuring peripheral devices.

[0006] Publication US 6 615 297 B1 discloses a system and method for editing private settings of a peripheral device. The peripheral device has a data memory with setting data for public settings of the peripheral device and private settings of the peripheral device.

[0007] Publication US 2007 / 0118674 A1 discloses a system for enhancing Universal Serial Bus (USB) applications, comprising an upstream processor, a downstream processor, and a main controller. The upstream processor accepts standard USB signals from a USB host and autonomously delivers the responses required by the USB specification within the required timeframe. The downstream processor, which can be connected to USB-compatible devices, accepts the USB signals from the USB-compatible devices and delivers the responses required by the USB specification within the required timeframe. SUMMARY

[0008] It is an object of the present invention to enable improved management of peripheral devices.

[0009] This object is solved by the subject matter of main claim 1 and the independent claims 15 and 21, which define the present invention.

[0010] Preferred embodiments of the present invention are the subject of the subclaims.

[0011] The disclosed apparatus includes a connection module that defines one or more communication bus cables that communicatively couple one or more peripheral devices to an information handling device. The apparatus also includes a data module that reads a data packet associated with a peripheral device over each of the one or more communication bus cables. Each data packet includes an identifier for a location where the peripheral device is installed.

[0012] The device further includes a topology module that determines a cable connection configuration for the one or more communication bus cables and the one or more peripheral devices based on the installation position identifier received from each of the data packets associated with the one or more peripheral devices. In one embodiment, the topology module provides the cable connection configuration of the communication bus cable and the peripheral devices to a basic input / output system (BIOS).

[0013] In another embodiment, the device includes a notification module that sends a notification in response to the determined cable connection configuration not matching a predefined cable connection configuration. In some embodiments, the one or more peripheral devices are each installed in a drive bay of a backplane, and the identifier includes a bay identifier and an associated slot identifier of the drive bay. In various embodiments, the data packet includes a plurality of fields defining the identifier. The plurality of fields may include a bay identifier field and a slot identifier field.

[0014] In one embodiment, the data packet further includes one or more fields containing data describing one or more characteristics of a storage enclosure processor (SEP) of a backplane. In various embodiments, the apparatus includes a tuning module that dynamically modifies one or more performance characteristics of a field programmable gate array (FPGA) based on the one or more characteristics of the SEP. The FPGA may be communicatively coupled to the SEP and one or more peripherals of the backplane using a communication bus cable.

[0015] In some embodiments, the one or more properties for the SEP include a bit flag indicating whether the SEP supports data parity, a maximum clock speed of the SEP, a timeout parameter for polling the SEP, and / or a maximum number of peripherals supported by the SEP. In certain embodiments, the apparatus includes an attestation module that verifies an integrity of data contained in one or more fields of the data packet using a checksum, which may be included in a checksum field of the data packet.

[0016] In some embodiments, the device includes a transmission module that receives a Virtual Pin Port (VPP) command from a VPP-enabled processor. The VPP command may be intended for a peripheral device on a backplane identified by the installation position identifier. In another embodiment, the transmission module writes the VPP command to a corresponding field in the data packet and sends the data packet containing the VPP command to a Storage Enclosure Processor (SEP) on the backplane using a communication bus cable coupled to the SEP and associated with the intended peripheral device.

[0017] In some embodiments, the transmit module writes a parity value into a parity field of the data packet, which can be used by the SEP to confirm the integrity of data written to the data packet. In another embodiment, the VPP command includes one or more of a peripheral enable command, a peripheral disable command, and / or a peripheral activity indication toggle command. In some embodiments, the communication bus cable includes a Peripheral Component Interconnection express ("") cable. In various embodiments, the peripheral includes a Non-Volatile Memory express (NVMe) storage device.

[0018] A method includes determining one or more communication bus cables communicatively coupling one or more peripheral devices to an information handling device. The method further includes reading a data packet associated with a peripheral device over the one or more communication bus cables. Each data packet includes an identifier for a location where the peripheral device is installed. The method further includes determining a cable connection configuration of the one or more communication bus cables and the one or more peripheral devices based on the installation location identifier received from each of the data packets associated with the one or more peripheral devices.

[0019] The method, in one embodiment, includes providing the cable connection configuration of the communication bus cable and the peripheral device to a Basic Input / Output System (“BIOS”) and sending a notification in response to the determined cable connection configuration not matching a predefined cable connection configuration.

[0020] In one embodiment, the one or more peripheral devices are each installed in a drive bay of a backplane, the identifier includes a bay identifier and an associated slot identifier of the drive bay, and the data packet includes a plurality of fields defining the identifier. The plurality of fields may include a bay identifier field and a slot identifier field.

[0021] In certain embodiments, the method includes dynamically modifying one or more performance characteristics of a field programmable gate array ("FPGA") based on one or more characteristics of a storage enclosure processor ("SEP") of a backplane. The FPGA may be communicatively coupled to the SEP and one or more peripherals of the backplane via a communication bus cable. The data packet may further include one or more fields containing data describing the one or more characteristics of the SEP.

[0022] In some embodiments, the method further includes receiving a Virtual Pin Port ("VPP") command from a VPP-enabled processor. The VPP command may be intended for a peripheral device on a backplane identified by the installation position identifier. The method may further include writing the VPP command to a corresponding field in the data packet and sending the data packet containing the VPP command to a Storage Enclosure Processor ("SEP") on the backplane using a communication bus cable coupled to the SEP and associated with the intended peripheral device.

[0023] A program product includes a computer-readable storage medium storing code executable by a processor. The executable code includes code for performing a process of determining one or more communication bus cables that communicatively couple one or more peripheral devices to an information handling device. The executable code includes code for performing a process of reading a data packet associated with a peripheral device over each of the one or more communication bus cables. Each data packet includes an identifier for a location where the peripheral device is installed.The executable code includes code for performing a determination of a cable connection configuration for the one or more communication bus cables and the one or more peripheral devices based on the installation position identifier received from each of the data packets associated with the one or more peripheral devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The embodiments briefly described above will be described in more detail with reference to specific embodiments illustrated in the accompanying drawings. While understanding that these drawings represent only some embodiments and are therefore not to be considered limiting, the embodiments will be described and explained in greater detail and specificity with reference to the accompanying drawings. In the drawings: Fig.1A is a schematic block diagram illustrating one embodiment of a system for managing peripheral devices using a data protocol; Fig. 1B is a schematic block diagram illustrating an embodiment of another system for managing peripheral devices using a data protocol; Fig. 1C is a schematic block diagram illustrating an embodiment of another system for managing peripheral devices using a data protocol, Fig. 2 is a schematic block diagram illustrating an embodiment of an apparatus for managing peripheral devices using a data protocol; Fig. 3 is a schematic block diagram illustrating an embodiment of another apparatus for managing peripheral devices using a data protocol; Fig.4 is a schematic flow diagram illustrating an embodiment of a method for managing peripheral devices using a data protocol; and Fig. 5 is a schematic flow diagram illustrating an embodiment of another method for managing peripheral devices using a data protocol. DETAILED DESCRIPTION

[0025] As will be understood by those skilled in the art, aspects of the embodiments may be implemented as a system, method, or program product. Accordingly, embodiments may take the form of an all-hardware embodiment, an all-software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which are referred to generally herein as a "circuit," "module," or "system." Furthermore, embodiments may take the form of a program product embodied in one or more computer-readable storage devices storing machine-readable code, computer-readable code, and / or program code, hereinafter referred to as code. The storage devices may be tangible, non-transitory, and / or non-transmitting. The storage devices may not embody signals.In one embodiment, the storage devices use signals only to access code.

[0026] Many of the functional units described in this specification have been labeled as modules to more clearly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising common VLSI circuits or gate arrays, standard semiconductors such as logic chips, transistors, or other individual components. A module may also be implemented in programmable hardware devices, such as field-programmable gate arrays, programmable array logic, programmable logic devices, or the like.

[0027] Modules may also be implemented in code and / or software for execution by different types of processors. For example, an identified module of code may comprise one or more physical or logical blocks of executable code, organized, for example, as an object, a flow, or a function. However, the executable instructions of an identified module need not be physically located together, but may comprise quite distinct instructions stored in different locations that, when logically combined, constitute the module and fulfill the module's stated purpose.

[0028] Indeed, a module of code may comprise a single instruction or many instructions, and may even be distributed across several different code segments, among different programs, and across multiple storage devices. Likewise, operational data may be identified and distributed within modules herein, and these may be implemented in any suitable form and organized in any suitable type of data structure. The operational data may be aggregated as a single set of data or may be distributed across various locations, including across different computer-readable storage devices. Where a module or portions of a module are implemented in software, the software portions are stored on one or more computer-readable storage devices.

[0029] Any combination of one or more computer-readable media may be used. The computer-readable medium may be a computer-readable storage medium. The computer-readable storage medium may be a storage device that stores the code. The storage device may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, holographic, micromechanical, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.

[0030] More specific examples (a non-exhaustive list) of the storage device would include: an electrical connection comprising one or more wires, a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium capable of containing or storing a program for use by or in connection with an instruction execution system, apparatus, or device.

[0031] Code for performing operations for embodiments may be written in any combination of one or more programming languages, including an object-oriented programming language such as Python, Ruby, Java, Smalltalk, C++, or the like, and conventional procedural programming languages such as the "C" programming language or the like, and / or machine languages such as assembly languages. The code may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server.In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, over the Internet using an Internet service provider).

[0032] Reference throughout the specification to "one embodiment" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrase "in an embodiment" and similar language throughout the specification may, but does not necessarily, refer to the same embodiment, but rather means "one or more, but not all, embodiments" unless otherwise specified. The terms "including," "comprising," "having," and variations thereof mean "including, but not limited to," unless otherwise specified. A list of elements does not imply that some or all of the elements are mutually exclusive unless otherwise specified.The terms “a” and “the” also refer to “one or more” unless otherwise specified.

[0033] Furthermore, the described features, structures, or characteristics of the embodiments may be combined in any suitable manner. In the following description, numerous specific details are provided, such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., in order to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that embodiments may be practiced without one or more of the specific details, or with different methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of an embodiment.

[0034] Aspects of the embodiments are described below with reference to schematic flow diagrams and / or schematic block diagrams of methods, apparatus, systems, and program products according to the embodiments. It should be understood that each block of the schematic flow diagram and / or schematic block diagram, and combinations of blocks in the schematic flow diagrams and / or schematic block diagrams, may be implemented by code.This code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine such that instructions executing via the processor of the computer or other programmable data processing device produce means for implementing the functions / acts specified in the block(s) of the schematic flowchart and / or schematic block diagram.

[0035] The code may also be stored on a storage device that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner such that the instructions stored in the storage device produce an article of manufacture, including instructions that implement the function / act specified in the block(s) of schematic flow diagrams and / or schematic block diagrams.

[0036] The code may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process, such that the code executing on the computer or other programmable data processing apparatus provides processes for implementing the functions / acts specified in the block(s) of the schematic flow diagrams and / or the schematic block diagrams.

[0037] The schematic flowcharts and / or schematic block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of devices, systems, methods, and program products according to various embodiments. In this regard, each block in the schematic flowcharts and / or schematic block diagrams may represent a module, segment, or portion of code that includes one or more executable instructions of code for implementing the specified logical function(s).

[0038] It should also be noted that in some alternative implementations, the functions specified in the blocks need not occur in the order shown in the figures. For example, two blocks shown in succession may actually execute substantially concurrently, or the blocks may sometimes execute in reverse order, depending on the associated functionality. Other steps and methods may be devised that are equivalent in function, logic, or effect to one or more of the blocks, or portions thereof, shown in the figures.

[0039] Although various types of arrows and lines have been used in the flow and / or block diagrams, these are not intended to limit the scope of the corresponding embodiments. Indeed, some arrows or other connecting elements may be used solely to indicate the logical flow of the depicted embodiment. For example, an arrow may indicate a wait or monitoring period of indefinite duration between enumerated steps of the depicted embodiment. It should also be noted that each block of the block diagrams and / or flow diagrams, and combinations of the blocks of the block diagrams and / or flow diagrams, may be implemented by special-purpose hardware-based systems that perform the specified functions or acts, or by combinations of special-purpose hardware and code.

[0040] The description of elements in each figure may refer to elements in preceding figures. Throughout the figures, like reference numerals indicate like elements, including alternative embodiments of like elements.

[0041] Fig.1A illustrates one embodiment of a system 100 for managing peripheral devices using a data protocol. In one embodiment, the system 100 includes an information handling device 102. The information handling device 102 may include a desktop computer, a laptop, a tablet, a smartphone, a set-top box, a game console, a smart TV, a smart watch, a fitness tracker or other wearable activity tracking device, an optical head-mounted display (e.g., a virtual reality headset, data glasses, or the like), a personal digital assistant, or other computing device that includes a processor 104, a volatile memory 108, and / or a non-volatile storage medium, which may be implemented as at least one of the peripheral devices 114a-n.

[0042] The processor 104 may include one or more central processing units (CPUs), one or more processor cores, a field programmable gate array (FPGA) or other programmable logic, an application-specific integrated circuit (ASIC), a controller, a microcontroller, and / or another semiconductor integrated circuit device. The processor 104 may include firmware used to perform hardware initialization during the boot process, such as from a basic input / output system (BIOS) 106. The BIOS 106, in one embodiment, may include an instance of Unified Extensible Firmware Interface (UEFI) firmware.

[0043] The system 100, in certain embodiments, includes one or more peripheral devices 114a-n (collectively, 114). The peripheral devices 114, as used herein, may include internal and / or external devices that provide input and / or output to the information handling device 102. For example, the peripheral devices 114 may be implemented as storage devices (e.g., non-volatile memory (NVM) devices, NVM-express (NVMe) devices, solid-state storage (SSSD) devices, and / or the like), flash memory devices, network cards, graphics cards, and / or the like.

[0044] In one embodiment, the peripheral devices 114 are connected to the information handling device 102 via a backplane 122. As used herein, the backplane 122 may be implemented as a printed circuit board (PCB) that includes a plurality of slots 117a-n (collectively 117), connectors, and / or the like for connecting a plurality of peripheral devices 114 or other printed circuit boards to the backplane 122. The backplane 122 may, for example, include a plurality of slots 117, cable connections (e.g., data bus 116 and / or management bus cable connections 118), and / or other types of connectors for connecting the NVMe storage devices to the information handling device 102. As used in Fig.1A, the backplane 122 may be enclosed in a separate device or enclosure, such as a separate storage enclosure, e.g., a storage rack, coupled to the information handling device 102 via one or more communication bus cables 123a-n (collectively, 123). In some embodiments, the backplane 122 is enclosed within the information handling device 102.

[0045] As used herein, a slot 117 on the backplane 122 may be an access point, connector, slot, or the like for connecting a communication bus cable 123 from the information handling device 102. The slot 117 may be configured for various types of communication bus cables 123, such as PCIe communication bus cables 123. Slots 117 may be identified, accessed, referenced, or the like using a slot identifier. The slot identifier may be globally unique to a slot 117, unique to a slot 117 based on a backplane 122, or the like. The slot identifier may be used, at least in part, to access a peripheral device 114 communicatively coupled to the communication bus cable 123 connected to the slot 117.

[0046] In some embodiments, the backplane 122 includes drive bays 121a-n (collectively 121) in which peripheral devices 114 can be installed, attached, mounted, and / or the like. For example, a drive bay 121 can be configured for mounting an NVMe storage device to the backplane 122. In some embodiments, each bay 121 is identified with an identifier that can be unique to the backplane 122, globally unique, and / or the like. If the bay identifier is unique to the backplane 122, in one embodiment, accessing a peripheral device 114 installed in a bay 121 may also require an identifier of the backplane 122 to ensure that the correct peripheral device 114 on the correct backplane 122 is accessed.In some embodiments, the slot identifier and the bay identifier are used to access a peripheral device 114 that is installed in the bay 121 identified by the bay identifier and communicatively coupled to the communication bus cable 123 connected to the slot 117 identified by the slot identifier.

[0047] In certain embodiments, the peripheral devices 114 are communicatively connected to the processor 104 using one or more communication bus cables 123. The communication bus cables 123 may include a data bus cable corresponding to a data bus 116a-n (collectively, 116) on the backplane 122, which may be implemented as a cable, a data line of a PCB of the backplane 122, and / or the like. The data bus cable and the corresponding data bus 116 on the backplane 122 may be used to perform input / output operations (e.g., transferring data) between the processor 104 and the peripheral devices 114.In certain embodiments, the data bus cable and / or the data bus 116 is a Peripheral Component Interconnect (PCI) bus, a PCI Extended (“PCI-X”) bus, an Accelerated Graphics Port (“AGP”) bus, a PCI Express (“PCIe”) bus, a Universal Serial Bus (“USB”), a Serial Advanced Technology Attachment (“SATA”) bus, and / or the like.

[0048] In some embodiments, each peripheral device 114 is coupled to the processor 104 via a separate data bus cable and / or data bus 116. For example, there may be a 1:1 relationship between the peripheral devices 114 and the data bus cables and / or data buses 116, such that each peripheral device 114 is coupled to the information handling device 102 via a separate and independent data bus cable and / or data bus 116.

[0049] In one embodiment, the communication bus cable 123 includes a management bus cable that corresponds to a management bus 118 on the backplane 122 and that may be implemented as a cable, as a data line of a PCB of the backplane 122, and / or the like. In one embodiment, a management bus 118 is configured to transmit management messages from the processor 104 via a management bus cable to the peripheral devices 114 and vice versa. A management bus 118 may be implemented as an Inter-Integrated Circuit ("I 2C") communication bus. Management messages may include messages that control a state of the peripheral device 114, such as power on / off, enable / disable, standby, reset, and / or the like. For example, an operating system running on the information handling device 102 may send a management message via a management bus cable and management bus 118 to a storage device connected to the information handling device 102 via a PCIe cable.

[0050] In some embodiments, each management bus cable and / or management bus 118 is communicatively connected to a single corresponding peripheral device 114. In such an embodiment, a 1:1 relationship may exist between management bus cables and / or management buses 118 and peripheral devices 114, such that each peripheral device 114 is connected to the information handling device 102 via a separate and independent management bus cable. Referring to Fig. 1A, each management bus connection 124a-n (collectively, 124) for the peripheral devices 114 may be associated with a separate and dedicated management bus 118 corresponding to a separate management bus cable. For example, each peripheral device 114 may be coupled to a corresponding management bus cable, rather than using a single management bus cable to manage multiple peripheral devices 114.

[0051] In another embodiment, a 1:n or 1:many relationship may exist between a management bus cable, a management bus 118, and a plurality of peripheral devices 114. In such an embodiment, a management bus 118 may include a plurality of management bus connections 124, each connectable to a peripheral device 114 and addressable using an identifier, a unique address (e.g., an address for the management bus connection 124, an address for a peripheral device 114, or the like), and / or the like.

[0052] In one embodiment, a management bus 118 is connected to a storage enclosure processor ("SEP") 115 of the backplane 122. As used herein, an SEP 115 may be a processor located on the backplane 122 to manage peripheral devices 114 on the backplane 122. For example, the SEP 115 may manage the management bus connections 124 for the management bus 118 to communicate management messages between the information handling device 102 and the peripheral devices 114 on the backplane 122 using a management bus cable and based on a unique address for the management bus connection 124 and / or the peripheral device 114.

[0053] For example, an operating system for the information handling device 102 may send a reset command to a peripheral device 114 by providing an identifier or address to the peripheral device 114 and / or the management bus connection 124 of the management bus 118. In one such example, the SEP 115 may use the provided identifier or address to send the reset command to the peripheral device 114 associated with the identifier or address. In another example, the SEP 115 may translate, map, or otherwise cross-reference the provided identifier or address to another identifier or address used to communicate with the peripheral device 114 on the backplane 122.

[0054] As used herein, a management connection between the processor 104, a data protocol device 110, or the like, and a peripheral device 114 is known as a management bus connection 124, whether a single management bus cable and / or a single management bus 118 is connected to each peripheral device 114 (e.g., one management bus connection 124 per management bus cable / management bus 118) or whether a single management bus cable and / or a single management bus 118 is connected to multiple peripheral devices 114 (e.g., multiple addressable management bus connections 124 per management bus cable / management bus 118).

[0055] The baseboard management controller (BMC) 113, in one embodiment, is a dedicated hardware component of the information handling device 102 used to manage the interface between system management software, such as the BIOS 106, an operating system, or other management software, and platform hardware, such as the peripherals 114, using a system management bus 119. For example, the BMC 113 may manage the communication of management messages between the processor, the BIOS 106, the cable management device 110, an operating system, and / or the like, and the peripherals 114, the SEP 115, and / or the like.

[0056] The bridge or switch 112, in one embodiment, connects the peripheral devices 114 to the processor 104 and / or the cable management device 110 via the communication bus cables 123. The bridge 112 may act as a switch and transfer data and / or management commands between the processor 104 and the corresponding peripheral devices 114 using the communication bus cables 123 (e.g., a data bus cable, a management bus cable, or a combined data bus / management bus cable). In certain embodiments, multiple bridges 112 may be located in the information handling device 102, with each bridge 112 connected to one or more peripheral devices 114 of one or more backplanes 122.

[0057] The data protocol device 110, in one embodiment, is configured to determine one or more properties associated with a peripheral device 114, a backplane 122, an SEP 115, and / or the like by reading a predefined data packet that includes one or more fields for the various properties. The data protocol device 110 is configured to determine one or more communication bus cables 123 that communicatively couple one or more peripheral devices 114 to an information handling device 102, read a data packet associated with a peripheral device 114 via a communication bus cable 123, and determine a cable connection configuration for the one or more communication bus cables 123 and the one or more peripheral devices 114 based on the properties included in the data packet read via the communication bus cable 123.In some embodiments, at least a portion of the data protocol device 110 is located on the processor 104, on the backplane 122, on the BMC 113, on the SEP 115, and / or the like. The data protocol device 110 is further described with reference to FIG. Fig. 2 and Fig. 3 described in more detail.

[0058] In one embodiment, information handling device 102 is connected to a data network 120. Data network 120, in one embodiment, includes a digital communications network that conveys digital communications. Data network 120 may include a wireless network, such as a cellular network, a local wireless network such as a Wi-Fi network, a Bluetooth® network, a short-range communication (NFC) network, an ad hoc network, and / or the like. Data network 120 may be a wide area network (WAN), a storage area network (SAN), a local area network (LAN), a fiber optic network, the Internet, or another digital network. Data network 120 may include two or more networks. Data network 120 may include one or more servers, routers, circuits, and / or other network equipment.The data network 120 may also include one or more computer-readable storage media, such as a hard disk drive, an optical drive, non-volatile memory, RAM, or the like.

[0059] In one embodiment, information handling device 102 is connected to one or more other computing devices 130 / 132 via data network 120. Other computing devices 130 may include, for example, smartphones, tablets, laptops, and / or the like. In another embodiment, other computing devices 132 may include servers, other devices in a data center located on local or external data network 120, and / or the like.

[0060] Fig.1B illustrates one embodiment of a “directly attached” system 150 for managing peripheral devices using a data protocol. In one embodiment, the system 150 includes elements substantially similar to elements described above with respect to Fig. 1A. The System 150 of Fig. 1B includes, in one embodiment, two separate processing units 202a-b (collectively, 202), each communicatively coupled to peripherals 114 on respective backplanes 122a-b (collectively, 122). Each processing unit 202 may include one or more processors 104, processor cores and / or the like, memory elements (e.g., registers), and / or the like.

[0061] Each processing unit 202 may be communicatively coupled to the peripheral devices 114 on each corresponding backplane 122 and to one or more data buses 216a-b (collectively 216) on the information handling device 102, e.g., on the motherboard or other PCB of the information handling device 102, and to one or more data buses 116 on the backplanes 122 using a communication bus cable 123 described above. A processing unit 202 may send various commands, data, instructions, and / or the like to the peripheral devices 114 using the communication buses 123 and / or the data buses 216, 116. For example, a processing unit 202 may send a read request command, a write request command, or the like to an NVMe peripheral storage device located at slot ID 10 and bay ID 62 on the backplane 122.

[0062] In another embodiment, each processing unit 202 is communicatively coupled to a Field Programmable Gate Array (FPGA) 204 or another programmable logic device, such as an application-specific integrated circuit (ASIC) or the like. In one embodiment, a processing unit 202 is configured to communicate with the processor using an I 2C communication bus, an SHP management bus, and / or some other serial communication bus. The FPGA 204 may be communicatively coupled to a backplane 122, and in particular to an SEP 115 and / or a peripheral device 114 located on the backplane 122, by means of one or more communication bus cables 123 and / or one or more management buses 218a-b (collectively, 218) located on the information handling device 102 and one or more management buses 118 located on the backplanes 122.

[0063] The FPGA 204, as used herein, may communicate, transmit, send / receive, or the like, data, information, commands, etc., between the processing units 202 and / or the data protocol device 110 on the information handling device 102 and the SEP 115 and / or the peripheral devices 114 on the backplane 122. For example, the FPGA 204 may communicate with the SEP 115 on a backplane 122 using a dedicated communication bus cable 123 to read a data packet including a slot ID and a bay ID for the peripheral device 114 coupled to the communication bus cable 123. In such an embodiment, the FPGA 204 may be configured as a bus master, and each SEP 115 on each backplane 122 may be configured as a bus slave.In such a master / slave configuration, the FPGA 204, acting as the bus master, forwards commands, data packets, information, or the like, via the communication bus cables 123 to the SEPs 115, which serve as bus slaves and are provided for one or more peripheral devices 114. The FPGA 204 can also request or read data packets from the SEPs 115 via various communication bus cables 123. In such an embodiment, each peripheral device 114 is configured as a slave device.

[0064] The FPGA 204 may track, store, capture, and / or the like the slot ID and bay ID information associated with each communication bus cable 123 and each peripheral device 114 coupled to the communication bus cable 123. In such an embodiment, the FPGA 204 may provide, send, or otherwise make available the slot ID and bay ID information for each peripheral device 114, including the communication bus cables 123 coupled to each peripheral device 114, to an operating system for the information handling device 102, to the BIOS 106, and / or the like. In certain embodiments, the management buses 118, 218 coupled to the FPGA 204 and the SEP 115 include SHP management buses.

[0065] In certain embodiments, the information handling device 102 or the motherboard of the information handling device 102 includes one or more slots 220a-n (collectively, 220) configured to receive a communication bus cable 123 coupled to a corresponding slot 117 on the backplane 122. The slot 220 may be identified using a slot ID, a PCIe lane identifier, and / or the like.

[0066] In one embodiment, each processing unit 202 is communicatively coupled to a platform controller hub (PCH) 206, which is configured to control data paths, such as data buses 216, and manage various functions offloaded from processing units 202, such as clocking. In some embodiments, processing units 202 use PCH 206 to send various data and management commands to peripherals 114 via FPGA 204. In such an embodiment, PCH 206 may be coupled to FPGA 204 using a communication bus 222, which may be implemented as an Enhanced Serial Peripheral Interface ("eSPI") bus.

[0067] In some embodiments, the data protocol device 110 is also coupled to the FPGA 204 via a communication bus 212 to perform the various functions of the data protocol device 110, as will be described in more detail below. Furthermore, the BMC 113 may also be coupled to the FPGA 204 via a communication bus 214 to manage the interface between system management software, such as the BIOS 106, an operating system, or other management software, and the peripherals 114, the SEP 115, and / or the like.

[0068] Fig. 1C illustrates one embodiment of a "switched" system 175 for managing peripheral devices using a data protocol. In one embodiment, the system 175 includes elements substantially similar to elements described above with reference to Fig. 1A and Fig.1B. In one embodiment, the system 175 includes a plurality of switching adapters 302a-b (collectively, 302) similar to the one described above with reference to Fig. 1A are similar to the switch 112 described.

[0069] Each switching adapter 302 may be configured to manage and communicate between each processing unit 202, the data protocol device 110, the BMC 113, or the like, and each peripheral device 114 of a backplane 122. For example, a processing unit 202 may provide data or management commands for a particular peripheral device 114 to a coupled switching adapter 302 via a communication bus 306a-b coupled to a communication bus port 304a-b of the switching adapter 302. The switching adapter 302 may forward or transmit the command to a particular peripheral device 114. The peripheral device 114 may be identified using a unique address, a slot ID, a bay ID, and / or the like. Based on the identifier, the switching adapter 302 can determine which communication bus cable 123 is coupled to the identified peripheral device 114.

[0070] Fig.2 illustrates an embodiment of an apparatus 200 for managing peripheral devices using a data protocol. The apparatus 200 includes an embodiment of a data protocol apparatus 110. The data protocol apparatus 110 includes a connection module 230, a data module 235, and a topology module 240, which are described in more detail below.

[0071] The interconnect module 230 determines one or more communication bus cables 123 that communicatively couple one or more peripheral devices 114 to an information handling device 102. In one embodiment, the interconnect module 230 may send a command over each communication bus cable 123 to determine which communication bus cable 123 is coupled to a peripheral device 114. In another embodiment, the BIOS 106 may perform a system check at system boot to determine which peripheral devices 114 are present and coupled to the information handling device 102 via a communication bus cable 123. The interconnect module 230 may build, create, manage, maintain, and / or the like a table for peripheral devices 114 connected to the information handling device 102 and the associated communication bus cables 123 coupled to the particular peripheral devices 114.

[0072] The data module 235 reads a data packet associated with a peripheral device 114 over each of the one or more communication bus cables 123. The data packet may include one or more data fields containing data, information, or the like for a peripheral device 114, for a backplane 122, for an SEP 115 of a backplane 122, and / or the like. The following Table 1 illustrates an example data packet for a protocol for managing peripheral devices 114. Table 1. NVMe register set Offset bit definition Details I2C Master (R / W) NVMe device ID 0 7 I2C slave device not ready Set to '1' if the I2C slave device is being configured and is not fully operational; otherwise, set to '0'. The master will poll this register to '0'. Offset Read only 1-9 is invalid when set to '1'. 6 Hard-coded to 4Eh ASCII 'N' for NVMe. Caution: This register is invalid even if NVMe Device ID bit 7 is '1'. 5 4 3 2 1 0 Version register 1 7 I2C slave device version in BCD The version should be represented in binary-coded decimals. For example, an I2C slave device version of ten is written as 10h. Read only 6 5 4 3 2 1 0 Skills Register 2 2 7 Reserved Reserved as Fh Read only 6 5 4 3 I2C master read timeout Defines the amount of time the NVMe I2C master must wait before reading the register set again. Encoded as 0h=0 s, 1h=50 ms, 2h=100 ms. Others reserved. 2 1 Dataparity Set to '1' if the I2C slave device support Data parity in the "Control / Status Register 0" register is supported and the "Payload Checksum" is valid. 0 I2C slave device bus speed capability Set to '1' if the I2C slave device supports 400 kHz (preferred), otherwise '0' for 100 kHz. A value of '1' does not imply that the master must run at 400 kHz. Skills register 3 7 Reserved Reserved as 1Fh Read only 6 5 4 3 2 Backplane type Indicates the type of backplane: 0h = NVMe only, 1h = NVMe + SAS, 2h = SAS only, others reserved 1 0 Skills Register 0 4 7 Total NVMe device support Number of NVMe devices supported by the I2C slave device. Encoded as 1h=1 total drive, FFh=225 total drives. This is Read only 6 5 4 3 2 1 0 calculated based on the number of I2C masters the I2C slave device sees. Control / Status Register 3 5 7 Slot ID Slot ID of the NVMe device. Since the NVMe is actually a PCIe slot, this defines the slot ID that the operating system will use. Read only 6 5 4 3 2 1 0 Control / Status Register 2 6 7 Shaft ID Bay ID of the NVMe device. Note that the bay ID is the physical location of the slot at the front of the system and will be the same as the SAS bay ID. Read only 6 5 4 3 2 1 0 Control / Status Register 1 7 7 Reserved Reserved as Fh Read only 6 5 4 3 IFDET_# State of the IFDET signal. For NVMe, this is '0'. 2 HP_PRESENT # State of the drive presence signal. For NVMe, this is '1'. 1 Auto-configuration status Set to '1' if BMC has set the port ID values, otherwise '0'. 0 HP_PWR_LED# NVME power LED (e.g., green) slightly active. A read reflects the state of the pin on the I2C slave device. Default '1'. Control / Status Register 0 8 7 Data parity If parity is not supported (see Capability Register 2 Bit 1), this bit is reserved as '1'. For I2C master reading, this bit reflects the SUM of bits 6 through 0 of Control / Status Register 0. For I2C master writing, the parity bit set by the master covers bits 6 through 0. If there is no parity match, the data is discarded. Reading / Writing 6 Reserved Reserved for 3 hours Read only 5 4 Device Scratchpad Scratch pad of the I2C master. Default '0'. Reading / Writing 3 HP_PERST# NVMe device zeroing active is low. A read value reflects the value of the last I2C master write to this position. Default '1'. 2 HP_ATN_LED Blink Rate Register Coded: 0h=0 Hz (fixed), 1h=1 Hz, 2h=2 Hz, 3h=4 Hz. The I2C master must enforce HP_ATN_LED# to activate the LED. Defaults to '0'. 1 0 HP_ATN_LED# NVMe Attention LED (e.g., amber) active low. A read value reflects the value of the last I2C master write to this location. Default '1'. Payload checksum 9 7 Checksum from byte 0 to byte 7 (e.g. contains Byte 0 + Byte 1 + ... + Byte 6 + Byte 7 Read only 6 5 4 3 2 this is not byte 8) 1 0

[0073] As shown in Table 1, each data packet includes one or more data fields containing information defining an identifier for a location where the peripheral device 114 is installed. For example, the data packet may include a data field for data identifying a bay ID that identifies a drive bay 121 where a peripheral device 114 is installed, and a data field for data that identifies a slot 117 connected to the communication bus cable 123 that is communicatively coupled to the peripheral device 114.

[0074] In another embodiment, the data packet further includes one or more fields containing data describing one or more characteristics of a SEP 115 of a backplane 122. In some embodiments, the data packet includes a bit switch indicating whether the SEP 115 supports data parity. For example, the FPGA 204 may write data to one or more writable fields of the data packet, including a parity data field containing parity data for the SEP 115 to be used to assert the integrity of the written data if the SEP 115 supports data parity, as indicated by the parity bit switch in the data packet.In such an example, the FPGA 204 may first retrieve a data packet for a particular peripheral device 114 from the SEP 115, read the parity data field, and include a parity bit along with the data of the data packet written to the other writable data fields before sending the data packet to the SEP 115.

[0075] In another example, the data packet may include a data field that includes data indicating a maximum, minimum, average, median, or the like clock speed of the SEP 115. In another example, the data packet may include a data field that includes data indicating a timeout parameter that defines a period of time before the data module 235 re-polls the SEP 115 for a data packet in response to not receiving a response from the SEP 115. In another example, the data packet may include a data field that indicates a maximum number of peripheral devices 114 supported by the SEP 115, the backplane 122 on which the SEP 115 is disposed, and / or the like.Additional data included in the data packet may include an identifier for the peripheral device 114, the backplane 122, the SEP 115, and / or the like, version information for the peripheral device 114, the backplane 122, the SEP 115, and / or the like, state information for the peripheral device 114 (e.g., active, enabled, disabled, or the like), a checksum for one or more data fields that may be used to confirm the integrity of one or more data fields, and / or the like. In certain embodiments, described in more detail below, the FPGA 204 tunes one or more performance characteristics based on the characteristics of the SEP 115, the peripheral devices 114, the backplane 122, and / or the like, as determined from the data included in the received data packet.

[0076] The topology module 240 determines a cable connection configuration for the one or more communication bus cables 123 and the one or more peripheral devices 114 based on the installation position identifier received from each of the data packets associated with the one or more peripheral devices 114. For example, the topology module 240 may generate a table of paths from the communication bus cables 123 to the corresponding installation position identifiers, such as the slot IDs and bay IDs of the peripheral devices 114 to which the communication bus cables 123 are communicatively coupled.

[0077] In one embodiment, the table of paths is implemented as an Advanced Configuration and Power Interface (ACPI) table. As used herein, an ACPI is a type of interface that enables an operating system to directly configure and manage hardware components. In such an embodiment, the topology module 240 provides the path table describing the cable connection configuration of the communication bus cables 123 and the peripheral devices 114 to the BIOS 106, the operating system of the information handling device 102, and / or the like. In another embodiment, the BIOS 106 and / or the operating system may use the ACPI table to program, assign, or otherwise associate a PCIe port on the information handling device 102 (e.g., on the motherboard) and / or on the backplane 122 with the identifier, e.g., the slot ID for a slot 117, received in the data packet.

[0078] In this manner, the data protocol device 110 provides a data packet or protocol for sending and receiving data describing various conditions, properties, statuses, and / or the like for peripheral devices 114, SEPs 115, backplanes 122, and / or the like in a system 100 / 150 / 175 that uses communication bus cables 123 to connect various peripheral devices 114 to an information handling device 102, as opposed to direct physical connections, e.g., communication bus lines on a circuit board between a processor 104 and a PCIe slot into which a peripheral device 114 is inserted. Accordingly, the processor 104, the FPGA 204, the BMC 113, the operating system, and / or other components of the information handling device 102 may be dynamically tuned to the characteristics of the peripherals 114, the backplane 122, the SEP 115, and / or the like.Additionally, the data logging device 110 may provide information, notifications, alerts, messages, and / or the like to the BIOS 106, the operating system, an end user, and / or the like to indicate a condition of the system 100 / 150 / 175, such as whether there is an issue, error, problem, or the like with the communication bus cable configuration between the information handling device 102 and one or more peripheral devices 114 of the backplanes 122.

[0079] Fig.3 illustrates an embodiment of an apparatus 300 for managing peripheral devices using a data protocol. The apparatus 300 includes an embodiment of a data protocol apparatus 110. The data protocol apparatus 110 includes a connection module 230, a data module 235, and a topology module 240, which are substantially similar to the connection module 230, the data module 235, and the topology module 240 described above with reference to Fig. 2. In one embodiment, the data protocol device 110 includes one or more notification modules 310, a voting module 315, a confirmation module 320, and a transmission module 325, which are described in more detail below.

[0080] In one embodiment, the notification module 310 sends a notification in response to the determined cable connection configuration not matching the predefined cable connection configuration. In certain embodiments, a specific system 100 / 150 / 0175 may include a recommended cable connection configuration between the information handling device 102 and one or more peripheral devices 114 of the backplanes 122, which defines a required or recommended cable connection topology, e.g., which communication bus cables 123 should be connected to which installation positions, e.g., which slots 117 and bays 121 for peripheral devices 114 on a backplane 122.

[0081] The notification module 310 sends a notification based on a determination that the particular communication bus cable configuration does not match the predefined communication bus cable configuration to warn or inform the BIOS 106, the operating system, the FPGA 204, an end user, and / or the like that the particular communication bus cable configuration is incorrect or configured in a manner other than recommended.

[0082] In one embodiment, the topology module 240 determines whether the determined communication bus cable configuration matches the predefined communication bus cable configuration by comparing data in the path table of installation position identifiers to the communication bus cables connected to the identifier installation position with a predefined path table of substantially similar installation position identifiers to communication bus cable paths. In certain embodiments, the notification module 310 sends various notifications based on information received in the data packet, including information regarding the states of the peripheral devices 114, the number of peripheral devices 114 present and / or active / disabled, and / or the like.

[0083] In one embodiment, the tuning module 315 dynamically modifies one or more performance characteristics of the FPGA 204 based on the one or more characteristics of the SEP 115. For example, the tuning module 315 may change how often the FPGA polls the SEP 115 for a data packet for a peripheral device 114 based on the data in the timeout field of the data packet. In another example, the tuning module 315 may tune the rate at which commands are sent to the SEP 115 from the FPGA 204 or the processor 104 via the FPGA 204 based on the clock speed of the SEP 115, whether the SEP 115 is currently active or not, the capabilities of the backplane 122 (e.g., the type of backplane 122, the communication bus speeds on the backplane 122, or the like), and / or the like.

[0084] In one embodiment, the confirmation module 320 checks or confirms the integrity of data contained in one or more fields of the data packet using a checksum. In some embodiments, the checksum is included in a checksum field of the data packet. For example, the SEP 115 may populate each data field of the data packet with data, generate a checksum using the data in the data packet, and store the checksum in the checksum field of the data packet. Accordingly, when the data module 235 receives the data packet over a communication bus cable 123, the confirmation module 320 uses the checksum to confirm that the data (e.g., the bay ID and slot ID, the capability data of the SEP 115 and / or the backplane 122, and / or the like stored in the data packet) is not corrupted, does not contain errors, and / or the like.

[0085] In one embodiment, the transmission module 325 receives a virtual pin port ("VPP") command from a VPP-enabled processor 104 or a processor 104 configured to send and receive commands over a VPP sideband connection. As used herein, a VPP may include a serial bus-based connection for peripheral devices 114, such as hot-pluggable PCIe NVMe devices. The VPPs may be part of an input / output hub of the processor 104, e.g., a VPP-enabled Intel® chipset, and may be configured to serially shift the hot-pluggable PCIe sideband signals.

[0086] The VPP architecture is designed for interfacing with peripheral devices 114 located in mechanically fixed slots, such as physical PCIe slots on a motherboard, and may not extend to interfacing with peripheral devices 114 connected to the processor 104 via communication bus cables 123. For example, the VPP architecture may provide support for activating a peripheral device 114, determining whether a drive is present in a particular physical slot, and / or controlling the activity indicator LED on the peripheral device 114.However, in systems 100 / 150 / 175 that use communication bus cables 123 to couple a processor 104 to one or more peripheral devices 114, the VPP architecture does not have the capabilities to fully manage peripheral devices 114 installed on a backplane 122 and connected to a processor 104 using one or more communication bus cables 123.

[0087] For example, if communication bus cables 123 are swapped and connected to the wrong installation position of a peripheral device 114, e.g., the wrong slot 117 and / or bay 121, the VPP architecture would be unaware of the misconfiguration of the communication bus cables 123, which may cause the operating system and / or BIOS 106 to be out of sync with the current hardware topology. Furthermore, the VPP architecture may not allow direct connections to multiple backplanes 122 due to electrical routing limitations, e.g., on the motherboard. Furthermore, the VPP architecture may not provide data integrity verification, such as checksums and data parity values.

[0088] Thus, the protocol described herein provides an expanded and more descriptive architecture that provides the capabilities to manage multiple peripheral devices 114 located on multiple backplanes 122 and connected to the processor 104 via one or more communication bus cables 123. In one embodiment, the transmit module 325 receives a VPP command from the processor 104 and transmits, transforms, encodes, or the like, the received VPP command into a corresponding data field in the data packet.

[0089] The VPP command, in some embodiments, may be intended for a peripheral device 114 on a backplane 122, identified by the installation position identifier received by the data module 235. In another embodiment, the transmit module writes the VPP command to a corresponding data field in the data packet. In some embodiments, the VPP command includes an enable command for a peripheral device 114, a disable command for a peripheral device 114, and / or a command to toggle an activity indicator on the peripheral device 114, such as an LED. Thus, the transmit module 325 may receive a VPP command, toggle the activity indicator LED on a specific peripheral device 114, determine which data packet of the data field corresponds to the received VPP command, and write a value corresponding to the value of the VPP command to the corresponding data field in the data packet.

[0090] In various embodiments, the transmission module 325 sends the data packet containing the VPP command to the SEP 115 on the backplane 122 using a communication bus cable 123 coupled to the SEP 115 and associated with the intended peripheral device 114. For example, the transmission module 325 may receive a VPP command to disable a peripheral device 114. The transmission module 325 may determine a slot ID and a bay ID for the intended peripheral device 114 and the communication bus cable 123 coupled to the determined slot ID and bay ID, e.g., using the path table provided by the topology module 240. The transmission module 325 may then encode the VPP command to a corresponding value in the data field of the data packet corresponding to the deactivation command and send the data packet to the SEP 115 via the identified communication bus cable 123.

[0091] In one embodiment, the transmit module 325 writes a parity value into a parity field of the data packet before sending the data packet to the intended peripheral device 114. The parity value may be used by the SEP 115 to confirm the integrity of the data written into the data packet, such as the integrity of the VPP command encoded into the data packet. The parity value may be generated using a combination of one or more bits from various data fields, as described above in Table 1. In one embodiment, the transmit module 325 generates a parity value and writes it into the parity field if the SEP 115 supports data parity, as indicated in various data fields of the data packet.

[0092] Fig.4 illustrates one embodiment of a method 400 for managing peripheral devices using a data protocol. The method 400 begins and determines 402 one or more communication bus cables 123 that couple one or more peripheral devices 114 to an information handling device 102. The method 400 reads 404, over each of the one or more communication bus cables 123, a data packet associated with a peripheral device 114. Each data packet includes an identifier for the location where the peripheral device 114 is installed. The method 400 determines 406 a cable connection configuration for the one or more communication bus cables 123 and the one or more peripheral devices 114 based on the installation location identifier received from each of the data packets associated with the one or more peripheral devices 114, and the method 400 ends.In some embodiments, the connection module 230, the data module 235, and / or the topology module 240 perform the various steps of the method 400.

[0093] Fig. 5 illustrates one embodiment of a method 500 for managing peripheral devices using a data protocol. The method 500 begins and determines 502 one or more communication bus cables 123 that communicatively couple one or more peripheral devices 114 to an information handling device 102. The method 500 reads 504, over each of the one or more communication bus cables 123, a data packet associated with a peripheral device 114. In one embodiment, the method 500 confirms 506 an integrity of data contained in one or more fields of the data packet using a checksum contained in a checksum field of the data packet.

[0094] In some embodiments, if the method 500 determines 508 that the integrity of the data packet is not present based on the checksum, which may indicate that there is an error in the data, that the data is corrupted, or the like, the method 500 ends. On the other hand, in certain embodiments, if the method 500 determines 508 that the integrity of the data is present, the method 500 determines 510 a cable connection configuration for the one or more communication bus cables 123 and the one or more peripheral devices 114 based on the installation position identifier received from each of the data packets associated with the one or more peripheral devices 114.

[0095] In some embodiments, method 500 provides 512 the cable connection configuration for communication bus cables 123 and peripheral devices 114 to the BIOS or operating system of information handling device 102. In one embodiment, method 500 determines 514 whether the determined cable connection configuration matches a predefined cable connection configuration. If not, in one embodiment, method 500 sends 516 a notification to indicate that the determined connection configuration of communication bus cables 123 does not match the predefined or recommended cable connection configuration.

[0096] In another embodiment, the method 500 dynamically tunes 518 one or more performance characteristics of the FPGA 204 based on one or more characteristics of the SEP 115 included in the data packet received by the method 500. As described above, in one embodiment, the FPGA 204 is communicatively coupled to the SEP 115 and one or more peripherals 114 of the backplane 122 using communication bus cables 123 in a master / slave configuration in which the FPGA 204 is the bus master and conducts or routes communications with the SEP 115 as the bus slave and the peripherals 114 as slave devices, and the method 500 ends.In some embodiments, the connection module 230, the data module 235 and / or the topology module 240, the notification module 310, the voting module 315, the confirmation module 320 and / or the transmission module 325 perform the various steps of the method 500.

[0097] Embodiments may be practiced in other specific forms. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is thus indicated by the appended claims rather than by the foregoing description. All changes which come within the spirit and meaning of equivalence to the claims are intended to be embraced within their scope.

Claims

[1] Device comprising: - a connection module (100) defining one or more communication bus cables (123) that communicatively couple one or more peripheral devices (114) installed on a backplane (122) to an information handling device (102), - a data module (235) that reads, via each of the one or more communication bus cables (123), a data packet associated with a peripheral device (114), each data packet including one or more data fields that define an identifier for a position at which the peripheral device (114) is installed on the backplane (122), and - a topology module (240) that determines a cable connection configuration for the one or more communication bus cables (123) and the one or more peripheral devices (114) based on the installation position identifier received from each of the data packets associated with the one or more peripheral devices (114); - wherein the data packet further comprises one or more fields containing data describing one or more properties of a Storage Enclosure Processor (SEP) (115) located on the backplane (122). [2] The device (110) of claim 1, wherein the topology module (240) provides the cable connection configuration of the communication bus cables (123) and the peripheral devices (114) to a Basic Input / Output System (BIOS). [3] The apparatus (110) of claim 2, further comprising a notification module that sends a notification in response to the determined cable connection configuration not matching a predefined cable connection configuration. [4] The apparatus (110) of claim 1, wherein each of the one or more peripheral devices (114) is installed in a drive bay (121) of the backplane, and the identifier comprises a bay identifier and an associated slot identifier of the drive bay (121). [5] The apparatus (110) of claim 4, wherein the data packet comprises a plurality of fields defining the identifier, the plurality of fields comprising a bay identifier field and a slot identifier field. [6] The apparatus (110) of claim 1, wherein the SEP manages the one or more peripheral devices (114) on the backplane (122) via a management bus (118) comprising management bus connections (124) to the one or more peripheral devices (114) on the backplane (122). [7] The apparatus (110) of claim 6, further comprising a tuning module (315) that dynamically modifies one or more performance characteristics of a Field Programmable Gate Array (FPGA) (204) based on the one or more characteristics of the SEP (115), wherein the FPGA (204) is communicatively coupled to the SEP (115) and one or more peripheral devices (114) via a communication bus cable. [8] The apparatus (110) of claim 6, wherein the one or more properties of the SEP (115) include: - a bit switch indicating whether the SEP (115) supports data parity, - a maximum clock speed for the SEP (115), a time-lock parameter for polling the SEP (115) and - a maximum number of peripherals supported by the SEP (115). [9] The apparatus (110) of claim 1, further comprising a confirmation module (320) that checks an integrity of data contained in one or more fields of the data packet using a checksum, the checksum being contained in a checksum field of the data packet. [10] The device (110) of claim 1, further comprising a transmission module (325) that performs the following: - receiving a virtual port connection (VPP) command from a VPP-enabled processor (104), the VPP command being intended for a peripheral device (114) on the backplane (122), the peripheral device (114) being identified by the installation position identifier, - Writing the VPP command into a corresponding field in the data packet and - sending the data packet containing the VPP command to the SEP (115) on the backplane (122) by means of a communication bus cable coupled to the SEP (115) and associated with the intended peripheral device (114). [11] The apparatus (110) of claim 10, wherein the transmission module (325) writes a parity value into a parity field of the data packet, the parity value being used by the SEP (115) to confirm an integrity of data written into the data packet. [12] The apparatus (110) of claim 10, wherein the VPP command comprises one or more of the following: - a peripheral device activation command, - a peripheral device deactivation command and - a peripheral activity indicator toggle command. [13] The device (110) of claim 1, wherein the communication bus cable (123) comprises a Peripheral Component Interconnection Express (PCIe) cable. [14] The device (110) of claim 1, wherein the peripheral device (114) comprises a Non-Volatile Memory Express (NVMe) storage device. [15] Method (500) comprising: - determining (502) one or more communication bus cables that communicatively couple one or more peripheral devices installed on a backplane to an information handling device, - reading (504) a data packet over each of the one or more communication bus cables associated with a peripheral device, each data packet including one or more data fields defining an identifier for a position at which the peripheral device is installed on the backplane, and - determining (510) a cable connection configuration for the one or more communication bus cables and the one or more peripheral devices based on the installation position identifier received from each of the data packets associated with the one or more peripheral devices, - wherein the data packet further comprises one or more fields containing data describing one or more properties of a Storage Enclosure Processor (SEP) located on the backplane. [16] The method (500) of claim 15, further comprising: - Providing (512) a cable connection configuration of the communication bus cables and the peripheral devices for a Basic Input / Output System (BIOS) and - sending (516) a notification in response to the particular cable connection configuration not matching a predefined cable connection configuration. [17] The method (500) of claim 15, wherein: - each of the one or more peripheral devices is installed in a drive bay of the backplane, the identifier comprises a bay identifier and an associated slot identifier of the drive bay, and - the data packet comprises a plurality of fields which identify the identifier, wherein the plurality of fields comprise a field for the shaft identifier and a field for the slot identifier. [18] The method (500) of claim 15, further comprising dynamically modifying one or more performance characteristics of a Field Programmable Gate Array (FPGA) based on the one or more characteristics of the SEP, wherein the FPGA is communicatively coupled to the SEP and one or more backplane peripherals via a communication bus cable. [19] The method (500) of claim 15, further comprising: - Receiving a virtual port (VPP) command from a VPP-enabled processor intended for a peripheral device on the backplane, the peripheral device being identified by the installation position identifier, - Writing the VPP command into a corresponding field in the data packet and - Sending the data packet containing the VPP command to the SEP using a communication bus cable coupled to the SEP and associated with the designated peripheral device. [20] The method (500) of claim 15, wherein the SEP manages the one or more peripheral devices on the backplane via a management bus comprising management bus connections to the one or more peripheral devices on the backplane. [21] A program product comprising a computer-readable storage medium storing code executable by a processor, the executable code comprising code for performing a method according to any one of claims 15 to 20.

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