Doping for semiconductor device with conductive feature

Abstract

Structure that includes the following: an active region of a transistor, wherein the active region comprises a source / drain region (92), wherein the source / drain region (92) is defined at least partially by a first dopant, which constitutes a first dopant concentration, wherein the source / drain region (92) further comprises a second dopant having a concentration profile that exhibits a constant concentration from an area of ​​the source / drain region (92) to a depth of the source / drain region (92), wherein the constant concentration is higher than the first dopant concentration, and wherein the depth is at least 5 nm; and a conductive feature (124) that contacts the source / drain area (92) at the surface of the source / drain area (92).

Description

GENERAL STATE OF THE ART

[0001] As integrated circuits become increasingly miniaturized, the silicide areas, and thus the contact area between the contact pins and the silicide areas, also become smaller. Consequently, the contact resistance can increase. For example, in fin field-effect transistors (FinFETs), the fins are very narrow, resulting in very small contact areas between the contacts and the fins.

[0002] US Patent 9,679,967 B1 discloses a method for reducing contact resistance in a source / drain region of a semiconductor device. The method comprises forming an oxide layer, etching native oxides of the oxide layer to an etch depth of 5 nm, and doping the device with silicon after etching, resulting in an increased doping concentration in the source / drain region, which contributes to a reduced contact resistance.

[0003] US patent 2017 / 0221724A1 describes a method for reducing contact resistance in a semiconductor device by boron-based doping. German patent DE 112011105702T5 discloses the use of a titanium silicide between a titanium-containing interface and a silicon-containing source / drain structure.

[0004] US 2011 / 0101457A1 describes a source / drain region with a doped area containing boron and indium, exhibiting a slightly decreasing concentration depth profile for boron (nearly constant on a logarithmic scale) and an initially increasing concentration depth profile for indium, which then decreases from a near-surface maximum. The doped area may contain gallium. SUMMARY OF THE INVENTION

[0005] The present invention relates to a structure according to claim 1, a structure according to claim 8 and a method according to claim 12. Advantageous embodiments are specified in the accompanying dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of this disclosure are best understood by reading the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity in the discussion. Fig. Figure 1 is a three-dimensional view of an example of a Fin field-effect transistor (FinFET) according to some embodiments. Fig. 2A-B, Fig. 3A-B, Fig. 4A-B, Fig. 5A-B, Fig. 6A-B, Fig. 7A-B, Fig. 8A-B, Fig. 9A-B, Fig. 10A-B, Fig. 11A-B, Fig. 12A-B, Fig. 13A-B, Fig. 14A-B, Fig. 15A-B, Fig. 16A-B and Fig. Figures 17A-B are cross-sectional views of intermediate stages in an exemplary process for forming one or more FinFETs according to some embodiments. Fig. 18A-B and Fig. Figures 19A-B are cross-sectional views of intermediate stages in another exemplary process for forming one or more FinFETs according to some embodiments. Fig. Figure 20 is a cross-sectional view of a conductive feature and source / drain region according to some embodiments. Fig. Figure 21 is a graphic representation illustrating various dopant profiles according to some embodiments. Fig. Figure 22 is a cross-sectional view of a section of an exemplary device structure according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples of various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purposes of simplicity and clarity and does not in itself prescribe a relationship between the various designs and / or configurations discussed.

[0008] Furthermore, terms describing a spatial relationship, such as "below," "under," "lower," "above," "upper," and the like, may be used here for the sake of simplicity to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It is intended that terms describing a spatial relationship encompass, in addition to the orientation depicted in the figures, various orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the descriptions of spatial relationships used here may be interpreted accordingly.

[0009] Conductive features, such as contacts, for example to the source / drain regions of transistors, and methods for creating such conductive features are described. In some examples, a dopant, such as gallium in some instances, is implanted into source / drain regions with a profile that exhibits a platform concentration near an area of ​​the source / drain region that is higher than the dopant concentration in the rest of the source / drain region. This platform concentration can reduce the resistance of a contact in the source / drain region.

[0010] Examples of conductive features described and illustrated herein are implemented in Fin field-effect transistors (FinFETs); however, conductive features within the scope of protection of this disclosure may also be implemented in planar transistors and / or other semiconductor devices. Furthermore, intermediate stages in the formation of FinFETs are illustrated. Some embodiments described herein are presented in the context of FinFETs formed using a replacement-gate process. In other examples, a gate-first process may be used. Several variations of the exemplary methods and structures are described. A person skilled in the art will readily understand other modifications that may be made and that are considered within the scope of protection of other embodiments.Although some forms of process execution may be described in a specific order, various other forms of process execution may be carried out in any logical order and may include fewer or more of the steps described here.

[0011] Fig. Figure 1 illustrates a simplified example of FinFETs 40 in a three-dimensional view. Other aspects may be relevant that are not illustrated or referenced in Figure 1. Fig. 1. The structure will be described, and this will become apparent from the following figures and description. Fig. 1 can be electrically connected or coupled in a way to function, for example, as one transistor or more, such as four transistors.

[0012] The FinFETs 40 comprise fins 46a and 46b on a substrate 42. The substrate 42 includes insulation regions 44, and fins 46a and 46b each project above and from between adjacent insulation regions 44. Gate dielectrics 48a and 48b are located along side walls and above the upper surfaces of fins 46a and 46b, and gate electrodes 50a and 50b are located above the gate dielectrics 48a and 48b, respectively. Source / drain regions 52a to 52f are arranged in corresponding regions of fins 46a and 46b. Source / drain regions 52a and 52b are located in opposite regions of fin 46a with respect to the gate dielectric 48a and the gate electrode 50a. The source / drain regions 52b and 52c are arranged in opposite regions of the fin 46a with respect to the gate dielectric 48b and the gate electrode 50b.The source / drain regions 52d and 52e are arranged in opposite regions of the fin 46a with respect to the gate dielectric 48a and the gate electrode 50a. The source / drain regions 52e and 52f are arranged in opposite regions of the fin 46b with respect to the gate dielectric 48b and the gate electrode 50b.

[0013] In some examples, four transistors can be implemented as follows: (1) source / drain regions 52a and 52b, gate dielectric 48a, and gate electrode 50a; (2) source / drain regions 52b and 52c, gate dielectric 48b, and gate electrode 50b; (3) source / drain regions 52d and 52e, gate dielectric 48a, and gate electrode 50a; and (4) source / drain regions 52e and 52f, gate dielectric 48b, and gate electrode 50b. As indicated, some source / drain regions can be shared by different transistors, and other source / drain regions not illustrated as being shared can be shared, for example, by adjacent transistors not illustrated. In some examples, different source / drain regions can be interconnected or coupled together in such a way that FinFETs function as two separate transistors. For example, if adjacent (e.g.,In contrast to opposite source / drain regions 52a to f, which are electrically connected, for example by connecting the regions through epitaxial growth (where, for example, source / drain regions 52a and 52d are connected, source / drain regions 52b and 52e are connected, etc.), two functional transistors can be implemented. Other embodiments in other examples can implement different numbers of functional transistors.

[0014] Fig. Figure 1 further illustrates reference cross-sections used in subsequent figures. Cross-section AA lies in a plane along, for example, channels in fin 46a between opposing source / drain areas 52a to f. Cross-section BB lies in a plane perpendicular to cross-section AA and crosses source / drain area 52a in fin 46a and source / drain area 52d in fin 46b. For clarity, the following figures refer to these reference cross-sections.

[0015] Fig. 2A-B and Fig. Figures 17A-B are cross-sectional views of intermediate stages in an exemplary process for forming one or more FinFETs according to some embodiments. Fig. Figures 2A-B to 17A-B, whose designation ends with an "A", illustrate cross-sectional views along a cross-section corresponding to cross-section AA in Fig. Figure 1 is similar, and figures whose designation ends with a "B" illustrate cross-sectional views along a cross-section that corresponds to cross-section BB in Fig. 1 is similar. It may be that in some figures, some reference symbols for building elements or features illustrated therein have been omitted to avoid making other building elements or features unclear; this serves the purpose of simplicity in the pictorial representation in the figures.

[0016] Fig. 2A and Fig. Figure 2B illustrates a semiconductor substrate 70. The semiconductor substrate 70 can be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. In general, an SOI substrate comprises a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as a multilayer or gradient substrate.In some embodiments, the semiconductor material of the semiconductor substrate layer may comprise silicon (Si); germanium (Ge); a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP; or a combination thereof.

[0017] Fig. 3A and Fig. Figure 3B illustrates the formation of fins 74 in the semiconductor substrate 70. In the illustrated example, a mask 72 (e.g., a hard mask) is used in the formation of the fins 74. For example, one or more mask layers are deposited over the semiconductor substrate 70, and the one or more mask layers are then patterned into the mask 72. In some examples, the one or more mask layers may comprise silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another deposition technique. The one or more mask layers may be patterned using photolithography.For example, a photoresist can be formed on one or more mask layers, such as by spin coating, and structured by exposing the photoresist to light using a suitable photomask. Exposed or unexposed sections of the photoresist can then be removed, depending on whether a positive or negative resist is used. The structure of the photoresist can then be transferred to one or more mask layers, such as by using a suitable etching process, thereby forming the mask 72. The etching process can include reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. Subsequently, the photoresist is removed, for example, by an ashing or wet peeling process.

[0018] Using the mask 72, the semiconductor substrate 70 can be etched such that grooves 76 are formed between adjacent pairs of fins 74, and such that the fins 74 protrude from the semiconductor substrate 70. The etching process can include a RIE, NBE, the like, or a combination thereof. The etching can be anisotropic.

[0019] Fig. 4A and Fig. Figure 4B illustrates the formation of isolation regions 78 in a corresponding trench 76. The isolation regions 78 can be or comprise an isolation material, such as an oxide (e.g., silicon dioxide), a nitride, the like, or a combination thereof, and the isolation material can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it into another material, such as an oxide), the like, or a combination thereof. Other isolation materials formed by any acceptable process can also be used. In the illustrated embodiment, the isolation regions 78 comprise silicon dioxide formed by an FCVD process.A planarization process, such as chemical-mechanical polishing (CMP), can remove any excess insulating material and any remaining mask 72 to form coplanar surfaces of the insulating material and the fins 74. The insulating material can then be recessed to form the insulating regions 78. The insulating material is recessed such that the fins 74 protrude from between adjacent insulating regions 78, thereby at least partially delineating the fins 74 as active regions on the semiconductor substrate 70. The insulating material can be recessed using an acceptable etching process, such as one that is selective for the insulating material.For example, chemical oxide removal can be performed using a CERTAS® etching tool or an Applied Materials SICONI tool, or dilute hydrofluoric acid (dHF). Furthermore, the upper surfaces of the insulation regions 78 can have a flat surface, as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof, which may result from an etching process.

[0020] The average expert will readily understand that, with reference to Fig. The process described in Sections 2A-B to 4A-B is merely one example of how fins 74 can be formed. In other embodiments, a dielectric layer can be formed over a top surface of the semiconductor substrate 70; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be deepened such that the homoepitaxial structures protrude from the dielectric layer to form fins. In still other embodiments, heteroepitaxial structures can be used for the fins. For example, the fins 74 can be deepened (e.g., after planarizing the insulating material of the insulating regions 78 and before deepening the insulating layer), and a material different from the fins can be epitaxially grown in their place.In yet another embodiment, a dielectric layer can be formed over a top surface of the semiconductor substrate 70; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the semiconductor substrate 70; and the dielectric layer can be deepened such that the heteroepitaxial structures protrude from the dielectric layer to form fins. In some embodiments where homoepitaxial or heteroepitaxial structures are allowed to grow epitaxially, the grown materials can be doped in place during growth, thus avoiding the need for prior implantation of the fins, although in-place doping and implantation can be used together.Furthermore, it can be advantageous to grow a material for an n-type device that differs from the material in a p-type device. In various embodiments, the fins can be silicon 74, silicon germanium (Si. x Ge 1-x , where x can be between approximately 0 and 100), silicon carbide, pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, materials for forming a III-V compound semiconductor include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0021] Fig. 5A and Fig. Figure 5B illustrates the formation of dummy gate stacks on the fins 74. Each dummy gate stack comprises an etch stop 80, a dummy gate 82, and a mask 84. The etch stop 80, the dummy gate 82, and the mask 84 can be formed by sequentially depositing appropriate layers and structuring these layers. For example, a layer for the etch stop 80 can comprise or be silicon oxide, silicon nitride, the like, or multiple layers thereof, and can be thermally grown or deposited, such as by plasma-enhanced CVD (PECVD), ALD, or another deposition technique. A layer for the dummy gate 82 can comprise or be silicon (e.g., polysilicon) or another material deposited by CVD, PVD, or another deposition technique.A layer for the mask 84 can comprise silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof, deposited by CVD, PVD, ALD, or another deposition technique. The layers for the mask 84, the dummy gate 82, and the etch stop 80 can then be patterned, for example, using photolithography and one or more etching processes, as described above with reference to [reference]. Fig. 3A and Fig. 3B described to form the mask 84, the dummy gate 82 and the etch stop 80 for each gate stack.

[0022] In the illustrated example, a dummy gate stack is used for a replacement gate process. In other examples, a gate-first process can be performed using gate stacks that include, for example, a gate dielectric instead of the etch stop 80 and a gate electrode instead of the dummy gate 82. In some gate-first processes, the gate stack can be formed using similar processes and materials as described with reference to the dummy gate stacks; although in other examples, different processes and materials can be used. For example, a gate dielectric can be or include a high-k dielectric, such as one having a k-value higher than about 7.0, which may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, multiple layers thereof, or a combination thereof.A gate dielectric can also be deposited by molecular beam deposition (MBD), ALD, PECVD, or another deposition technique. A gate electrode can also consist of a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, multiple layers thereof, or a combination thereof.

[0023] Fig. 6A and Fig. Figure 6B illustrates the formation of gate spacers 86. The gate spacers 86 are formed along the sidewalls of the dummy gate stack (e.g., sidewalls of the etch stop 80, dummy gates 82, and mask 84). The gate spacers 86 can be formed, for example, by conformal deposition of one or more layers for the gate spacers 86 and anisotropic etching of the one or more layers. The one or more layers for the gate spacers 86 can comprise silicon nitride, silicon oxynitride, silicon carbonitride, the like, several layers thereof, or a combination thereof, and the etching process can include RIE, NBE, or another etching process.

[0024] Fig. 7A and Fig. Figure 7B illustrates the formation of recesses 90 for source / drain regions 70. As illustrated, the recesses 90 are formed in the fins 74 on opposite sides of the dummy gate stack. The recession can be achieved by an etching process. The etching process can be isotropic or anisotropic, or furthermore, selective with respect to one or more crystalline planes of the semiconductor substrate 70. Thus, the recesses 90 can exhibit different cross-sectional profiles based on the etching process performed. The etching process can be a dry etch, such as a RIE, NBE, or the like, or a wet etch, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or another etchant.

[0025] Fig. 8A and Fig. Figure 8B illustrates the formation of epitaxial source / drain regions 92 in the recesses 90. The epitaxial source / drain regions 92 can contain silicon germanium (Si x Ge 1-x, where x can be between approximately 0 and 100), silicon carbide, silicon phosphorus, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, materials for forming a III-V compound semiconductor include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. The epitaxial source / drain regions 92 can be formed in the wells 90 by epitaxial growth of a material in the wells 90, such as by metal-organic vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), vapor-phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. As shown in Fig. 8A and Fig. As illustrated in Figure 8B, due to the barrier effect of the isolation regions 78, the epitaxial source / drain regions 92 are initially allowed to grow vertically in the recesses 90, while they do not grow horizontally during this time. After the recesses 90 are completely filled, the epitaxial source / drain regions 92 can grow both vertically and horizontally to form facets that may correspond to crystalline planes of the semiconductor substrate 70. In some examples, different materials are used for epitaxial source / drain regions in p-type and n-type devices. Appropriate masking during the deepening or epitaxial growth phases can enable the use of different materials in different devices.

[0026] The average expert will readily understand that the deepening and epitaxial growth of Fig. 7A-B and Fig. 8A-B can be omitted and that source / drain regions can be formed by implanting dopants into the fins 74. In some examples where epitaxial source / drain regions 92 are executed, the epitaxial source / drain regions 92 can also be doped, such as by doping in place during epitaxial growth and / or by implanting dopants into the epitaxial source / drain regions 92 after epitaxial growth. Examples of dopants may include, for example, boron for a p-type device and phosphorus or arsenic for an n-type device, although other dopants may be used. The epitaxial source / drain regions 92 (or other source / drain regions) can have a dopant concentration in the range of about 10 19 cm -3 up to about 10 21 cm -3exhibit. Thus, a source / drain area can be delineated by doping (e.g., if applicable, by implantation and / or on-site during epitaxial growth) and / or, if applicable, by epitaxial growth, which further delineates the active area in which the source / drain area is defined.

[0027] Fig. 9A and Fig. Figure 9B illustrates an amorphization implant 94. The amorphization implant 94 can be omitted in some embodiments. In some examples, the amorphization implant 94 involves implanting a foreign atom species into the epitaxial source / drain regions 92 to render the upper portions 96 of the epitaxial source / drain regions 92 amorphous. The upper portions 96 that are rendered amorphous can, for example, extend from corresponding upper surfaces of the epitaxial source / drain regions 92 to a depth of about 2 nm to about 20 nm. In some examples, such as for a p-type device, the epitaxial source / drain regions 92 are Si x Ge 1-xGermanium is the species implanted to amorphize the upper sections 96 of the epitaxial source / drain regions 92. In such examples, the implantation energy can be in a range of about 1 keV to about 15 keV, such as about 10 keV, with a dosage concentration in the range of about 5 × 10 13 cm -2 up to about 5×10 14 cm -2 lay.

[0028] Fig. 10A and Fig. Figure 10B illustrates a dopant implant 98 in the upper sections 96 of the epitaxial source / drain regions 92. The dopant implant 98 can implant dopants into the upper sections 96 to reduce contact resistance between the corresponding epitaxial source / drain region 92 and a conductive feature (e.g., comprising a contact) that is subsequently formed. In some examples, the dopant species used for the dopant implant 98 can amorphize the upper sections 96 upon implantation (and can therefore be described as self-amorphizing). In these examples, or in different examples, the amorphization implant 98 can be Fig. 9A and Fig. 9B is omitted. The dopant implant 98 implants dopant materials into the upper sections 96 according to the invention, such that the upper sections 96, from the corresponding upper surfaces of the upper sections 96 to depths of 5 nm or greater, possibly 10 nm or greater, or 15 nm or greater, have a uniform concentration of the dopant. The uniform concentration of the dopant may be higher than the concentration of the dopant that at least partially delineates the source / drain regions (e.g., formed by implantation and / or doping on site during epitaxial growth). The concentration of the dopant in the epitaxial source / drain regions 92 may decrease from the uniform concentration to further depths of the epitaxial source / drain regions 92.Additional exemplary details of the dopant implant 98 and the concentrations of the dopant resulting from the dopant implant 98 are given below with reference to . Fig. 20 and Fig. 21 described.

[0029] In some examples, such as for a p-type device, the epitaxial source / drain regions are 92 Si x Ge 1-x Gallium is the species that is implanted for the dopant implant 98 into the upper sections 96 of the epitaxial source / drain regions 92. In such examples, the implantation energy can be in a range of about 0.5 keV to about 10 keV, with a dosage concentration in a range of about 1 × 10 15 cm -2 up to about 1×10 16 cm -2 The uniform concentration of gallium from the upper surfaces of the epitaxial source / drain regions 92 down to the depth can be found in a range of approximately 10 21 cm-3 up to about 10 22 cm -3 and in particular about 5×10 21 cm -3 lay.

[0030] Following the dopant implant 98, annealing is performed to activate the dopants and recrystallize the upper sections 96 that have been amorphized (e.g., by the amorphization implant 94 and / or by the dopant implant 98). In some examples, the annealing may be carried out at a temperature in the range of approximately 600°C to approximately 900°C for a duration of approximately one minute or less, 12 seconds or less, or 1 second or less. In other examples, the annealing may be laser annealing performed for a duration of several nanoseconds, such as approximately 100 ns or less. In still other examples, the annealing may be melt annealing performed for a duration of a few nanoseconds, such as approximately 1 ns.

[0031] Fig. 11A and Fig. Figure 11B illustrates the formation of one or more dielectric layers 100. The one or more dielectric layers 100 can, for example, comprise an etch stop layer (ESL) and an interlayer dielectric (ILD). In general, an etch stop layer can provide a mechanism for stopping an etching process when, for example, contacts or vias are formed. An etch stop layer can be formed from a dielectric material that has an etch selectivity that differs from that of adjacent layers, for example, the interlayer dielectric. The etch stop layer can be conformally deposited over the epitaxial source / drain regions 92, dummy gate stacks, spacers 86, and isolation regions 78.The etch stop layer can comprise silicon nitride, silicon carbonitride, silicon carbon oxide, carbonitride, the like, or a combination thereof, and can be deposited by CVD, PECVD, ALD, or another deposition technique. The dielectric intermediate layer can be silicon dioxide, a low-K dielectric (e.g., a material with a dielectric constant lower than that of silicon dioxide), such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorosilicate glass (FSG), organosilicate glasses (OSG), or SiO₂. x C y The material may include or be spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite material thereof, the like, or a combination thereof. The dielectric interlayer may be deposited by spin deposition, CVD, FCVD, PECVD, PVD, or another deposition technique.

[0032] The one or more dielectric layers 100 are formed with (one) top surface(s) that are coplanar with the top surfaces of the dummy gates 82. A planarization process, such as a CMP, can be performed to make the top surface of the one or more dielectric layers 100 planar with the top surfaces of the dummy gates 82. The CMP can also remove the mask 84 (and in some cases, top sections of the spacers 86) on the dummy gates 82. Accordingly, the top surfaces of the dummy gates 82 are exposed through the one or more dielectric layers 100.

[0033] Fig. 12A and Fig. Figure 12B illustrates the replacement of the dummy gate stacks with gate dielectrics 102, gate electrodes 104, and masks 106. The dummy gates 82 and etch stops 80 are removed, for example, by one or more etching processes. The dummy gates 82 can be removed by an etching process, with the etch stops 80 acting as etch stop layers, and subsequently, the etch stops 80 can be removed by a different etching process. The etching processes can be, for example, RIE, NBE, wet etching, or another etching process.

[0034] A layer of gate dielectric 102 is formed, for example, where the dummy gates 82 and etch stops 80 have been removed. For instance, the gate dielectric layer 102 can be conformally deposited along the sidewalls of the gate spacers 86, the top surfaces and sidewalls of the fins 74 where dummy gate stacks have been removed, and over the top surface of one or more dielectric layers 100. The gate dielectric layer 102 can be silicon oxide, silicon nitride, a high-k dielectric, several layers thereof, or another dielectric. A high-k dielectric can have a k-value higher than approximately 7.0 and can comprise a metal oxide or metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof. The layer for the gate dielectrics 102 can be deposited by ALD, PECVD, MBD or another deposition technique.

[0035] A layer for the gate electrodes 104 is formed over the layer for the gate dielectrics 102. The layer for the gate electrodes 104 can fill remaining areas where the dummy gate stacks have been removed. The layer for the gate electrodes can be a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, multiple layers thereof, or a combination thereof. The layer for the gate electrodes 104 can be deposited by ALD, PECVD, MBD, or another deposition technique.

[0036] Sections of the layers for the gate electrodes 104 and the gate dielectrics 102 above the top surface of one or more dielectric layers 100 are removed. For example, a planarization process, such as CMP, can remove the sections of the layers for the gate electrodes 104 and the gate dielectrics 102 above the top surface of the one or more dielectric layers 100. Subsequently, back-etching can recess the top surfaces of the gate electrodes 104 and gate dielectrics 102 to a level below the top surface of the one or more dielectric layers 100. The back-etching can be, for example, RIE, wet etching, or another etching process. The gate electrodes 104 and gate dielectrics 102 can therefore be formed as shown in Fig. 12A illustrates this.

[0037] A layer for the masks 106 is formed over the gate electrodes 104 and gate dielectrics 102 (e.g., where the gate electrodes 104 and gate dielectrics 102 have been back-etched) and over the one or more dielectric layers 100. The layer for the masks 106 can comprise silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof, and can be deposited by CVD, PVD, ALD, or another deposition technique. Sections of the layer for the masks 106 over the top surface of the one or more dielectric layers 100 are removed. For example, a planarization process, such as CMP, can remove the sections of the layer for the masks 106 over the top surface of the one or more dielectric layers 100, and top layers of the masks 106 can be formed coplanar with the top surface of the one or more dielectric layers 100.

[0038] As previously stated, gate stacks with one gate dielectric and one gate electrode can be executed in a gate-first process instead of, as illustrated, in a replacement-gate process. In such examples, some process steps that refer to Fig. 11A-B and Fig. The sections described in 12A-B can be omitted. For example, if a planarization process in Fig. When using 11A-B, the upper surface of one or more dielectric layers can remain 100° above the upper surfaces of the gate stack. The removal of dummy gate stacks and replacement gate dielectrics, gate electrodes, and masks in Fig. 12A-B can be omitted.

[0039] Fig. 13A and Fig. Figure 13B illustrates the formation of openings 110 through the one or more dielectric layers 100 to the epitaxial source / drain regions 92, in order to expose at least corresponding sections of the epitaxial source / drain regions 92. A mask 112 is formed on the one or more dielectric layers 100 and masks 106 to form the openings 110. A layer for the mask 112 can comprise silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof, deposited by CVD, PVD, ALD, or another deposition technique. The layer for the mask 112 can then be patterned, for example, using photolithography and one or more etching processes. Using the mask 112, the openings 110 can be formed through the one or more dielectric layers 100 using one or more etching processes, such as RIE, NBE, or another etching process.

[0040] Although not specifically illustrated, an amorphization implant can be performed to amorphize upper portions of the epitaxial source / drain regions 92 where silicide regions are to be formed, as described below. The amorphized upper portions of the epitaxial source / drain regions 92 may enable more efficient and / or faster silicide formation compared to silicide formation without the use of an amorphization implant. In some examples, the species used for the amorphization implant is germanium or another species.

[0041] Fig. 14A and Fig. Figure 14B illustrates the formation of a metal layer 114 and a barrier layer 116 in the openings 110. The metal layer 114 is conformally deposited in the openings 110, and the barrier layer 116 is conformally deposited on the metal layer 114. Specifically, the metal layer 114 is deposited on the upper surfaces of the epitaxial source / drain regions 92 exposed by the openings 110 and along other surfaces of the openings 110. The metal layer 114 can be, for example, titanium, cobalt, nickel, the like, or a combination thereof, and can be deposited by ALD, CVD, or another deposition technique. The metal layer 114 can, for example, be deposited to a thickness in the range of 2 nm to about 15 nm.The barrier layer 116 can be or comprise titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, the like, or a combination thereof, and can be deposited by ALD, CVD, or another deposition technique. The barrier layer 116 can, for example, be deposited to a thickness in the range of 2 nm to approximately 15 nm.

[0042] Fig. 15A and Fig. Figure 15B illustrates the formation of silicide regions 118 on upper portions of epitaxial source / drain regions 92. The silicide regions 118 can be formed by the reaction of upper portions of the epitaxial source / drain regions 92 with the metal layer 114 and / or barrier layer 116. Annealing is performed to facilitate the reaction of the epitaxial source / drain regions 92 with the metal layer 114 and / or barrier layer 116. The annealing can be carried out at a temperature in the range of about 500 °C to about 600 °C for a duration of 10 seconds or longer. The silicide regions 118 can, for example, have a thickness in the range of 2 nm to about 20 nm. In some examples, etching can be performed to remove unreacted portions of the metal layer 114 and / or barrier layer 116.

[0043] Fig. 16A and Fig. Figure 16B illustrates the formation of contacts 120 that fill the openings 110. The contacts 120 can be or comprise tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and can be deposited by CVD, ALD, PVD, or another deposition technique. After the contact material 120 has been deposited, excess material can be removed using a planarization process, such as CMP. The planarization process can remove excess material from the contacts 120, barrier layer 116, metal layer 114, and mask 112 above the top surface of the one or more dielectric layers 100. Thus, the top surfaces of the contacts 120, barrier layer 116, metal layer 114, and the one or more dielectric layers 100 can be coplanar.Accordingly, conductive features comprising the contacts 120, barrier layer 116, metal layer 114 and / or silicide areas 118 can be formed on the epitaxial source / drain areas 92.

[0044] Although the conductive features (which include, for example, the contacts 120) are depicted in the figures as having a specific configuration, the conductive features can have any configuration. For example, separate conductive features can be formed to separate epitaxial source / drain regions 92. The average person will readily understand modifications to the process steps described here to achieve different configurations.

[0045] Fig. 17A and Fig. Figure 17B illustrates the formation of one or more dielectric layers 122 and conductive features 124 within the one or more dielectric layers 122. The one or more dielectric layers 122 may, for example, comprise an etch stop layer (ESL) and an interlayer dielectric (ILD) or an intermetal dielectric (IMD). The etch stop layer may be deposited over the one or more dielectric layers 100, contacts 120, masks 106, etc. The etch stop layer may comprise silicon nitride, silicon carbonitride, silicon carbon oxide, carbonitride, the like, or a combination thereof, and may be deposited by CVD, PECVD, ALD, or another deposition technique.The dielectric interlayer or intermetal dielectric can be silicon dioxide, a low-K dielectric such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiO. x C y The dielectric interlayer or intermetal dielectric may comprise or be spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite material thereof, the like, or a combination thereof. The dielectric interlayer or intermetal dielectric may be deposited by spin deposition, CVD, FCVD, PECVD, PVD, or any other deposition technique.

[0046] Recesses and / or openings are formed in and / or through the one or more dielectric layers 122, where the conductive features 124 are to be formed. The one or more dielectric layers 122 can be structured with the recesses and / or openings, for example, using photolithography and one or more etching processes. The conductive features 124 can then be formed in the recesses and / or openings. The conductive features 124 can, for example, comprise a barrier layer and conductive material formed on the barrier layer. The barrier layer can be conformally deposited in the recesses and / or openings and over the one or more dielectric layers 122.The barrier layer can be, for example, titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, the like, or a combination thereof, and can be deposited by ALD, CVD, or another deposition technique. The conductive material can be, or comprise, tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and can be deposited by CVD, ALD, PVD, or another deposition technique. After the material of the conductive contacts 124 has been deposited, excess material can be removed using a planarization process, such as CMP. The planarization process can remove excess material of the conductive features 124 from above a top surface of the one or more dielectric layers 122. Thus, the top surfaces of the conductive features 124 and the one or more dielectric layers 122 can be coplanar.The conductive features 124 can be contacts, vias, conductive traces, etc., or can be described as such.

[0047] Fig. 18A-B and Fig. Figures 19A-B are cross-sectional views of intermediate stages in an exemplary process for forming one or more FinFETs according to some embodiments. Fig. Figures 18A-B to 19A-B, whose designation ends with an "A", illustrate cross-sectional views along a cross-section corresponding to cross-section AA in Fig. Figure 1 is similar, and figures whose designation ends with a "B" illustrate cross-sectional views along a cross-section that corresponds to cross-section BB in Fig. 1 is similar. It may be that in some figures, some reference symbols for building elements or features illustrated therein have been omitted to avoid making other building elements or features unclear; this serves the purpose of simplicity in the pictorial representation in the figures.

[0048] In the exemplary process of Fig. 18A-B to 19A-B, the processing will be as described above with reference to Fig. 2A-B to 8A- and 11A-B described by the formation of openings 110 through one or more dielectric layers 100 in Fig. 13A-B continued. In this example, the processing that occurs in Fig. 9A-B and Fig. The processing shown in 10A-B is omitted. Fig. 18A-B resumed.

[0049] Fig. 18A and Fig. Figure 18B illustrates an amorphization implant 140. The amorphization implant 140 can be omitted in some embodiments. In some examples, the amorphization implant 140 involves implanting a foreign atom species through the openings 110 through the one or more dielectric layers 100 into the epitaxial source / drain regions 92 to render the upper portions 142 of the epitaxial source / drain regions 92 amorphous. The upper portions 142 that are rendered amorphous can extend, for example, from corresponding upper surfaces of the epitaxial source / drain regions 92 to a depth of about 2 nm to about 20 nm. In some examples, such as for a p-type device, the epitaxial source / drain regions 92 are Si x Ge 1-xGermanium is the species implanted to amorphize the upper sections 142 of the epitaxial source / drain regions 92. In such examples, the implantation energy can be in a range of about 1 keV to about 15 keV, such as about 10 keV, with a dosage concentration in a range of about 5 × 10 13 cm -2 up to about 5×10 14 cm -2 lay.

[0050] Fig. 19A and Fig. Figure 19B illustrates a dopant implant 144 in the upper sections 142 of the epitaxial source / drain regions 92. The dopant implant 144 can implant dopants through the openings 110 through the one or more dielectric layers 100 in the upper sections 142 to reduce contact resistance between the corresponding epitaxial source / drain region 92 and a conductive feature (e.g., comprising a contact) that is subsequently formed. In some examples, the dopant species used for the dopant implant 144 can amorphize the upper sections 142 upon implantation (and can therefore be described as self-amorphizing). In these examples, or in different examples, the amorphizing implant 140 can be Fig. 18A and Fig. 18B is omitted. The dopant implant 144 implants dopant materials into the upper sections 142 according to the invention, such that the upper sections 142, from the corresponding upper surfaces of the upper sections 142 to depths of 5 nm or greater, possibly 10 nm or greater, or 15 nm or greater, have a uniform concentration of the dopant. The uniform concentration of the dopant may be higher than the concentration of the dopant that at least partially delineates the source / drain regions (e.g., formed by implantation and / or doping on site during epitaxial growth). The concentration of the dopant in the epitaxial source / drain regions 92 may decrease from the uniform concentration to further depths of the epitaxial source / drain regions 92.Additional exemplary details of the dopant implant 144 and the concentrations of the dopant resulting from the dopant implant 144 are given below with reference to . Fig. 20 and Fig. 21 described.

[0051] In some examples, such as for a p-type device, the epitaxial source / drain regions are 92 Si x Ge 1-x Gallium is the species that is implanted into the upper sections 142 of the epitaxial source / drain regions 92 for the dopant implant 144. In such examples, the implantation energy can be in a range of about 0.5 keV to about 10 keV, with a dosage concentration in a range of about 1 × 10 15 cm -2 up to about 1×10 16 cm -2 The uniform concentration of gallium from the upper surfaces of the epitaxial source / drain regions 92 down to the depth can be found in a range of approximately 10 21 cm-3 up to about 10 22 cm -3 and in particular about 5×10 21 cm -3 lay.

[0052] Following the dopant implantation 144, annealing is performed to activate the dopants and recrystallize the upper sections 142 that have been amorphized (e.g., by the amorphization implant 140 and / or by the dopant implant 144). In some examples, the annealing may be carried out at a temperature in the range of approximately 600°C to approximately 900°C for a duration of approximately one minute or less, approximately 12 seconds or less, or approximately one second or less. In other examples, the annealing may be laser annealing performed for a duration of several nanoseconds, such as approximately 100 ns or less. In still other examples, the annealing may be melt annealing performed for a duration of a few nanoseconds, such as approximately 1 ns.

[0053] In the exemplary process of Fig. 18A-B to 19A-B, processing with an amorphization implant, if performed, is carried out by processing of Fig. 14A-B to Fig. 17A-B resumed.

[0054] Fig. Figure 20 illustrates a cross-sectional view of the conductive feature (which includes, for example, the contact 120) and the epitaxial source / drain region 92 according to some embodiments. The epitaxial source / drain region 92 comprises a platform dopant region 200 and a residual dopant region 202. The dopant concentration, for example, of the dopant that is in Fig. 10A-B and Fig. The concentration of 19A-B implanted in the platform dopant region is essentially uniform or constant across the platform dopant region 200. From the essentially uniform or constant dopant concentration in the platform dopant region 200, the dopant concentration decreases with a gradient in the residual dopant region 202.

[0055] Fig. Figure 21 is a graphical representation illustrating various dopant profiles according to some embodiments. The graphical representation illustrates a profile 300 of the dopant as implanted (e.g., with or without an amorphization implant preceding the dopant implant), a first dopant profile 302 as annealed, without a preceding amorphization implant, and a second dopant implant 304 as annealed, without a preceding amorphization implant. The illustrated dopant profiles are for gallium implanted in silicon germanium. Any amorphization implants for profiles 300 and 304 use germanium as the implant species, and annealing processes for profiles 302 and 304 are rapid thermal annealing at 1000 °C. Other examples may involve different dopants, materials into which the dopant is implanted, amorphization species, or annealing processes.

[0056] As illustrated, each of profiles 300, 302, and 304 exhibits a substantially uniform or constant dopant concentration over an entire depth of up to approximately 8 nm (e.g., for profile 302) or approximately 12 nm (e.g., for profiles 300 and 304). These substantially uniform or constant dopant concentrations may, in some examples, constitute the platform doping region 200. From these substantially uniform or constant dopant concentrations (e.g., starting at a depth of approximately 8 nm, e.g., for profile 302, or approximately 12 nm, e.g., for profiles 300 and 304), the dopant concentrations decrease as the profile extends further from the substantially uniform or constant dopant concentrations in profiles 300, 302, and 304 (e.g., with increasing depth).

[0057] As previously described, the dopant species for the dopant implant can be gallium in some examples. Gallium can have advantageous aspects in some cases. For example, gallium has a higher solid-state solubility in germanium than other dopant species, such as boron. Thus, if the germanium content in the epitaxial source / drain regions is high, gallium may exhibit higher activation and therefore contribute more holes compared to other dopants. Furthermore, gallium (e.g., Ga) can 69 ) may be larger on an atomic scale than other species, such as boron. This may allow gallium implants to be self-amorphizing, thus eliminating the need for an amorphization implant preceding a gallium implant.

[0058] Furthermore, the platform concentrations of the dopant profiles, which are in Fig. Figure 21 illustrates the processes that can be achieved by implanting gallium, facilitating the presence of a suitable concentration on an area of ​​the epitaxial source / drain regions 92 and / or silicide regions 118. For example, in some exemplary processes, a certain loss of the epitaxial source / drain regions 92 can be carried out as a result of etching, such as during the processing described in Fig. Figure 13A-B illustrates this. In some examples, even with a certain loss of epitaxial source / drain regions 92, such as a loss of 5 nm (e.g., such that the platform concentration remains at a depth of 3 nm, 5 nm, 7 nm, or 10 nm in the epitaxial source / drain regions 92), the platform concentration can allow the dopant concentration at the surface to remain essentially unchanged. It may be that other dopant species are unable to achieve a platform concentration, and thus, with a certain loss of epitaxial source / drain regions 92, the dopant concentration at the surface can decrease. Accordingly, in some examples, a high dopant concentration can be achieved, which can reduce the contact resistance to the epitaxial source / drain region 92 (e.g., between the conductive feature 120 and the epitaxial source / drain region 92).

[0059] Gallium also exhibits a lower probability of diffusion compared to other dopant species. This allows the dopant profile to remain close to the implanted profile after subsequent processing, such as annealing. This can permit greater flexibility in the thermal balance during processing. For example, the dopant implantation can be performed prior to various high-temperature processes. Furthermore, because gallium is less susceptible to diffusion, short-channel effects in a transistor, such as a FinFET, can be mitigated.

[0060] As previously stated, the device structures can vary in different designs. Fig. Figure 22 illustrates a cross-sectional view of a section of another embodiment of a device structure according to some embodiments. The structure of Fig. 22 can be described as a “crown” structure, whereas the structure of, for example, Fig. 4B can be described as a "non-crown" structure. As in Fig. As illustrated in Figure 22, the lower surfaces of the isolation regions 78 can be located on different planes. This can be obtained during the structuring of the semiconductor substrate 70 when forming the fins 74, for example by two or more structuring and etching processes.

Claims

[1] Structure comprising the following: an active region of a transistor, wherein the active region comprises a source / drain region (92), wherein the source / drain region (92) is defined at least partially by a first dopant, which constitutes a first dopant concentration, wherein the source / drain region (92) further comprises a second dopant having a concentration profile that exhibits a constant concentration from an area of ​​the source / drain region (92) to a depth of the source / drain region (92), wherein the constant concentration is higher than the first dopant concentration, and wherein the depth is at least 5 nm; and a conductive feature (124) that contacts the source / drain area (92) at the surface of the source / drain area (92). [2] Structure according to claim 1, wherein the active region comprises a fin (74) and the transistor is a fin field-effect transistor. [3] Structure according to claim 1 or 2, wherein the source / drain region (92) comprises a material containing germanium and the second dopant comprises a species containing gallium. [4] Structure according to any of the preceding claims, wherein the depth is at least 10 nm. [5] Structure according to any one of the preceding claims 1 to 3, wherein the depth is at least 15 nm. [6] Structure according to one of the preceding claims, wherein the constant concentration is higher than 1×10 21 cm -3 is. [7] Structure according to one of the preceding claims, further comprising a dielectric layer (122), wherein at least one section of the conductive feature (124) is located in at least one section of the dielectric layer (122) and wherein the conductive feature (124) comprises a silicide (118) on the surface of the source / drain region (92) and a contact (120) to the silicide (118). [8] Structure comprising the following: a substrate (70) comprising a fin (74), wherein the fin (74) has a source / drain region (92), the source / drain region (92) comprising a material containing germanium, the source / drain region (92) further comprising a profile of a gallium concentration, the profile having a platform on a surface of the source / drain region (92) and decreasing from the platform into the source / drain region (92), the platform extending at least 5 nm into the source / drain region (92) from the surface of the source / drain region (92); a gate structure above the fin (74); a silicide area (118) on the surface of the source / drain area (92); and a contact (120) on the silicide area (118) [9] Structure according to claim 8, wherein the platform extends from the surface of the source / drain region (92) at least 10 nm into the source / drain region (92). [10] Structure according to any one of the preceding claims 8 to 9, wherein the platform has a concentration higher than 1×10 21 cm -3 is. [11] Structure according to any one of the preceding claims 8 to 10, wherein the source / drain region (92) comprises a dopant having a concentration which is lower across the source / drain region (92) than the concentration of the platform. [12] Method comprising the following: Defining an active region on a substrate (70), wherein the active region comprises a source / drain region (92), wherein the source / drain region (92) is at least partially defined by a first dopant having a first concentration; Implanting a second dopant (98; 144) into the source / drain region (92), wherein the second dopant has a constant concentration extending from an area of ​​the source / drain region (92) to a depth in the source / drain region (92), the constant concentration being higher than the first concentration, the depth being at least 5 nm; and Forming a conductive feature that contacts the source / drain area (92). [13] Method according to claim 12, wherein the source / drain region (92) comprises a material containing germanium and the second dopant comprises a species containing gallium. [14] Method according to claim 12 or 13, wherein the implantation of the second dopant into the source / drain region (92) amorphizes at least one section (96; 142) of the source / drain region (92). [15] Method according to any one of the preceding claims 12 to 14, further comprising the amorphization of at least one section (96; 142) of the source / drain region (92), which includes the implantation of an amorphization foreign atom (94; 140) into the source / drain region (92) prior to the implantation of the second dopant. [16] Method according to any one of the preceding claims 12 to 15, wherein the depth is at least 15 nm. [17] Method according to any one of the preceding claims 12 to 15, wherein the depth is at least 10 nm. [18] Method according to any one of the preceding claims 12 to 17, wherein defining the active area on the substrate (70) comprises defining the source / drain region (92) in the active region, wherein defining the source / drain region (92) comprises epitaxial growth of the source / drain region (92). [19] Method according to claim 18, wherein the epitaxial growth of the source / drain region (92) comprises doping on site of the source / drain region (92) with the first dopant.

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