Semiconductor device

Abstract

Semiconductor device (1) with a half-bridge arrangement comprising: at least one P-terminal (21) connected to an upper end of a half-bridge; at least one N-terminal (22) connected to a lower end of the half-bridge; a power output terminal (23) which is connected to a connection point between an upper switching element (2) of the half-bridge and a lower switching element (3) of the half-bridge; at least one power supply connection (25) and at least one ground (GND) connection (26), each connected to a control circuit (4) and configured to control the upper switching element (2) and the lower switching element (3); at least one control terminal (24) through which the control circuit (4) is configured to control the upper switching element (2) and the lower switching element (3); and a housing (20) which is rectangular in a top view and accommodates the upper switching element (2), the lower switching element (3) and the control circuit (4), wherein the at least one control terminal (24) is arranged on a first side of the housing (20) opposite a second side on which the power output terminal (23) is arranged, and wherein the at least one P-terminal (21), the at least one N-terminal (22), the at least one power supply terminal (25) and the at least one ground (GND) terminal (26) are arranged orthogonally to the second side on a third side of the housing (20).

Description

Background of the inventionField of the invention

[0001] The present invention relates to power semiconductor devices. Description of the state of the art

[0002] A conventional DIPIPM (registered trademark) includes an insulated gate bipolar transistor (IGBT) with a three-phase full bridge, a freewheeling diode (FWD), and a control circuit. Output terminals (U, V, W) are arranged between terminals used to conduct a main current, that is, between a P-type input terminal, which is a main terminal, and an N-type input terminal, which is a main terminal. The control circuit includes a plurality of power supply terminals. On a substrate of an inverter, a three-phase AC power supply is connected to the P-type and N-type terminals of the DIPIPM through a diode bridge and a smoothing capacitor. A power supply of the control circuit is supplied separately by a device such as a transformer.The DIPIPM acts to protect against short circuit and is able to protect the IGBT by sensing a voltage across a shunt resistor through which the control circuit is connected to the N terminal.

[0003] The main terminals and the control circuit terminals are conventionally arranged opposite each other on sides of a package. Therefore, on the main terminal sides, a wire connected to the P terminal, a wire connected to the N terminal through the shunt resistor, and an output wire cross each other; and in the terminals of a control circuit side, a power supply wire and a ground (GND) wire cross each other. Further, in the control circuit, the wire from the N terminal is connected to a terminal for detecting and protecting against short circuits. As such, the wires running from the main terminal sides to the terminals of the control circuit side are complicated. Therefore, when a module has a high current consumption, it is difficult to obtain a sufficient cross-sectional area of ​​a wire pattern on the substrate.This leads to the need for a multilayer substrate or a wiring material such as a jumper wire.

[0004] For example, Japanese Unexamined Patent Application Publication (Translation of a PCT Application) JP 2007-502544 A discloses a module on which a power device is mounted. This module is configured such that an output line and a pin line are disposed opposite each other on sides of a molded body. The module is also configured such that a power input line (corresponding to the P terminal) and a ground line (corresponding to the N terminal) are disposed on a side of the molded body orthogonal to the side on which the output line is disposed. Such an arrangement prevents the wire connected to the P terminal, the wire connected to the N terminal, and the output wire from crossing each other.

[0005] However, the module of unexamined Japanese patent application publication (translation of a PCT application) JP 2007-502544 A does not include a control circuit. Unexamined Japanese patent application publication (translation of a PCT application) JP 2007-502544 A fails to disclose a positional relationship between the power supply terminal of the control circuit and the GND terminal. Thus, the use of the technique of unexamined Japanese patent application publication (translation of a PCT application) JP 2007-502544 A in the conventional DIPIPM would not eliminate the crossover of the power supply wire and the GND wire in the terminals of the control circuit. Simple wiring is therefore difficult when mounting the module.

[0006] From DE 44 18 426 A1 a semiconductor power module is known in which a copper pattern is exposed on an outer surface of the unit, the copper pattern being provided on a power substrate having a DBC substrate structure. Summary of the invention

[0007] It is an object of the present invention to provide a semiconductor device capable of achieving easy wiring in mounting the semiconductor device.

[0008] The semiconductor device according to one aspect of the present invention comprises a half-bridge arrangement. The semiconductor device comprises at least one P-terminal, at least one N-terminal, a power output terminal, at least one power supply terminal, at least one ground (GND) terminal, at least one control terminal, and a package that is rectangular in plan view. The at least one P-terminal is connected to a top end of a half-bridge. The at least one N-terminal is connected to a bottom end of the half-bridge. The power output terminal is connected to a connection point between a top-side switching element of the half-bridge and a bottom-side switching element of the half-bridge.Each of the at least one power supply terminal and the at least one GND terminal is connected to a control circuit configured to control the top-side switching element and the bottom-side switching element. The at least one control terminal configures the control circuit to control the top-side switching element and the bottom-side switching element. The housing accommodates the top-side switching element, the bottom-side switching element, and the control circuit. The at least one control terminal is arranged on a first side of the housing opposite a second side on which the power output terminal is arranged. The at least one P-terminal, the at least one N-terminal, the at least one power supply terminal, and the at least one GND terminal are arranged on a third side of the housing orthogonal to the second side.

[0009] The at least one control terminal is arranged on the first side of the housing opposite the second side. Such an arrangement prevents a wire connected to the at least one control terminal and a wire connected to the power output terminal from crossing each other. The at least one P-terminal, the at least one N-terminal, the at least one power supply terminal, and the at least one GND terminal are arranged on the third side of the housing orthogonal to the second side. Such an arrangement enables a plurality of semiconductor devices to be connected to each other so as to be adjacent to the third side when the semiconductor devices have a full-bridge arrangement.As a result, wires connected to the at least one P terminal, the at least one N terminal, the at least one power supply terminal, and the at least one GND terminal are partially enclosed within the package. This provides for easy wiring when mounting the semiconductor device.

[0010] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following description of the present invention when taken in conjunction with the accompanying drawings. Short description of the drawings Fig. 1 is a top perspective view of a semiconductor device according to a first preferred embodiment; Fig. 2 is a cross-sectional view taken along a line AA in Fig. 1 is recorded; Fig. 3 is a circuit diagram of the semiconductor device according to the first preferred embodiment; Fig. 4 is a circuit diagram of an exemplary arrangement of a three-phase inverter of the semiconductor device according to the first preferred embodiment; Fig. 5 is a cross-sectional view of a semiconductor device according to a second preferred embodiment; Fig. 6 is a top perspective view of a semiconductor device according to a third preferred embodiment; Fig. 7 is a cross-sectional view taken along a line BB in Fig. 6 is included; and Fig. 8 is a circuit diagram of an exemplary arrangement of a three-phase inverter of a semiconductor device according to a basic technique. Description of the preferred embodiments<Erste bevorzugte Ausführungsform>

[0011] The following describes a first preferred embodiment of the present invention with reference to the drawings. Fig. 1 is a top perspective view of a semiconductor device 1 according to the first preferred embodiment. Fig. 2 is a cross-sectional view taken along a line AA in Fig. 1 is recorded. Fig. 3 is a circuit diagram of the semiconductor device 1.

[0012] As in Fig. 1 and Fig. As shown in Figure 2, the semiconductor device 1 is a transfer molded power module. The semiconductor device 1 includes an insulated gate bipolar transistor (IGBT) 2, an IGBT 3, a control circuit 4, freewheeling diodes (FWDs) 5 and 6, lead frames 7 to 13, P-type terminals 21, N-type terminals 22, a power output terminal 23, control terminals 24, power supply terminals 25, ground (GND) terminals 26, and a package 20. The IGBT 2 is a top-side switching element. The IGBT 3 is a bottom-side switching element.

[0013] Each of the lead frames 7 to 13 is a machined, thin metal plate in a wire shape. The IGBT 2 is mounted on an upper surface of the lead frame 7. The lead frame 7 is a first lead frame. The IGBT 3 is mounted on an upper surface of the lead frame 8 and is connected in series with the IGBT 2 by an internal wire. The lead frame 8 is a second lead frame. The control circuit 4 is mounted on an upper surface of the lead frame 12. The control circuit 4 is connected to the gate terminals of the IGBT 2 and the IGBT 3 by internal wires and controls switching operations of the IGBT 2 and the IGBT 3. The control circuit 4 is also connected to the N-terminals 22 by an internal wire and detects overcurrents of the IGBT 2 and the IGBT 3 in response to an input from the N-terminals 22 to protect against a short circuit.

[0014] As in Fig. 1, Fig. 2 and Fig. 3, the respective P-terminals 21 are arranged at one end of the lead frame 7 and one end of the lead frame 9. The P-terminals are connected by an internal wire to a collector terminal of the IGBT 2. This collector terminal is a top end of a half-bridge. The N-terminals 22 are arranged at both ends of the lead frame 10 and are connected by an internal wire to an emitter terminal of the IGBT 3. This emitter terminal is a bottom end of the half-bridge. The power output terminal 23 is arranged at one end of the lead frame 8 and is connected by an internal wire to a connection point between the IGBT 2 and the IGBT 3, more precisely to a connection point between an emitter terminal of the IGBT 2 and a collector terminal of the IGBT 3.

[0015] The FWD 5 is mounted on the upper surface of the lead frame 7. The FWD 5 is connected between the emitter terminal and the collector terminal of the IGBT 2, with the emitter terminal close to an anode of the FWD 5. The FWD 5 allows a reverse current to flow while the IGBT 2 is turned off. The FWD 6 is mounted on the upper surface of the lead frame 8. The FWD 6 is connected between the collector terminal and the emitter terminal of the IGBT 3, with the emitter terminal close to the anode of the FWD 6. The FWD 6 allows a reverse current to flow while the IGBT 3 is turned off.

[0016] The control circuit 4 controls the IGBT 2 and the IGBT 3 through the control terminals 24. Each of the control terminals 24 is arranged at one end of the lead frame 13 and is connected to the control circuit 4 by an internal wire. The semiconductor device 1 has six control terminals 24 and is configured such that a bootstrap diode (BSD) 27 and a resistor 28 are connected between two of the control terminals 24. The power supply terminals 25 are arranged at both ends of the lead frame 11 and are connected to the control circuit 4 by an internal wire. The GND terminals 26 are arranged on both sides of the lead frame 12 and are connected to the control circuit 4 by an internal wire.

[0017] The housing 20 is made of molded resin and is rectangular in plan view. The housing 20 seals and houses the IGBTs 2 and 3, the control circuit 4, the FWDs 5 and 6, and the lead frames 7 to 13, except for the locations where the terminals are arranged.

[0018] The following describes a positional relationship of the individual terminals in the semiconductor device 1 by referring to Fig. 1. The power output terminal 23 is in Fig. 1 on the lower side of the housing 20. The control terminals 24 are in Fig. 1 on the upper side of the housing 20; that is, the control terminals 24 are arranged on a side of the housing 20 opposite the lower side on which the power output terminal 23 is arranged. The P terminals 21, the N terminals 22, the power supply terminals 25 and the GND terminals 26 are in Fig. 1 are arranged on the left and right sides of the housing 20; that is, these terminals are arranged on the sides of the housing 20 orthogonal to the lower side on which the power output terminal 23 is arranged. The P terminals 21, the N terminals 22, and the power output terminal 23 are main terminals.

[0019] The following describes an exemplary arrangement of a three-phase inverter of the semiconductor device 1. Fig. 4 is a circuit diagram of the exemplary arrangement of the three-phase inverter of the semiconductor device 1.

[0020] As in Fig. 4, the semiconductor device 1 has a half-bridge configuration. Thus, for the semiconductor device 1 to have a full-bridge configuration, it is assumed that three semiconductor devices 1 are arranged, and for use, the P terminals 21 of the adjacent semiconductor devices 1 are connected to each other, the N terminals 22 of the adjacent semiconductor devices 1 are connected to each other, the power supply terminals 25 of the adjacent semiconductor devices 1 are connected to each other, and the GND terminals 26 of the adjacent semiconductor devices 1 are connected to each other. A three-phase AC power supply 40 is connected to the P terminals 21 through a diode bridge 41 and a smoothing capacitor 42. The three-phase AC power supply 40 is also connected to the N terminals 22 through the diode bridge 41, the smoothing capacitor 42, and a shunt resistor 44.During operation of the three-phase inverter, the three-phase AC power supply 40 applies a DC power supply voltage between the P terminals 21 and the N terminals 22 through the diode bridge 41 and the smoothing capacitor 42. A DC power supply 43 is connected to the power supply terminals 25. A motor 45 is connected to the power output terminals 23.

[0021] Fig. Figure 4 illustrates an example of a three-phase inverter. In a two-phase inverter, two semiconductor devices 1, each having a half-bridge configuration, are connected together. Furthermore, a required number of semiconductor devices 1, each having a half-bridge configuration, is used to form a plurality of inverters operating from a single power supply, as shown in Fig. 4 shown arrangement added.

[0022] The following describes an advantage achieved due to the semiconductor device 1 according to the first preferred embodiment by referring to a comparison with a semiconductor device according to a basic technique. Fig. 8 is a circuit diagram of an exemplary arrangement of a three-phase inverter of the semiconductor device according to the basic technique.

[0023] First, reference is made to a three-phase inverter 100 having the semiconductor devices according to the basic technique. As shown in Fig. As shown in Figure 8, the three-phase inverter 100 is configured such that main terminals and terminals of a control circuit are arranged on opposite sides of a case 101. Thus, wires connected to P terminals, wires connected to N terminals through a shunt resistor, and an output wire cross each other at main terminal sides. Further, a power supply wire and a GND wire cross each other at terminals of a control circuit side. Still further, the wires from the N terminals are connected to terminals in the control circuit for detecting and protecting against a short circuit. As such, the wires passing from the main terminal sides through the terminals of the control circuit side are complicated. Therefore, when the three-phase inverter 100 has a high current consumption, it is difficult to obtain a sufficient cross-sectional area of ​​a wiring pattern on a substrate.This leads to the need for a multilayer substrate or a wiring material such as a jumper wire.

[0024] In contrast, the semiconductor device 1 according to the first preferred embodiment is as shown in Fig. 4, the semiconductor device 1 is configured such that control terminals 24 are arranged on the side of the package 20 opposite the lower side on which the power output terminal 23 is arranged. Such an arrangement prevents wires connected to the control terminals 24 and the wire connected to the power output terminal 23 from crossing each other. Furthermore, the semiconductor device 1 is configured such that the P-terminals 21, the N-terminals 22, the power supply terminals 25, and the GND terminals 26 are arranged on the side of the package 20 orthogonal to the lower side on which the power output terminal 23 is arranged.Such an arrangement allows a plurality of semiconductor devices 1 to be connected to each other so that they are adjacent to the side on which the P-terminals 21, the N-terminals 22, the power supply terminals 25, and the GND terminals 26 are arranged when the semiconductor devices 1 have the full-bridge arrangement. As a result, the wires connected to the P-terminals 21, the N-terminals 22, the power supply terminals 25, and the GND terminals 26 are partially enclosed in the housing 20. This provides easy wiring when mounting the semiconductor device 1. Consequently, the area of ​​a substrate is used efficiently.

[0025] The control circuit 4 is connected to the N-terminals 22 by the internal wire. The control circuit 4 further detects the overcurrents of the IGBT 2 and the IGBT 3 in response to the input from the N-terminals 22, thus protecting against short circuits. Such an arrangement enables short-circuit protection for multiple phases when a plurality of semiconductor devices 1 are connected together to form a multi-phase inverter.

[0026] In the basic technique, the N-terminals and the terminal of the short-circuit detection and protection control circuit are connected by an external wire, as described above. Thus, the wires pass from the main terminal sides through the terminals of the control circuit side. This causes complicated wiring. The control circuit 4 is connected to the N-terminals 22 by the internal wire. This eliminates the need for the external wire used to connect the N-terminals 22 and the short-circuit detection and protection terminal. Consequently, simple wiring is provided when mounting the semiconductor device 1.

[0027] The P terminals 21, the N terminals 22, the power supply terminals 25, and the GND terminals 26 are arranged on the same side of the housing 20. Such an arrangement prevents the wires from the three-phase AC power supply 40, which are connected to the P terminals 21, the N terminals 22, the power supply terminals 25, and the GND terminals 26, from crossing each other. <Zweite bevorzugte Ausführungsform>

[0028] The following describes a semiconductor device 1A according to a second preferred embodiment. Fig. 5 is a cross-sectional view of the semiconductor device 1A according to the second preferred embodiment. In the second preferred embodiment, Fig. 5 to Fig. 2. In the second preferred embodiment, the same components as those described in the first preferred embodiment are denoted by the same reference numerals. Thus, the description of the same components is omitted.

[0029] As in Fig. As shown in Figure 5, the semiconductor device 1A further includes an insulator 50 disposed on the lower surfaces of the lead frame 7 and the lead frame 8, and a metal plate 51 disposed on the lower surface of the insulator 50. The insulator 50 is preferably made of a resin with a ceramic filler. The metal plate 51 is preferably made of a metal with high radiance, such as aluminum or copper.

[0030] As described above, the semiconductor device 1A according to the second preferred embodiment further includes: the lead frame 7 on which the IGBT 2 is mounted, the lead frame 7 having the P-terminals 21; the lead frame 8 on which the IGBT 3 is mounted, the lead frame 8 having the power output terminal 23; the insulator 50 disposed on the lower surfaces of the lead frame 7 and the lead frame 8; and the metal plate 51 disposed on the lower surface of the insulator 50. Therefore, such an arrangement improves heat conduction from the IGBT 2 and the IGBT 3 to a heat radiation surface and thus provides a uniform thickness of a heat radiation path compared to the arrangement of the first preferred embodiment. <Dritte bevorzugte Ausführungsform>

[0031] The following describes a semiconductor device 1B according to a third preferred embodiment. Fig. 6 is a top perspective view of the semiconductor device 1B according to the third preferred embodiment. Fig. 7 is a cross-sectional view taken along a line BB in Fig. 6. In the third preferred embodiment, the same components as those described in the first and second preferred embodiments are denoted by the same reference numerals. Thus, the description of the same components is omitted.

[0032] As in Fig. 6 and Fig. As shown in FIG. 7, the semiconductor device 1B according to the third preferred embodiment includes a substrate 57 on which the IGBT 2 is mounted and a substrate 58 on which the IGBT 3 is mounted, instead of the lead frame 7 and the lead frame 8. The substrate 57 is a first insulating substrate. The substrate 58 is a second insulating substrate. Metal wire patterns (corresponding to metal patterns) are formed in regions where the IGBT 2 and the IGBT 3 are mounted, for example, by etching on an insulating material such as ceramic. This completes the substrate 57 and the substrate 58.

[0033] Fig. 6 and Fig. 7 illustrate that the IGBT 2 and the FWD 5 are mounted on the substrate 57; and the IGBT 3 and the FWD 6 are mounted on the substrate 58. The control circuit 4 may also be mounted on the substrate 57 or the substrate 58.

[0034] As described above, the semiconductor device 1B according to the third preferred embodiment includes the substrate 57 on which the IGBT 2 is mounted and the substrate 58 on which the IGBT 3 is mounted. The substrate 57 has the metal wire pattern in the region on which the IGBT 2 is mounted, and the substrate 57 is the first insulating substrate. The substrate 58 has the metal wire pattern in the region on which the IGBT 3 is mounted, and the substrate 58 is the second insulating substrate. The second preferred embodiment describes that the insulator 50 is made of a resin so that the lead frame 7 and the lead frame 8 are well connected to each other. In contrast, the third preferred embodiment describes that the substrate 57 and the substrate 58 are made by forming the metal wire patterns on the insulating material such as ceramic.Therefore, the substrate 57 and the substrate 58 have improved heat radiation performance than the insulator 50. Consequently, the third preferred embodiment achieves further improved heat radiation performance than the second preferred embodiment.

[0035] In summary, a semiconductor device is provided that is capable of achieving simple wiring upon mounting the semiconductor device. A semiconductor device 1 has a half-bridge arrangement. The semiconductor device 1 has at least one P-terminal 21, at least one N-terminal 22, a power output terminal 23, at least one power supply terminal 25, at least one ground (GND) terminal 26, at least one control terminal 24, and a housing 20 that is rectangular in plan view and accommodates an insulated gate bipolar transistor (IGBT) 2, an IGBT 3, and a control circuit 4. The at least one control terminal 24 is arranged on a first side of the housing 20 opposite a second side on which the power output terminal 23 is arranged.The at least one P-terminal 21, the at least one N-terminal 22, the at least one power supply terminal 25 and the at least one GND terminal 26 are arranged on a third side of the housing 20 orthogonal to the second side. List of reference symbols 1, 1A, 1B semiconductor device 2, 3 Insulated gate bipolar transistor (IGBT) 4 Control circuit 5, 6 Freewheeling diode (FWD) 7 - 13 ladder frames 20 housings 21 P-connection 22 N-connector 23 Power output connector 24 control connection 25 Power supply connection 26 Ground (GND) connection 27 Bootstrap Diode (BSD) 28 Resistance 40 three-phase AC power supply 41 Diode bridge 42 smoothing capacitor 43 DC power supply 44 Shunt resistance 45 engine 50 insulators 51 metal plate 57, 58 Substrat 100 three-phase inverters 101 housings

Claims

[1] Semiconductor device (1) with a half-bridge arrangement, comprising: at least one P-terminal (21) connected to a top end of a half-bridge; at least one N-terminal (22) connected to a lower end of the half-bridge; a power output terminal (23) connected to a connection point between a top-side switching element (2) of the half-bridge and a bottom-side switching element (3) of the half-bridge; at least one power supply terminal (25) and at least one ground (GND) terminal (26), each connected to a control circuit (4) and configured to control the upper-side switching element (2) and the lower-side switching element (3); at least one control terminal (24) through which the control circuit (4) is configured to control the upper-side switching element (2) and the lower-side switching element (3); and a housing (20) which is rectangular in plan view and accommodates the upper-side switching element (2), the lower-side switching element (3) and the control circuit (4), wherein the at least one control terminal (24) is arranged on a first side of the housing (20) opposite a second side on which the power output terminal (23) is arranged, and wherein the at least one P terminal (21), the at least one N terminal (22), the at least one power supply terminal (25) and the at least one ground (GND) terminal (26) are arranged on a third side of the housing (20) orthogonal to the second side. [2] The semiconductor device according to claim 1, wherein the control circuit (4) is connected to the at least one N-terminal (22) by an internal wire and is configured to detect an overcurrent of the high-side switching element (2) and an overcurrent of the low-side switching element (3) in response to an input from the at least one N-terminal (22) to protect against a short circuit. [3] A semiconductor device according to claim 1 or 2, further comprising: a first lead frame (7) on which the top-side switching element (2) is mounted, the first lead frame (7) having the at least one P-terminal (21); a second lead frame (8) on which the lower-side switching element (3) is mounted, the second lead frame (8) having the power output terminal (23); an insulator (50) disposed on a lower surface of the first lead frame (7) and a lower surface of the second lead frame (8); and a metal plate (51) arranged on a lower surface of the insulator (50). [4] A semiconductor device according to claim 1 or 2, further comprising: a first insulating substrate (57) on which the top-side switching element (2) is mounted, the first insulating substrate (57) having a metal pattern in a region on which the top-side switching element (2) is mounted; and a second insulating substrate (58) on which the lower-side switching element (3) is mounted, wherein the second insulating substrate (58) has a metal pattern in a region on which the lower-side switching element (3) is mounted.

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