Semiconductor diode

Abstract

Semiconductor diode with a plate-shaped semiconductor element (1), having a top (2), a bottom (3) and edges (4), wherein the edges (4) are formed as straight lines, wherein the top (2) is provided with a continuous p-doped layer (11) and the bottom (3) with a continuous heavily n-doped layer (12), wherein a weakly n-doped layer (13) and a moderately n-doped layer (14) are arranged between the heavily n-doped layer (12) and the p-doped layer (11), wherein the edges (4) have edge grooves (21) in which the thickness of the plate-shaped semiconductor element (1) is reduced, wherein in the region of the edge grooves (21) the p-doped layer (11) directly contacts the weakly n-doped layer (13), wherein further grooves (23) are provided starting from the bottom (3) which are not aligned parallel to the edge grooves (21),and wherein only the weakly n-doped layers (13) are arranged in the region of the edges (4).

Description

[0001] The invention relates to a semiconductor diode according to the class of independent patent claims.

[0002] Semiconductor diodes are known from US 7 521 774 B2, DE 43 20 780 A1, and DE 199 38 209 A1, each comprising a plate-shaped semiconductor element with a p-doped layer on the top side and a heavily n-doped layer on the bottom side. Between these two layers are a weakly n-doped layer and a moderately n-doped layer. In an edge region of these plate-shaped semiconductor elements, the p-doped layer directly contacts the weakly n-doped layer. This prevents breakdown of the semiconductor diode in the edge region when a reverse voltage is applied. Advantages of the invention

[0003] In contrast, the semiconductor diode according to the invention, with the features of the independent claims, has the advantage that the forward voltage drop and / or forward resistance are significantly reduced. When this diode is used, the power dissipation is correspondingly reduced, which improves its use in rectifiers or generators. This effect is achieved without negatively impacting the blocking behavior.

[0004] Further advantages and improvements result from the features of the dependent patent claims. By selecting the appropriate angle between the various grooves, the risk of breakage, particularly during the manufacturing of the semiconductor diode, can be reduced. Furthermore, very precise orientation of the angle is no longer necessary, which reduces the adjustment effort and thus the manufacturing effort.

[0005] Further advantages and improvements result from the features of the dependent claims. Certain angular ranges, particularly 20 to 70 degrees, preferably 40 to 50 degrees, allow for large tolerances in the orientation of the grooves on the top and bottom surfaces. A large number of grooves on the bottom surface reduces the voltage drop accordingly. Additional grooves on the top surface also reduce the voltage drop. Appropriate metallization allows the plate-shaped diode elements to be easily assembled using standard packaging techniques. Drawings

[0006] Exemplary embodiments of the invention are shown in drawings 5 ​​and 6 and are explained in more detail in the following description.

[0007] They show: Fig. 1 a semiconductor diode according to US 7 521 774 B2, Fig. 2 a semiconductor diode according to DE 43 20 780 A1, Fig. 3 a semiconductor diode according to DE 199 38 209 A1, Fig. 4 a supervision of Fig. 3, Fig. 5 a view of the semiconductor diode according to the invention and Fig. 6 a cross-sectional view through the Fig. 5.

[0008] In the Fig. Figure 1 shows a diode, as already known from US 7 521 774 B2. Fig. Figure 1 shows a cross-section through a plate-shaped semiconductor element 1, which has a top surface 2 and a bottom surface 3. Plate-shaped means that the thickness, i.e., the distance between the top surface 2 and the bottom surface 3, is significantly less than the lateral extent on the top surface 2 or bottom surface 3 between the edges 4. For example, such a plate-shaped semiconductor element 1 has a thickness on the order of 200 µm and a distance between opposite edges 4 on the order of a few millimeters. Typically, such plate-shaped semiconductor elements 1 are manufactured from a very large sheet, a so-called wafer, and then individual plate-shaped semiconductor elements are cut from this wafer by sawing.Since such saw cuts can usually only be made along straight lines, the edges 4 are also usually formed as straight lines, as is shown, for example, below with regard to the . Fig. 4 will be explained further. Since all the aforementioned layers are applied to the large semiconductor wafers, the saw cuts create the edges 4, which extend between the top surface 2 and the bottom surface 3. It should be noted that damage to the semiconductor material is created in the area of ​​the edges 4, necessitating special measures in this area.

[0009] The plate-shaped semiconductor element 1 has a p-doped layer 11 on its top surface, which covers the entire top surface 2. Furthermore, the plate-shaped semiconductor element 1 has a heavily doped n-layer 12, which extends over the entire bottom surface 3. Between the p-doped layer 11 and the heavily n-doped layer 12 are a lightly n-doped layer 13 and a moderately n-doped layer 14. The p-doped layer 11 has a pn junction to both the lightly n-doped layer 13 and the moderately n-doped layer 14. These pn junctions form the actual diode element.

[0010] At the edges 4, the crystal structure of the semiconductor material is damaged due to the sawing process used to cut the large semiconductor wafers into individual semiconductor elements 6. Because of this damage, even very low reverse voltages would cause breakdown in the region of the edges 4, significantly impairing the properties of the pn diode. Therefore, only the weakly n-doped layers 13 are arranged in the region of the edges 4, counteracting premature breakdown. This prevents premature breakdown of the diode in the region of the edges 4, so that the reverse behavior of the diode is determined solely by the pn junction between layers 11 and 14.

[0011] It should also be noted that US patent 7,521,774 B2 uses a process in which a mechanical structuring layer is created by sawing a groove into the top surface 2. In the finished semiconductor element 1, this groove is still visible as a marginal groove 21 in the area of ​​the edges 4.

[0012] In the Fig. Figure 2 shows a similar semiconductor diode, in which a structuring step is also carried out by sawing a trench in the top surface, according to DE 43 20 780 A1. This semiconductor element 1 also has a top surface 2 and a bottom surface 3, a p-doping layer 11 arranged on the top surface, a strong n-doping layer 12 arranged on the bottom surface 3, a weakly n-doped layer 13, and a moderately n-doped layer 14. Furthermore, there is again a rim trench 21 in the region of the edge 4. In contrast to the Fig. However, in 1, the weakly n-doped layer 13 and the moderately n-doped layer 14 are not arranged next to each other, but one above the other, with the p-layer 11 contacting only the weakly doped layer 13 in the region of the edge 4 or the edge grooves 21. Due to this configuration, the breakdown process on the diode according to the Fig. 2 is determined only by the pn junction between the p-doping layer 11 and the n-doped layer 14.

[0013] The behavior of the diodes after the Fig. 1 and Fig. The forward voltage drop in the n-direction is primarily determined by the resistance and thickness of the moderately n-doped layer 14 and the weakly n-doped layer 13. The resistance of the heavily doped layer 12 can be kept relatively low by using a correspondingly high doping concentration. Essentially, only the thickness of the moderately n-doped layer 14 and the weakly n-doped layer 13 can be influenced to minimize the forward voltage drop. However, the thickness of this layer is limited by the overall thickness of the device, as further reduction of the thickness of the semiconductor element 1 across the entire surface is hampered by the risk of breakage of the large, flat semiconductor wafer from which this device is manufactured.However, a method is known from DE 199 38 209 A1 with which the thickness of the semiconductor device 1 can be reduced, at least in certain areas, thereby already enabling a significant improvement in the forward resistance of the diode. In the . Fig. 3. An alternative design is shown, which is essentially the same as the design of the Fig. 1 corresponds to. In contrast to Fig. However, a further trench structure 22 is introduced on the top surface 2. This trench structure 22, located in a central region of the semiconductor element 1, reduces the overall thickness of the device in this central region, so that the p-layer 11 contacts the central n-doped layer at a greater depth, at least in one region of this further trench 22. Specifically, the trench structure 22 establishes contact between the p-layer 11 and the moderately n-doped layer 14. With a total wafer thickness of, for example, 200 µm and a depth of the further trench structure 22 of 30 µm, the thickness of the semiconductor substrate at this point is therefore only 170 µm, and, in particular, the moderately n-doped layer 14 is also contacted at least at one point where this layer is thinner.Although such contact only occurs in the area of ​​the further trench 22, this additional trench structure 22 significantly reduces the resistance of the semiconductor element in the flux direction.

[0014] In the Fig. 4 will show a top view of the upper surface 3 of the semiconductor element after the Fig. Figure 3 shows that, as can be seen in the top view, the edges 4 form a square semiconductor element 1, which is always completely surrounded by a border trench 21 in the area of ​​the edges 4.

[0015] In the central region of the plate-shaped element, the additional trenches 22 are also visible in the top view. These trench structures 21 and 22 are visible in the top view of the upper surface 2, i.e., in the top view of the p-doped layer 11, because the thickness of the semiconductor element 1 is reduced in the region of the edge trenches 21 and the additional trenches 22, respectively.

[0016] According to the invention, it is now provided that the Fig. 1, Fig. 2 or Fig. 3 and Fig. The semiconductor elements described in section 4 are further supplemented by additional trench structures starting from the underside 3. The semiconductor elements according to the invention are placed in the Fig. 5 and Fig. 6 shown.

[0017] In the Fig. Figure 5 again shows a view of a semiconductor element 1, which is essentially the same as the view according to the Fig. 4 corresponds. In accordance with the Fig. Figure 4 again shows a top view of the upper surface 2 of a semiconductor element 1, showing edge grooves 21 and further grooves 22. Furthermore, grooves 23 on the underside of the semiconductor element 1 are also shown. These grooves are not actually visible in the top view, but are shown here to illustrate the invention. They are grooves that are formed in the underside 3, which further reduces the thickness of the semiconductor element 1 in the area of ​​these further grooves 23 in the underside 3.

[0018] It is essential that these additional ditches 23 form an angle with respect to the perimeter ditches 21. Here, "angle" refers to an orientation that is not parallel to the perimeter ditches 21 or to the straight lines forming the edges 4. In the examples following the Fig. For example, the additional trenches 23 are formed at an angle of 45 degrees or 135 degrees to the edge trenches 21 or to the straight edges 4. This measure, that is, the orientation of these additional trenches 23 at an angle relative to the edge trenches 21 or to the straight edges 4, reduces the risk of breakage of the semiconductor element 1. Accordingly, the risk of breakage during manufacturing, i.e., during the processing of the semiconductor wafers from which the semiconductor elements 1 are then sawn, is also reduced. With such an angular orientation of the additional trenches 23 relative to the edge trenches 21, the edge trench 21 and the additional trench 23 only overlap at specific points on the underside 3 of the semiconductor element 1, and do not overlap or run parallel to each other in certain areas.If the grooves on the top and bottom surfaces were parallel and spaced a certain distance apart, handling the large semiconductor wafers could lead to a stress concentration between two such parallel grooves, potentially causing the wafer to break. However, this risk is reliably eliminated by arranging them at an angle to each other.

[0019] In the example after the Fig. The additional grooves 22, which are incorporated into the top surface 3 of the semiconductor element 1, are also oriented parallel to the edge grooves 21, thus automatically forming an angle with the additional grooves 23, which are incorporated into the bottom surface 3. If the edge grooves 21 and the additional grooves 22 are not aligned parallel to each other, but also form an angle, care must be taken to ensure that the additional grooves 22 on the top surface 2 also form an angle with the additional grooves 23 on the bottom surface 3.

[0020] Semiconductor elements are typically rectangular. However, it is also possible to create other geometric shapes, such as triangles, by making straight saw cuts. In such cases, the edge grooves 21 can also have different orientations relative to each other and to the other grooves 23 on the underside 3. It is essential that the other grooves 23 on the underside each form an angle with the edges 4.

[0021] In the example after the Fig. 5 The relative orientation of the further grooves 23 on the underside 3 is chosen to be at an angle of 45 or 135 degrees relative to the straight edges 4. Alternatively, other angles are also possible, but these are preferably in the range between 20 and 70 degrees or 110 and 180 degrees, or even better in the range of 40 and 50 degrees or 130 and 140 degrees. Such angles reliably reduce the risk of breakage in these semiconductor elements.

[0022] In the Fig. In addition to point 5, four more points, 51, 52, 53 and 54, are shown, which correspond to the cross-section as shown in the Fig. 6 is shown, find again.

[0023] In the Fig. 6 is a cross-section through the semiconductor device 1 according to the Fig. 5 shown. The cross-section is positioned so that the in the Fig. Points 51 to 54 shown in the 5 are again shown accordingly in the Fig. 6 appear.

[0024] At point 51, a marginal trench 21 and another trench 23 on the underside occur simultaneously at a single point. As can be seen, at this point, only a very thin, weakly n-doped layer 13 is arranged between the p-layer 11 and the heavily n-doped layer 12. Thus, at this point, the resistance in the forward direction is determined solely by the very small thickness of the weakly n-doped layer 13. Although the current flows through the weakly n-doped layer 13, the overall resistance at point 51 is particularly low and therefore contributes to a corresponding reduction in the overall resistance of the component. Such a configuration always occurs where a trench 21 or 22 on the top side coincides with a trench 23 on the underside at a single point.

[0025] At point 52, the upper p-layer contacts the moderately n-doped layer 14, with the current flowing forward through the entire thickness of the moderately n-doped layer 14. Therefore, the voltage drop, i.e., the resistance, is comparatively high at this point.

[0026] At point 53, the p-layer 11 contacts the weakly n-doped layer 13, which, however, is thinner in this area than the moderately n-doped layer 14. Therefore, the resistance is reduced at this point compared to point 52.

[0027] At point 54, no trench is provided on the top side. However, another trench 23 is provided on the bottom side. It should be noted that after the trenches 23 are created, a further diffusion step takes place in which the doping of the heavily doped layer 12 is increased again. For this purpose, the bottom side 3 is coated with an n-type dopant, which, due to the trenches 23, also diffuses into the semiconductor material at the bottom of the trenches 23. In the area of ​​the additional trenches 23, the heavily n-doped layer 12 is therefore thickened and extends slightly into the moderately n-doped layer 14, or at point 51 into the weakly n-doped layer 13. This measure thus reduces the thickness of the overlying weakly n-doped layers 13 and 14 in the area of ​​the additional trenches 23 on the bottom side 3 of the semiconductor element.At point 54, the thickness of the moderately n-doped layer 14 is also reduced, thereby facilitating current flow at this point by reducing resistance. Thus, the forward resistance of the diode is also reduced at point 54.

[0028] The resistance or voltage drop at the various positions 51 to 54 decreases in the sequence 52, 54, 53, and 51. Even though a reduction in resistance or voltage drop in the forward direction is achieved at individual points or along the grooves 23, this results in an overall improvement of the diode in the forward direction. This improvement manifests itself in a lower diode loss when current flows in the forward direction. Overall, this allows for the production of a significantly improved diode.

[0029] It should also be noted that all dopings mentioned here can be interchanged accordingly, i.e., the p-doping becomes an n-doping and all n-dopings become correspondingly heavily doped p-dopings.

[0030] The width and depth of the trenches on the upper side 22 and on the lower side 23 can be identical or chosen differently.

Claims

[1] Semiconductor diode with a plate-shaped semiconductor element (1), having a top (2), a bottom (3) and edges (4), wherein the edges (4) are formed as straight lines, wherein the top (2) is provided with a continuous p-doped layer (11) and the bottom (3) with a continuous heavily n-doped layer (12), wherein a weakly n-doped layer (13) and a moderately n-doped layer (14) are arranged between the heavily n-doped layer (12) and the p-doped layer (11), wherein the edges (4) have edge grooves (21) in which a thickness of the plate-shaped semiconductor element (1) is reduced, wherein in the region of the edge grooves (21) the p-doped layer (11) directly contacts the weakly n-doped layer (13), wherein further grooves (23) are provided starting from the bottom (3) which are not aligned parallel to the edge grooves (21),and wherein only the weakly n-doped layers (13) are arranged in the region of the edges (4). [2] Semiconductor diode according to claim 1, wherein the further trenches (23) extending from the underside (3) have an angle of 20 degrees to 70 degrees, preferably 40 degrees to 50 degrees, relative to the edge trenches (21). [3] Semiconductor diode according to one of the preceding claims, wherein a plurality of parallel further grooves (23) are provided in the underside (3). [4] Semiconductor diode according to one of the preceding claims, wherein further grooves (22) are provided starting from the top (2) of the semiconductor element (1), which are not aligned parallel to the further grooves (23) of the bottom (3). [5] Semiconductor diode according to one of the preceding claims, wherein a metallization is applied on the top side (2) on the p-doped layer (11) and a further metallization is applied on the bottom side (2) on the heavily n-doped layer (12), wherein the metallization has an ohmic contact to the p-doped layer (11) and the further metallization has an ohmic contact to the heavily n-doped layer (12). [6] Semiconductor diode according to claim 5, wherein the metallization or further metallization is designed as a solderable metallization.

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