PROCESSING UNIT, ELECTRONIC CONTROL UNIT AND PROCESSING METHOD

Abstract

Processing unit (2, 12), comprising: multiple processor cores (31 to 3n), and an interrupt control (8), wherein: the multiple processor cores (31 to 3n) perform parallel processing with barrier synchronization; the interrupt control (8) retains interrupt request target information to determine one of the processor cores (31 to 3n) to perform interrupt handling due to the occurrence of an interrupt; the interrupt control (8) is supplied with an interrupt request target determination signal by one of the processor cores (31 to 3n) and then retains the interrupt request target determination signal as interrupt request target information; and the processor core that first reaches a barrier point to enter a synchronization wait state outputs an interrupt request target determination signal to the interrupt controller (8) and designates itself as the interrupt request target of the interrupt handler.

Description

[0001] The present invention relates to a processing unit, an electronic control unit and a processing method.

[0002] Conventionally, a processing unit is provided that performs parallel processing using barrier synchronization on multiple processor cores (e.g., JP 2000 - 305 919 A).

[0003] When an interrupt occurs, this type of processing unit delivers an interrupt request to any of the multiple processor cores. The processor core receiving the interrupt request performs interrupt handling. However, an interrupt request may be delivered to one of the processor cores that requires the longest processing time for parallel processing. This delays the completion time of the parallel processing performed by all processor cores participating in barrier synchronization, namely the completion time for barrier synchronization.In particular, the motor control requires real-time implementation, tends to cause diversified interrupts to perform timely processes in response to the input of a timer signal or a sensor signal, and is remarkably susceptible to an influence due to a delay in the timing of completing the barrier synchronization.

[0004] US 7 191 294 B2 also discloses a method for synchronizing processors in a system with multiple processors.

[0005] It is an object of the present invention to provide a processing unit, an electronic control unit and a processing method for minimizing a delay in the timing for completing barrier synchronization.

[0006] This object is achieved by the processing unit, the electronic control unit, and the processing method having the features according to the independent claims. Advantageous embodiments are the subject of the dependent claims.

[0007] The above and other aspects, features, and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. In the drawings: Fig. 1 is a functional block diagram showing a first embodiment of the present invention; Fig. 2 a flow chart; Fig. 3 a flow chart; Fig. 4 a flow chart; Fig. 5 a flow chart; Fig. 6 is a functional block diagram showing a second embodiment of the present invention; Fig. 7 a flow chart; Fig. 8 a flow chart; and Fig. 9 a flow chart. (First embodiment)

[0008] The following description explains the first embodiment of the present invention with reference to the Fig. 1 to 5. An electrical control unit 1 performs, for example, engine control and comprises a microcontroller 2 (corresponds to a processing unit). The microcontroller 2 comprises n (n is a natural number) processor cores 31 to 3n, namely a first processor core 31 (PE#1 in Fig. 1) to an n-th processor core 3n (PE#n in Fig. 1), ROM 4, RAM 5, a timer 6, an A / D converter 7 and an interrupt controller 8, which are interconnected via a system bus 9.

[0009] Microcontroller 2 is configured so that multiple processor cores 31 to 3n all participate in barrier synchronization. Processor cores 31 to 3n perform parallel processing using barrier synchronization. Processor cores 31 to 3n start parallel processing concurrently, i.e., each at the same time. Each processor core starts barrier synchronization when a barrier point is reached after completing parallel processing. The processor core updates a synchronization flag, then starts a synchronization flag check process, and waits for the other processor cores 31 to 3n to reach the barrier point. Specifically, processor cores 31 to 3n each complete parallel processing, reach the barrier point, and then enter the synchronization wait state, which leaves sufficient processing capacity for parallel processing.Processor cores 31 to 3n all reach the barrier point to complete barrier synchronization and then simultaneously start the next parallel processing (different from the previously performed parallel processing) at the same starting time. Not all processor cores 31 to 3n need to participate in barrier synchronization. Some of the processor cores 31 to 3n may participate in barrier synchronization.

[0010] Processor cores 31 to 3n can communicate with barrier synchronizer 10. Barrier synchronizer 10 includes multiple synchronization flags corresponding to each of processor cores 31 to 3n. Processor cores 31 to 3n set the corresponding synchronization flags to "0," communicate with barrier synchronizer 10 when parallel processing is completed and the barrier point is reached, and rewrite the corresponding synchronization flag from "0" to "1" to update it. Processor cores 31 to 3n communicate with barrier synchronizer 10 at the time of completion of each barrier synchronization or at the time of simultaneous start of other parallel processing, and rewrite the corresponding synchronization flag from "1" to "0" to update it.

[0011] ROM 4 stores a program that is started by each of the processor cores 31 to 3n. The processor cores 31 to 3n each start the program stored in ROM 4 to perform parallel processing or interrupt handling. RAM 5 functions as a working memory used by the processor cores 31 to 3n to perform parallel processing or interrupt handling.

[0012] When a timer signal output condition is met, the timer 6 outputs a timer signal to the interrupt controller 8, for example, to allow a count value to reach a predetermined setpoint. The A / D converter 7 is supplied with sensor signals from various sensors provided externally to the electronic control unit 1, converts an input sensor signal from an analog signal to a digital signal, and outputs it to the interrupt controller 8.

[0013] The interrupt controller 8 maintains interrupt request destination information for determining one of the processor cores 31 to 3n that performs interrupt handling upon the occurrence of an interrupt. The interrupt controller 8 is supplied with an interrupt request destination designation signal from any one of the processor cores 31 to 3n, and then maintains the information (e.g., a processor core ID) for determining one of the processor cores 31 to 3n as the originator of the interrupt request destination designation signal. This information is maintained as the interrupt request destination information.The interrupt controller 8 determines that an interrupt occurs based on the input of a timer signal from the timer 6 or the input of a sensor signal from the A / D converter 7, and then issues an interrupt request to one of the processor cores 31 to 3n, which is determined by the interrupt request destination information maintained at that time. Each of the processor cores 31 to 3n performs interrupt processing when supplied with the interrupt request from the interrupt controller 8.

[0014] The following description explains the behavior of the above configuration with reference to the Fig. 2 to 5. In the following, it is assumed that processor cores 31 to 3n are all involved in the barrier synchronization. Processor cores 31 to 3n each complete the parallel processing, reach the barrier point, and then execute a Fig. 2. The following description uses the first processor core 31 as a representative of the processor cores 31 to 3n and explains the barrier synchronization process performed by the first processor core 31.

[0015] The first processor core 31 starts the barrier synchronization process, communicates with the barrier synchronizer 10, and rewrites its own synchronization flag from "0" to "1" to update it (S1). The first processor core 31 reads a synchronization flag different from its own stored in the barrier synchronizer 10 (S2) and checks the read synchronization flag, which is different from its own, to determine whether any of the processor cores 31 to 3n other than itself has already reached the barrier point (S3).

[0016] The first processor core 31 may determine that the processor cores 31 to 3n, except itself, include synchronization flags set to "0" and no processor core other than itself reaches the barrier point (S3: NO), and then determines that the first processor core 31 itself reaches the barrier point first. The first processor core 31 outputs an interrupt request destination designation signal to the interrupt controller 8 and designates itself as an interrupt request destination of the interrupt handling (S4).

[0017] The first processor core 31 may determine that any synchronization flag other than its own is set to "1" and any processor core other than itself reaches the barrier point (S3: YES), and then determines that the first processor core 31 itself reaches the barrier point second. The first processor core 31 does not output an interrupt request destination designation signal to the interrupt controller 8 and does not designate itself as an interrupt request destination of the interrupt handler.

[0018] The first processor core 31 determines whether all of the processor cores 31 to 3n have reached the barrier point (S5). The first processor core 31 may determine that none of the processor cores 31 to 3n have reached the barrier point yet and all of the processor cores 31 to 3n have not reached the barrier point (S5: NO), and then returns to S2. The first processor core 31 may determine that all of the processor cores 31 to 3n have reached the barrier point (S5: YES), and then terminates the barrier synchronization process and determines that the barrier synchronization is complete.

[0019] Thereafter, the first processor core 31 simultaneously starts parallel processing other than the previously performed parallel processing at the same start time as the other processor cores 32 to 3n. The processor cores, except the first processor core 31, perform the above-mentioned barrier synchronization process in a similar manner. One of the processor cores 31 to 3n that reaches the barrier point first is assumed to be an interrupt request target of the interrupt handler. The processor cores 31 to 3n may include a processor core that was previously designated as an initial interrupt request target and designates itself as an interrupt request target of the interrupt handler at the time of starting another parallel processing. This processor core retains the setting.Processor cores 31 to 3n may include a processor core that has been previously designated as an interrupt request target and does not designate itself as an interrupt request target of the interrupt handler at the time of starting another parallel processing. This processor core outputs an interrupt request target designation signal to the interrupt controller 8 and designates itself as an interrupt request target of the interrupt handler. As above, processor cores 31 to 3n configure the interrupt request target information in the interrupt controller 8 using software; however, the interrupt request target information in the interrupt controller 8 may also be configured using hardware.

[0020] The following description assumes n as “3” and shows a configuration in which the first processor core 31 up to and including the third processor core 33 participate in the barrier synchronization. Fig. 3 assumes the following: The first processor core 31 through the third processor core 33 in the microcontroller 2 simultaneously start parallel processing A (t1). After that, the second processor core 32 reaches the barrier point first to update the synchronization flag (t2). Then, the third processor core 33 reaches the barrier point to update the synchronization flag (t3). The first processor core 31 finally reaches the barrier point to update the synchronization flag (t4) and complete the barrier synchronization (t5). The first processor core 31 through the third processor core 33 then simultaneously start parallel processing B.

[0021] Suppose an interrupt request target of the interrupt handler is fixed at the first processor core 31. As shown in Fig. As shown in Figure 4, an interrupt occurs in the microcontroller 2 after the second processor core 32 reaches the barrier point. An interrupt request is given to the first processor core 31 even though the second processor core 32 reaches the barrier point. The first processor core 31, upon being provided with the interrupt request, interrupts the current parallel processing A and starts interrupt handling (t11). The first processor core 31 completes the interrupt handling and then restarts the interrupted parallel processing A (t12). The microcontroller 2 is subject to a delay in the timing for all of the first processor core 31 through the third processor core 33 to complete the parallel processing A, namely the timing to complete the barrier synchronization when the first processor core 31 interrupts the parallel processing A and performs the interrupt handling.

[0022] In contrast, it is assumed that one of the first to third processor cores 31-33 that reaches the barrier point first is adopted as the interrupt request target of the interrupt handler. In this case, the microcontroller 2 operates as follows. As shown in Fig. 5, the first processor core 31 is assumed to be an interrupt request target immediately after the first to third processor cores 31-33 start parallel processing A in the microcontroller 2 at the same time. However, the second processor core 32 is updated to be an interrupt request target of the interrupt handler when the second processor core 32 reaches the barrier point first.

[0023] Suppose an interrupt occurs in microcontroller 2 in this state, after the second processor core 32 has reached the barrier point. In this case, an interrupt request is sent to the second processor core 32, which has already reached the barrier point, not to the first processor core 31. The second processor core 32 interrupts a synchronization flag check process and starts interrupt handling (t21) when it receives the interrupt request. The second processor core completes the interrupt handling and then restarts the interrupted synchronization flag check process (t22). In microcontroller 2, the first processor core 31 does not perform interrupt handling, and the second processor core 32 performs interrupt handling. The first processor core 31 does not interrupt parallel processing A.There is no delay in timing for all the first to third processor cores 31-33 to complete the parallel processing A in time to complete the barrier synchronization.

[0024] As above, the first embodiment can provide the following effects.

[0025] One of the processor cores 31 to 3n in microcontroller 2 is designated as an interrupt request target of the interrupt handler upon entering the synchronization wait state. An interrupt request is sent to the processor core in the synchronization wait state, provided that the processor core is available when an interrupt occurs. The processor core in the synchronization wait state performs the interrupt handler to effectively utilize additional processing capacity and minimize the delay in completing barrier synchronization.

[0026] When barrier synchronization is completed, microcontroller 2 simultaneously starts a different parallel processing than the previously performed parallel processing. Any one of processor cores 31 to 3n predetermined as an initial interrupt request target is designated as an interrupt request target of the other interrupt processing. The processor core predetermined as the initial interrupt request target can be designated as an interrupt request target to start simultaneously with another parallel processing at the time after barrier synchronization is completed. (Second embodiment)

[0027] The following description explains the second embodiment of the present invention with reference to the Fig. 6 to 9. The same components as in the above-mentioned first embodiment are omitted from the description, and only the differences are explained. The first embodiment is configured under the condition that an interruption occurs during the execution of a single parallel processing. The second embodiment is configured under the condition that multiple interruptions occur during the execution of a single parallel processing.

[0028] A microcontroller 12 (corresponding to a processing unit) in an electronic control unit 11 includes a barrier synchronizer 13 instead of the barrier synchronizer 10 explained in the first embodiment. The barrier synchronizer 13 includes a plurality of synchronization flags corresponding to the processor cores 31 to 3n and a plurality of interrupt setup flags corresponding to the processor cores 31 to 3n. The processor cores 31 to 3n each start the barrier synchronization process, communicate with the barrier synchronizer 13, and reset the interrupt setup flags to "0" to initialize them. The processor cores 31 to 3n each output an interrupt request destination signal to the interrupt controller 8, communicate with the barrier synchronizer 13, and rewrite the interrupt setup flags from "0" to "1" to update them.

[0029] The following description explains the behavior of the above configuration with reference to the Fig. 6 to 9. The following description also uses the first processor core 31 as a representative of the processor cores 31 to 3n and explains the barrier synchronization process performed by the first processor core 31. The following description explains the occurrence of two interrupts (ie, a first interrupt and a second interrupt) during the execution of a single parallel processing.

[0030] The first processor core 31 starts the barrier synchronization process, communicates with the barrier synchronizer 13, rewrites its own synchronization flag from "0" to "1" to update it, and resets its interrupt setup flag to "0" to initialize it (S11). The first processor core 31 reads a synchronization flag different from its own stored in the barrier synchronizer 13 (S12) and reads its own interrupt setup flag stored in the barrier synchronizer 10 (S13). The first processor core 31 determines whether the read own interrupt setup flag is set to "0" to determine whether the first processor core 31 itself is designated as an interrupt request target of the interrupt handler (S14).

[0031] The first processor core 31 may determine that its interrupt setup flag is set to "0," namely, that the first processor core 31 itself is not designated as an interrupt request target of the interrupt handler (S14: YES), and then determines a synchronization flag other than its own. The first processor core 31 determines whether any other of the processor cores 31 to 3n has already reached the barrier point (S15).

[0032] The first processor core 31 may determine that all synchronization flags of the processor cores 31 to 3n, except its own, are set to "0" and no other processor core except itself reaches the barrier point (S15: NO), and then determine that the first processor core 31 itself reaches the barrier point first. The first processor core 31 outputs an interrupt request destination designation signal to the interrupt controller 8, designates itself as an interrupt request destination of the first interrupt action, and updates its interrupt setup flag from "0" to "1" (S16).

[0033] The first processor core 31 may determine that a synchronization flag of one of the processor cores 31 to 3n, except its own, is set to "1" and a processor core other than itself has already reached the barrier point (S15: YES), and then determines whether a processor core other than itself has reached the barrier point (S17). The first processor core 31 may determine that a processor core other than itself has reached the barrier point (S17: YES), and then determines that the first processor core 31 itself is the second to reach the barrier point. The first processor core 31 outputs an interrupt request destination designation signal to the interrupt controller 8, designates itself as an interrupt request destination of the second interrupt handler, and updates its interrupt setup flag from "0" to "1" (S18).

[0034] The first processor core 31 determines whether all of the processor cores 31 to 3n reach the barrier point (S19). The first processor core 31 may determine that any of the processor cores 31 to 3n have not yet reached the barrier point and that all of the processor cores 31 to 3n have not reached the barrier point (S19: NO), and then returns to S12. The first processor core 31 may determine that all of the processor cores 31 to 3n reach the barrier point (S19: YES), and then terminates the barrier synchronization process and determines that the barrier synchronization is complete.

[0035] Thereafter, the first processor core 31 simultaneously starts parallel processing, which is different from the previously performed parallel processing, at the same start time as the other processor cores 32 to 3n. Processor cores other than the first processor core 31 perform the above-mentioned barrier synchronization process in a similar manner. The processor core that reached the barrier point first among the processor cores 31 to 3n is designated as an interrupt request target of the first interrupt handling. The processor core that reached the barrier point second is designated as the interrupt request target of the second interrupt handling.Likewise, in this case, the processor cores 31 to 3n may include a processor core that was previously designated as an initial interrupt request target and that designates itself as the interrupt request target of the first or second interrupt handling at that time to start further parallel processing. This processor core retains the setting. The processor cores 31 to 3n may include a processor core that was previously designated as an initial interrupt request target and that does not designate itself as the interrupt request target of the first or second interrupt handling at that time to start further parallel processing. This processor core outputs an interrupt request target designation signal to the interrupt controller 8 and designates itself as the interrupt request target of the first or second interrupt handling.

[0036] The following description also assumes that n is "3" and shows a configuration in which the first processor core 31 up to and including the third processor core 33 participate in the barrier synchronization, perform the interrupt handling X as the first interrupt handling and perform the interrupt handling Y as the second interrupt handling. As shown in Fig. As shown in Figure 8, an interrupt request destination of the interrupt handler X or Y is fixed at the first processor core 31. An interrupt occurs in the microcontroller 2 after the second processor core 32 reaches the barrier point. An interrupt request is also given to the first processor core 31 when the second processor core 32 reaches the barrier point. When supplied with an interrupt request for the interrupt X, the first processor core 31 interrupts the current parallel processing A and starts the interrupt handler X (t31). The first processor core 31 completes the interrupt handler X and then resumes the interrupted parallel processing A (t32). When supplied with an interrupt request for the interrupt Y, the first processor core 31 interrupts the current parallel processing A and starts the interrupt handler Y (t33).The first processor core 31 completes interrupt processing Y and then resumes the interrupted parallel processing A (t34). The microcontroller 2 is subject to a delay in the timing for all the first through third processor cores 31-33 to complete parallel processing A, namely the timing for completing barrier synchronization when the first processor core 31 interrupts parallel processing A and executes interrupt processing X and Y.

[0037] In contrast, it is assumed that one of the first to third processor cores 31-33 that reaches the barrier point first is adopted as an interrupt request target of interrupt handling X, and a processor core that reaches the barrier point second is adopted as an interrupt request target of interrupt handling Y. In this case, the microcontroller 2 operates as follows. As shown in Fig. As shown in Figure 9, the first processor core 31 is assumed to be an interrupt request target of the interrupt handlers X and Y immediately after the first to third processor cores 31-33 simultaneously start parallel processing A in the microcontroller 2. However, the second processor core 32 is updated to be an interrupt request target of the interrupt handlers X when the second processor core 32 reaches the barrier point first. The third processor core 33 is updated to be an interrupt request target of the interrupt handlers Y when the third processor core 33 reaches the barrier point second.

[0038] Suppose interruption X occurs in microcontroller 2 after at least the second processor core 32 reaches the barrier point. In this case, an interrupt request for interruption X is sent to the second processor core 32, which has already reached the barrier point, not to the first processor core 31. Upon receiving the interrupt request for interruption X, the second processor core 32 interrupts the synchronization flag check process and starts interruption handling X (t41). When interrupt handling X is completed, the second processor core 32 resumes the interrupted synchronization flag check process (t42). Suppose interruption Y occurs in microcontroller 2 after at least the third processor core 33 reaches the barrier point.In this case, an interrupt request is given to the third processor core 32, which has already reached the barrier point, not to the first processor core 31. When it is provided with the interrupt request for interrupt Y, the third processor core 33 interrupts the synchronization flag check process and starts interrupt handling Y (t43). When interrupt handling Y is completed, the third processor core 33 resumes the interrupted synchronization flag check process (t44). In the microcontroller 2, the first processor core does not execute either of the interrupt handling X or Y, the second processor core 32 executes interrupt handling X, and the third processor core 33 executes interrupt handling Y. Therefore, the first processor core 31 does not interrupt the parallel processing A, similar to the first embodiment.There is no delay in the timing for the first to third processor cores 31-33 to complete the parallel processing A, namely the timing for completing the barrier synchronization.

[0039] The case where two interrupts occur during the execution of a single parallel processing operation has been described. However, the same applies to a case where three or more interrupts occur during the execution of a single parallel processing operation. Namely, the processor core determines whether the processor core itself is the mth (m is a natural number) to reach the barrier point. The processor core designates itself as an interrupt request target of the mth interrupt handler and can operate similarly to the above, even if three or more interrupts occur.

[0040] The second embodiment can provide the same effect as the above first embodiment. Suppose multiple interrupts occur during the execution of a single parallel processing operation. Even in such a case, a processor core in the synchronization wait state, if available, is provided with an interrupt request at the time the interrupt occurs and executes the interrupt handling. The processor core in the synchronization wait state can thereby effectively utilize additional processing capacity and minimize the delay in the completion of barrier synchronization. (Other embodiments)

[0041] The present invention is not limited to the embodiments described above. Various modifications and extensions can be made to the invention without departing from its spirit and scope.

[0042] The configuration in which the barrier synchronizer maintains the synchronization flag or the interrupt setup flag was shown. However, the barrier synchronizer does not necessarily have to maintain the synchronization flag or the interrupt setup flag. For example, the RAM can maintain the synchronization flag or the interrupt setup flag.

[0043] Fig. 5 shows that the first processor core 31 is designated as an initial interrupt request target. However, the initial interrupt request target is not limited to the first processor core 31. Fig.8 shows that the first processor core 31 is designated as an initial interrupt request target for interrupt handler X or Y. However, the initial interrupt request target for interrupt handler X or Y is not limited to the first processor core 31. An initial interrupt request target of interrupt handler X may differ from an initial interrupt request target of interrupt handler Y.

[0044] It should be noted that a flowchart or flowchart development of the present invention includes sections (also referred to as steps), each of which is represented, for example, as S1. Furthermore, each section may be divided into several subsections, and some sections may be combined into a single section. Furthermore, each of these configured sections may also be referred to as a device, a module, or a means.

Claims

[1] Processing unit (2, 12), comprising: multiple processor cores (31 to 3n), and an interrupt control (8), wherein: the plurality of processor cores (31 to 3n) perform parallel processing with barrier synchronization; the interrupt controller (8) maintains interrupt request destination information for determining one of the processor cores (31 to 3n) that performs interrupt handling due to an occurrence of an interrupt; the interrupt controller (8) is supplied with an interrupt request destination signal from one of the processor cores (31 to 3n) and then retains the interrupt request destination signal as interrupt request destination information; and the processor core that first reaches a barrier point to enter a synchronization wait state outputs an interrupt request destination designation signal to the interrupt controller (8) and designates itself as the interrupt request destination of the interrupt handler. [2] Processing unit (2, 12) according to claim 1, wherein: the processor core that first reached the barrier point outputs an interrupt request destination designation signal to the interrupt controller (8) and designates itself as the interrupt request destination of a first interrupt handling; and the processor core that secondly reached the barrier point outputs an interrupt request destination designation signal to the interrupt controller (8) and designates itself as the interrupt request destination of a second interrupt handling different from the first interrupt handling. [3] Processing unit (2, 12) according to one of claims 1 or 2, wherein: when the barrier synchronization is completed and all processor cores (31 to 3n) are ready to execute a next parallel processing, a predetermined one of the plurality of processor cores (31 to 3n) is determined as the interrupt request destination. [4] Electronic control unit (1, 11), comprising: the processing unit (2, 12) according to one of claims 1 to 3. [5] Processing method comprising the following steps: Executing parallel processing with barrier synchronization by multiple processor cores (31 to 3n); Maintaining interrupt request destination information for determining one of the processor cores (31 to 3n) that performs interrupt handling due to an occurrence of an interrupt by an interrupt controller (8); Supplying the interrupt controller (8) of one of the processor cores (31 to 3n) with an interrupt request destination designation signal and retaining the interrupt request destination designation signal as interrupt request destination information by the interrupt controller (8); and Outputting an interrupt request destination designation signal to the interrupt controller (8) and designating itself as the interrupt request destination of the interrupt handler by the processor core that first reached a barrier point. [6] Processing method according to claim 5, further comprising: Outputting an interrupt request destination designation signal to the interrupt controller (8) and designating itself as the interrupt request destination of a first interrupt handling by the processor core that first reached the barrier point; and Outputting an interrupt request destination designation signal to the interrupt controller (8) and designating itself as the interrupt request destination of a second interrupt handling different from the first interrupt handling by the processor core that secondly reached the barrier point. [7] Processing method according to one of claims 5 or 6, further comprising: Determining a predetermined one of the plurality of processor cores (31 to 31n) as the interrupt request destination when the barrier synchronization is completed and all of the plurality of processor cores (31 to 3n) are ready to execute the next parallel processing.

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