Method, device, system for early granular side indications using a PCIE device

Abstract

Method for performing a data prefetch from a cache memory, wherein the method is performed by a root complex compliant with a Peripheral Component Interconnect Express (PCIe) protocol, and wherein the method comprises: Receiving a data packet (502) from a device connected to the root complex via a PCIe-compliant connection; Identify a memory transaction hint bit (506) based on the received data packet; Determining a memory transaction using the memory transaction indicator bit; and Performing an optimization process based at least in part on the specified memory transaction (508), wherein performing the optimization process (508) includes performing a caching behavior optimization process and wherein the caching behavior optimization process includes performing an advance retrieval of ownership in response to the memory transaction hint indicating a streaming write operation.

Description

AREA OF INVENTION

[0001] The invention relates to a method, device, and system for early granular page references using a PCIe device. In particular, the invention relates to a method, performed by a root complex compliant with a Peripheral Component Interconnect Express (PCIe) protocol, for performing a data pre-fetch at a cache memory and a corresponding computer program product. BACKGROUND

[0002] Modern server and client processing units can support a large number of core and input / output (I / O) agents. Each core and I / O agent can compete for low latency and high bandwidth access to shared resources to achieve better performance. Such shared resources can include cache memory and storage.

[0003] US 2013 / 0346655 A1 concerns computer bus agents for generating and executing atomic operations. An exemplary bus protocol-compliant requester comprises: a bus protocol port for transmitting bus protocol-compliant requests to a bus protocol link; and an extended atomic operation generation system coupled to the bus protocol port to generate an extended atomic operation by using at least one bit in a field of a standard bus protocol request that is not an opcode field, and to deliver the extended atomic operation to the bus protocol port for transmission to a bus protocol link-coupled completer.

[0004] WO 2010 / 138230 A2 relates to a method and device for enabling ID-based streams over PCIe. An exemplary device includes memory ordering logic for ordering packets to be transmitted over a serial point-to-point link, wherein the memory ordering logic bridges a blocked first packet with a second packet that arrived after the first packet if the second packet contains an attribute flag that is set to indicate that the second packet is order-independent, and if the second packet contains an ID that is different from an ID assigned to the first packet. SUMMARY OF THE INVENTION

[0005] It can therefore be considered an object of the present invention to propose a method and a computer program product which supports early granular page references.

[0006] The foregoing problem is solved according to the invention by a method according to main claim 1 and a computer program product according to dependent claim 13. The dependent claims define further developments of the method and the computer program product according to the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates an embodiment of a block diagram for a computer system that has a multicore processor. Fig. Figure 2 is a schematic diagram of a system architecture 200 according to embodiments of the present disclosure. Fig. Figure 3 is a schematic diagram of a data packet configured with indicator bits, according to embodiments of the present disclosure. Fig. Figure 4 is a process flow diagram for a device for configuring a data packet with indicator bits according to embodiments of the present disclosure. Fig. Figure 5 is a process flow diagram for a root complex for processing a received data packet according to embodiments of the present disclosure. Fig. Figure 6 illustrates an embodiment of a computer system that has a wiring architecture. Fig. Figure 7 illustrates an embodiment of a interconnection architecture that features a layered stack. Fig. Figure 8 illustrates an embodiment of a request or packet that is to be generated or received within a interconnection architecture. Fig. Figure 9 illustrates an embodiment of a transmitter-receiver pair for a circuit architecture. Fig. Figure 10 illustrates an embodiment of a multicore processor. Fig. Figure 11 illustrates another embodiment of a block diagram for a computer system. Fig.Figure 12 illustrates an embodiment of a block for a computer system that includes multiple processor sockets.

[0007] The figures may not be to scale. Identical reference symbols denote the same elements in all the different figures. DETAILED DESCRIPTION

[0008] The following description presents numerous specific details, such as examples of specific processor types and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / altitudes, specific processor pipeline stages and operation, etc., to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to carry out the present invention.In other cases, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits / code for described algorithms, specific firmware code, specific interconnection operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific shutdown and gate techniques / logic, and other specific operational details of computer systems, were not described in detail in order to avoid unnecessary obfuscation of the present invention.

[0009] Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as computer platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings from embodiments described herein can be applied to other types of circuits or semiconductor devices that can also benefit from improved energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™ and can also be used in other devices, such as handheld devices, tablets, other thin notebooks, system-on-a-chip (SoC) devices, and other embedded applications.Some examples of handheld devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system-on-a-chip, a network computer (NetPC), set-top boxes, network hubs, wide-area network (WAN) switches, or any other system capable of performing the functions and operations described below. Furthermore, the devices, methods, and systems described here are not limited to physical computing equipment but may also include software optimizations for energy conservation and efficiency.

[0010] With reference to Fig.Figure 1 shows an embodiment of a block diagram for a computer system comprising a multicore processor. A processor 100 comprises any processor or processing components, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system-on-a-chip (SoC), or other components for executing code. In one embodiment, the processor 100 comprises at least two cores, namely cores 101 and 102, which may be asymmetric cores or symmetric cores (the illustrated embodiment). However, the processor 100 may include any number of processing elements, which may be symmetric or asymmetric.

[0011] In one embodiment, a processing element refers to hardware or logic for supporting a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a processing unit, a context, a context unit, a logic processor, a hardware thread, a core, and / or any other element capable of maintaining a state for a processor, such as an execution state or an architectural state. In other words, in one embodiment, a processing element refers to any hardware capable of being independently associated with code, such as a software thread, an operating system, an application, or other code.A physical processor (or processor socket) usually refers to an integrated circuit that may include any number of other processing elements, such as cores or hardware threads.

[0012] A kernel often refers to logic placed on an integrated circuit and capable of maintaining independent architectural states, where each independently maintained architectural state is associated with at least some execution resources. In contrast, a hardware thread typically refers to any logic placed on an integrated circuit and capable of maintaining independent architectural states, where the independently maintained architectural states share access to execution resources. As can be seen, the boundary between the nomenclature of a hardware thread and a kernel overlaps when certain resources are shared and others are associated with an architectural state.Nevertheless, an operating system often treats a core and a hardware thread as individual logic processors, with the operating system being able to schedule operations on each logic processor individually.

[0013] The physical processor 100, as in Fig.Figure 1 illustrates two cores—cores 101 and 102. Here, cores 101 and 102 are considered symmetric cores, meaning cores with the same configurations, functional units, and / or logic. In another embodiment, core 101 contains an out-of-order processor core, while core 102 contains an in-order processor core. However, cores 101 and 102 can be individually selected from any core type, such as a native core, a software-managed core, a core adapted to run a native instruction set architecture (ISA), a core adapted to run a translated instruction set architecture (ISA), a co-developed core, or any other known core.In a heterogeneous kernel environment (that is, asymmetric kernels), a form of translation, such as binary translation, can be used to schedule or execute code on one or both kernels. To further stimulate discussion, the functional units illustrated in kernel 101 are described in detail below, since the units in kernel 102 operate similarly in the depicted embodiment.

[0014] As shown, the core 101 has two hardware threads, 101a and 101b, which can also be called hardware thread slots 101a and 101b. Software entities, such as an operating system, therefore potentially see the processor 100 in one embodiment as four separate processors, that is, four logical processors or processing units capable of executing four software threads simultaneously. As mentioned above, a first thread is assigned to architecture state registers 101a, a second thread is assigned to architecture state registers 101b, a third thread can be assigned to architecture state registers 102a, and a fourth thread can be assigned to architecture state registers 102b. Here, each of the architecture state registers (101a, 101b, 102a, and 102b) can be called processing units, thread slots, or thread units, as described above.As illustrated, the architecture state registers 101a are replicated in architecture state registers 101b such that individual architecture states / contexts can be stored for logical processor 101a and logical processor 101b. Within core 101, other smaller resources, such as instruction pointers and rename logic in an assigner and rename block 130, can also be replicated for threads 101a and 101b. Some resources, such as reorder buffers in reorder / reset unit 135, ILTB 120, load / store buffers, and queues, can be shared by partitioning. Other resources, such as internal general-purpose registers, page table base registers, data cache and low-level data TLB 115, execution unit(s) 140, and parts of the out-of-order unit 135, are potentially shared entirely.

[0015] The processor 100 often includes other resources that can be fully shared, divided by partitioning, or assigned to / from processing element(s). In Fig. Figure 1 illustrates an embodiment of a purely exemplary processor with illustrative logical units / resources of a processor. It should be noted that a processor may include or omit any of these functional units, as well as other known functional units, logic, or firmware not shown. As illustrated, core 101 includes a simplified, representative out-of-order (OOO) processor core. However, an in-order processor can be used in various embodiments. The OOO core includes a branch target buffer 120 to predict branches to be executed / taken and an instruction translation buffer (I-TLB) 120 to store address translation entries for instructions.

[0016] The core 101 also includes the decode module 125, which is coupled to the fetch unit 120 to decode fetched elements. In one embodiment, the fetch logic has individual sequencers, each associated with thread slots 101a and 101b. Typically, the core 101 is associated with a first ISA that defines / specifies instructions executable on the processor 100. Often, machine code instructions belonging to the first ISA have a section of the instruction (called an opcode) that references / specifies an instruction or operation to be executed. The decode logic 125 has circuits that recognize these instructions from their opcodes and pass the decoded instructions into the pipeline for processing as defined by the first ISA.As discussed in more detail below, Decoder 125, in one embodiment, incorporates logic designed or adapted to recognize specific instructions, such as a transaction instruction. As a result of recognition by the Decoder 125, the Architecture or Core 101 executes specific, predefined actions to perform tasks associated with the corresponding instruction. It is important to note that any of the tasks, blocks, operations, and procedures described herein can be executed in response to one or more instructions; some of these may be new or existing instructions. Note that in one embodiment, Decoder 126 recognizes the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, the Decoder 126 recognizes a second ISA (either a subset of the first ISA or a different ISA).

[0017] In one example, the allocation and rename block 130 contains an allocation to reserve resources, such as register files for storing instruction processing results. However, threads 101a and 101b can potentially execute out of order, with allocation and rename block 130 also reserving other resources, such as reorder buffers, to track instruction results. Unit 130 may also include a register renamer to rename program / instruction reference registers to other registers internally to processor 100. The reorder / retirement unit 135 includes components such as the reorder buffers mentioned above, load buffers, and memory buffers to support out-of-order execution and subsequent in-order retirement of instructions that were executed out of order.

[0018] In one embodiment, a scheduler and execution unit block 140 includes a scheduler unit for scheduling instructions / operations to execution units. For example, a floating-point instruction is scheduled on a port of an execution unit that has an available floating-point execution unit. Register files associated with the execution units are also included for storing information instruction processing results. Example execution units include a floating-point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a memory execution unit, and other known execution units.

[0019] The lower-level data cache and data translation buffer (D-TLB) 150 are coupled to the execution unit(s) 140. The data cache is intended to store recently used / operated elements, such as data operands, which are potentially held in memory coherence states. The D-TLB is intended to store recent virtual / linear to physical address translations. As a specific example, a processor might include a page table structure to partition physical memory into multiple virtual pages.

[0020] Here, cores 101 and 102 share access to a higher-level or further-out cache, such as a second-level cache associated with on-chip interface 110. It's important to note that higher-level or further-out refers to cache levels that increase in or are further away from the execution unit(s). In one embodiment, the higher-level cache is a last-level data cache—the last cache in the memory hierarchy on processor 100—such as a second- or third-level data cache. However, the higher-level cache is not so limited, as it can be associated with or include an instruction cache. A trace cache—a type of instruction cache—can instead be coupled after decoder 125 to store recently decoded traces.Here, an instruction potentially refers to a macro instruction (that is, a general instruction recognized by the decoders) which can be decoded into a number of micro instructions (micro-operations).

[0021] In the configuration shown, the processor 100 also includes the on-chip interface module 110. Historically, a memory controller, described in more detail below, was integrated into a computer system outside of the processor 100. In this scenario, the on-chip interface 11 communicates with devices outside of the processor 100, such as system memory 175, a chipset (often including a memory controller hub for connecting to the memory 175 and an I / O controller hub for connecting peripherals), a memory controller hub, a northbridge, or another integrated circuit. And in this scenario, the bus 105 can have a known interconnection, such as a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache-coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

[0022] The memory 175 can be intended for the processor 100 alone or used in conjunction with other components in a system. Conventional examples of these types of memory 175 include DRAM, SRAM, non-volatile memory (NV memory), and other known memory devices. The component 180 can include a graphics accelerator, a processor or card coupled with a memory controller hub, data storage coupled with an I / O controller hub, a wireless transmitter / receiver, a flash component, an audio controller, a network controller, or another known component.

[0023] Since more logic and components are integrated onto a single die, such as a SoC, each of these components can be integrated onto a processor 100. In one embodiment, for example, a memory controller hub is located on the same package and / or die as the processor 100. Here, a section of the core (an "on-core" section) 110 has one or more controllers for interfaces with other components, such as the memory 175 or a graphics component 180. The configuration that has interconnects and controllers for interfaces with such components is often called an "on-core" (or an on-core configuration). As an example, an on-chip interface 110 has a ring interconnect for on-chip communication and a high-speed serial point-to-point link 105 for off-chip communication.In the SOC environment, even more components, such as a network interface, co-processors, memory 175, graphics processor 180 and any other known computer components / interfaces, can be integrated on a single die or a single integrated circuit to provide a small form factor with high functionality and low power consumption.

[0024] In one embodiment, the processor 100 is capable of executing compiler, optimizer, and / or translator code 177 to compile, translate, and / or optimize application code 176 to support or interface with the device and procedures described herein. A compiler often includes a program or set of programs for translating source text / code into target text / code. Typically, program / application code is compiled in multiple stages and passes to convert high-level programming language code into low-level machine or assembly language code. However, single-pass compilers can still be used for simple compilation.A compiler can use any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

[0025] Larger compilers often have multiple phases, but these phases are usually contained within two main phases: (1) a frontend, which generally involves syntactic processing, semantic processing, and some transformation / optimization, and (2) a backend, which generally involves analysis, transformations, optimizations, and code generation. Some compilers refer to a middle ground, illustrating the blurring of clear distinctions between a compiler's frontend and backend. As a result, references to insertion, association, generation, or any other compiler operation can occur in any of the phases or passes mentioned above, as well as in any other known phases or passes of a compiler. As an illustrative example, a compiler might potentially insert operations, call, function, etc.Dynamic compilation involves one or more compilation phases, such as inserting calls / operations in a front-end compilation phase and then converting those calls / operations into low-level code during a transformation phase. It's worth noting that during dynamic compilation, compiler code or dynamic optimization code can insert such operations / calls and optimize the code for execution at runtime. As a specific illustrative example, binary code (already compiled code) can be dynamically optimized at runtime. Here, the program code can include the dynamic optimization code, the binary code, or a combination of these.

[0026] Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and / or translate code. References to code execution, application code, program code, or other software environments can therefore refer to: (1) executing one or more compiler programs, optimization code optimizers, or translators, dynamically or statically, to compile program code, maintain software structures, perform other operations, optimize code, or translate code; (2) executing main program code that includes operations / calls, such as application code that has been optimized / compiled; (3) executing other program code, such as libraries, associated with the main program code to maintain software structures, execute other software related to operations, or optimize code; or (4) a combination of these.

[0027] Shared processor core architectures attempt to balance traffic from I / O agents and rely on various techniques to optimize these competing accesses. To improve core performance, the architecture employs several methods, including cache prefetching, differentiated caching policies, and memory bandwidth optimizations, each of which can be based on predicting future core accesses based on current traffic patterns.

[0028] Hardware prefetch engines can help identify patterns and prefetch them in a dedicated or shared cache (mid-level cache, L2 cache, or last-level cache (LLC) prefetch). A hint or indication from the kernel itself regarding the traffic type can be used to help balance competition for shared resources. Examples of such kernel hints include dead block predictors, non-temporary hints, and so on.

[0029] Characterizing I / O traffic into predictable patterns can be difficult because I / O traffic tends to exhibit large variance depending on the type of device, application, and platform. I / O traffic also tends to lack non-uniform memory access (NUMA) affinity due to I / O and platform connectivity limitations. Thus, a hardware prefetch engine can suffer from inefficiency for I / O traffic. Unlike the kernel, I / O devices also lack a standard mechanism for sending hints to the structure for optimization for different traffic types. As a result, traditional methods for optimizing cache and memory bandwidth latency for kernels have not been widely applicable to I / O.

[0030] This disclosure describes systems, methods, and devices for enabling I / O devices to send an advance message regarding the nature of the traffic that will be received from the device to the root complex. The root complex can then use this information to make various decisions and optimize the traffic it expects to receive. A PCIe-connected device can provide the processor core with a "hint" regarding the nature of the traffic that will be received from the device. The processor core can use the hint to optimize the device's transaction with the shared resource.

[0031] Fig.Figure 2 is a schematic diagram of a system architecture 200 according to embodiments of the present disclosure. The system architecture 200 can include a host system 201 and several devices 220a-c connected to the host system 201 by a PCIe-compliant switching structure 230. The system architecture 200 can have one or more processors 202. The processors 202 can be coupled to the root complex by a connection, such as a front-end bus. The processors 202 can include the cache memory 204. The cache memory 204 can temporarily store data from the storage 206.

[0032] The host system 201 can also include a root complex 210. The root complex 210 can act as a controller hub for PCIe-compliant systems and devices. The root complex 210 connects the processor 202 and the storage 206 to the PCIe-compliant switching structure 230, which is composed of one or more switching devices. The root complex 210 also connects the devices 220a-c to the host system 201 through the switching structure 230.

[0033] In embodiments, the devices 220a-c can compete for processing and memory resources hosted by the host system 201. The devices 220a-c can leverage the existing PCIe packet architecture to transmit hints or advance information to the root complex 210, enabling the root complex to perform certain optimization processes before receiving further data packets from the devices 220a-c. The devices 220a-c can access the host system 201 for memory reads, writes, streaming writes, cacheable operations, atomic operations, partial operations, Data Direct I / O, and so on. Other use cases include caching policy determination (including cache prefetching), page initialization, security policy setting, and other processes. The PCIe-compliant packet architecture is described in Fig. 3 shown in more detail.

[0034] Fig.Figure 3 is an exemplary PCIe-compliant data packet 300 according to embodiments of the present disclosure. By using the data packet 300 to transmit a hint, the device discloses to the root complex the pages it intends to access in advance.

[0035] The exemplary package 300, which is in Fig.Figure 3 shows an Address Translation Service (ATS) packet. ATS packets allow a device to send a virtual address (VA) / guest physical address (GPA) to the physical host address (HPA) translation request to the root complex at a page granularity prior to the actual memory access request (e.g., DMA request). The ATS packet is particularly useful for providing hints regarding future memory accesses by the device, as the ATS packet is transmitted before data read / write operations. Other types of data packets can be transmitted to achieve similar results. For example, a zero-length write operation can be used to process hint bits by utilizing unused or reserved bits in the zero-length write operation data packet.

[0036] Data packet 300 can contain reserved bits at various duplicate words within the packet. These reserved bits can be used to provide clues about the memory accesses the device is attempting to perform. Table 1 provides an example of how reserved and unused bits can be used to provide clues to the root complex. Table 1. Example allocation of reserved bits for hints ATS Zero-lengths- Opcode Memory read operation Memory write AT  01 00 or 10 transaction DW0.byte1[0] (currently reserved)  0 BE 0xFF  0x00 length 0X2 (Multiple)  0x1 8-bit vector DW3.byte2[3:0],DW3.byte3[7:4] (currently reserved) Addr[11:4] Note (2 bits) DW3.byte3[2:1] (currently reserved) Addr[2:1] 1 bit for future expansion DW3.byte3[3] (currently reserved) Addr[3]

[0037] When linking Table 1 with Fig. The transaction hint (TH) bit 304, DW 0, byte 1, bit 0 of data packet 300, is assigned to DW 0. TH bit 304 can be used to indicate to the root complex that the data packet carries a hint regarding an upcoming memory access. Hint bits 302 can be assigned to DW 3, byte 3, bits [2:1]. For ATS packets, hint bits 302 occupy bits that were previously reserved.

[0038] Similarly, for a zero-length write operation as defined in Table 1, the lower address bits, which are unused, are used to provide the same information as a translation request.

[0039] Hint bits 302 are used to communicate the intended use from the device's perspective. Hint bits 302 are optional and are enabled when the device sets the transaction hint (TH) bit 304. Other reserved bits (such as reserved bit 306) can be used to provide subpage granularity. (Note that even when hints are enabled, they can be ignored by the root complex.)

[0040] Fig.Figure 4 is a process flow diagram 400 for a device for configuring a data packet with hint bits according to embodiments of the present disclosure. The device can determine an impending memory transaction (402). The memory transaction can be a memory read or write operation or another type of memory transaction. The determination of the impending memory transaction can be made with respect to a specific page in the memory to which the device is attempting to access. The impending memory transaction can involve a memory transaction that will occur for the data stream that the device is processing. The device can program a data packet to be sent to a root complex of a host system with a transaction hint (TH) bit (404). The TH bit can occupy a reserved bit of the data packet or the first part of a reserved bit field of the data packet.For example, in an ATS packet, the TH bit DW0.byte 1.bit 0 can be occupied, where DW0.byte 1.bits [1:0] are reserved bits. The device can program the data packet with processing hint bits (and in some embodiments can specify sub-level granularity bits) that indicate the nature of the upcoming memory transaction (406). The processing hint bits can occupy one or more reserved bits of the data packet.

[0041] For example, the processing hint bits can contain 2 bits and DW3.byte can occupy 3 bits [2:1]. The encodings for the hint bits can be as follows: 00 streaming write operations 01 Read operations 10 Atomic / Partial / DDIO 11 Cacheable operations (for coherent devices)

[0042] Other reserved bits can also be used to provide subpage granularity. For example, eight bits (DW3, byte 3, bits [7:3] and DW3, byte 2, bits [2:0]) are used to provide subpage granularity. Thus, for a 4KB page, these 8 bits provide a one-hot vector, which then provides 512B granularity for the hints. The processing hint bits can indicate a page granularity of the memory address space that will be accessed. Within a large page, the processing hints can belong to a subset of a page within the memory address space that will be accessed.

[0043] The device can then transfer the packet to the root complex (408).

[0044] Fig.Figure 5 is a process flow diagram 500 for a root complex for processing a received data packet according to embodiments of the present disclosure. The root complex can receive a data packet from a device via a PCIe-compliant connection (502). The root complex can determine that a transaction hint bit is set in a first part of a reserved bit field of the received data packet (504). For example, the root complex can mark a TH bit that is set in a reserved bit field. The presence of a marked bit in a specified bit or bit field can cause the root complex to examine other predetermined reserved parts of the received data packet. For example, the presence of a marked bit at a predefined bit location can cause the root complex to mark a hint bit that is set at another predefined bit location of the data packet (506).The root complex can use the indicator bits to signal an optimization process to be performed in preparation for an upcoming memory transaction for the device (508).

[0045] If the root complex provides advance information about how a device intends to use a given address range or page in memory, it can perform various optimizations in a CPU-specific way. Some examples of these optimizations are given below, but this is not an exhaustive list. Caching behavior

[0046] Several caching optimizations may be available that the root complex can choose to activate, depending on the type of device and the type of cue received in the data packet. For example, the root complex may choose to pre-claim ownership in response to receiving a cue for "streaming writes." In some embodiments, the root complex may pre-claim and cache data in response to a cue for "reads." In other embodiments, the root complex may pre-claim ownership and data for "atomic / partial" or "cacheable operations."

[0047] In addition to prefetching, the root complex can choose to make optimizations regarding cache allocation and replacement policies, depending on the type of device. For example, the root complex can choose not to enable DDIO for streaming writes (which can cause cache flutter), or it can choose a differentiated replacement policy in other cases (using a lower / higher LRU value). Metadata update & page initialization

[0048] Depending on the information received in the data packet, the root complex can choose to initialize a given page with specific characteristics. This initialization can include updating metadata stored with the page in memory. This metadata update can provide additional capabilities, such as setting up security zones for the device.

[0049] The root complex can then receive a data packet for the memory transaction (510) and process the memory transaction using the optimization processes performed on the advice given (512).

[0050] A key interconnect architecture is the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to enable components and devices from various manufacturers to interact within an open architecture spanning multiple market segments: clients (desktops and mobile), servers (standard and enterprise), and embedded and communications devices. PCIe is a universal, high-performance I / O interconnect protocol defined for a wide range of future computing and communications platforms. While some PCI attributes, such as the usage model, load memory architecture, and software interfaces, have been retained through revisions, earlier parallel bus implementations have been replaced by a highly scalable, fully serial interface.Newer versions of PCI Express leverage advancements in point-to-point interconnects, switch-based technology, and the packaged protocol to deliver new levels of performance and features. Power management, Quality of Service (QoS), hot-plug / hot-swap support, data integrity, and error handling are among the advanced features supported by PCI Express.

[0051] With reference to Fig.Figure 6 illustrates an embodiment of a structure consisting of point-to-point connections that interconnect a set of components. A system 600 includes a processor 605 and a system memory 610 coupled to a controller hub 615. The processor 605 includes any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or another processor. The processor 605 is coupled to the controller hub 615 by a front-side bus (FSB) 606. In one embodiment, the FSB 606 is a serial point-to-point interconnect, as described below. In another embodiment, the connection 606 has a serial differential interconnect architecture that conforms to different interconnect standards.

[0052] System Memory 610 includes any storage device, such as random-access memory (RAM), non-volatile memory (NV memory), or other memory that devices in System 600 can access. System Memory 610 is coupled to a controller hub 615 via Memory Interface 616. Examples of memory interfaces include a double-data-rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

[0053] In one embodiment, the Controller Hub 615 is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe) interconnect hierarchy. Examples of the Controller Hub 615 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH), a southbridge, and a root controller / hub. Often, the term chipset refers to two physically separate controller hubs, namely a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). It should be noted that current systems often have the MCH integrated into the 605 processor, while the Controller 615 is intended to communicate with I / O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing is optionally supported by the Root Complex 615.

[0054] The Root Complex 615 can receive a data packet from an attached device, such as an I / O device 625. The data packet may contain a hint bit group, which instructs the Root Complex to evaluate one or more reserved bits to determine whether a hint bit is present in the data packet. The hint bit can provide the Root Complex with a hint or preliminary information about how the I / O device 625 intends to use a designated address range or page in memory. The Root Complex 615 can perform various optimizations on behalf of a processor core, as described previously.

[0055] Here, the controller hub 615 is coupled to a switch / bridge 620 via serial connection 619. Input / output modules 617 and 621, which can also be called interfaces / ports 617 and 621, comprise / implement a layered protocol stack to provide communication between the controller hub 615 and the switch 620. In one embodiment, multiple devices can be coupled to the switch 620.

[0056] The switch / bridge 620 routes packets / messages from device 625 upstream, that is, upwards in the hierarchy towards a root complex (e.g., controller hub 615), and downstream, that is, downwards in the hierarchy away from a root controller, from the processor 605 or the system memory 610 to device 625. In one embodiment, the switch 620 is called a logical arrangement of several virtual PCI-to-PCI bridge devices.Device 625 includes any internal or external device or component intended to connect to an electronic system, such as an I / O device, network interface controller (NIC), expansion card, audio processor, network processor, hard disk, storage device, CD / DVD-ROM drive, monitor, printer, mouse, keyboard, router, portable storage device, FireWire device, Universal Serial Bus (USB) device, scanner, and other input / output devices. Often, in PCIe terminology, such as device, it is referred to as an endpoint. Although not specifically shown, Device 625 may include a PCIe-to-PCI / PCI-X bridge to support established PCI devices or PCI devices of other configurations. Endpoint devices in PCIe are commonly classified as established PCIe or Root Complex Integrated Endpoints.The device 625 can be coupled to the switch 620 via a serial connection 623.

[0057] A graphics accelerator 630 is also coupled to the controller hub 615 via serial connection 632. In one embodiment, the graphics accelerator 630 is coupled to an MCH, which is coupled to an ICH. The switch 620, and consequently the I / O device 625, is then coupled to the ICH. I / O modules 631 and 618 are also intended to implement a layered protocol stack for communication between the graphics accelerator 630 and the controller hub 615. Similar to the MCH discussion above, a graphics controller or the graphics accelerator 630 itself can be integrated into the processor 605.

[0058] With reference to Fig.Figure 7 illustrates an embodiment of a layered protocol stack. A layered protocol stack 700 contains any form of layered communications stack, such as a Quick-Path Interconnect (QPI) stack, a PCIe stack, a next-generation high-performance computer interconnect stack, or any other layered stack. Although the discussion immediately below refers to Fig. Since 6-12 relates to a PCIe stack, the same concepts can be applied to other interconnection stacks. In one embodiment, the protocol stack 700 is a PCIe protocol stack comprising a transaction layer 705, a link layer 710, and a physical layer 720. An interface, such as interfaces 617, 618, 621, 622, 626, and 631 in Fig.6, can be represented as a communication protocol stack 700. The representation as a communication protocol stack can also be described as a module or interface that implements / contains a protocol stack.

[0059] PCI Express uses packets to communicate information between components. Packets are formed at the transaction layer (705) and the data link layer (710) to carry information from the transmitting component to the receiving component. As the transmitted packets pass through the other layers, they are augmented with additional information necessary for handling packets at those layers. On the receiving side, the reverse process occurs, and packets are transformed from their physical layer (720) representation to the data link layer (710) representation and finally (for transaction layer packets) to a form that can be processed by the receiving device's transaction layer (705). Transaction layer

[0060] In one embodiment, the transaction layer 705 provides an interface between a component's processing core and the interconnect architecture, such as the data link layer 710 and the physical layer 720. In this respect, a primary responsibility of the transaction layer 705 is the assembly and disassembly of packages (i.e., transaction layer packages or TLPs). The transaction layer 705 typically manages credit-based flow control for TLPs. A PCIe implements split transactions, meaning transactions with a request and response separated by time, allowing one link to carry other traffic while the target component gathers data for the response.

[0061] Furthermore, PCIe employs credit-based guidance control. In this system, a component announces an initial credit amount for each of the receive buffers in transaction layer 705. An external component at the opposite end of the link, such as the controller hub 115 in Fig. 1. This counts the number of credits consumed by each TLP. A transaction can be transferred if it does not exceed a credit limit. Upon receiving a response, a credit amount is restored. One advantage of the credit system is that the latency of credit return does not affect performance, provided the credit limit is not reached.

[0062] In one embodiment, four transaction address spaces comprise a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions involve one or more read and write requests to transfer data to / from a memory-mapped location. In one embodiment, the memory space transactions are capable of using two different address formats, for example, a short address format such as a 32-bit address, or a long address format such as a 64-bit address. Configuration space transactions are used to access the configuration space of PCIe devices. Transactions to the configuration space involve read and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

[0063] Therefore, in one implementation, transaction layer 705 specifies packet header / payload 706. The format for current packet headers / payloads can be found in the PCIe specification on the PCIe specification website.

[0064] With quick reference to Fig. Figure 8 illustrates an embodiment of a PCIe transaction descriptor. In one embodiment, the transaction descriptor 800 is a mechanism for carrying transaction information. In this respect, the transaction descriptor 800 supports the identification of transactions in a system. Other potential uses include monitoring changes to default transaction orders and associations of transactions with channels.

[0065] The transaction descriptor 800 has a global identifier field 802, an attribute field 1004, and a channel identifier field 806. In the illustrated example, a global identifier field 802 is shown, which includes a local transaction identifier field 808 and a source identifier field 810. In one embodiment, the global transaction identifier 802 is the same for all pending requests.

[0066] According to one implementation, the local transaction identifier field 808 is a field generated by a requesting agent and represents all pending requests that require completion for that requesting agent. Furthermore, in this example, the source identifier 810 uniquely identifies the requesting agent within a PCIe hierarchy. Together with the source ID 810, the local transaction identifier field 808 thus provides global identification of a transaction within a hierarchy domain.

[0067] Attribute field 804 specifies characteristics and relationships of the transaction. In this respect, attribute field 804 is potentially used to provide additional information that allows for modification of the standard transaction processing. In one implementation, attribute field 804 includes a priority field 812, a reserved field 814, an ordering field 816, and a no-snoop field 818. Here, the priority subfield 812 can be modified by an initiator to assign a priority to the transaction. A reserved attribute field 814 is reserved for future use or for vendor-defined use. Possible usage models that utilize priority or security attributes can be implemented using the reserved attribute field.

[0068] In this example, the ordering attribute field 816 is used to provide optional information that conveys the ordering type, which can modify default ordering rules. According to one example implementation, an ordering attribute of "0" means that default ordering rules are applied, while an ordering attribute of "1" denotes looser ordering, where writes can propagate writes in the same direction and read completions can propagate writes in the same direction. The snooping attribute field 818 is used to determine whether transactions are snooped. As shown, the channel ID field 806 identifies a channel to which a transaction is associated. transmission layer

[0069] With reference to Fig.In section 7, the data link layer 710, also called the data link layer 710, acts as an intermediate layer between the transaction layer 705 and the physical layer 720. In one embodiment, one responsibility of the data link layer 710 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components of a link. One side of the data link layer 710 accepts TLPs assembled by the transaction layer 705, applies the single packet sequence identifier 710 (i.e., an identification number or packet number), calculates and applies an error detection code (CRC 712), and submits the modified TLPs to the physical layer 720 for transmission across a physical component to an external component. Physical layer (bit transmission layer)

[0070] In one embodiment, the physical layer 720 comprises a logical subblock 721 and an electrical subblock 722 for physically transferring a packet to an external component. Here, the logical subblock 721 is responsible for the "digital" functions of the physical layer 721. In this respect, a logical subblock comprises a transmit section to prepare outgoing information for transmission through the physical subblock 722, and a receive section to identify and prepare received information before passing it on to the transmission layer 1110.

[0071] The physical block 722 comprises a transmitter and a receiver. The transmitter is supplied with symbols by the logical subblock 721, which the transmitter serializes and transmits to an external component. The receiver is supplied with serialized symbols from an external component and converts the received signals into a bitstream. The bitstream is deserialized and supplied to the logical subblock 721. In one embodiment, an 8b / 10b transmission code is used, in which ten-bit symbols are transmitted / received. Here, special symbols are used for framing a packet with frames 723. Additionally, in one example, the receiver also provides a symbol clock that is recovered from the incoming serial stream.

[0072] As stated above, although transaction layer 705, link layer 710, and physical layer 1020 are discussed in relation to a specific implementation of a PCIe protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol can be included / implemented. As an example, a port / interface represented as a layered protocol includes: (1) a first layer to order packets, that is, a transaction layer; (2) a second layer to sequence packets, that is, a link layer; and (3) a third layer to transmit packets, that is, a physical layer. A Common Standard Interface (CSI) layer protocol is used as a specific example.

[0073] Next, referring to Fig.Figure 9 illustrates an embodiment of a serial PCIe point-to-point structure. Although one embodiment of a serial PCIe point-to-point connection is illustrated, a serial point-to-point connection is not so limited, as it includes any transmission path for transmitting serial data. In the embodiment shown, a basic PCIe connection includes two differentially operated low-voltage signal pairs: a transmit pair 906 / 911 and a receive pair 912 / 907. Accordingly, device 905 includes transmit logic 906 to transmit data to device 910 and receive logic 907 to receive data from device 910. In other words, two transmit paths, that is, paths 916 and 917, and two receive paths, that is, paths 918 and 919, are contained in one PCIe connection.

[0074] A transmission path refers to any path used to transmit data, such as a transmission line, a copper wire, an optical line, a wireless communication channel, an infrared communication link, or any other communication path. A connection between two devices, such as Device 905 and Device 910, is called a link, such as Link 915. A link can support a lane—each lane representing a group of differential signal pairs (one pair for transmit, one pair for receive). To scale bandwidth, a link can aggregate multiple lanes, designated xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0075] A differential pair involves two transmission paths, such as lines 916 and 917, to transmit differential signals. For example, when line 916 transitions from a low-voltage level to a high-voltage level (a rising edge), line 917 transitions from a high logic level to a low logic level (a falling edge). Differential signals exhibit potentially better electrical characteristics, such as improved signal integrity (i.e., reduced cross-coupling, voltage overshoot / undershoot, and oscillation). This allows for a narrower time window, enabling faster transmission frequencies.

[0076] It should be noted that the devices, methods, and systems described above can be implemented in any electronic component or system as mentioned above. The following figures provide specific illustrations of exemplary systems for the use of the invention as described herein. Since the following systems are described in more detail, a number of different circuit configurations are disclosed, described, and revisited from the discussion above. And, as is readily apparent, the advances described above can be applied to any of these circuit configurations, structures, or architectures.

[0077] Now, with reference to Fig. Figure 10 shows a block diagram of an embodiment of a multicore processor. As in the embodiment of Fig.As shown in Figure 10, the 1000 processor has multiple domains. In particular, a core domain 1030 has multiple cores 1030A-1030N, a graphics domain 1060 has one or more graphics engines, including a media engine 1065, and a system agent domain 1010.

[0078] In various embodiments, the system agent domain 1010 processes power control events and power management such that individual units of domains 1030 and 1060 (e.g., cores and / or graphics engines) can be controlled independently to dynamically operate in a suitable power mode / level (e.g., active turbo, sleep, idle, deep sleep, or other advanced configuration power interface-like state) in light of the activity (or inactivity) occurring in the given unit. Each of domains 1030 and 1060 can operate at a different voltage and / or power, and furthermore, the individual units within the domains can each potentially operate at an independent frequency and voltage. It should be noted that, although only three domains are shown, the scope of the present invention is not limited in this respect, and additional domains may be present in other embodiments.

[0079] As shown, each 1030 core also includes low-level caches in addition to various execution units and additional processing elements. Here, the various cores are coupled to each other and to a shared cache memory formed from multiple units or pieces of a 1040A-1040N last-level cache (LLC); these LLCs often include storage and cache controller functionality and are shared among the cores and potentially also among the graphics engine.

[0080] As can be seen, a ring interconnect 1050 couples the cores together and provides a connection between the core domain 1030, the graphics domain 1060, and the system agent circuits 1010 via several ring stops 1052A-1052N, each at a coupling between a core and an LLC segment. As shown in Fig.As shown in Figure 10, the 1050 interconnect is used to carry various pieces of information, including address, data, acknowledgment, and snoop / invalid information. Although a ring interconnect is illustrated, any known on-die interconnect or structure can be used. As an illustrative example, some of the previously discussed structures (e.g., another on-die interconnect, Intel On-Chip System Fabric (IOSD), an Advanced Microcontroller Bus Architecture (AMBA) interconnect, a multidimensional grid structure, or other known interconnect architectures) can be used in a similar manner.

[0081] As further illustrated, the system agent domain 1010 includes a display engine 1012, which provides control of and an interface to an associated display. The system agent domain 1010 may include other units, such as: an integrated memory controller 1020, which provides an interface to system memory (e.g., DRAM implemented with multiple DIMMs); ​​and coherence logic 1022 for performing memory coherence operations. Multiple interfaces may be provided to enable interconnection between the processor and other circuitry. For example, in one embodiment, at least one Direct Media Interface (DMI) 1016 interface and one or more PCIe™ interfaces 1014 are provided. The display engine and these interfaces are typically coupled via a PCIe™ bridge 1018.Furthermore, one or more other interfaces (e.g., an Intel® Quick Path Interconnect (QPI) structure) can be provided to enable communication between other agents, such as additional processors or other circuits.

[0082] If you turn next Fig.Figure 11 shows an embodiment of a system-on-a-chip (SOC) design according to the inventions. As a specific illustrative example, SOC 1100 is included in a user equipment (UE). In one embodiment, UE refers to any device used by an end user for communication, such as a portable telephone, smartphone, tablet, ultrathin notebook, notebook with a broadband adapter, or any other similar communication device. Often, a UE connects to a base station or node that is potentially equivalent in nature to a mobile station (MS) in a GSM network.

[0083] Here, the SOC 1100 includes two cores – 1106 and 1107. Similar to the discussion above, cores 1106 and 1107 can correspond to an instruction set architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or users. Cores 1106 and 1107 are coupled to cache controller 1108, bus interface unit 1109, and L2 cache memory 1110 to communicate with other parts of the system 1100. The interconnect 1110 includes on-chip interconnects, such as IOSF, AMBA, or other interconnects discussed above, which potentially implement one or more aspects of the described invention.

[0084] Interface 1110 provides communication channels to other components, such as Subscriber Identity Module (SIM) 1130 for connecting to a SIM card, Boot ROM 1135 for holding boot code for execution by cores 1106 and 1107 to initialize and start the SOC 1100, SDRAM controller 1140 for connecting to external memory (e.g., DRAM 1160), Flash controller 1145 for connecting to non-volatile memory (e.g., Flash 1165), peripheral controller 1150 (e.g., Serial Peripheral Interface) for connecting to peripheral devices, video codecs 1120 and video interface 1125 for displaying and receiving input (e.g., touch-enabled input), GPU 1115 for performing graphics-related calculations, etc. Any of these interfaces may incorporate aspects of the invention described herein.

[0085] Additionally, the system illustrates peripheral communication devices, such as the Bluetooth module 1170, 3G modem 1175, GPS 1185, and WiFi 1185. It should be noted, as mentioned above, that a UE includes a radio for communication. Consequently, not all of these peripheral communication modules are required. However, a UE should contain some form of radio for external communication.

[0086] With reference to now Fig. Figure 12 shows a block diagram of a second system 1200 according to an embodiment of the present invention. As in Fig.As shown in Figure 12, the multiprocessor system 1200 is a point-to-point interconnect system and comprises a first processor 1270 and a second processor 1280, which is coupled via a point-to-point interconnect 1250. Each of the processors 1270 and 1280 can be any version of a processor. In one embodiment, 1252 and 1254 are part of a coherent serial point-to-point interconnect fabric, such as Intel's Quick Path Interconnect (QPI) architecture. As a result, the invention can be implemented within the QPI architecture.

[0087] Although it is shown with only two processors 1270, 1280, it must be understood that the scope of protection of the present invention is not limited thereto. In other embodiments, one or more additional processors may be present in a given processor.

[0088] The 1270 and 1280 processors are shown each having integrated memory controller units 1272 and 1282, respectively. The 1270 processor has point-to-point (PP) interfaces 1276 and 1278 as part of its bus controller units; the second processor, 1280, similarly has PP interfaces 1286 and 1288. The 1270 and 1280 processors can exchange data via a point-to-point (PP) interface 1250 using PP interface circuits 1278 and 1288. As shown in Fig. As shown in Figure 12, IMCs 1272 and 1282 couple the processors with respective memories, namely a memory 1232 and a memory 1234, which can be parts of a main memory that are attached locally to the respective processors.

[0089] The 1270 and 1280 processors can each exchange information with a 1290 chipset via individual PP interfaces 1252 and 1254 using point-to-point interface circuits 1276, 1294, 1286, and 1298. The 1290 chipset also exchanges information with a high-performance graphics circuit 1238 via an interface circuit 1292 along a high-performance graphics circuit 1239.

[0090] A shared cache (not shown) may be contained within both processors or outside of both processors, but be connected to the processors via a PP connection such that when one processor is put into a low-power mode, the local cache information of one or both processors is stored in the shared cache.

[0091] The chipset 1290 can be coupled to a first bus 1216 via an interface 1296. In one embodiment, the first bus 1216 can be a PCI bus (PCI: Peripheral Component Interconnect) or a bus such as a PCI Express bus or another third-generation I / O interconnect bus, although the scope of protection of the present invention is not limited thereto.

[0092] As in Fig.As shown in Figure 12, various I / O devices 1214 can be coupled to the first bus 1216 together with a bus bridge 1218, which couples the first bus 1216 to a second bus 1220. In one embodiment, the second bus 1220 has an LPC (Low Pin Count) bus. Various devices are coupled to a second bus 1220 in one embodiment, which, for example, includes a keyboard and / or mouse 1222, communication devices 1227, and a storage unit 1228, such as a disk drive or other mass storage device, which often contains instructions / code and data 1230. Furthermore, an audio I / O 1224 is shown coupled to the second bus 1220. It should be noted that other architectures are possible, with varying components and interconnection architectures. For example, a system can use a point-to-point architecture instead of the... Fig. 12. Implement a multi-drop bus or other such architecture.

[0093] Although the present invention has been described with reference to a limited number of embodiments, the person skilled in the art will be able to appreciate numerous modifications and variants thereof. It is intended that the attached claims cover all such modifications and variants as fall within the true spirit and scope of protection of this present invention.

[0094] A design can go through several stages, from design to simulation to manufacturing. Data representing a design can represent it in a number of ways. First, the hardware, which is useful in simulations, can be represented using a hardware description language or another functional description language. Additionally, at some stages of the design process, a circuit-level model with logic and / or transistor gates can be created. Furthermore, most designs at some point reach a data level that represents the physical placement of various devices within the hardware model.In cases where conventional semiconductor manufacturing techniques are used, the data representing the hardware model can be data specifying the presence or absence of various features on different mask layers used to fabricate the integrated circuit. In any design representation, the data can be stored on any form of machine-readable medium. A memory or magnetic or optical storage medium, such as a disk, can be the machine-readable medium for storing information transmitted via optical or electrical waves that are modulated or otherwise generated to transmit such information.When an electrical carrier wave, which displays or carries the code or design, is transmitted to the extent that copying, buffering, or retransmission of the electrical signal is performed, a new copy is created. Thus, a communications provider or network operator can, at least temporarily, store an item, such as information encoded in a carrier wave, on a tangible, machine-readable medium by employing techniques of embodiments of the present invention.

[0095] A module, as used here, refers to any combination of hardware, software, and / or firmware. For example, a module includes hardware, such as a microcontroller, associated with a non-volatile medium for storing code designed to be executed by the microcontroller. Thus, in one embodiment, a reference to a module refers to the hardware specifically configured to recognize and / or execute the code stored on the non-volatile medium. Furthermore, in another embodiment, the use of a module refers to the non-volatile medium containing the code specifically adapted for execution by the microcontroller to perform predetermined operations. As can be inferred, in yet another embodiment, the term "module" (in this example) can refer to the combination of the microcontroller and the non-volatile medium.Module boundaries, often depicted as separate, are generally variable and potentially overlap. For example, a first and second module might share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, the use of the term "logic" includes hardware such as transistors, registers, or other hardware such as programmable logic devices.

[0096] The use of the phrase "for" or "designed for" in an embodiment relates to arranging, assembling, manufacturing, offering for sale, importing, and / or designing a device, hardware, logic, or element to perform a designated or specific task. In this example, a device or element thereof that is not operating is still "designed" to perform a designated task if it is designed, coupled, and / or interconnected to perform the designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. However, a logic gate that is "designed" to provide an enable signal to a clock does not have every potential logic gate that might provide a 1 or a 0.Instead, the logic gate is one that is coupled in some way, where, during operation, the output 1 or 0 is intended to enable the clock. It should be noted again that the use of the term "designed for" does not require operation, but instead focuses on the latent state of a device, hardware, and / or element, where the latent state of the device, hardware, and / or element is designed to perform a specific task when the device, hardware, and / or element is operational.

[0097] Furthermore, the use of the phrases "capable of" and / or "operable of" in an embodiment refers to any device, logic, hardware, and / or element that is designed to enable the use of the device, logic, hardware, and / or element in a specified manner. It should be noted, as above, that a use of "capable of" or "operable of" in an embodiment refers to the latent state of the device, logic, hardware, and / or element, wherein the device, logic, hardware, and / or element is not operational but is designed to enable the use of a device in a specified manner.

[0098] As used here, a value has any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values ​​is also referred to as 1s and 0s, which simply represent binary logic states. For example, 1 refers to a high logic level, and 0 refers to a low logic level. In one embodiment, a memory cell, such as a transistor or flash cell, may be able to hold a single logical value or multiple logical values. However, other representations of values ​​have been used in computer systems. For example, the decimal number ten can also be represented as a binary value of 1010 and a hexadecimal letter A. Therefore, a value encompasses any representation of information that can be held in a computer system.

[0099] Furthermore, states can be represented by values ​​or segments of values. For example, a first value, such as a logical one, can represent a default or initial state, whereas a second value, such as a logical zero, can represent a non-default state. Additionally, in one embodiment, the terms Reset and Set refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e., Reset, whereas an updated value potentially includes a low logical value, i.e., Set. It should be noted that any combination of values ​​can be used to represent any number of states.

[0100] The embodiments of methods, hardware, software, firmware, or code described above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium, which are executable by a processing element. A non-volatile machine-accessible / machine-readable medium includes any mechanism that provides (that is, stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system.For example, a non-transitory, machine-accessible medium includes random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; a magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals), etc.; which must be distinguished from the non-transitory ones that can receive information from them.

[0101] Instructions used to program logic and execute embodiments of the invention can be stored within a memory such as DRAM, cache, flash memory, or other storage media within the system. Furthermore, the instructions can be distributed over a network or via other computer-readable media.Thus, a machine-readable medium can include, among other things, any mechanism for storing or transmitting information in a form that can be read by a machine (for example, a computer), such as: floppy disks, optical disks, compact disks, read-only memory (CD-ROM) and magneto-optical disks, read-only memory (ROM), random-access memory (RAM), erasable-programmable read-only memory (EPROM), electrically-erasable-programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or any tangible, machine-readable storage device used in the transmission of information over the Internet via electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.).Accordingly, computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (for example, a computer).

[0102] Throughout this specification, reference to "(exactly) one embodiment" or "an embodiment" means that a specific feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the present techniques. Therefore, the appearance of the phrases "in (exactly) one embodiment" or "in an embodiment" at various points throughout the specification does not necessarily always refer to the same embodiment. Furthermore, the specific features, structures, or characteristics may be combined in one or more embodiments in any suitable manner.

[0103] The preceding specification provided a detailed description with reference to specific exemplary embodiments. However, it is obvious that various modifications and changes can be made to it without deviating from the broader spirit and scope of protection of the invention as set forth in the appended claims. The specification and the drawings should therefore be considered in an illustrative rather than a limiting sense. Furthermore, the preceding use of "embodiment" and other exemplary language does not necessarily refer to the same embodiment or example, but may refer to other and different embodiments as well as potentially to the same embodiment.

[0104] The following section provides examples of various embodiments disclosed herein.

[0105] Example 1 is a method for performing a data prefetch from a cache memory, wherein the method is performed by a root complex compliant with a Peripheral Component Interconnect Express (PCIe) protocol, and wherein the method includes receiving a data packet from a device connected to the root complex via a PCIe-compliant connection; identifying a memory transaction indicator bit from the received device; determining a memory transaction from the memory transaction indicator bit; and performing an optimization process based at least in part on the determined memory transaction.

[0106] Example 2 can include the subject of Example 1 or Example 5 and further features the marking of a hint indicator bit in the data packet, wherein the hint indicator bit indicates that a hint bit is set in the data packet.

[0107] Example 3 may include the subject of Example 2, wherein the marking of a hint indicator bit in the data packet involves reading a predetermined bit from a group of reserved bits and determining that the predetermined bit indicates that a hint bit is set.

[0108] Example 4 may include the subject matter of any of Examples 1-3, wherein marking a memory transaction indicator bit includes reading a predetermined bit from a group of reserved bits; and determining that the predetermined bit indicates an impending memory transaction.

[0109] Example 5 can include the subject of any of Examples 1-4, wherein the received data packet contains an address translation service request packet.

[0110] Example 6 can include the subject of Example 5, where the memory transaction hint bit occupies a packet location defined by DW0.byte3.bits[2:0].

[0111] Example 7 may include the subject of any of Examples 5-6 and further features the identification of memory address location information based on the received data packet, wherein the memory address location information occupies a group of reserved bits defined by DW3, byte 3, bits [7:3] and DW3, byte 2, bits [2:0].

[0112] Example 8 can include the subject of any of Examples 1-4, wherein the received data packet contains a zero-length write packet.

[0113] Example 9 can include the subject of Example 8, where the memory transaction hint bit occupies unused lower address bits of the zero-length write data packet.

[0114] Example 10 may include the subject of any of Examples 1-9, wherein performing the optimization process includes performing a caching behavior optimization process.

[0115] Example 11 may include the subject of any of Examples 1-10, where the caching behavior optimization process involves performing an advance ownership retrieval in response to the memory transaction hint indicating a streaming write operation.

[0116] Example 12 may include the subject of any of Examples 1-10, wherein the caching behavior optimization process involves performing a prefetch of data and loading the data into a cache memory in response to the memory transaction hint indicating a read transaction.

[0117] Example 13 may include the subject of any of Examples 1-10, wherein the caching behavior optimization process involves performing a prefetch of ownership and data in response to the memory transaction cue indicating an atomic or cacheable operation.

[0118] Example 14 may include the subject of any of Examples 1-10, wherein performing the optimization process involves initializing a labeled memory page that includes predetermined features.

[0119] Example 15 may include the subject of Example 14, wherein initializing the labeled memory page includes updating metadata stored with the page in memory.

[0120] Example 16 can include the subject of Example 15, where updating metadata includes adding capabilities to the page, the capabilities including security features for the storage transaction.

[0121] Example 17 is a computer program product tangiblely embodied in non-volatile, computer-readable media, wherein the computer program product includes code which, when executed, causes a root complex hardware element to receive a data packet from a device attached to the root complex via a PCIe-compliant connection; identify a memory transaction indicator bit based on the received device; determine a memory transaction based on the memory transaction indicator bit; and perform an optimization process that is based, at least in part, on the determined memory transaction.

[0122] Example 18 can include the subject of Example 17, wherein, when executed, the code causes the root complex to mark a hint indicator bit in the data packet, the hint indicator bit indicating that a hint bit is set in the data packet.

[0123] Example 19 may include the subject of any of Examples 17-18, wherein the code, when executed, causes the root complex to designate a memory transaction indicator bit by reading a predetermined bit from a set of reserved bits; and determines that the predetermined bit indicates an impending memory transaction.

[0124] Example 20 may include the subject of any of Examples 17-19, where the optimization process involves performing a caching behavior optimization process.

[0125] Example 21 may include the subject of Example 20, wherein the caching behavior optimization process includes performing an ownership prefetch in response to the memory transaction hint indicating a streaming write operation, performing an ownership prefetch and loading the data into a cache memory in response to the memory transaction hint indicating a read transaction, performing an ownership prefetch and data prefetch in response to the memory transaction hint indicating an atomic operation or a cacheable operation.

[0126] Example 22 may include the subject of any of Examples 17-21, wherein the optimization process involves initializing a labeled memory page that has predetermined features.

[0127] Example 23 may include the subject of Example 22, wherein initializing the labeled memory page includes updating metadata stored with the page in memory.

[0128] Example 24 can include the subject of Example 23, where updating metadata includes adding capabilities to the page, the capabilities including security features for the storage transaction.

[0129] Example 25 is a method performed on an apparatus connected to a root complex via a Peripheral Component Interconnect Express (PCIe) compliant link, wherein the method comprises determining an impending memory transaction using memory connected to the root complex; setting a hint indicator bit in a first reserved bit of a data packet; setting a memory transaction bit in a second reserved bit of the data packet; and transferring the data packet to the root complex via the PCIe compliant link.

[0130] Example 26 may include the subject of Example 25 and may also include setting other reserved bits to add granularity to the memory transaction display.

[0131] Example 27 is a root complex structure, wherein the root complex structure is coupled to a processor and memory, and wherein the root complex structure is connected to multiple attached devices via a switching structure compliant with the PCIe protocol. The root complex may include logic, implemented at least partially in hardware, to receive a data packet from a device connected to the root complex via a PCIe-compliant connection; to identify a memory transaction indicator bit based on the received device; to determine a memory transaction based on the memory transaction indicator bit; and to perform an optimization process based at least partially on the determined memory transaction.

[0132] Example 28 can include the subject of Example 27, wherein the code, when executed, causes the root complex to mark a hint indicator bit in the data packet, the hint indicator bit indicating that a hint bit is set in the data packet.

[0133] Example 29 may include the subject of any of Examples 27-28, wherein the code, when executed, causes the root complex to designate a memory transaction indicator bit by reading a predetermined bit from a set of reserved bits; and determines that the predetermined bit indicates an impending memory transaction.

[0134] Example 30 may include the subject of any of Examples 27-29, where the optimization process involves performing a caching behavior optimization process.

[0135] Example 31 may include the subject of Example 30, wherein the caching behavior optimization process includes performing an ownership prefetch in response to the memory transaction hint indicating a streaming write operation, performing an ownership prefetch and loading the data into a cache memory in response to the memory transaction hint indicating a read transaction, performing an ownership prefetch and data prefetch in response to the memory transaction hint indicating an atomic operation or a cacheable operation.

[0136] Example 32 may include the subject of any of Examples 27-31, wherein the optimization process involves initializing a labeled memory page that has predetermined features.

[0137] Example 33 may include the subject of Example 32, wherein initializing the labeled memory page includes updating metadata stored with the page in memory.

[0138] Example 34 may include the subject of Example 33, where updating metadata includes adding capabilities to the page, the capabilities including security functions for the storage transaction.

Claims

[1] Method for performing a data prefetch from a cache memory, wherein the method is performed by a root complex compliant with a Peripheral Component Interconnect Express (PCIe) protocol, the method comprising: Receiving a data packet (502) from a device connected to the root complex via a PCIe-compliant connection; Identify a memory transaction hint bit (506) based on the received data packet; Determining a memory transaction using the memory transaction indicator bit; and Performing an optimization process based at least in part on the specified memory transaction (508), wherein performing the optimization process (508) includes performing a caching behavior optimization process and wherein the caching behavior optimization process includes performing an advance retrieval of ownership in response to the memory transaction hint indicating a streaming write operation. [2] Method according to claim 1, further comprising identifying a hint indicator bit in the data packet (504), wherein the hint indicator bit indicates that a hint bit is set in the data packet. [3] Method according to claim 2, wherein the marking of a hint indicator bit in the data packet (504) comprises reading a predetermined bit from a group of reserved bits and determining that the predetermined bit indicates that a hint bit is set. [4] Method according to claim 1, wherein the marking of a memory transaction indicator bit (506) comprises reading a predetermined bit from a group of reserved bits; and determining that the predetermined bit indicates an impending memory transaction. [5] Method according to claim 1, wherein the received data packet includes an address translation service request packet. [6] Method according to claim 5, wherein the memory transaction hint bit occupies a packet location defined by DW0.byte3.bits[2:0]. [7] Method according to claim 5, further comprising identifying memory address location information based on the received data packet, wherein the memory address location information occupies a group of reserved bits defined by DW3, byte 3, bits [7:3] and DW3, byte 2, bits [2:0]. [8] Method according to claim 1, wherein the received data packet comprises a zero-length write packet. [9] Method according to claim 8, wherein the memory transaction indicator bit occupies unused lower address bits of the zero-length write data packet. [10] Method according to claim 1, wherein performing the optimization process (508) comprises initializing a characterized memory page having predetermined features. [11] Method according to claim 10, wherein initializing the characterized memory page comprises updating metadata stored with the page in the memory. [12] Method according to claim 11, wherein updating metadata includes adding capabilities to the storage page, the capabilities including security functions for the storage transaction. [13] Computer program that is tangibly embodied in non-volatile, computer-readable media, wherein the computer program product includes code which, when executed, causes a root complex hardware element to perform the following: Receiving a data packet (502) from a device connected to the root complex via a PCIe-compliant connection; Identify a memory transaction hint bit (506) based on the received data packet; Determining a memory transaction using the memory transaction indicator bit; and Performing an optimization process based at least in part on the specified memory transaction (508), wherein the optimization process (508) includes performing a caching behavior optimization process and wherein the caching behavior optimization process includes performing an advance ownership retrieval in response to the memory transaction hint indicating a streaming read operation. [14] Computer program product according to claim 13, wherein the code, when executed, causes the root complex to mark a hint indicator bit in the data packet (504), wherein the hint indicator bit indicates that a hint bit is set in the data packet. [15] Computer program product according to claim 13, wherein the code, when executed, causes the root complex to designate a memory transaction indicator bit by reading a predetermined bit from a group of reserved bits; and determines that the predetermined bit indicates an impending memory transaction. [16] Computer program product according to claim 13, wherein the optimization process (508) comprises initializing a characterized memory page having predetermined features. [17] Computer program product according to claim 16, wherein initializing the characterized memory page comprises updating metadata stored with the page in the memory. [18] Computer program product according to claim 17, wherein updating metadata includes adding capabilities to the page, the capabilities including security functions for the storage transaction.

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