Processor, chip, system, method, computer program product and machine-readable storage medium for bit matrix multiplication

Abstract

Processor, comprising: a core that, in response to a single matrix multiplication instruction specifying a first source bit matrix, a second source bit matrix, a destination matrix, and an operation selector, performs operations corresponding to the single matrix multiplication instruction, including: for each multi-bit position in the target matrix: Process bit values from bit positions of a corresponding row of the first source bit matrix and bit values from corresponding bit positions of a corresponding column of the second source bit matrix with one of a plurality of different types of logical operations selected by the operation selector to produce corresponding results, wherein the plurality of different types of logical operations comprise at least one of a logical AND operation or NAND operation, a logical OR operation or NOR operation, and a logical exclusive-OR operation, XOR operation, or NOT-XOR operation; to accumulate the results; and to store a result corresponding to the accumulation of the results at the multi-bit position in the destination matrix, wherein the matrix multiplication instruction defines a row size and a column size of the first source bit matrix that is different from the row size, a row size and a column size of the second source bit matrix that is different from the row size, wherein the row size of the second source bit matrix corresponds to the column size of the first source bit matrix, and a row size and a column size of the destination matrix, wherein the row size of the destination matrix corresponds to the row size of the first source bit matrix and wherein the column size of the destination matrix corresponds to the column size of the second source bit matrix.

Description

FIELD OF THE INVENTIONThe field of the invention relates to a processor, a chip, a system, a method, a computer program product and a machine readable storage medium for bit matrix multiplication.PRIOR ARTVarious instances of bioinformatics, software defined radio (software defined radio), image acquisition and cryptology applications (various encryption algorithms, secure hash functions, etc.) use bit-matrix multiplication (BMM). Various operations may be more efficient when implemented as BMM, such as S-boxes, bit permutations, Hadamard transform, bitwise neural networks, Galois field multiplications (used in cryptography and channel coding), etc., as well as for bit manipulations.US 5 175 862 A relates to a method and apparatus for a specific arithmetic-Boolean unit for performing extremely parallel bit-level Boolean operations and matrix manipulations. The particular arithmetic-Boolean unit is capable of performing extremely parallel Boolean operations on bit-level, particularly bit-matrix manipulations. The arithmetic-Boolean special purpose unit is particularly suited for use in conventional vector processors, thereby enabling a vector processor to effectively solve extremely parallel Boolean MIMD or SIMD problems without requiring an array processor or massively parallel supercomputer.Hilewith et al.: "Bit Matrix Multiplication on Commodity Processors", describes processor instructions that implement simpler bit matrix multiplication operations for commercially available processors.Lemuet et al.: "The Potential Energy Efficiency of Vector Acceleration", describes a vector accelerator architecture.US 2015 / 0339101 A1 relates to a processor with data rearrangement functionality, in particular using a bit matrix multiplication unit. By way of example, a processor will be described that includes in its instruction set a bit-matrix multiplication instruction that includes a first double-precision operand representing a first matrix to be multiplied, a second operand that explicitly designates any two single-precision registers whose common content represents a second matrix to be multiplied, and a target parameter that explicitly designates any two single-precision registers that collectively include a matrix representing the result of the multiplication.SUMMARY OF THE INVENTIONIt can therefore be considered an object of the present invention to propose a processor, a chip, a system, a method, a computer program product and a machine-readable storage medium for performing bit matrix multiplication with improved efficiency and flexibility.The above object is achieved according to the invention with the processor according to the main claim 1, the chip according to the subordinate claim 15, the system according to the subordinate claim 16, the method according to the subordinate claim 19, the computer program product according to the subordinate claim 26 and the machine-readable storage medium according to the subordinate claim 27. The dependent claims define further developments of the solutions according to the invention.BRIEF DESCRIPTION OF THE DRAWINGSThe present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, wherein like references indicate like elements and: FIG. 1 illustrates an embodiment of a selected portion of execution of a BMM instruction having as sources an 8x8 bit matrix with an 8x64 bit matrix; FIG. 2 illustrates an embodiment of a selected portion of execution of a BMM instruction having as sources a 64x8 bit matrix with an 8x8 bit matrix; FIG. 3 illustrates an embodiment of a selected portion of execution of a BMM instruction having as sources an 8x64 bit matrix with a 64x64 bit matrix; FIG. 4 illustrates an embodiment of a selected portion of execution of a BMM instruction having as sources a 64x64 bit matrix with a 64x8 bit matrix; FIG. 5 illustrates one embodiment of hardware for processing an instruction, such as a BMM instruction; FIG. 6 illustrates an embodiment of a method performed by a process for processing a BMM command; FIG. 7 illustrates a more detailed description of execution of a BMM instruction; FIGS. 8A-8B are block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof, according to embodiments of the invention; FIG. 9A is a block diagram illustrating an example specific vector friendly instruction format according to embodiments of the invention; FIG. 9B is a block diagram illustrating fields of the specific vector friendly instruction format 900 forming the full opcode field 874 according to an embodiment of the invention; FIG. 9C is a block diagram illustrating fields of the specific vector friendly instruction format 900 constituting the register index field 844, according to an embodiment of the invention; FIG. 9D is a block diagram illustrating fields of the specific vector friendly instruction format 900 constituting the auxiliary operation field 850 according to an embodiment of the invention; FIG. 10 is a block diagram of a register architecture 1000, according to an embodiment of the invention; FIG. 11A is a block diagram illustrating both an example in-order (out-of-order) pipeline and an example out-of-order (out-of-order) register rename issue / execution pipeline, in accordance with embodiments of the invention; FIG. 11B is a block diagram illustrating both an example embodiment of a high-level architectural core and an example level register rename output / execution architectural core to be included in a processor, in accordance with embodiments of the invention; FIGS. 12A-B illustrate a block diagram of a more specific example in-order (in-order) core architecture whose core would be one of multiple logic blocks (including other cores of the same type and / or other types) in a chip; FIG. 13 is a block diagram of a processor 1300 that may have more than one core, may have an integrated memory controller, and may have integrated graphics, according to embodiments of the invention; FIG. 14 is a block diagram of a system according to an embodiment of the present invention; FIG. 15 is a block diagram of a first more specific exemplary system according to an embodiment of the present invention; FIG. 16 is a block diagram of a second more specific exemplary system according to an embodiment of the present invention; FIG. 17 is a block diagram of a system-on-a-chip (SoC) according to an embodiment of the present invention; and FIG. 18 is a block diagram illustrating use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set remotely, in accordance with embodiments of the invention.DETAILED DESCRIPTIONTypically, processor cores are optimized around processing words, not bits. Therefore, bit-level complex operations are typically not supported as well.Embodiments of BMM instructions and their execution are described in detail herein. Depending on the implementation, the instructions detailed herein may include general purpose registers (e.g., 64-bit GPRs), packed data (sometimes vector or single-instruction multiple data (SIMD) registers, or register blocks or memory-based (e.g., 64-bit, 512-bit, 4096-bit, etc.) Use operands. These instructions are improvements to a computer itself because they provide support for BMM that was not previously possible. In particular, execution of a BMM instruction results in bit-matrix multiplication of two source matrices being performed, with the particular circuitry used in multiplication and addition aspects being selected via the instruction. In some embodiments, element-by-element multiplying is performed using an AND operation and term-by-term summing is performed using an exclusive OR operation (XOR). As described in detail below, embodiments of the BMM instructions described in detail herein may have selectable multiplying and / or summing circuitry. For example, a immediate operand (or other operand(s)) indicates which multi-dictionary and adder arrangements are used in the BMM. Example multiplication circuits (⊗) include, among other things: bitwise AND, NAND, XOR, XNOR, and / or NOR. Exemplary addition circuits (≅) include, among others: bitwise XOR, NOR, OR, XNOR; majority (=1 if majority is 1); and minority. In the following discussion, brackets [ ] indicate the value of a specific bit, ⊗ indicates bit field multiplication (e.g., AND), and ≅ indicates bit accumulation (e.g., XOR).FIG. 1 illustrates an embodiment of a selected portion of execution of a BMM instruction having as sources an 8x8 bit matrix with an 8x64 bit matrix; the format of this BMM instruction includes fields for an opcode ("VBMM8x64" is the opcode mnemonic in this illustration), a first source bit matrix operand identifier (shown as "SOURCE 1"), a second source bit matrix operand identifier (shown as "SOURCE 2 / MEM"), a immediate operand, and a destination bit matrix operand identifier (shown as "DESTINATION").The two source operand fields represent a location of a first source bit array operand 101 and a second source bit array operand 103. These locations may be a storage location (e.g., an address in memory, such as a hard disk or RAM), or one or more registers.In this illustration, the first source bit array operand 101 is an 8×8 bit array. In some embodiments of BMM instructions, an 8×8 bit matrix is stored in memory or in one or more registers as a sequence of 8 8-bit rows beginning with row 0. Thus, the access to the bit in row I, column J of matrix M would be: M[I,J]=M[I*8+J], and if stored in memory: (M[I]>>J) &1.In this illustration, the second source bit array operand 101 is an 8x64 bit array. In some embodiments, an 8x64 bit array (8 lines of 64 bits) is stored in memory or in one or more registers as a sequence of 64-bit lines starting with line 0. Thus, the access to the bit in row I, column J of matrix M would be: M[I,J] = M[I*64+J] (this refers to bit, not byte), or otherwise, to obtain the value of bit M[I,J] stored in memory, some (M[I*8]>>J)&1 would use, presuming byte addressing.The destination bit-matrix operand field represents a destination bit-matrix operand 121 which stores the result of the bit-matrix multiplication operation. As previously stated, this operand 121 may be stored in a register (e.g., 512-bit registers), a collection of registers, or locations in memory.As shown, execution circuitry 111 includes multiple multiplication arrays 113 and multiple adder arrays 115. The immediate operand of the instruction is used to select a type of multiplication array 113 and a type of adder array 115. For example, in some embodiments, bits 4:7 of an 8-bit immediate operand are used by the multiplication selector 117 to select the multiplication circuitry from the plurality of multiplication arrays 113. For example, imm8[4:7] selects from the circuits XOR, AND, OR, NOR, NAND, and XNOR for multiplication. In some embodiments, bits 0:3 of an 8-bit immediate operand are used by the adder selector 119 to select the multiplication circuitry from the plurality of adder arrays 115. For example, imm8[0:3] selects from the circuits XOR, AND, OR, NOR and XNOR for addition. Any particular arrangement may be used to signal the selection, but an example table of selections is given below:TABLE 1 TABLE 10000XOR0000XOR0001AND0001AND0010OR0010OR0011NOR0011NOR0100XNOR0100XNOR01010101NANDThe plot shows two positions of the calculated result (TARGET[0] and TARGET

[168] ). TARGET[0] is calculated as follows: TARGET[0*64+ 0] = QUELLE1[0*8+0]⊗QUELLE2[0*64 + 0] ≅ QUELLE1[0*8+1]@QUELLE2[1 *64+ 0] ≅... ≅ QUELLE1[0*8+7]⊗QUELLE2[7*64 + 0]. TARGET

[168] is calculated as follows: TARGET[2*64+40] = QUELLE1[2*8+0]⊗QUELLE2[0*64 +40] ≅ QUELLE1[2*8+1]⊗QUELLE2[1 *64+40] ≅... ≅ QUELLE1[2*8+7]⊗QUELLE2[7*64 +40].FIG. 2 illustrates an embodiment of a selected portion of execution of a BMM instruction having as sources a 64x8 bit matrix with an 8x8 bit matrix; the format of this BMM instruction includes fields for an opcode ("VBMM64x8" is the opcode mnemonic in this illustration), a first source bit matrix operand identifier (shown as "SOURCE 1"), a second source bit matrix operand identifier (shown as "SOURCE 2 / MEM"), a immediate operand, and a destination bit matrix operand identifier (shown as "DESTINATION").The two source operand fields represent a location of a first source bit array operand 201 and a second source bit array operand 203. These locations may be a storage location (e.g., an address in memory, such as a hard disk or RAM), or one or more registers.In this illustration, the first source bit array operand 201 is a 64x8 bit array. In some embodiments of BMM instructions, a 64x8 bit array (8 lines of 64 bits) is stored as a sequence of 8 64-bit lines. Thus, the access to the bit in row I, column J of matrix M would be: M[I,J] = M[I*64+J] (this refers to bit, not byte), or otherwise, to obtain the value of bit M[I,J] stored in memory, some (M[I*8]>>J)&1 would use, presuming byte addressing. Loading this type of array into a 512 bit register involves reading from a start address of the first row.In this illustration, the second source bit array operand 203 is an 8x8 bit array. In some embodiments of BMM instructions, an 8x8 bit matrix is stored in memory or in one or more registers as a sequence of 8 8-bit lines starting with line 0. Thus, the access to the bit in row I, column J of matrix M would be: M[I,J]=M[I*8+J], and if stored in memory: (M[I]>>J) &1.The destination bit-matrix operand field represents a destination bit-matrix operand 221 which stores the result of the bit-matrix multiplication operation. As previously stated, this operand 221 may be stored in a register (e.g., 512-bit registers), a collection of registers, or locations in memory.As shown, execution circuitry 211 includes multiple multiplication arrays 213 and multiple adder arrays 215. The immediate operand of the instruction is used to select a type of multiplication array 213 and a type of adder array 215. For example, in some embodiments, bits 4:7 of an 8-bit immediate operand are used by the multiplication selector 217 to select the multiplication circuitry from the plurality of multiplication arrays 213. For example, imm8[4:7] selects from the circuits XOR, AND, OR, NOR, NAND, and XNOR for multiplication. In some embodiments, bits 0:3 of an 8-bit immediate operand are used by the adder selector 219 to select the multiplication circuitry from the plurality of adder arrays 215. For example, imm8[0:3] selects from the circuits XOR, AND, OR, NOR and XNOR for addition. Any particular arrangement may be used to signal the selection, but an example table of selections is given below:TABLE 2 TABLE 20000XOR0000XOR0001AND0001AND0010OR0010OR0011NOR0011NOR0100XNOR0100XNOR01010101NANDThe plot shows two positions of the calculated result (TARGET[0] and TARGET

[511] ). TARGET[0] is calculated as follows: TARGET[0*8+ 0] = QUELLE1[0*8+0]⊗QUELLE2[0*8 + 0] ≅ QUELLE1[0*8+1]⊗QUELLE2[1 *8+ 0] ≅...≅ QUELLE1[0*8+7]⊗QUELLE2[7*8 + 0]. TARGET

[511] is calculated as: TARGET[63*8+7] = QUELLE1[63*8+0]⊗QUELLE2[0*8 + 7] ≅ QUELLE1[63*8+1]@QUELLE2[1*8 +7] ≅... ≅ QUELLE1[63*8+7]⊗QUELLE2[7*8 + 7].FIG. 3 illustrates an embodiment of a selected portion of execution of a BMM instruction having as sources an 8x64 bit matrix with a 64x64 bit matrix; the format of this BMM instruction includes fields for an opcode ("VBMM8x64x64" is the opcode mnemonic in this illustration), a first source bit matrix operand identifier (shown as "SOURCE 1"), a second source bit matrix operand identifier (shown as "SOURCE 2 / MEM"), a immediate operand, and a destination bit matrix operand identifier (shown as "DESTINATION").The two source operand fields represent a location of a first source bit array operand 301 and a second source bit array operand 303. These locations may be a storage location (e.g., an address in memory, such as a hard disk or RAM), or one or more registers.In this illustration, the first source bit array operand 301 is an 8x64 bit array. In some embodiments, an 8x64 bit array (8 lines of 64 bits) is stored in memory or in one or more registers as a sequence of 64-bit lines starting with line 0. Thus, the access to the bit in row I, column J of matrix M would be: M[I,J] = M[I*64+J] (this refers to bit, not byte), or otherwise, to obtain the value of bit M[I,J] stored in memory, some (M[I*8]>>J)&1 would use, presuming byte addressing.In this illustration, the second source bit array operand 303 is a 64x64 bit array. In some embodiments of BMM instructions, a 64x64 bit array is stored in memory as a sequence of 64 64-bit lines starting with line 0. Thus, access to a bit in row I, column J of matrix M would be: M[I,J] = M[I*64+J] (this refers to bits, not bytes), or otherwise, to obtain the value of bit M[I,J] stored in memory, some (M[I*8]>>J)&1 would use, presuming byte addressing.The destination bit-matrix operand field represents a destination bit-matrix operand 321 storing the result of the bit-matrix multiplication operation. As previously stated, this operand 321 may be stored in a register (e.g., 512-bit register), collection of registers, or locations in memory.As shown, execution circuitry 311 includes multiple multiplication arrays 313 and multiple adder arrays 315. The immediate operand of the instruction is used to select a type of multiplication array 313 and a type of adder array 315. For example, in some embodiments, bits 4:7 of an 8-bit immediate operand are used by the multiplication selector 317 to select the multiplication circuitry from the plurality of multiplication arrays 313. For example, imm8[4:7] selects from the circuits XOR, AND, OR, NOR, NAND, and XNOR for multiplication. In some embodiments, bits 0:3 of an 8-bit immediate operand are used by the adder selector 319 to select the multiplication circuitry from the plurality of adder arrays 315. For example, imm8[0:3] selects from the circuits XOR, AND, OR, NOR and XNOR for addition. Any particular arrangement may be used to signal the selection, but an example table of selections is given below:TABLE 3 TABLE 30000XOR0000XOR0001AND0001AND0010OR0010OR0011NOR0011NOR0100XNOR0100XNOR01010101NANDThe plot shows two positions of the calculated result (TARGET[0] and TARGET

[168] ). TARGET[0] is calculated as follows: TARGET[0*64 + 0] = QUELLE[0*64+0]@MEM[0*64 + 0] ≅ QUELLE[0*64+1]⊗MEM[1*64 + 0] ≅... ≅ QUELLE[0*64+63]⊗MEM[63*64 + 0]. TARGET

[168] is calculated as follows: TARGET[2*64+40] = QUELLE[2*64+0]⊗MEM[0*64 +40] ≅ QUELLE[2*64+1]⊗MEM[1 *64+40] ≅... ≅ QUELLE[2*64+63]@MEM[63*64 +40].FIG. 4 illustrates an embodiment of a selected portion of execution of a BMM instruction having as sources a 64x64 bit array with a 64x8 bit array; the format of this BMM instruction includes fields for an opcode ("VBMM8x64x64" in this illustration, is opcode mnemonic), a first source bit array operand identifier (shown as "SOURCE 1"), a second source bit array operand identifier (shown as "SOURCE 2 / MEM"), a immediate operand, and a destination bit array operand identifier (shown as "DESTINATION").The two source operand fields represent a location of a first source bit array operand 401 and a second source bit array operand 403. These locations may be a storage location (e.g., an address in memory, such as a hard disk or RAM), or one or more registers.In this illustration, the first source bit array operand 401 is a 64x64 bit array. In some embodiments of BMM instructions, a 64x64 bit array is stored in memory as a sequence of 64 64-bit lines starting with line 0. Thus, access to a bit in row I, column J of matrix M would be: M[I,J] = M[I*64+J] (this refers to bits, not bytes), or otherwise, to obtain the value of bit M[I,J] stored in memory, some (M[I*8]>>J)&1 would use, presuming byte addressing.In this illustration, the second source bit array operand 403 is a 64x8 bit array. In some embodiments of BMM instructions, a 64x8 bit array (8 lines of 64 bits) is stored as a sequence of 8 64-bit lines. Thus, the access to the bit in row I, column J of matrix M would be: M[I,J] = M[I*64+J] (this refers to bit, not byte), or otherwise, to obtain the value of bit M[I,J] stored in memory, some (M[I*8]>>J)&1 would use, presuming byte addressing. Loading this type of array into a 512 bit register involves reading from a start address of the first row.The destination bit-matrix operand field represents a destination bit-matrix operand 421 which stores the result of the bit-matrix multiplication operation. As previously stated, this operand 421 may be stored in a register (e.g., 512-bit register), collection of registers, or locations in memory.As shown, execution circuitry 411 includes multiple multiplication arrays 413 and multiple adder arrays 415. The immediate operand of the instruction is used to select a type of multiplication array 413 and a type of adder array 415. For example, in some embodiments, bits 4:7 of an 8-bit immediate operand are used by the multiplication selector 417 to select the multiplication circuitry from the plurality of multiplication arrays 413. For example, imm8[4:7] selects from the circuits XOR, AND, OR, NOR, NAND, and XNOR for multiplication. In some embodiments, bits 0:3 of an 8-bit immediate operand are used by the adder selector 419 to select the multiplication circuitry from the plurality of adder arrays 415. For example, imm8[0:3] selects from the circuits XOR, AND, OR, NOR and XNOR for addition. Any particular arrangement may be used to signal the selection, but an example table of selections is given below:TABLE 4 TABLE 40000XOR0000XOR0001AND0001AND0010OR0010OR0011NOR0011NOR0100XNOR0100XNOR01010101NANDThe plot shows two positions of the calculated result (TARGET[0] and TARGET

[25] ). TARGET[0] is calculated as follows: TARGET[0*7 + 0] = MEM[0*64+0]⊗QUELLE[0*8 + 0] ≅ MEM[0*64+1]⊗QUELLE[1*8 + 0] ≅... ≅ MEM[0*64+63]⊗QUELLE[63*8 + 0]. TARGET

[25] is calculated as follows: TARGET[3*7+ 4] = MEM[3*64+0]@QUELLE[0*8 + 4] ≅ MEM[3*64+1]⊗QUELLE[1*8 + 4] ≅... ≅ MEM[3*64+63]@QUELLE[63*8 + 4].Additionally, in some embodiments, the multiplication and / or addition operations may be logical (AND / OR / XOR / XNOR / NAND), or arithmetic (add, subtract, multiply) with and without saturation. This may result in a variety of definitions, some of which may be selected and implemented with the immediate operands as selectors. Therefore, some operations may not be simply AND / NAND / etc., but are table-based. For example, 2 bits may be interpreted as being 0.1,2,3 or -0,1,-2,-1, or as being 0.1,invalid,-1. -1+ -1 may be -1 when saturation is active and -2 when not. 1+1 may be 1 if it is unsigned 2 bits (-1,0,1,no 2). These tables may be predefined and the immediate operand selects one of such tables. AND / NANDs are only specific cases and may also be implemented as tables. The following Tables 5 and 6 provide examples of tables for immediate operands. TABLE 5 TABLE 52-bit0000000011111110-2N.A. (-1)-22211-1-1-1334-Bit0000000000001111110010222220011333330100444440101555550110666660111777771000-8N.A. (-7)-8881001-7-7-7991010-6-6-610101011-5-5-511111100-4-4-412121101-3-3-313131110-2-2-214141111-1-1-11515FIG. 5 illustrates one embodiment of hardware for processing an instruction, such as a BMM instruction. As shown, the memory 503 stores a BMM command 501 to be executed.Instruction 501 is received by decode circuitry 505. For example, decode circuitry 505 receives this instruction from fetch logic / circuitry. The instruction includes fields for an opcode, first and second bit matrix sources, a destination, and a immediate operand. In some embodiments, the sources and destination are registers, and in other embodiments, they are one or more memory locations.More detailed embodiments of at least one instruction format will be described in detail later. The decode circuitry 505 decodes the instruction into one or more operations. In some embodiments, this decoding includes generating multiple micro-operations to be performed by execution circuitry (such as execution circuitry 509). Decoding circuitry 505 also decodes instruction prefixes.In some embodiments, register rename, register allocator and / or scheduler circuit 507 provides functionality for one or more of: 1) rename logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) allocator status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution at the execution circuitry from an instruction pool (e.g., using a reservation station in some embodiments).Registers (register file) and / or memory 508 store data as operands of the instruction for operation at execution circuitry 509. Exemplary register types include packed data registers, general purpose registers, and floating point registers.Execution circuitry 509 executes the decoded instruction. Execution of the decoded instruction causes the execution circuitry to perform a bit-matrix multiplication of the source bit-matrices, with the particular circuitry used in the multiplying and adding aspect being selected via the instruction.In some embodiments, the retirement / write back circuitry 511 enables the architecture of the destination register into the registers or memory 508 and retirements the instruction.One embodiment of a format for a BMM instruction is BMMOCODE TARGET, SOURCE1, SOURCE2, IMM. BMMOPID is the opcode of the instruction. Example opcode mnemonics are listed above. DESTINATION is a field indicating a destination bit matrix operand. SOURCE1 and SOURCE2 are one or more fields for source operand identifiers, such as a register, register block, and / or memory location. IMM is a field for a immediate (immediate) operand. In some embodiments, the operand fields are encoded using VVVV field 920, MOD R / M 940, and / or SIB 950.In some embodiments, BMM instructions are for operands having multiple bits (e.g., 2, 4, and 8 bits). In these embodiments, the opcode defines the bit size, row and column size of the sources to be used, and row and column size of the destination. The latter size is seen in the previous examples. For example, opcode mnemonic V[S]BMM[R1][C1=R2][C2] represents one approach to defining these elements. In this example, [S] indicates the bit size; R1, C1 define the row and column sizes of the first source bit array; C1, C2 define the row and column sizes of the second source bit array; and R1, C2 define the row and column sizes of the target bit array.Examples of these instructions and their functionality are described in detail below. In each of these examples, the immediate operand (imm8) is used as detailed above:V2BMM8x8x32 TARGET, SOURCE1, SOURCE2 / m512, imm8 - multiplying an 8×8-2-bit matrix (SOURCE1) by an 8×32-bit matrix (SOURCE2) and storing the result in an 8×32-bit target matrix (TARGET).V2BMM32x8x8 TARGET, SOURCE1, SOURCE2 / m512, imm8 - multiplying a 32×8-2-bit matrix (SOURCE1) by an 8×8-2-bit matrix (SOURCE2) and storing the result in a 32×8-2-bit target matrix (TARGET).V2BMM8x8x32 TARGET, SOURCE1, SOURCE2 / m512, imm8 - multiplying an 8×8-2-bit matrix (SOURCE1) by an 8×32-bit matrix (SOURCE2) and storing the result in an 8×32-bit target matrix (TARGET).V2BMM32x8x8 TARGET, SOURCE1, SOURCE2 / m512, imm8 - multiplying a 32×8-2-bit matrix (SOURCE1) by an 8×8-2-bit matrix (SOURCE2) and storing the result in an a32×8-2-bit target matrix (TARGET).V2BMM8x32x32 TARGET, SOURCE1, MEM, imm8 - multiplying an 8×32-bit matrix (SOURCE1) by a 32×32-bit matrix in memory (MEM) and storing the result in an 8×32-bit target matrix (TARGET).V2BMM32x32x8 TARGET, MEM, SOURCE2, imm8 - multiplying a 32×32-bit matrix in the memory (MEM) by a 32×8-2-bit matrix (SOURCE2) and storing the result in a 32×8-2-bit target matrix (TARGET).V4BMM8x8x16 TARGET, SOURCE1, SOURCE2 / m512, imm8 - multiplying an 8×8-4-bit matrix (SOURCE1) by an 8×16-4-bit matrix (SOURCE2) and storing the result in an 8×16-4-bit target matrix (TARGET).V4BMM16x8x8 TARGET, SOURCE1, SOURCE2 / m512, imm8 - multiplying a 16×8-4-bit matrix (SOURCE1) by an 8×8-4-bit matrix (SOURCE2) and storing the result in a 16×8-4-bit target matrix (TARGET).V4BMM8x16x16 TARGET, SOURCE1, MEM, imm8 - multiplying an 8×16-4-bit matrix (SOURCE1) by a 16×16-4-bit matrix in memory (MEM) and storing the result in an 8×16-4-bit target matrix (TARGET).V4BMM16x16x8 TARGET, MEM, SOURCE2, imm8 - multiplying a 16×16-4-bit matrix in the memory (MEM) by a 16×8-4-bit matrix (SOURCE2) and storing the result in a 16×8-4-bit target matrix (TARGET).In embodiments, encodings of the instruction include a memory addressing operand of the SIB (scale index basis) type that indirectly identifies multiple indexed destinations in memory (e.g., field QAA50). In one embodiment, an SIB-type memory operand may include encoding identifying a base address register. The contents of the base address register may represent a base address in memory from which the addresses of the particular destinations in memory are calculated. For example, the base address may be the address of the first position in a block of potential target positions for an extended vector instruction. In one embodiment, an SIB-type memory operand may include encoding identifying an index register. Each element of the index register may indicate an index or offset value usable to calculate from the base address an address of a respective destination within a block of potential destinations. In one embodiment, an SIB-type memory operand may include encoding indicating a scaling factor to apply to each index value when calculating a respective destination address. For example, if a scale factor value of four is encoded in the SIB-type memory operand, each index value obtained from an element of the index register may be multiplied by four and then added to the base address to calculate a destination address.In one embodiment, an SIB-type memory operand of the form vm32{x,y,z} may identify a vector array of memory operands specified using SIB memory addressing. In this example, the array of memory addresses is specified using a common base register, a constant scale factor, and a vector index register that contains individual elements, each of which is a 32-bit index value. The vector index register may be a 128-bit register (vm 32×) (e.g., XMM), a 256-bit register (vm 32y) (e.g., YMM), or a 512-bit register (vm 32z) (e.g., ZMM). In another embodiment, an SIB-type memory operand of the form vm64{x,y,z} may identify a vector array of memory operands specified using SIB memory addressing. In this example, the array of memory addresses is specified using a common base register, a constant scale factor, and a vector index register that contains individual elements, each of which is a 64-bit index value. The vector index register may be a 128-bit register (vm64x) (e.g., XMM), a 256-bit register (vm64y) (e.g., YMM), or a 512-bit register (vm64z) (e.g., ZMM).Exemplary Execution of BMM InstructionsFIG. 6 illustrates an embodiment of a method performed by a process for processing a BMM command.At 601, an instruction is fetched. For example, a BMM instruction is fetched. The BMM instruction includes fields for an opcode, first and second source bit-matrix operand identifiers, a destination bit-matrix operand identifier, and a immediate operand. In some embodiments, the instruction is fetched from an instruction cache. The opcode of the BMM instruction indicates the size of the matrices. In some embodiments, the opcode also indicates the bit sizes within the framework of the bit matrix multiplication.The fetched instruction is decoded at 603. For example, the fetched BMM instruction is decoded by a decoding circuit as described in detail herein.Data values associated with the identified source operands of the decode instruction are fetched at 605 and the decoded instruction is scheduled (as needed). For example, if an identified source operand is a memory operand, the data is retrieved from the specified memory location.At 607, the decoded instruction is executed by execution circuitry (hardware) as described in detail herein. In the BMM instruction, execution results in the execution circuitry performing a matrix multiplication of the identified first source bit matrix operand with the identified second source bit matrix operand and storing a result of the matrix multiplication in the identified destination bit matrix operand, wherein the immediate operand of the decoded instruction indicates the multiplication and addition circuitry to be used in the matrix multiplication.In some embodiments, the command is submitted or withdrawn at 609.FIG. 7 illustrates a more detailed description of execution of a BMM instruction. This is typically accomplished by execution circuitry such as that described in detail herein. In some embodiments, execution is performed according to a state machine executed in hardware.At 701, a type of multiplication circuitry array is selected based on the immediate operand. For example, the multiplication circuitry is selected from circuits such as XOR, AND, OR, NOR, NAND, and XNOR circuits.At 703, a type of addition circuitry array is selected based on the immediate operand. For example, the multiplication circuitry is selected from circuits such as XOR, AND, OR, NOR, and XNOR circuits.At 705, multiple operations are performed for each S-bit position of the identified destination operand. The "S" value is determined from the opcode and is a value of 1, 2, 4 or 8.At 707, a value from a bit position of a corresponding row in the identified first source bit matrix is multiplied by a value of a corresponding S-bit position of a corresponding column in the identified second source bit matrix. These multiplications are performed using the selected multiplication circuitry.At 709, each of the multiplications is accumulated (added together). These additions are made using the selected multiplication circuitry.At 711, a result of the accumulation is stored.The following details example instruction formats, architectures, and systems that may be used for the above detailed instructions. For example, an example pipeline supporting the instructions includes circuitry to perform the methods described in detail herein is detailed.Instruction SetsAn instruction set may include one or more instruction formats. A given instruction format may define various fields (number of bits, location of bits) for indicating, among other things, the operation to be performed (opcode) and the operand or operands on which the operation is to be performed, and / or other data field(s) (e.g., mask). Some instruction formats are further partitioned by defining instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the fields of the instruction format (the included fields are typically in the same order, but at least some have different bit positions because there are fewer fields included), and / or defined to have a given field that is interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for indicating the operation and operands. For example, an example ADD instruction has a specific opcode and instruction format that includes an opcode field to indicate that opcode and operand fields to select operands (source1 / destination and source2); and an occurrence of that ADD instruction in an instruction stream has specific contents in the operand fields that select specific operands. A set of SIMD extensions referred to as Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Advanced Vector Extensions (VEX) coding scheme have been edited and / or published (see, e.g., Intel ®64 and IA-32 Architectures Software Developer's Manual, September 2014; and see Intel ® Advanced Vector Extensions Programming Reference, October 2014).Example Instruction FormatsEmbodiments of the instruction or instructions described herein may be embodied in different formats. In addition, example systems, architectures, and pipelines are described in detail below. Embodiments of the instruction or instructions may be executed on such systems, architectures, and pipelines, but are not limited to those listed.Generic Vector Friendly Instruction FormatA vector friendly instruction format is an instruction format suitable for vector instructions (e.g., there are certain fields specific to vector operations). While embodiments are described in which both vector and scalar operations are supported by the vector friendly format, alternative embodiments only use vector operations in the vector friendly instruction format.FIGS. 8A-8B are block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof, according to embodiments of the invention; FIG. 8A is a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof, according to embodiments of the invention; while FIG. 8B is a block diagram illustrating generic vector friendly instruction format and class B instruction templates thereof, according to embodiments of the invention. In particular, a generic vector friendly instruction format 800 for which class A and class B instruction templates are defined, both of which include no memory access 805 instruction templates and memory access 820 instruction templates. The term "generic" in the context of the vector friendly instruction format refers to the instruction format not being bound to a specific instruction set.While embodiments of the invention are described in which the vector friendly instruction format supports: a 64-byte vector operand length (or size) with data element widths (or sizes) of 32 bits (4 bytes) or 64 bits (8 bytes) (and thus a 64-byte vector consists of either 16 elements in doubleword size or alternatively 8 elements in quadword size); a 64-byte vector operand length (or size) with data element widths (or sizes) of 16 bits (2 bytes) or 8 bits (1 byte); 32 byte vector operand length (or size) having data element widths (or sizes) of 32 bits (4 bytes), 64 bits (8 bytes), 16 bits (2 bytes) or 8 bits (1 byte); and 16 byte vector operand length (or size) having data element widths (or sizes) of 32 bits (4 bytes), 64 bits (8 bytes), 16 bits (2 bytes) or 8 bits (1 byte); alternative embodiments may support more, fewer and / or different vector operand sizes (e.g., 256 byte vector operands) having more, fewer or different data element widths (e.g., data element widths of 128 bits (16 bytes)).The class A instruction templates in FIG. 8A include: 1) within the no memory access instruction templates 805, an instruction template for a full round control type no memory access operation 810 and an instruction template for a data transform type no memory access operation 815 are shown; and 2) within the memory access instruction templates 820, a temporal memory access instruction template 825 and a non-temporal memory access instruction template 830 are shown. The class B instruction templates in FIG. 8B include: 1) within the no memory access instruction templates 805, an instruction template for a partial round-control type write mask control operation 812 and an instruction template for a vsize type write mask control operation 817 are shown; and 2) within the memory access instruction templates 820, an instruction template with write mask control with memory access 827 are shown.The generic vector friendly instruction format 800 includes the following fields, listed below in the order shown in Figs. 8A-8B.Format field 840 - a specific value (an instruction format identifier value) in this field uniquely identifies the vector friendly instruction format and therefore occurrences of instructions in the vector friendly instruction format in instruction streams. Therefore, this field is optional in the sense that it is not required for an instruction set having only the generic vector friendly instruction format.Basic Operation Field 842 - its content distinguishes the different basic operations.Register index field 844 - its content, directly or via address generation, indicates the locations of the source and destination operands, whether in registers or in memory. This includes a sufficient number of bits to select N registers from a PxQ register file (e.g., 32x512, 16x128, 32x1024, 64x1024). While in one embodiment N may be up to three sources and one destination register, alternative embodiments may support more or fewer sources and destination registers (e.g., may support up to two sources, with one of these sources also acting as the destination; may support up to three sources, with one of these sources also acting as the destination; may support up to two sources and one destination).Modifier field 846 - its content distinguishes occurrences of instructions in the generic vector instruction format that indicate memory access from those that do not; that is, between no memory access instruction templates 805 and memory access instruction templates 820. Memory access operations read and / or write to the memory hierarchy (in some cases, indicating the source and destination addresses using values in registers), while non-memory access operations do not (e.g., the source and destinations are registers). While in one embodiment this array also selects between three different ways to perform memory address computations, alternative embodiments may support more, fewer, or different ways to perform memory address computations.Auxiliary operation field 850 - distinguishes its content which of several different operations are to be performed in addition to the basic operation. This field is context specific. In one embodiment of the invention, this field is divided into a class field 868, an alpha field 852, and a beta field 854. The auxiliary operation field 850 allows common groups of operations to be performed in a single instruction rather than 2, 3 or 4 instructions.Scaling field 860 - its content allows the content of the index field to be scaled for memory address generation (e.g., for address generation using 2 Skalierung* index+base).Displacement field 862A- its content is used as part of memory address generation (e.g., for address generation using 2 Skalierung ∗ index + base + displacement).Displacement Factor field 862B (note that the position of displacement field 862A directly over displacement Factor field 862B indicates that one or the other is being used) - its content is used as part of address generation; indicates a displacement factor to be scaled by the size of a memory access (N) - where N is the number of bytes in the memory access (e.g., for address generation using 2 Skalierung* index + base + scaled displacement). Low order redundant bits are ignored and therefore the contents of the displacement factor field are multiplied by the total memory operand size (N) to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 874 (described later herein) and the data manipulation field 854C. The displacement field 862A and the displacement factor field 862B are optional in the sense that they are not used for the no memory access 805 instruction templates, and / or different embodiments may implement only one or none of the two.Data element width field 864 - its content distinguishes which of a number of data element widths is to be used (in some embodiments for all instructions; in other embodiments only for some of the instructions). This field is optional in the sense that it is not needed when supporting only one data element width and / or supporting data element widths using some aspects of opcodes.Write Mask Field 870 - controls its content, based on the data element position, whether that data element position in the destination vector operand reflects the result of the basic operation and auxiliary operation. Class A instruction templates support merge write masking, while class B instruction templates support both merge and nulling write masking. When merging, vector masks allow each set of elements in the target to be protected from updates during execution of any operation (indicated by the base operation and the auxiliary operation); in another embodiment, maintaining the old value of each element of the target where the associated mask bit has a 0. In contrast, when zeroing, vector masks allow any set of elements in the target to be zeroed during execution of any instruction (indicated by the base operation and the auxiliary operation); in one embodiment, an element of the target is set to 0 when the associated mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation to be performed (i.e. the range of elements being modified, from the first to the last); however, it is not necessary for the elements being modified to follow one another. Thus, the write mask field 870 partially allows vector operations, including load operation, stores, arithmetic, logic, etc. While embodiments of the invention are described in which the contents of the write mask field 870 selects one of a number of write mask registers that contains the write mask to be used (and thus the contents of the write mask field 870 indirectly identifies the masking to be performed), alternative embodiments instead or additionally allow the contents of the write mask field 870 to directly indicate the masking to be performed.Immediate field 872 - its content allows specification of an immediate. This field is optional in the sense that it is not present in a generic vector friendly format implementation that does not support direct execution and that it is not present in instructions that do not use direct execution.Class field 868 - its content distinguishes between different classes of instructions. Referring to Figures 8A-B, the contents of this field select between class A and class B instructions. In FIGS. 8A-B, rounded corner squares are used to indicate that a specific value is present in a field (e.g., class A 868A and class B 868B, respectively, for class field 868 in FIGS. 8A-B ).Class A Instruction TemplatesIn the case of the non-memory access class A instruction templates 805, the alpha field 852 is interpreted as an RS field 852A, whose content distinguishes which of the different auxiliary operation types are to be performed (e.g., round 852A.1 and data transform 852A.2 are indicated for the non-memory access round type operation 810 and the non-memory access data transform type operation 815, respectively), while the beta field 854 distinguishes which of the operations of the indicated type are to be performed. In the no memory access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement scale field 862B are not present.No Memory Access - Full Round Control Type Operation Instruction TemplatesIn the instruction template for the full round control type operation without memory access 810, the beta field 854 is interpreted as a round control field 854A whose content(s) provide static round. While in the described embodiments of the invention, the round control field 854A includes a suppress all floating point exceptions (SAE) field 856 and a round operation control field 858, alternative embodiments may support and encode these two concepts into the same field or have only one or the other of these concepts / fields (e.g., may have only the round operation control field 858).SAE field 856 - its content distinguishes whether or not reporting exception events should be disabled; if the content of SAE field 856 indicates that suppression is enabled, a given instruction does not report any type of floating point exception flags and does not indicate a floating point exception handler.Round operation control field 858 - distinguishes its content that is to be performed from a group of round operations (e.g., round up, round down, round direction zero, and round to the nearest round number). Thus, the round operation control field 858 allows the round mode to be changed on an instruction basis. In one embodiment of the invention, where a processor includes a control register for indicating the rounding modes, the contents of the round operation control field 850 overwrites this register value.No Memory Access - Data Transform Type Operation Instruction TemplatesIn the no memory access operation 815 command template, the beta field 854 is interpreted as a data transform field 854B, whose content distinguishes which of a number of data transformations is to be performed (e.g., no data transformation, merging, sending).In the case of a memory access class A instruction template 820, the alpha field 852 is interpreted as a clearing hint field 852B, whose content distinguishes which of the clearing hint is to be used (in FIG. 8A, temporal 852B.1 and non-temporal 852B.2 are indicated for the memory access temporal instruction template 825 and the memory access non-temporal instruction template 830, respectively), while the beta field 854 is interpreted as a data manipulation field 854C, whose content distinguishes which of a number of data manipulation operations (also known as primitives) are to be performed (e.g., no manipulation; sending; up-converting a source; and down-converting a destination). Memory access instruction templates 820 include scale field 860, and optionally, displacement field 862A or displacement scale field 862B.Vector store instructions perform vector load operations from and vector store operations in memory with conversion support. As with regular vector instructions, vector memory instructions transfer data element-by-element from / to memory, the elements that are actually transferred being determined by the contents of the vector mask selected as a write mask.Memory Access - Temporal Instruction TemplatesTemporal data is data that is likely to be reused soon enough to benefit from caching. However, this is an indication and different processors may implement this in different ways, including ignoring the indication completely.Memory Access - Non-Temporal - Instruction TemplatesNon-temporal data is data that is likely not to be reused soon enough to benefit from caching in the level 1 cache and should be given priority for clearing. However, this is an indication and different processors may implement this in different ways, including ignoring the indication completely.Class B Instruction TemplatesIn the case of the class B instruction templates, the alpha field 852 is interpreted as a write mask control field (Z) 852C, whose content distinguishes whether the write masking controlled by the write mask field 870 is to be merging or zeroing.In the case of the non-memory access class B instruction templates 805, a portion of the beta field 854 is interpreted as an RL field 857A, whose content distinguishes which of the different auxiliary operation types are to be performed (e.g., round 857A.1 and vector length (VSIZE) 857A.2 are respectively indicated for the partial non-memory access round control operation instruction template 812 and the non-memory access write mask control operation instruction template 817), while the remainder of the beta field 854 distinguishes which of the operations of the indicated type are to be performed. In the no memory access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement scale field 862B are not present.In the instruction template for partial round-control type no memory access write mask control operation 810, the rest of the beta field 854 is interpreted as a round operation field 859A, and reporting exception events is disabled (a given instruction does not report any type of floating point exception flag and does not indicate a floating point exception handler).Round operation control field (round operation) 859A-as with round operation control field 858 distinguishes its content to be performed from a group of round operations (e.g., round-up, round-down, round-down direction zero, and round-down to the nearest round number). Therefore, the round operation control field 859A allows the round mode to be changed on an instruction basis. In one embodiment of the invention, where a processor includes a control register for indicating the rounding modes, the contents of the round operation control field 850 overwrites this register value.In the instruction template of the VSIZE-type write mask control operation without memory access 817, the rest of the beta field 854 is interpreted as a vector length field 859B, the contents of which distinguishes which one of a number of data vector lengths is to be performed (e.g., 128, 256, or 512 bytes).In the case of a memory access class B instruction template 820, a portion of the beta field 854 is interpreted as a transmit field 857B, the contents of which discriminates whether or not the transmit type data manipulation operation is to be performed, while the remainder of the beta field 854 is interpreted as the vector length field 859B. Memory access instruction templates 820 include scale field 860, and optionally, displacement field 862A or displacement scale field 862B.With respect to the generic vector friendly instruction format 800, a full opcode field 874 is shown, including the format field 840, the base operation field 842, and the data element width field 864. While an embodiment is shown where full opcode field 874 includes all of these fields, full opcode field 874 includes less than all of these fields in embodiments that do not support all. The full opcode field 874 provides the opcode (opcode).The add-in operation field 850, the data element width field 864 and the write mask field 870 enable these features to be specified on an instruction-by-instruction basis in the generic vector friendly instruction format.The combination of write mask field and data element width field generates type commands in that they allow the mask to be applied based on different data element widths.The various instruction templates found in class A and class B are advantageous in different situations. In some embodiments of the invention, different processors or different cores may support only class A, only class B, or both classes. For example, a high performance universal out-of-order (out-of-order) core intended for universal computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core having some mix of templates and instructions from both classes, but not all templates and instructions from both classes, is within the scope of the invention). In addition, a single processor may include multiple cores, all of which support the same class or different cores of which support different classes. For example, in a processor with separate graphics and universal cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only class A, while one or more of the universal cores may be high performance universal cores with out-of-order (out-of-order) execution and register renaming intended for universal computing that support only class B. Another processor that does not have a separate graphics core may include one or more In-Order (In-Order) or Out-of-Order (Out-of-Order) cores that support both class A and class B. Of course, in various embodiments of the invention, features of one class may also be implemented in the other class. Programs written in a high level language would be brought into a variety of different executable forms (e.g., just-in-time compiled or statically compiled) including: 1) a form having only class(s) instructions supported for execution by the target processor; or 2) a form having alternative routines written using different combinations of all classes and having control flow code that selects the routines to be executed based on the instructions supported by the processor currently executing the code.Example Specific Vector Friendly Instruction FormatFIG. 9A is a block diagram illustrating an example specific vector friendly instruction format according to embodiments of the invention; FIG. 9A illustrates a specific vector friendly instruction format 900 that is specific in the sense that it indicates the location, size, interpretation, and order of the fields, as well as values for some of these fields. The specific vector friendly instruction format 900 may be used to expand the x86 instruction set, and thus some of the fields are similar to or the same as those used in the existing x86 instruction set and extensions thereof (e.g., AVX). This format remains consistent with the prefix encoding field, the real opcode byte field, the MOD R / M field, the SIB field, the displacement field, and the immediate execution field of the existing x86 instruction set with extensions. The fields of Fig. 8 into which the fields of Fig. 9A are mapped are shown.It should be understood that although embodiments of the invention are described for purposes of illustration with reference to the specific vector friendly instruction format 900 in the context of the generic vector friendly instruction format 800, the invention is not limited to the specific vector friendly instruction format 900 except where claimed. For example, the generic vector friendly instruction format 800 takes into account a variety of possible sizes for the various fields, while the specific vector friendly instruction format 900 is shown as having fields with specific sizes. As a specific example, while the data element width field 864 is depicted as a one bit field in the specific vector friendly instruction format 900, the invention is not so limited (i.e., the generic vector friendly instruction format 800 contemplates other sizes for the data element width field 864).The generic vector friendly instruction format 800 includes the following fields, listed below in the order shown in FIG. 9A.EVEX prefix (bytes 0-3) 902- is encoded in a four byte form.Format field 840 (EVEX byte 0, bits [7:0]) - the first byte (EVEX byte 0) is the format field 840 and it contains 0x62 (the unique value used to distinguish the vector friendly instruction in one embodiment of the invention).The second through fourth bytes (EVEX bytes 1-3) comprise a number of bit fields that provide specific capability.REX field 905 (EVEX byte 1, bits [7-5]) - consists of an EVEX.R bit field (EVEX byte 1, bit [7] - R), an EVEX.X bit field (EVEX byte 1, bit [6] - X) and a 857BEX byte 1, bit [5] - B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the associated VEX bit fields and are encoded using the one's complement form, i.e., ZMM0 is encoded as 1111B, ZMM15 is encoded as 0000B. Other fields of the instructions encode the lower three bits of the register indicia as is known in the art (rrr, xxx, and bbb) so that Rrrr, Xxxx, and Bbbb may be formed by adding EVEX.R, EVEX.X, and EVEX.B.REX' field 810 - this is the first part of REX' field 810 and is the EVEX.R' bit field (EVEX byte 1, bit [4]-R') used to encode either the upper 16 or the lower 16 of the extended 32 register set. In one embodiment of the invention, this bit, along with others as indicated below, is stored in bit inverted format to distinguish (in well known x86 32-bit mode) from the BOUND instruction whose real opcode byte is 62, but does not accept in the MOD R / M field (described below) the value of 11 in the MOD field; alternative embodiments of the invention do not store this and the other bits indicated below in inverted format. A value of 1 is used to encode the lower 16 registers. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R, and the other RRR from other fields.Opcode map field 915 (EVEX byte 1, bits [3:0] - mmmm) - its content encodes an implied leading opcode byte (0F, 0F 38, or 0F 3).Data element width field 864 (EVEX byte 2, bit [7] - W) - is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the data type (either 32-bit data elements or 64-bit data elements).EVEX.vvvv 920 (EVEX byte 2, bits [6:3]-vvvv) - the role of EVEX.vvvv may comprise: 1) EVEX.vvvv encodes the first source register operand specified in inverted form (one's complement) and is valid for instructions having 2 or more source operands; 2) EVEX.vvvv encodes the destination register operand specified in one's complement form for certain vector offsets; or 3) EVEX.vvvv does not encode an operand, the field is reserved and should contain 1111b. Thus, EVEX.vvvv field 920 encodes the low order 4 bits of the first source register specifier stored in inverted form (one's complement). Depending on the instruction, an additional different EVEX bit field is used to expand the specifier size to 32 registers.EVEX.U class field 868 (EVEX byte 2, bit [2]-U) - If EVEX.U = 0, this indicates class A or EVEX.U0; if EVEX.U = 1, this indicates class B or EVEX.U1.Prefix encoding field 925 (EVEX byte 2, bits [1:0]-pp) provides additional bits for the base operation field. In addition to providing support for legacy SSE instructions in the EVEX prefix format, this also has the advantage of compacting the SIMD prefix (rather than requiring a byte to express the SIMD prefix, the EVEX prefix requires only 2 bits). In one embodiment, to support the legacy SSE instructions that use a SIMD prefix (66H, F2H, F3H) in both the legacy and EVEX prefix formats, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field and are extended into the legacy SIMD prefix at runtime before being provided to the decoder's PLA (so that the PLA can execute both the legacy and EVEX formats of these legacy instructions without modifications). Although newer instructions may use the contents of the EVEX prefix encoding field directly as an opcode extension, certain embodiments extend in a similar manner for consistency purposes, but allow different meanings to be indicated by these legacy SIMD prefixes. An alternative embodiment may re-design the PLA to support the 2-bit SIMD prefix encodings and therefore do not require the extension.Alpha field 852 (EVEX byte 3, bit [7] - EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control (write mask control) and EVEX.N; also shown as a) - as previously described, this field is context specific.Beta field 854 (EVEX byte 3, bits [6:4]-SSS, also known as EVEX.s 2-0, EVEX.r 2-0, EVEX.rr1, EVEX.LL0, EVEX.LLB; also represented by ββββ) -- as previously described, this field is context specific.REX' field 810 - this is the remainder of the REX' field and is the EVEX.V' bit field (EVEX byte 3, bit [3]-V') that can be used to encode either the upper 16 or the lower 16 of the extended 32 register set. This bit is stored in bit inverted format. A value of 1 is used to encode the lower 16 registers. In other words, V'VVVV is formed by combining EVEX.V', EVEX.vvvv.Write mask field 870 (EVEX byte 3, bits [2:0]-kkk) - its contents indicate the index of a register in the write mask registers as previously described. In one embodiment of the invention, the specific value EVEX.kkk=000 has a special behavior, implying that no write mask is used for the particular instruction (this can be implemented in various ways, including using a write mask, hard wired to all, or hardware bypassing the masking hardware).The real opcode field 930 (byte 4) is also known as the opcode byte. A portion of the opcode is specified in this field.MOD R / M field 940 (byte 5) includes MOD field 942, Reg field 944, and R / M field 946. As described above, the contents of the MOD field 942 distinguish between memory access and no memory access operations. The role of Reg field 944 may be summarized for two situations: encoding either the destination register operand or a source register operand, or treated as an opcode extension and not used to encode an instruction operand. The role of R / M field 946 may include: encoding the instruction operand that relates to a memory address, or encoding either the destination register operand or a source register operand.Scale Index Base (SIB) byte (byte 6) - As described above, the contents of the scale field 850 are used for memory address generation. SIB.xxx 954 and SIB.bbb 956 - the contents of these fields have been previously referred to in connection with the register indexes Xxxx and Bbbb.Displacement field 862A (bytes 7-10) - when MOD field 942 includes a 10, bytes 7-10 are displacement field 862A and functions exactly as the older 32-bit displacement (disp32) and operates at byte granularity.Displacement Factor field 862B (byte 7) - if MOD field 942 contains a 01, byte 7 is the displacement Factor field 862B. The location of this field is the same as that of the older 8-bit shift (disp8) in the x86 instruction set, which operates with byte granularity. Since disp8 is sign extended, it can only address offsets between -128 and 127 bytes; in conjunction with 64-byte cache lines, disp8 uses eight (8) bits which can be set to only four truly reasonable values -128, -64, 0, and 64; since a larger range is often needed, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 862B is a reinterpretation of disp8; using displacement factor field 862B, the actual displacement is determined by the contents of the displacement factor field multiplied by the size of the memory operand access (N). This type of shift is referred to as disp8*N. This reduces the average instruction length (a single byte is used for the shift, but with a much larger area). Such a compressed shift is based on the assumption that the effective shift is a multiple of the granularity of the memory access and that therefore the lower order redundant bits of the address offset need not be encoded. In other words, the displacement factor field 862B replaces the 8-bit displacement of the legacy x86 instruction set. Therefore, the displacement factor field 862B is encoded in the same manner as an 8-bit displacement of the x86 instruction set (i.e., no changes in the ModRM / SIB encoding rules), with the only exception that disp8 is overcharged to disp8*N. In other words, there are no changes in the encoding rules or lengths, but only in interpreting the offset value by hardware (which must scale the offset by the size of the memory operand to obtain a bytewise address offset). Immediate operand field 872 operates as previously described.Full opcode fieldFIG. 9B is a block diagram illustrating fields of the specific vector friendly instruction format 900 forming the full opcode field 874 according to an embodiment of the invention. In particular, the full opcode field 874 includes the format field 840, the base operation field 842, and the data element width field (W) 864. The base operation field 842 includes the prefix encoding field 925, opcode map field 915, and real opcode field 930.Register Index fieldFIG. 9C is a block diagram illustrating fields of the specific vector friendly instruction format 900 forming the register index field 844, according to an embodiment of the invention. In particular, register index field 844 includes REX field 905, REX' field 910, MODR / M.reg field 944, MODR / M.r / m field 946, VVVV field 920, xxx field 954, and bbb field 956.Add-in Operation fieldFIG. 9D is a block diagram illustrating fields of the specific vector friendly instruction format 900 forming the auxiliary operation field 850, according to an embodiment of the invention. If class field (U) 868 contains a 0, this means EVEX.UO (class A 868A); if it contains a 1, this means EVEX.U1 (class B 868B). If U=0 and MOD field 942 contains an 11 (significant no memory access operation), alpha field 852 (EVEX byte 3, bit [7] - EH) is interpreted as rs field 852A. If rs field 852A contains a 1 (round 852A.1), beta field 854 (EVEX byte 3, bits [6:4]-SSS) is interpreted as round control field 854A. The round control field 854A includes a one-bit SAE field 856 and a two-bit round operation field 858. If rs field 852A contains a 0 (data transform 852A.2), beta field 854 (EVEX byte 3, bits [6:4]-SSS) is interpreted as the three bit data transform field 854B. If U=0 and MOD field 942 contains 00, 01 or 10 (significant memory access operation), alpha field 852 (EVEX byte 3, bit [7] - EH) is interpreted as clearing hint field (EH, Evecition Hint) 852B, and beta field 854 (EVEX byte 3, bits [6:4] - SSS) is interpreted as a three bit data manipulation field 854C.If U=1, the alpha field 852 (EVEX byte 3, bit [7] - EH) is interpreted as the write mask control field (Z) 852C. If U=1 and MOD field 942 contains an 11 (significant no memory access operation), a portion of beta field 854 (EVEX byte 3, bit [4]-S 0) is interpreted as RL field 857A; If it contains a 1 (round 857A.1), the rest of the beta field 854 (EVEX byte 3, bit [6-5]-S 2-1) is interpreted as the round operation field 859A, while if the RL field 857A contains a 0 (VSIZE 857.A2), the rest of the beta field 854 (EVEX byte 3, bit [6-5]-S 2-1) is interpreted as the vector length field 859B (EVEX byte 3, bit [6-5]-L 1-0). If U=1 and MOD field 942 contains 00, 01 or 10 (significant memory access operation), beta field 854 (EVEX byte 3, bits [6:4]-SSS) is interpreted as vector length field 859B (EVEX byte 3, bit [6-5]-L 1-0) and transmit field 857B (EVEX byte 3, bit [4]-B).Example Register ArchitectureFIG. 10 is a block diagram of a register architecture 1000, according to an embodiment of the invention. In the illustrated embodiment, there are 32 vector registers 1010 that are 512 bits wide; these registers are referred to as zmm0 through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format 900 operates on this overlaid register file as shown in the following tables.Instruction Templates Not Comprising Vector Length Field 859BA (8A; U=0)810, 815, 825, 830zmm registers (vector length is 64 bytes)B (8B; U=1)812zmm registers (vector length is 64 bytes)Instruction Templates Comprising Vector Length Field 859BB (8B; U=1)817, 827zmm, ymm or xmm registers (vector length is 64 bytes, 32 bytes or 16 bytes) depending on the vector length field 859BIn other words, vector length field 859B selects between a maximum length and one or more other shorter lengths, each of such shorter lengths being half the length of the previous length, and instruction templates without vector length field 859B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format 900 operate on single / double precision packed or scalar floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in a zmm / ymm / xmm register; the higher order data element positions are either left as they were before the instruction or zeroed, depending on the embodiment.Write mask registers 1015 - in the illustrated embodiment, there are 8 write mask registers (k0 to k7) each having a size of 64 bits. In an alternative embodiment, write mask registers 1015 are 16-bit in size. As described above, in one embodiment of the invention, vector mask register k0 cannot be used as a write mask; when the encoding that would normally indicate k0 is used for a write mask, it selects a hardwired write mask 0xFFFF, thereby effectively disabling write masking for that instruction.General purpose registers 1025 - in the illustrated embodiment, there are sixteen general purpose 64-bit registers that are used along with the existing x86 addressing modes to address memory operands. These registers are labeled RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.The scalar floating point stack (x87) register file 1045, which is used as alias for the packed integer flat MMX register file 1050-in the illustrated embodiment, the x87 stack is an eight element stack used to perform scalar floating point operations on 32 / 64 / 80 bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64 bit packed integer data as well as to hold operands for some operations performed between the MMX and XMM registers.Alternative embodiments of the invention may use more or narrower registers. In addition, alternative embodiments of the invention may use more, fewer, or different register files and registers.Example Core Architectures, Processors, and Computer ArchitecturesProcessor cores may be implemented in various ways, for various purposes, and in different processors. For example, implementations of such cores may include: 1) a universal in-order (in-order) core intended for universal computing; 2) a universal out-of-order (high-performance) core intended for universal computing; 3) a special core primarily intended for graphics and / or scientific (throughput) computation. Implementations of different processors may include: 1) a CPU, one or more general purpose in-order (in-order) cores intended for general purpose computing including and / or one or more general purpose out-of-order (out-of-order) cores intended for general purpose computing; and 2) a coprocessor, including one or more special purpose cores primarily intended for graphics and / or science (throughput). Such different processors result in different computer system architectures that may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same die as a CPU; 3) the coprocessor on the same die as a CPU (in this case, such coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and / or scientific (throughput) logic, or special purpose cores); and 4) a system on a die that may include, on the same die, the described CPU (sometimes referred to as the application core or processors), the coprocessor described above, and additional functionality. Example core architectures are described next, followed by descriptions of example processors and computer architectures.Example Core ArchitecturesBlock Diagram of True Order (In-Order) and Out-of-Order (Out-of-Order) CoreFIG. 11A is a block diagram illustrating both an example in-order (out-of-order) pipeline and an example out-of-order (out-of-order) register rename issue / execution pipeline, in accordance with embodiments of the invention. FIG. 11B is a block diagram illustrating both an example embodiment of a high-level architectural core and an example level register rename output / execution architectural core to be included in a processor, in accordance with embodiments of the invention. The solid line fields in FIGS. 11A-B represent the high-order pipeline and the high-order core, while the optional addition of dashed line fields represents the out / execution register renamed array(s). In view of the fact that the true-of-order (in-order) aspect is a subset of the out-of-order (out-of-order) aspect, the ordered aspect will be described.In FIG. 11A, a processor pipeline 1100 includes a fetch stage 1102, a length decode stage 1104, a decode stage 1106, an allocation stage 1108, a renaming stage 1110, a scheduling (also known as a dispatch or issue) stage 1112, a register read / memory read stage 1114, an execute stage 1116, a write back / memory write stage 1118, an exception handling stage 1122, and a commit stage 1124.FIG. 11B shows processor core 1190 including a front end unit 1130 coupled to an execution engine unit 1150, and both are coupled to a memory unit 1170. The core 1190 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 1190 may be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) computing core, a graphics core, or the like.The front end unit 1130 includes a branch prediction unit 1132 coupled to an instruction cache unit 1134 coupled to an instruction translation lookaside buffer (TLB) 1136, coupled to an instruction fetch unit 1138, coupled to a decode unit 1140. The decode unit 1140 (or decoder) may decode instructions and generate as an output one(s) or more micro-operations, micro-code entry points, microinstructions, or other instructions, or other control signals, that have been decoded from or otherwise reflect or are otherwise derived from the original instructions. The decoding unit 1140 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), Read Only Memories (ROMs), etc. In one embodiment, the core 1190 includes a microcode ROM or other medium that stores microcode for certain microinstruction (e.g., in decode unit 1140 or otherwise within the front end unit 1130). Decode unit 1140 is coupled to rename / allocator unit 1152 in execution engine unit 1150.Execution engine 1150 includes rename / allocator 1152 coupled to a retirement unit 1154 and a set of one or more scheduler units 1156. Scheduler unit(s) 1156 represents any number of different scheduler units, including reservation stations, central instruction window, etc. Scheduler unit(s) 1156 is coupled to physical register file units 1158. Each of the physical register file(s) units 1158 represents one or more physical register files, different ones of which store one or more different types of data, such as scalar integers, scalar floating point numbers, packed integers, packed floating point numbers, vector integers, vector floating point numbers, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit 1158 includes a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) register file(s) unit(s) 1158 are overlapped by the retirement unit 1154 to represent various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer and a retirement register file; using a future file, a history buffer, and a retirement register file; using a register map and a collection of registers, etc.). The retirement unit 1154 and physical register file(s) unit(s) 1158 are coupled to the execution cluster 1160. The execution cluster 1160 includes a set of one or more execution units 1162 and a set of one or more memory access units 1164. The execution units 1162 may perform various operations (e.g., shifts, addition, subtraction, multiplication) on various types of data (e.g., scalar floating point data, packed integer data, packed floating point data, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated specifically to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) 1156 physical register file(s) unit(s) 1158, and the execution cluster(s) 1160 are shown as possibly multiple, as certain embodiments generate separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each having its own scheduler(s)(s), physical register file(s) unit, and / or execution clusters - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of that pipeline has the memory access unit(s) 1164). It will also be appreciated that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution pipelines and the remaining in-order pipelines.The set of memory access units 1164 is coupled to the memory unit 1170, which includes a data TLB unit 1172 coupled to a data cache unit 1174 coupled to a level 2 cache unit (L2) 1176. In an example embodiment, memory access units 1164 may include a load unit, a memory address unit, and a memory data unit, each coupled to data TLB unit 1172 in memory unit 1170. The instruction cache unit 1134 is further coupled to a level 2 cache unit (L2) 1176 in the memory unit 1170. The L2 cache unit 1176 is coupled to one or more other levels of cache and eventually to main memory.As an example, the example register renamed out-of-order / execution core architecture may implement pipeline 1100 as follows: 1) instruction fetch 1138 performs fetch and length decode stages 1102 and 1104; 2) decode unit 1140 performs decode stage 1106; 3) rename / allocator unit 1152 performs allocator stage 1108 and rename stage 1110; 4) sequencer unit(s) 1156 performs sequencer stage 1112; 5) physical register file(s) unit(s) 1158 and memory unit 1170 performs register read / memory read stage 1114; execution cluster 1160 performs execution stage 1116; In addition, FIG. 6 ) the memory unit 1170 and physical register file(s) unit(s) 1158 perform the write back / memory write stage 1118; 7) various units may be involved in the exception handling stage 1122; and 8) the retirement unit 1154 and physical register file(s) unit(s) 1158 perform the commit stage 1124.The core 1190 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added to newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA), including the instructions described herein. In one embodiment, core 1190 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2) by enabling operations used by many multimedia applications to be performed on packed data.It should be appreciated that the core may support multi-threading (or multi-threading, executing two or more parallel sets of operations or threads), and may do so in a variety of ways, including time slicing multi-threading, simultaneous multi-threading (where a single physical core provides a logical core for each of the threads that the physical core simultaneously handles multi-threading), or a combination thereof (e.g., time slicing fetch and decode and simultaneous multi-threading thereafter, such as in Intel ® Hyper-threading technology).While register renaming is described in the context of out-of-order (out-of-order) execution, it should be appreciated that register renaming may be used in an in-order (in-order) architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units 1134 / 1174 and a shared L2 cache unit 1176, alternative embodiments may have a single internal cache for instructions and data, such as, for example, a level 1 internal cache (L1) or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache external to the core and / or the processor. Alternatively, the entire cache may be external to the core and / or the processor.Specific Example In-Order (Core) ArchitectureFIGS. 12A-B illustrate a block diagram of a more specific example in-order (in-order) core architecture, the core of which would be one of multiple logic blocks (including other cores of the same type and / or other types) in a chip; the logic blocks communicate via a high bandwidth interconnect network (e.g., a ring network) with some fixed function logics, memory I / O interfaces, and other necessary I / O logics, depending on the application.FIG. 12A is a block diagram of a single processor core, along with its connection to the on-die interconnect network 1202 and with its local subset of the level 2 cache (L2) 1204, in accordance with embodiments of the invention. In one embodiment, an instruction decoder 1200 supports the x86 instruction set with a packed data instruction set extension. An L1 cache 1206 allows low latency accesses to a cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit 1208 and a vector unit 1210 use separate register sets (respectively, scalar registers 1212 and vector registers 1214) and data transferred between them is written to memory and then read back from a level 1 cache (L1) 1206, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allows data to be transferred between the two register files without being written and read back).The local subset of the L2 cache 1204 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 1204. Data read by a processor core is stored in its L2 cache subset 1204 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 1204 and is flushed from other subsets, if necessary. The ring network ensures coherence of the shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012bit wide per direction.FIG. 12B is an expanded view of a portion of the processor core in FIG. 12A, in accordance with embodiments of the invention. FIG. 12B includes an L1 data cache 1206A as part of the L1 cache 1204, as well as further details regarding the vector unit 1210 and the vector registers 1214. In particular, vector unit 1210 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 1228) that executes one or more integer instructions, single-precision floating point instructions, and double-precision floating point instructions. The VPU supports merging of the register inputs with merging unit 1220, numerical conversion with numerical conversion units 1222A-B, and replication with replication unit 1224 on the memory input. Write mask registers 1226 allow prediction of resulting vector writes.FIG. 13 is a block diagram of a processor 1300 that may have more than one core that may have an integrated memory controller and may have integrated graphics, according to embodiments of the invention; the solid line fields in FIG. 13 represent a processor 1300 having a single core 1302A, a system agent 1310, and a set of one or more bus controller units 1316, while the optional addition of dashed line fields represents an alternative processor 1300 having multiple cores 1302A-N, a set of one or more integrated memory controller units 1314 in the system agent unit 1310, and special purpose logic 1308.Thus, various implementations of the processor 1300 may include: 1) a CPU, wherein the special purpose logic 1308 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and wherein the cores 1302A-N are one or more universal cores (e.g., universal ordering (in-order) cores, universal ordering (out-of-order) cores, a combination of the two); 2) a coprocessor, wherein the cores 1302A-N are a large number of special cores, primarily intended for graphics and / or scientific (throughput) computing; and 3) a coprocessor, wherein the cores 1302A-N are a large number of universal ordering (in-order) cores. Thus, the processor 1300 may be a general purpose processor, coprocessor, or special purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, general purpose graphics processing unit (GPGPU), high-throughput many integrated core (MIC) coprocessor (comprising 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 1300 may be a portion of and / or may be implemented on one or more substrates using any number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.The memory hierarchy includes one or more levels of cache within the cores, a set of one or more shared cache units 1306, and external memory (not shown) coupled to the set of integrated memory controller units 1314. The set of shared cache units 1306 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof. While in one embodiment a ring-based interconnect unit 1312 interconnects the integrated graphics logic 1308 (integrated graphics logic 1308 is an example of and is referred to herein as special purpose logic), the set of shared cache units 1306, and the system agent unit 1310 / integrated memory controller unit(s) 1314, alternative embodiments may use any number of well known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units 1306 and cores 1302-A-N.In some embodiments, one or more of cores 1302A-N are capable of multi-threading. System agent 1310 includes those components that coordinate and operate cores 1302A-N. The system agent unit 1310 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed to regulate the power state of the cores 1302A-N and the integrated graphics logic 1308. The display unit is for driving one or more externally connected displays.Cores 1302A-N may be homogeneous or heterogeneous with respect to the architectural instruction set; that is, two or more of cores 1302A-N may be capable of executing the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.Example Computer ArchitecturesFIGS. 14-17 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network nodes, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, mobile phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a vast variety of systems or electronic devices capable of incorporating a processor and / or other execution logic as disclosed herein are generally suitable.Referring now to FIG. 14, shown is a block diagram of a system 1400 in accordance with an embodiment of the present invention. The system 1400 may include one or more processors 1410, 1415 coupled to a control node 1420. In one embodiment, control node 1420 includes a graphics memory controller hub (GMCH) 1490 and an input / output hub (IOH) 1450 (which may be located on separate chips); GMCH 1490 includes memory and graphics controllers to which memory 1440 and a coprocessor 1445 are coupled; IOH 1450 couples input / output devices (I / O) 1460 to GMCH 1490. Alternatively, the memory and / or graphics controller are integrated into the processor (as described herein), the memory 1440 and the coprocessor 1445 are directly coupled to the processor 1410, and the control node 1420 is integrated into a single chip with the IOH 1450.The optional nature of the additional processors 1415 is indicated by broken lines in Figure 14. Each processor 1410, 1415 may include one or more of the processing cores described herein and may be a version of the processor 1300.The memory 1440 may be, for example, a dynamic random access memory (DRAM), a phase change memory (PCM), or a combination of the two. In at least one embodiment, control node 1420 communicates with processors 1410, 1415 via a multi-drop bus, such as a front-side bus (FSB), a point-to-point interface, such as QuickPath Interconnect (QPI), or similar connection 1495.In one embodiment, coprocessor 1445 is a dedicated processor such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like. In one embodiment, the control node 1420 may include an integrated graphics accelerator.There may be a variety of differences between the physical resources 1410, 1415 with respect to a spectrum of relevant metrics, including architectural, microarchitectural, thermal, power consumption characteristics, and the like.In one embodiment, processor 1410 executes instructions that control data processing operations of a general type. Embedded in the instructions may be coprocessor instructions. Processor 1410 recognizes that these coprocessor instructions are of a type to be executed by referenced coprocessor 1445. Accordingly, processor 1410 outputs these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other connection to coprocessor 1445. One or more coprocessors 1445 accept and execute the received coprocessor instructions.Referring now to FIG. 15, shown is a block diagram of a first more specific system 1500 in accordance with an embodiment of the present invention. As shown in FIG. 15, multiprocessor system 1500 is a point-to-point interconnect system and includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. Each of the processors 1570 and 1580 may be a version of the processor 1300. In one embodiment of the invention, processors 1570 and 1580 are processors 1410 and 1415 respectively, while coprocessor 1538 is coprocessor 1445. In another embodiment, processors 1570 and 1580 are processor 1410 and coprocessor 1445, respectively.Processors 1570 and 1580 are shown including integrated memory controllers (IMC) 1572 and 1582, respectively. Processor 1570 also includes as part of its bus control units point-to-point (P-P) interfaces 1576 and 1578; similarly, second processor 1580 includes P-P interfaces 1586 and 1588. Processors 1570, 1580 may exchange information via a point-to-point (P-P) interface 1550 using P-P interface circuits 1578, 1588. As shown in FIG. 15, IMCs 1572 and 1582 couple the processors to respective memories, particularly a memory 1532 and a memory 1534, which may be portions of main memory locally coupled to the respective processors.Processors 1570, 1580, may also each exchange information with a chipset 1590 via individual P-P interfaces 1552, 1554 using point-to-point interface circuits 1576, 1594, 1586, 1598. Chipset 1590 may optionally exchange information with coprocessor 1538 via high performance interface 1592. In one embodiment, coprocessor 1538 is a dedicated processor such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.A shared cache (not shown) may be included in either processor or outside both processors; however, it may be connected to the processors via a P-P interconnect, such that local cache information of either or both processors may be stored in the shared cache when a processor is placed in a low power mode.Chipset 1590 may be coupled to a first bus 1516 via an interface 1596. In one embodiment, the first bus 1516 may be a peripheral component interconnect (PCI) bus or a bus such as a PCI Express bus or another third generation I / O interconnect bus, although the scope of the present invention is not so limited.As shown in FIG. 15, various I / O devices 1514 may be coupled to first bus 1516, along with a bus bridge 1518 that couples first bus 1516 to a second bus 1520. In one embodiment, one or more additional processors 1515, such as coprocessors, high-throughput MIC processors, GPGPUs, accelerators (such as, e.g., graphics accelerators or digital signal processing units (DSPs)), field programmable gate arrays, or any other processor, are coupled to first bus 1516. In one embodiment, the second bus 1520 may be a low pin count (LPC) bus. Various devices may be coupled to a second bus 1520 including, for example, a keyboard and / or mouse 1522, communication devices 1527, and a storage unit 1528 such as a disk drive or other mass storage device, which, in one embodiment, may include instructions / code and data 1530. Further, an audio I / O 1524 may be coupled to the second bus 1520. It should be noted that other architectures are possible. For example, instead of the point-to-point architecture of FIG. 15, a system may implement a multi-drop bus or other such architecture.Referring now to FIG. 16, shown is a block diagram of a second more specific system 1600 in accordance with an embodiment of the present invention. Similar elements in FIGS. 15 and 16 bear similar reference numerals, and certain aspects of FIG. 15 have been omitted from FIG. 16 to prevent turbidity from other aspects of FIG. 16.FIG. 16 illustrates that processors 1570, 1580 may include integrated memory and control logic ("CL") 1572, 1582, respectively. Thus, CL 1572, 1582 includes integrated memory controller units and includes I / O control logic. FIG. 16 illustrates that not only are the memories 1532, 1534 coupled to the CL 1572, 1582, but also I / O devices 1614 are also coupled to the control logic 1572, 1582. Legacy I / O devices 1615 are coupled to chipset 1590.Referring now to FIG. 17, shown is a block diagram of a SoC 1700 in accordance with an embodiment of the present invention. Similar elements in Fig. 13 bear similar reference numerals. Additionally, dashed line fields are optional features on advanced SoCs. In FIG. 17, interconnect unit(s) 1702 are coupled to: an application processor 1710 comprising a set of one or more cores 1302A-N comprising cache units 1304A-N and shared cache unit(s) 1306; a system agent unit 1310; one or more bus control units 1316; one or more integrated memory control units 1314; a set of one or more coprocessors 1720 that may comprise integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1730; a direct memory access (DMA) unit 1732; and a display unit 1740 for coupling to one or more external displays. In one embodiment, coprocessor(s) 1720 includes a dedicated processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, or the like.Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code that execute on programmable systems, including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.Program code, such as code 1530 shown in FIG. 15, may be applied to the input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. In the context of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing different logic within the processor, which, when read by a machine, cause the machine to generate logic to perform the techniques described herein. Such representations, also known as "IP cores", may be stored on a tangible, machine-readable medium and provided to various customers or manufacturing facilities to load into the manufacturing machines that actually fabricate the logic or processor.Such machine-readable storage media may include, but are not limited to: non-transitory, tangible arrangements of articles manufactured or formed by a machine, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), Static Random Access Memories (SRAMs), Erasable Programmable Read-Only Memories (EPROMs), flash memories, Electrically Erasable Programmable Read-Only Memories (EEPROMs), Phase Change Memories (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as hardware description language (HDL) defining structures, circuits, devices, processors, and / or system features as described herein. Such embodiments may also be referred to as program products.Emulation (including binary translation, code morphing, etc.)In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate an instruction into one or more other instructions to be processed by the core (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or partially on and partially off processor.FIG. 18 is a block diagram illustrating use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set remotely, in accordance with embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although the instruction converter may alternatively be implemented in software, firmware, hardware, or various combinations thereof. FIG. 18 illustrates how a high level language program 1802 may be compiled with an x86 compiler 1804 to generate x86 binary code 1806, which may be internally executed by a processor with at least one x86 instruction set core 1816. The processor with at least one x86 instruction set core 1816 represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software intended to be executed on an Intel processor with at least one x86 instruction set core to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler 1804 represents a compiler that is operable to generate x86 binary code 1806 (e.g., object code) that may be executed with or without additional linkage processing on the processor with at least one x86 instruction set core 1816. Similarly, FIG. 18 shows how the high level language program 1802 may be compiled with an alternative instruction set compiler 1808 to generate alternative instruction set binary code 1810 that may be executed internally by a processor without at least one x86 instruction set core 1814 (e.g., a processor with cores executing the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and / or executing the ARM instruction set of ARM Holdings of Sunnyvale, CA). The instruction converter 1812 is used to convert the x86 binary code 1806 to code that can be executed internally by the processor without an x86 instruction set core 1814. This converted code is likely not the same as the alternative instruction set binary code 1810 because an instruction converter that could achieve this is difficult to build; however, the converted code satisfies the general operation and consists of instructions from the alternative instruction set. Thus, the instruction converter 1812 represents software, firmware, hardware, or a combination thereof that, by emulation, simulation, or any other process, enables a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1806.Examples of various embodiments are explained below.Example 1: a processor comprising:decoding circuitry for decoding an instruction with fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and a immediate operand, andExecution circuitry for executing the decoded instruction to perform a bit-matrix multiplication of the identified first source bit-matrix with the identified second source bit-matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the bit-matrix multiplication into the identified target bit-matrix.Example 2. the processor of example 1, wherein the operation selector is an 8-bit immediate.Example 3. The processor of any of Examples 1-2, wherein four bits of the immediate operand are used to select the accumulation operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 4. the processor of any of Examples 1-2, wherein four bits of the immediate operand are used to select the multiplication operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 5. the processor of any of Examples 1-4, wherein the identified first source matrix is an 8x8 bit matrix and the identified second source bit matrix is an 8x64 bit matrix.Example 6. the processor of any of Examples 1-4, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is an 8x8 bit matrix.Example 7. the processor of any of Examples 1-4, wherein the identified first source matrix is an 8x64 bit matrix and the identified second source bit matrix is a 64x64 bit matrix.Example 8. the processor of any of Examples 1-7, wherein the identified second source bit array is stored in memory.Example 9. the processor of any of Examples 1-4, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is a 64x8 bit matrix.Example 10. the processor of any of Examples 1-8, wherein the identified first source bit array is stored in memory.Example 11. the processor of any of Examples 1-10, wherein the bit matrix multiplication comprises: for each bit position in the destination, multiplying a value of each bit position of a corresponding row in the identified first source bit matrix by a value of the corresponding S-bit position of a corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing a result of the accumulating.Example 12. a processor comprising:decoding circuitry for decoding an instruction with fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and a immediate operand, andExecution circuitry for executing the decoded instruction to perform multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and the multiplication are performed by the multiplication.Accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified target bit matrix, where S is indicative of a multiple bit size.Example 13. the processor of example 12, wherein S is indicative of a bit size of 1, 2, 4, or 8.Example 14. The processor of any of Examples 12-13, wherein the operation selector is an 8-bit immediate operand.Example 15. The processor of any of Examples 12-14, wherein four bits of the immediate operand are used to select the accumulation operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 16. The processor of any of Examples 12-15, wherein four bits of the immediate operand are used to select the multiplication operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 17. the processor of any of Examples 12-16, wherein the identified first source matrix is an 8x8 bit matrix and the identified second source bit matrix is an 8x64 bit matrix.Example 18. The processor of any of Examples 12-16, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is an 8x8 bit matrix.Example 19. the processor of any of Examples 12-16, wherein the identified first source matrix is an 8x64 bit matrix and the identified second source bit matrix is a 64x64 bit matrix.Example 20. The processor of any of Examples 12-19, wherein the identified second source bit array is stored in memory.Example 21, The processor of any of Examples 12-16, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is a 64x8 bit matrix.Example 22. the processor of any of Examples 12-21, wherein the identified first source bit array is stored in memory.Example 23. the processor of any of Examples 12-22, wherein the bit matrix multiplication comprises: for each S-bit position group in the destination, multiplying an S-bit group value of each S-bit position group of a corresponding row in the identified first source bit matrix by a value of the corresponding S-bit position group of a corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing a result of the accumulating.Example 24. Method comprising:decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and a immediate operand, and executing the decoded instruction to perform a multiplication of a matrix of S bit elements of the identified first source bit matrix with S bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a multiple bit size.Example 25. The method of example 24, wherein S is indicative of a bit size of 1, 2, 4, or 8.Example 26. The method of any of Examples 24-25, wherein the operation selector is an 8-bit immediate operand.Example 27. the method of any of Examples 24-26, wherein four bits of the immediate operand are used to select the accumulation operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 28. The method of any of Examples 24-27, wherein four bits of the immediate operand are used to select the multiplication operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 29. The method of any of Examples 24-28, wherein the identified first source matrix is an 8x8 bit matrix and the identified second source bit matrix is an 8x64 bit matrix.Example 30. the method of any of Examples 24-28, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is an 8x8 bit matrix.Example 31. The method of any of Examples 24-28, wherein the identified first source matrix is an 8x64-bit matrix and the identified second source bit matrix is a 64x64-bit matrix.Example 32. the method of any of Examples 24-31, wherein the identified second source bit array is stored in memory.Example 33. The method of any of Examples 24-27, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is a 64x8 bit matrix.Example 34. the method of any of Examples 24-33, wherein the identified first source bit array is stored in memory.Example 35. the method of any of Examples 24-34, wherein the bit matrix multiplication comprises: for each S-bit position group in the destination, multiplying an S-bit group value of each S-bit position group of a corresponding row in the identified first source bit matrix by a value of the corresponding S-bit position group of a corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing a result of the accumulating.Example 36. a non-transitory machine-readable medium storing an instruction that, when executed by a processor, causes the processor to perform a method, the method comprising: decoding an instruction with fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a target bit matrix, and a immediate operand; and executing the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified target bit matrix, wherein S is indicative of a multiple bit size.Example 37. The non-transitory machine-readable medium of example 36, wherein S indicates a bit size of 1, 2, 4, or 8.Example 38. The non-transitory machine-readable medium of any of Examples 36-37, wherein the operation selector is an 8-bit immediate operand.Example 39. the non-transitory machine readable medium of any of Examples 36-38, wherein four bits of the immediate operand are used to select the accumulation operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 40. The non-transitory machine-readable medium of any of Examples 36-39, wherein four bits of the immediate operand are used to select the multiplication operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 41. the non-transitory machine-readable medium of any of Examples 36-40, wherein the identified first source matrix is an 8x8 bit matrix and the identified second source bit matrix is an 8x64 bit matrix.Example 42. the non-transitory machine-readable medium of any of Examples 36-40, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is an 8x8 bit matrix.Example 43. The non-transitory machine-readable medium of any of Examples 36-40, wherein the identified first source matrix is an 8x64-bit matrix and the identified second source bit matrix is a 64x64-bit matrix.Example 44. the non-transitory machine-readable medium of any of examples 36-40, wherein the identified second source bit array is stored in memory.Example 45. The non-transitory machine-readable medium of any of Examples 36-40, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is a 64x8 bit matrix.Example 46. the non-transitory machine-readable medium of any of examples 36-45, wherein the identified first source bit array is stored in memory.Example 47. the non-transitory machine-readable medium of any of Examples 36-46, wherein the bit-matrix multiplication comprises: for each S-bit position group in the destination, multiplying an S-bit group value of each S-bit position group of a corresponding row in the identified first source bit-matrix by a value of the corresponding S-bit position group of a corresponding column in the identified second source bit-matrix, accumulating each of the multiplications, and storing a result of the accumulating.Example 48: An apparatus comprising: decoding means for decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and a immediate operand; and executing means for executing the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S is indicative of a multiple bit size.Example 49. the apparatus of example 48, wherein S indicates a bit size of 1, 2, 4, or 8.Example 50. the apparatus of any of Examples 48-49, wherein the operation selector is an 8-bit immediate operand.Example 51: The apparatus of any of Examples 48-50, wherein four bits of the immediate operand are used to select the accumulation operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 52: The apparatus of any of Examples 48-51, wherein four bits of the immediate operand are used to select the multiplication operation of the group of exclusive OR (XOR), AND, OR, and NOR.Example 53. The apparatus of any of Examples 48-52, wherein the identified first source matrix is an 8x8 bit matrix and the identified second source bit matrix is an 8x64 bit matrix.Example 54: The apparatus of any of Examples 48-52, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is an 8x8 bit matrix.Example 55. The apparatus of any of Examples 48-52, wherein the identified first source matrix is an 8x64-bit matrix and the identified second source bit matrix is a 64x64-bit matrix.Example 56. the apparatus of any of Examples 48-55, wherein the identified second source bit array is stored in memory.Example 57. the apparatus of any of Examples 48-52, wherein the identified first source matrix is a 64x8 bit matrix and the identified second source bit matrix is a 64x8 bit matrix.Example 58. the apparatus of any of Examples 48-57, wherein the identified first source bit array is stored in memory.Example 59. the apparatus of any of Examples 48-58, wherein the bit matrix multiplication comprises: for each S-bit position group in the destination, multiplying an S-bit group value of each S-bit position group of a corresponding row in the identified first source bit matrix by a value of the corresponding S-bit position group of a corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing a result of the accumulating.

Claims

A processor comprising: a core that, in response to a single matrix multiplication instruction indicating a first source bit matrix, a second source bit matrix, a target matrix, and an operation selector, performs operations corresponding to the single matrix multiplication instruction, including: for each multi-bit position in the target matrix: processing bit values from bit positions of a corresponding row of the first source bit matrix and bit values from corresponding bit positions of a corresponding column of the second source bit matrix with one of a plurality of different types of logical operations selected by the operation selector to generate corresponding results, wherein the plurality of different types of logical operations include at least one logical AND operation or a non-AND operation, a logical OR operation or a NOR operation and an exclusive logical OR operation, an XOR operation, or a NON-XOR operation; to accumulate the results; and storing a result corresponding to the accumulation of the results at the multi-bit position in the target matrix, wherein the matrix multiplication instruction defines a row size and a different row size of the first source bit matrix, a row size and a different row size of the second source bit matrix, wherein the row size of the second source bit matrix corresponds to the column size of the first source bit matrix, and a row size and a column size of the target matrix, wherein the row size of the target matrix corresponds to the row size of the first source bit matrix, and wherein the column size of the target matrix corresponds to the column size of the second source bit matrix.The processor of claim 1, wherein the results are to be accumulated using an operation specified by the operation selector.The processor of claim 1 or 2, wherein the matrix multiplication instruction permits a plurality of different sizes for the first source bit matrix and the second source bit matrix.The processor of any of claims 1 to 3, wherein the matrix multiplication instruction is also capable of performing matrix multiplication on 4-bit data element matrices.The processor of any of claims 1 to 4, wherein the matrix multiplication instruction is also capable of performing matrix multiplication on matrices having data elements of one of a plurality of possible sizes.The processor of any of claims 1 to 5, wherein the first source bit array comprises at least 512 bits.The processor of any of claims 1 to 6, wherein the first source bit array comprises 4096 bits.The processor of any of claims 1 to 7, wherein the matrix multiplication instruction indicates a data element size of 1 bit.The processor of any of claims 1 to 8, wherein the first source bit array is stored in a plurality of registers.The processor of any one of claims 1 to 9, comprising a plurality of cores including the core.The processor of claim 10, wherein the plurality of cores comprises graphics cores.The processor of claim 10, wherein the plurality of cores is heterogeneous.The processor of any of claims 1 to 12, further comprising an instruction converter to convert the matrix multiplication instruction into one or more instructions of another instruction set executable by the core.The processor of any of claims 1 to 13, wherein the result to be stored in the target matrix comprises a one-bit matrix multiplication of the first source bit matrix and the second source bit matrix.A chip, comprising: a plurality of memory controllers; a level two cache, L2 cache, memory coupled to the plurality of memory controllers; the processor of any of claims 1 to 14, wherein the processor is coupled to the plurality of memory controllers and to the L2 cache; an interconnect coupled to the processor; and a bus controller coupled to the processor.A system comprising: a memory; and a chip according to claim 15, wherein the chip is coupled to the memory.The system of claim 16, further comprising a mass storage device coupled to the chip.The system of claim 16 or 17, further comprising a display coupled to the chip.A method comprising: performing a single matrix multiplication instruction with a core, the matrix multiplication instruction indicating a first source bit matrix, a second source bit matrix, a target matrix, and an operation selector, wherein performing the single matrix multiplication instruction comprises, for each multi-bit position in the target matrix: processing bit values from bit positions of a corresponding row of the first source bit matrix and bit values from corresponding bit positions of a corresponding column of the second source bit matrix with one of a plurality of different types of logical operations selected by the operation selector to generate corresponding results, wherein the plurality of different types of logical operations comprise at least one logical AND operation or a non-AND operation, a logical OR operation or a NOR operation and an exclusive logical OR operation, an XOR operation, or a NON-XOR operation; accumulating the results; and storing a result corresponding to the accumulation of the results at the multi-bit position in the target matrix, wherein the matrix multiplication instruction defines a row size and a different row size of the first source bit matrix, a row size and a different row size of the second source bit matrix, wherein the row size of the second source bit matrix corresponds to the column size of the first source bit matrix, and a row size and a column size of the target matrix, wherein the row size of the target matrix corresponds to the row size of the first source bit matrix, and wherein the column size of the target matrix corresponds to the column size of the second source bit matrix.The method of claim 19, wherein accumulating the results comprises accumulating the results using an operation specified by the operation selector, and wherein the matrix multiplication instruction permits a plurality of different sizes for the first source bit matrix and the second source bit matrix.The method of claim 19 or 20, wherein the matrix multiplication instruction is to indicate a data element size of 1 bit, and wherein the first source bit matrix is stored in a plurality of registers.The method of any of claims 19 to 21, wherein the first source bit array comprises at least 512 bits.The method of any of claims 19 to 22, further comprising converting the matrix multiplication instruction to one or more instructions of another instruction set executable by the core.The method of any of claims 19 to 23, further comprising: accessing memory with a plurality of memory controllers; and storing data in a level two cache, L2 cache.An apparatus comprising means for carrying out the method of any one of claims 19 to 24.A computer program product comprising instructions which, when executed by one or more machines, cause the one or more machines to perform the method of any one of claims 19 to 24.A machine readable storage medium having stored thereon the computer program product of claim 26.

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