Switching converter that uses pulse frequency modulation and current operating control

Abstract

Circuit that features: a power conversion circuit containing an inductor (Lo) and designed to convert an input voltage (V) IN ) corresponding to at least one switching signal (S ON ) to convert into an output voltage (Vo); a first current sensing circuit (CS) configured to detect a current sensing signal (V CS ), which induces an inductance current (i L ) represents, to generate; a voltage sensing circuit (VS) designed to detect a voltage sensing signal (V VS ), which determines the output voltage (V O ) represents, to generate; a switching controller with an error amplifier (EA) designed to generate an error signal (V E ), which is the difference between a reference voltage (V REF ) and the voltage sensing signal (V VS ) represents, to generate; an oscillator circuit (11', 11'') designed to transmit the switching signal (S ON ) for pulse frequency modulation operation of the power conversion circuit as a sequence of pulses with a pulse repetition frequency (fsw) determined by the error signal (V E ) and the current sensing signal (V CS ) depends on generating; an overfrequency detector circuit (OFD) coupled to the oscillator circuit (11', 11'') and configured to detect when the pulse repetition frequency (fsw) exceeds a frequency threshold (f TH ) reaches or exceeds, wherein, in order to activate and deactivate current feedback, the first current detection circuit (CS) is configured to be activated or connected to the oscillator circuit (11', 11'') when the overfrequency detector circuit (OFD) indicates that the pulse repetition frequency (f SW ) the frequency threshold (f TH) has reached or exceeded, and otherwise to be deactivated or disconnected from the oscillator circuit (11', 11").

Description

TECHNICAL AREA

[0001] The present disclosure relates to the field of switching converters such as DC / DC buck converters or the like. BACKGROUND

[0002] Switching converters are typically operated in different modes depending on one or more parameters, such as the input voltage, output voltage, and output current (i.e., the load). The different operating modes are distinguished by the switching control of the electronic switches that regulate the current flow through an inductor (choke) of the switching converter. Switching converters can operate in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In CCM, the inductor current flows continuously through the inductor without dropping to zero, whereas in DCM, the inductor current exhibits a discontinuous waveform because the current drops to zero in each switching cycle. A switching regulator for pulse frequency modulation is known from US 7,728,567 B1.The switching regulator contains an inductor with one terminal where an output voltage is provided. The current through the inductor is also measured. Depending on the output voltage and the current through the inductor, a timer circuit generates a pulse-frequency modulated signal to control a driver circuit.

[0003] The switching operation of electronic switches is determined by a switching signal that triggers the activation / deactivation of the electronic switches. This switching signal is a logic signal (i.e., it assumes only a logic high or a logic low level) that can be modulated using various modulation schemes to, for example, control the output voltage or output current. Conventional modulation schemes are pulse-width modulation (PWM) and pulse-frequency modulation (PFM). When using PWM, the duty cycle of the switching signal is set by adjusting the on-time (i.e., the pulse width) of the switching signal in each switching cycle, while the switching frequency remains constant. When using PFM, the switching frequency is set by adjusting the timing of the pulses of the switching signal, while the pulse width (i.e., the on-time in a switching cycle) remains constant.

[0004] Both modes, CCM and DCM, can be combined with either the PWM or PFM modulation schemes. In this example, four operating modes can be distinguished: PFM-DCM, PWM-DCM, PWM-CCM, and PFM-CCM. The achievable efficiency of the power conversion can vary for different operating modes at a given operating point (e.g., for a specific combination of input voltage, output voltage, and output current). Furthermore, some operating modes may be unsuitable for a particular range of operating conditions. To optimize efficiency, multi-mode switching converters have been developed, designed to operate in two or more different modes. The operating point of the switching converter is monitored, and when a mode switching condition is met, the operating mode is changed.

[0005] In some operating modes, stability problems can occur, whereas stable operation is usually ensured when PWM-CCM is used. However, PFM-CCM, in particular, can cause undesirable behavior of the switching controller in a certain range of operating points, such as operating points with high input voltage (compared to the output voltage) and high output current (high load). One of the problems underlying the invention can therefore be seen as avoiding the aforementioned stability problems and improving the stability of the circuit. OVERVIEW

[0006] The aforementioned problem is solved by the circuit according to claim 1 and the method according to claim 15. Various embodiments and further developments are the subject of the dependent claims. A circuit is described below. According to one embodiment, the circuit includes a power conversion circuit with an inductor and is configured to convert an output voltage into an output voltage corresponding to at least one switching signal.The circuit further includes a first current sensing circuit configured to generate a current sensing signal representing an inductance current, a voltage sensing circuit configured to generate a voltage sensing signal representing the output voltage, and a switching controller with an error amplifier configured to generate an error signal representing the difference between a reference voltage and the voltage sensing signal. The switching converter further includes an oscillator circuit configured to generate the switching signal for pulse frequency modulation (PFM) operation of the power conversion circuit as a sequence of pulses with a pulse repetition frequency that depends on the error signal and the current sensing signal.

[0007] Furthermore, a method is described herein. According to one embodiment, the method includes sensing an output voltage at a power conversion circuit and providing a corresponding voltage sensing signal, which indicates an inductance current flowing through an inductor of the power conversion circuit, and providing a corresponding current sensing signal, and determining an error signal based on the voltage sensing signal and a reference voltage. The method further includes generating at least one pulse-frequency modulated switching signal using an oscillator that generates the switching signal for pulse-frequency modulation (PFM) operation of the power conversion circuit as a sequence of pulses with a pulse repetition frequency that depends on the error signal and the current sensing signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The invention can be better understood with reference to the following drawings and descriptions. The components in the figures are not necessarily to scale; rather, emphasis has been placed on illustrating the principles of the invention. In the figures, identical reference numbers denote corresponding parts. Regarding the drawings: Fig. Figure 1 is a circuit diagram illustrating a general example of a buck converter that controls both the output voltage and the inductance current (current-based control). Fig. Figure 2 is a circuit diagram illustrating an example of a switching controller for PWM operation. Fig. Figure 3 is a circuit diagram illustrating an example of a switching controller for PFM operation. Fig. Figure 4 is a circuit diagram illustrating a design of a switching controller for PFM operation with current feedback. Fig. Figure 5 illustrates an exemplary implementation of the generic example of Fig. 4 using transconductance amplifiers. Fig. Figure 6 illustrates a modification of the example of Fig. 4, according to which current feedback can be deactivated for low switching frequencies. Fig. Figure 7 illustrates an exemplary design of an overfrequency detector that can be used to demonstrate the following example: Fig. 6. To activate current feedback for higher frequencies. Fig. Figure 8 illustrates an exemplary design of a multi-mode switching converter, where the switching controller performs the functions of the examples in the Fig. 2 and Fig. 4 combined. Fig. Figure 9 illustrates two examples of a monostable one-shot multivibrator, as in the example of Fig. 8 is used. Fig. 10 is a modification of the example of Fig. 8, where instead of the inductance current, the transistor currents flowing through the transistor bridge are measured. DETAILED DESCRIPTION

[0009] Fig. Figure 1 is a circuit diagram illustrating a general example of a buck converter. However, it is understood that the concepts described herein can readily be applied to other switching converter topologies such as flyback converters, buck-boost converters, boost converters, etc.

[0010] In the present example, the buck converter contains a switching circuit that connects an input circuit node N IN and is connected to a reference node GND. Between the input circuit node N IN and the reference node GND, which is usually located at a reference potential V GND (e.g., ground potential), an input voltage V is present. INIn the present example, the switching circuit is a transistor half-bridge consisting of a high-side transistor T. HS and a low-side transistor T LS It is implemented. The two transistors T LS and T HS are at an output circuit node N B The switching circuit is connected in series. In the present example, the two transistors T LS and T HS as MOS transistors (MOSFETs). However, any other transistor type can be used instead. In some examples, the low-side transistor T can be replaced with a different transistor. LS a diode is used.

[0011] The switching converter also contains an inductance Lo, which is connected between an output circuit node N. Bof the switching converter (e.g., the transistor half-bridge) and an output circuit node No (referred to as output) of the switching converter, at which the output voltage V OUT The circuit is supplied and connected. In the present example, an output capacitor Co is connected between the output No of the switching converter and the reference circuit node GND (e.g., ground node) to buffer the output voltage Vo. In general, the switching circuit is configured to supply the input voltage V IN and the reference voltage V GND to be applied alternately to the LC circuit composed of the inductor Lo and the capacitor Co.

[0012] The switching operation of the switching circuit can be determined by one or more switching signals generated by the switching controller 10. In the present example of Fig. 1 is the switching signal that goes to the high-side transistor T HS is supplied with SON denoted, while the switching signal supplied to the low-side transistor is denoted by S ON is designated. It is noted that the signal S ON essentially the inverse version of the signal S ON is (except for a small dead time). In other implementations, a single signal S can ON sufficient, for example, because the switching circuit only has an electronic switch or a circuit for distributing the switching signal S ON It contains two or more electronic switches. It is noted that in some specific operating modes (e.g., DCM burst mode), both transistors of the half-bridge may be temporarily switched off simultaneously to prevent discharge of the output capacitor Co.

[0013] Pulse-width modulation (PWM) is well-known in the field of switching converters, and therefore the generation of the switching signals will only be briefly summarized here. In general, the switching signal S ON a constant frequency, denoted by fsw, while the one-time T ON of the switching signal S ON is set in each switching cycle. The ratio between the on-time T ON and the leap period T SW = f SW -1 This is commonly referred to as the duty cycle. In other words, the duty cycle of the switching signal is updated in each switching cycle to regulate the output voltage or output current, during the switching period T. SW is essentially constant. The switching frequency f SW can be provided by a clock signal S CLKThe frequency that can be generated by an oscillator (OSC) must be determined. The OSC can be implemented using any known oscillator circuit, such as a relaxation oscillator circuit or the like.

[0014] Another modulation technique commonly used in switching converters is pulse frequency modulation (PFM). When PFM is used, the one-time T ON of the switching signal S ON essentially constant, and the switching frequency fsw is set by the switching controller, so that the output voltage V O is maintained at or near a desired target value.

[0015] To regulate the output voltage, the switching controller needs some information about the output voltage Vo. Therefore, the circuit can include a voltage sensing circuit VS, which is designed to measure the output voltage V. Oto detect directly or indirectly and a corresponding voltage detection signal V VS , which is based on the actual output voltage V O to provide (voltage feedback). According to a specific example, the voltage sensing circuit can be implemented as a simple voltage divider. However, more complex voltage sensing circuits can be used in other examples. In some operating modes, the switching controller 10 can implement a so-called current-based control, for which current feedback is used. Accordingly, the switching controller can include a current sensing circuit CS configured to measure the inductance current i. L to detect directly or indirectly and a corresponding current detection signal V CS , which is based on the actual inductance current i LProvides a current sensing circuit. In a simple example, the current sensing circuit might include a current sensing resistor. In other examples, more complex current sensing circuits, such as so-called sense FET arrays, might be used to detect the current.

[0016] Fig. Figure 2 illustrates an exemplary implementation of the switching controller 10, showing only those components used for current control during PWM operation and relevant to the following explanations. As in Fig. As shown in Figure 2, the current-driven control uses two feedback loops, i.e., current feedback and voltage feedback. Essentially, a first (inner) control loop regulates the inductance current i. L The (peak) current setpoint (see Fig. 1. Error signal V EThe current control is determined by a second (outer) control loop and adjusted so that the output voltage V O is stabilized at a desired voltage setpoint.

[0017] In the example of Fig. 2. The switching controller contains an RS flip-flop FF1, which receives the clock signal S. CLK at a set input S. Accordingly, the switching signal S ON , which is provided at the output Q of the RS flip-flop FF1, regularly and synchronously to the clock signal S CLK The signal is set to a high level. The RS flip-flop FF1 receives a reset signal S at a reset input R. OFF , where the reset signal S OFF (by applying a high level to the reset input R) indicates the time at which the inductance current i L The target current value has been reached. The inductance current i L is provided by a current detection signal V CSrepresented, and the current setpoint by the current level or the error signal V E The switching controller 10 contains a comparator K1, which is designed to measure the current sensing signal V. CS with the error signal V E to compare. In the present example, this comparison is implemented such that the comparator K1 actually compares the difference V. E -V CS compares to the reference potential (e.g., 0 volts). Each time the current sensing signal V CS the current level of the fault signal V E achieved (and thus the difference V) E -V CS (when the value is zero), the comparator K1 signals the switching signal S to the RS flip-flop FF1. ON to reset to a low signal level. The inverse switching signal S ON is provided at an output Q. In the present example, the difference V is obtained. E -V CSfrom subtraction block 13. The RS flip-flop FF1, in combination with the comparator K1, essentially acts as a duty cycle control circuit; the RS flip-flop is set in each switching cycle, while the reset (and thus the duty cycle) is triggered by the comparator K1. It is understood that many different ways of implementing the function of the generic circuit of Fig. 2 are known as such.

[0018] The aforementioned error signal V E (i.e., the current setpoint for the inner control loop) is output to an operational amplifier designed to measure the control error V VS - V REF to reinforce, provided, whereby V VS a voltage sensing signal that measures the output voltage V OUT represents, and V REFThis is a reference voltage that represents the voltage setpoint for the external control loop. Optionally, an integrator and / or a loop filter can be coupled between the error amplifier EA and the comparator K1.

[0019] To summarize the above: In PWM-CCM, the switching controller 10 uses two feedback loops, the first feedback loop being formed by the current sensing circuit CS and the comparator K1, and the second feedback loop being formed by the voltage sensing circuit VS and the error amplifier EA. The first feedback loop is part of a control loop used to control the inductance current i L is used, while the second feedback loop is part of a control loop used to control the output voltage Vo.

[0020] As mentioned above, PWM-CCM may not be suitable in some situations. For example, if the switching converter is subjected to a very low load (low output current) or if the ratio V IN / V O If the voltage is high, a mode switch to PFM-DCM or PFM-CCM (or other modes such as burst mode) may be necessary to maintain output voltage regulation. Since multi-mode switching controllers are known as such, mode switching conditions are not discussed in detail here.

[0021] An example of a switching controller operating in PFM-CCM mode is in Fig. Figure 3 shows the circuitry, but to keep the illustration simple, only those components relevant to the following explanations are shown. Accordingly, only those parts of the switching controller 10 used for PFM control are shown. It should be understood that the switching controller 10 may also contain the circuit components used for PWM control, the circuit components used for PFM operation, and other circuitry for triggering mode switches or the like.

[0022] According to Fig. The switching circuit (transistor half-bridge), the inductor Lo, the output capacitor Co, the voltage sensing circuit VS, and the error amplifier EA are the same as in the example of Fig. 2. However, the configuration of the switching controller differs from the previous example. Accordingly, the output signal V EThe error signal of the error amplifier EA is integrated by an (inverting) integrator INT, and the integrated error signal is compared by a comparator K2 with a threshold value Vx (which can be 0 volts in this example). The output of comparator K2 is coupled to a monostable multivibrator MF1, which is configured to detect a pulse with a defined (and constant) pulse length T. ON,min to produce.

[0023] In response to comparator K2 detecting that the integrated error signal fed to comparator K2 has reached the threshold value Vx, a pulse is generated. The pulse length (on-time T) is... ON,min ) of the pulse in the switching signal is determined, while the switching frequency fsw (pulse repetition frequency) is determined according to the measured error signal V. E changes. As in the previous example of Fig. 1 becomes the switching signal S ON the high-side transistor T HSand an inverse switching signal S ON the low-side transistor T LS fed to the half-bridge. It is noted that the integrator INT and the comparator K2, in combination with the monostable multivibrator MF1, which provides the reset signal RES, are used. INT for the integrator INT, as a type of voltage-controlled oscillator (VCO) that is in Fig. 3, which is labelled VCO 11, can be viewed. The higher the input voltage V E The steeper the edge of the integrator output voltage V, the greater the slope. I and therefore the higher the pulse repetition frequency (switching frequency fsw) of the pulse at the output of the monostable multivibrator MF1 (signal S). ON In each switching cycle, the integration time starts at the end of the on-time T. ON,min anew.

[0024] As in Fig. As can be seen in Figure 3, only one feedback loop is used during conventional PFM operation; the current sensing circuit CS is not used in the PFM operating modes. The in Fig. The control structure shown in point 3 essentially generates the integrated error signal V every time it is triggered. E a certain threshold value Vx is reached, a pulse of the switching signal S ON However, this can be the case with the example of Fig. 3. The control concept used may lead to instabilities at some operating points (e.g., when output current stages occur); these instabilities can cause increased noise / oscillations in the output signal Vo, which is undesirable in some applications.

[0025] Fig. 4 is a switching converter with a switching controller 10, which is similar to the switching controller of the preceding example of Fig. 3. Again, only those circuit components used in PFM operation and relevant for the following explanations are shown. Essentially, the circuit is of Fig. 4 identical to the circuit of Fig. 3 with a significant improvement that enables a type of power operation control during PFM operation. Compared to the previous example of Fig. 3. The switching controller 10 uses an additional current feedback loop, which is the current sensing circuit CS (see Fig. 1) contains, wherein the current sensing signal V CS with the error signal V E The signal provided at the output of the error amplifier EA is combined (e.g., subtracted from it). Accordingly, the (inverting) integrator INT receives the difference signal V. E - V CS and integrates it (and changes the sign); the resulting, integrated signal V IThe signal is provided at the output of the integrator INT and fed to the comparator K2, as in the previous example. With the exception of this additional feedback loop, the circuit is as follows: Fig. 4 the same as in Fig. 3, and reference is made to the corresponding explanations above. The integrator INT and the comparator K2 in combination with the monostable multivibrator MF1, which provides the reset signal RES. INT The INT integrator can be considered a type of voltage-controlled oscillator (VCO) that is integrated into... Fig. 4, labeled VCO 11', should be considered. The higher the input voltage V E The steeper the edge of the integrator output voltage V, the greater the slope. I and therefore the higher the pulse repetition rate (switching frequency f). SW ) the pulses at the output of the monostable multivibrator MF1 (signal S) ON ). In contrast to the preceding example of Fig. 3. The VCO 11' is not purely voltage-controlled, but also receives current feedback, which improves the stability of the closed control loop and avoids oscillations / ringing at the output node.

[0026] Fig. Figure 5 illustrates an exemplary implementation of the general example of Fig. 4. Accordingly, the error amplifier EA is implemented as a transconductance amplifier, which has a resistance (or more generally an impedance) Zc coupled to its output; the output current i E The error amplifier EA is proportional to the difference V REF - V VS and therefore points to the control error concerning the output voltage V O close. The current i E flows through impedance Zc and causes a voltage drop V E (Error signal). The impedance Zc may include a capacitor for drift compensation.

[0027] The integration of the difference V E - V CS (cf.) Fig. 4) is provided by the transconductance amplifiers A1 and A2 and the capacitor C INT implemented. Accordingly, the transconductance amplifier A1 converts the error signal V. E in a stream i EC , and the transconductance amplifier A2 converts the current sensing signal V CS into a (negative) current ics (i.e., the transconductance amplifier A2 acts as a current sink). The outputs of the transconductance amplifiers A1 and A2 are connected to a circuit node N. INT to a capacitor C INT connected, so that the currents i EC and i CS superimposed and the differential current i EC - i CS through capacitor C INT flows. Accordingly, the voltage drop V I above the capacitor VI=1CINT□∫0tiEC−iCSdτ=1CINT∫0tg1VE−g2VCSdτ, where g1 and g2 denote the transconductance of the transconductance amplifiers A1 and A2, respectively. A switch SW is connected in parallel to the capacitor C. INT It is switched and configured to discharge in response to a pulse generated by the monostable multivibrator MF1. Accordingly, the switch opens at the end of a one-time period T in each cycle. ON,min , and the differential current i E - i CS will be during the (variable) off-time T OFF integrated (integration time t = 0 ... T OFF ). As soon as the voltage drop V I above capacitor C INT When the trigger threshold of the monostable multivibrator MF1 is reached, another pulse is generated by the monostable multivibrator MF1, and the off-time T OFF ends. The total leap period Tsw is therefore T ON,min + T OFF , where the one-time T ON,min is constant and the off-time T OFF from the level of the feedback signal (current sensing signal V) CSand voltage detection signal V VS ) depends. Apart from the specific implementation of the switching controller 10, the circuit of Fig. 5 the same as in the preceding example, and reference is made to the corresponding explanations above.

[0028] Fig. Figure 6 illustrates a modification / improvement of the in Fig. 4. Example shown. Compared to the example of Fig. 4. The present example contains an over-frequency detection circuit (OFD) that detects the switching signal S ON (or the inverse signal S) ON ) receives and is designed to detect whether the switching frequency fsw of the switching signal S ON below a frequency threshold f TH has dropped. If the switching frequency fsw is below the frequency threshold f TH lies (f SW < f TH), then the overfrequency detection circuit OFD interrupts the current feedback loop, e.g. using a switch SW. OF Accordingly, the SW switch can OF between the current sensing circuit CS and the subtraction circuit, which calculates the difference V E - V CS The current sensing circuit CS is provided, arranged, and configured to connect and disconnect it from the subtraction circuit according to an overfrequency signal provided by the overfrequency detection circuit OFD. Alternatively, the current sensing circuit CS can be deactivated, which can be achieved in various ways depending on the implementation of the current sensing circuit CS.

[0029] Furthermore, in the present example, the current sensing circuit CS detects the current through the low-side transistor T. LS, whereas in the preceding example, the current i flowing through the inductance Lo was used instead L is used. However, since the current information is only required during the off-time – i.e., when the high-side transistor T is switched on – HS is off and the low-side transistor T LS If it is - it does not matter that during the (constant) one-time T ON,min No power information is available.

[0030] As mentioned, current feedback can help improve stability and prevent oscillations / ringing at output node No. However, instabilities mainly occur at higher output currents when the switching converter operates in PFM-CCM mode. Therefore, current feedback is not necessary at lower output currents when the switching converter operates in PFM-DCM mode. Disconnecting / disabling the current sensing circuit CS allows for a reduction in quiescent current consumption during low-load (and therefore low output current) operating conditions, thus improving efficiency during low-load operation.

[0031] Fig. Figure 7 illustrates an exemplary implementation of the overfrequency detection circuit OFD. It is understood that the function provided by the overfrequency detection circuit OFD can be implemented in various other ways. In the illustrated example, the overfrequency detection circuit OFD includes a capacitor C. OF , where the voltage across the capacitor is V OF is designated. The capacitor is connected between an input of a comparator K. H , which may exhibit hysteresis, and a reference potential, e.g., ground potential. The capacitor C OF is via an electronic switch SW OF , which corresponds to the switching signal S ON (see Fig. 6) is activated and deactivated, coupled to a current source Q1. Furthermore, the capacitor C OF connected to a current sink Q2, which has a switching period T SW = 1 / f SWa constant current i2 draws (current sink), while the current source Q1 only draws current during the on-time T. ON outputs a current i1. The capacitor charge is located for f SW = f TH in the steady state, when the net charge applied to the capacitor is zero, that is to say i1TON=i2fTH. Consequently, the capacitor voltage V increases OF on (until the current source is saturated) as soon as the switching frequency exceeds the frequency threshold f TH exceeds: fSW>i2i1TON.

[0032] If the above condition is true, the capacitor voltage V reaches OF quickly determine the trigger threshold of the comparator K H , and the comparator output signal S OF Can the current sensing circuit CS (see) be (re-)activated? Fig. 6) display.

[0033] The examples of Fig. 4 to 6 refer to a switching converter that uses PFM (e.g., PFM-DCM or PFM-CCM) and current feedback to the voltage-controlled oscillator (see VCO 11 and the Fig. 4-6) works, while the example of Fig. 2 refers to a conventional PWM operation. These two concepts can be combined; the resulting switching converter is a multi-mode converter that automatically switches from PFM operation to PWM operation and vice versa. Fig. Figure 8 illustrates an exemplary implementation of such a multi-mode switching controller and essentially represents a combination of the examples from Fig. 2 and Fig. 4, where the voltage-controlled oscillator (VCO) 11" performs the function of the oscillator OSC during PWM operation (see Fig. 2) takes over. During PFM operation (at low load), the VCO 11" provides a variable frequency fsw that increases when the error signal V E(for a given stream i L ) increases. The VCO 11" is essentially the same as in the preceding example of Fig. 4. However, the output comparator K2 (instead of the monostable multivibrator MF1 used in the previous examples) is connected to a timing circuit 12, which ensures that the output signal S P a certain minimum one-time T ON,min as well as a certain minimum downtime T OFF,min This is sufficient. Therefore, the timing circuit 12 can be considered a type of (one-shot) monostable multivibrator that, when triggered, outputs a pulse with pulse length T. ON,min (On-time) is generated, while a retrigger occurs before the minimum off-time T. OFF,min It is not possible after the pulse has elapsed. Accordingly, the minimum switching period T is ON,min + T OFF,min , and the corresponding maximum switching frequency f SW,max is 1 / T SW,minAccordingly, the switching frequency of the VCO 11" is limited to a maximum switching frequency f. SW,max limited.

[0034] If the switching frequency fsw in PFM operation is the maximum switching frequency f SW,max Once a certain threshold is reached (e.g., because the required output power increases), the PFM operation stops "automatically," and voltage regulation continues using PWM, with the duty cycle being adjusted using comparator K1 as in the example of Fig. 2 is changed. The parameters f are changed. SW,max and T ON,min chosen to ensure a smooth transition between PFM and PWM (and vice versa).

[0035] When switching between Fig. 8. The RS flip-flop FF1 is practically neutral (transparent) when operating in PFM mode. The timing circuit 12 (one-shot monostable multivibrator) ensures that the RS flip-flop FF1 maintains a set state for the minimum one-time T. ON,minretains, and the comparator K1 causes an immediate reset of the RS flip-flop FF1 after the minimum on-time T. ON,min In PWM operation (at maximum switching frequency f) SW,max The RS flip-flop FF1 essentially has the same function as in the example of Fig. 2, i.e., it works in conjunction with the comparator K1 as a duty cycle control circuit. That is, the RS flip-flop FF1 is regularly set and reset in each switching cycle when the current feedback signal V CS the level of the error signal V E as in the example of Fig. 2 is reached, thereby reaching the duty cycle of the switching signal S ON is established, while the switching frequency fsw is at its maximum f SW,max is located.

[0036] If the duty cycle during PWM operation (during f SW = f SW,max ) becomes so small that the one-time T ON the minimum one-time T ON,minOnce a certain threshold is reached (e.g., because the required output power decreases), the level of the output signal Vo increases (slightly) because the duty cycle cannot be reduced further. This results in a lower level of the error signal V. E (or even to the point that V E becomes negative), which causes the VCO 11" to reduce the switching frequency fsw below the maximum switching frequency f SW,max to reduce, while the minimum one-time T ON,min The PWM operation ends "automatically," and further operation continues in PFM mode. As mentioned, the RS flip-flop FF1 has virtually no effect during PFM operation (i.e., it is neutral / transparent); VCO 11" keeps the RS flip-flop FF1 active for at least the minimum one-time period T. ON set, while the comparator K1 sets the RS flip-flop practically immediately after the minimum one-time T. ON resets.

[0037] Diagrams (a) and (b) of Fig. Figure 9 illustrates two examples of the timing circuit. Figure 12 follows the example of diagram (a) from Fig. 9 contains the timing circuit 12, a one-shot monostable multivibrator MF2 with a reset input RES. As soon as it is pierced by a signal S P (see Fig. 8) Once triggered, the one-shot monostable multivibrator MF2 cannot be triggered again before it is reset. The reset signal is a delayed output of the monostable multivibrator MF2's output signal, with a delay T. SW,min This is achieved by a delay circuit D1, which is coupled between the output of the monostable multivibrator and its reset input RES. Accordingly, the reset occurs after a time T. SW,min after the MF2 monostable multivibrator is triggered. Regarding the connection with Fig. For the 9 circuit components not discussed, reference is made to the above description of the Fig. 2 and Fig. 4.

[0038] According to the example of diagram (b) of Fig. 9 contains the timing circuit 12 an RS flip-flop FF2, which is controlled by the signal S P (see Fig. 8) is set. The output of the RS flip-flop FF2 is set after the on-time T. ON,min deleted, resulting in a pulse with a pulse length of T at the output of timing circuit 12. ON,min The pulse can be generated using any conventional circuit, such as the delay element D2 (delay T). ON,minThe output signal of the timing circuit 12 is generated by the inverter G3, the AND gate G1, where a non-inverting input of the AND gate G1 is connected to the output of the RS flip-flop FF2, and an inverting input of the AND gate G1 is coupled to the output of the RS flip-flop FF2 via the delay element D2. The output signal of the timing circuit 12 is provided at the output of the AND gate G1. Any re-triggering of the timing circuit 12 before the RS flip-flop FF2 has been reset has no effect. The reset is performed by the inverter G3, the AND gate G2, and the delay circuit D3 (delay T). OFF,min). The output of AND gate G1 is inverted by inverter G3 and delayed by delay circuit D3. The inverted signal is fed to the non-inverting input of AND gate G2, and the delayed inverted signal is fed to the inverting input of AND gate G2. Therefore, AND gate G2 generates a reset pulse that is T later than the output pulse generated by AND gate G1. OFF,min is delayed.

[0039] It goes without saying that there are numerous other options to utilize the functions provided by the in Fig. The nine example circuits shown are provided for implementation. The actual implementation may depend on the semiconductor technology used.

[0040] Fig. Figure 10 illustrates another example of a multi-mode switching converter with improved control when operating in PFM mode. The circuit of Fig. 10 is essentially the same as the preceding example of Fig. 8 with the exception of the implementation of current sensing. While the inductance current i L Whereas in the preceding examples the current is measured at the output of the half-bridge, the present example measures the transistor currents i HS and i LS , which is driven by the high-side transistor T HS or the low-side transistor T LS the half-bridge. This allows, for example, the use of common sense FET circuits for current sensing. As from Fig. As can be seen in 10, the inductance current i L during the on-time, the same as that achieved by the high-side transistor T HS flowing current, which passes through a current sensing circuit CS' (current sensing signal V) CS ') is measured. Similarly, the inductance current i L during the off-time, the current is the same. LS , which is controlled by the low-side transistor T LSflows, which passes through a current sensing circuit CS (current sensing signal V) CS ) is measured.

[0041] Since the integrator INT of the VCO 11" is only active during the off time, the current sensing signal V CS , which the current i LS represented in which VCO 11" is used as the current feedback signal, and the current sensing signal V CS As in the previous examples, the current is fed to the subtraction circuit 13. In PWM mode, the duty cycle control (comparator K1) is only active during the on-time, and thus the current sensing signal V is... CS ' of the subtraction circuit 13', which calculates the difference V supplied to the comparator K1 E - V CS 'provides, supplied. Especially when separate current sensing circuits are used to detect the current through the high-side transistor T HS and the low-side transistor T LSWhen used, it may be advantageous to deactivate the current sensing circuit CS during PFM operation if the switching frequency fsw is below the threshold frequency f TH falls (f SW < f TH Furthermore, the current sensing circuit CS' is not required during PFM operation and can be deactivated. Therefore, the overfrequency detector circuit OFD of the example from Fig. 6 also in the present example of Fig. 10 can be used to reduce quiescent current consumption at very low loads, since in such an operating state the current feedback V CS This is not required to improve stability. Therefore, efficiency can be improved by selectively disabling the current sensing circuits CS (during operation in PFM and f). SW < f TH ) and the current sensing circuit CS' (during operation in PFM) will be improved.

Claims

[1] Circuit which features: a power conversion circuit containing an inductor (Lo) and designed to convert an input voltage (V) IN ) corresponding to at least one switching signal (S ON ) to convert into an output voltage (Vo); a first current sensing circuit (CS) configured to detect a current sensing signal (V CS ), which induces an inductance current (i L ) represents, to generate; a voltage sensing circuit (VS) designed to detect a voltage sensing signal (V VS ), which determines the output voltage (V O ) represents, to generate; a switching controller with an error amplifier (EA) designed to generate an error signal (V E ), which is the difference between a reference voltage (V REF ) and the voltage sensing signal (V VS ) represents, to generate; an oscillator circuit (11', 11'') designed to transmit the switching signal (S ON ) for pulse frequency modulation operation of the power conversion circuit as a sequence of pulses with a pulse repetition frequency (fsw) determined by the error signal (V E ) and the current sensing signal (V CS ) depends on generating; an overfrequency detector circuit (OFD) coupled to the oscillator circuit (11', 11'') and configured to detect when the pulse repetition frequency (fsw) exceeds a frequency threshold (f TH ) reaches or exceeds, wherein, in order to activate and deactivate current feedback, the first current detection circuit (CS) is configured to be activated or connected to the oscillator circuit (11', 11'') when the overfrequency detector circuit (OFD) indicates that the pulse repetition frequency (f SW ) the frequency threshold (f TH) has reached or exceeded, and otherwise to be deactivated or disconnected from the oscillator circuit (11', 11"). [2] Circuit according to claim 1, wherein the pulse repetition frequency (fsw) is determined by the difference (V) E - V CS ) between the error signal (V E ) and the current sensing signal (V CS depends. [3] Circuit according to one of claims 1 to 2, wherein the oscillator circuit (11', 11'') includes an integrator (INT) coupled to the error amplifier (EA) and the current sensing circuit (CS). [4] Circuit according to claim 3, wherein the integrator (INT) is configured to generate a signal that represents the difference between the error signal (V) E ) and the current sensing signal (V CS ) represents, to integrate. [5] Circuit according to claim 3 or 4, wherein the integrator includes a capacitor (C INT ) contains a differential current (i D), which is the difference between the error signal (V E ) and the current sensing signal (ics) is represented and received. [6] Circuit according to any one of claims 3 to 5, wherein the oscillator circuit (11', 11") further comprises a pulse generation circuit coupled downstream of the integrator (INT) and configured to generate a pulse of the switching signal (S) in response to the integrator output signal exceeding a certain threshold (Vx). ON to generate. [7] Circuit according to claim 6, wherein the integrator is configured to respond to each pulse of the switching signal (S ON ) to be reset. [8] Circuit according to any one of claims 1 to 7, wherein the pulse repetition frequency (f SW ) to a maximum switching frequency (f SW,max ) is limited. [9] Circuit according to claim 8, wherein the switching controller further comprises: a duty cycle control circuit designed to control the on-time of the switching signal (S ON ) - for pulse width modulation (PWM) operation, while the pulse repetition frequency (fsw) is equal to the maximum switching frequency (f SW,max ) is - dependent on the error signal (V E to change. [10] Circuit according to claim 9, wherein the duty cycle control circuit includes a flip-flop coupled to the oscillator circuit (11', 11'') and configured to be set in response to each pulse and depending on the error signal (V E ) to be reset. [11] Circuit according to claim 9 or 10, wherein the duty cycle control circuit is configured to determine the on-time of the switching signal (S ON ) depending on the error signal (V E ) and further dependent on the inductance current (i L to change. [12] Circuit according to any one of claims 1 to 11, wherein the power conversion circuit is a series connection of a high-side switch (T HS ) and a low-side switch (T LS ) contains, which between an input terminal designed to carry the input voltage (V IN ) to receive, and another terminal which is supplied with a reference potential during operation is connected; wherein a common circuit node of the high-side switch (T HS ) and the low-side switch (T LS ) is coupled to the inductance (Lo), such that the inductance current (i L ) either via the high-side switch (T HS ) or the low-side switch (T LS ) is referred to. [13] Circuit according to claim 12, wherein the first current sensing circuit (CS) is configured to detect the current measured by the low-side switch (T LS ) to detect the flowing current. [14] Circuit according to any one of claims 1 to 11, wherein the power conversion circuit is a series connection of a high-side switch (T HS ) and a low-side switch (T LS ) contains, which between an input terminal designed to carry the input voltage (V IN ) to receive, and another terminal which is supplied with a reference potential during operation is connected; wherein a common circuit node of the high-side switch (T HS ) and the low-side switch (T LS ) is coupled to the inductance (Lo), such that the inductance current (i L ) either via the high-side switch (T HS ) or the low-side switch (T LS ) is related to wherein the circuit further includes a second current sensing circuit (CS') configured to detect the current sensing through the high-side switch (T LS) to detect the flowing current and generate a corresponding second current detection signal (V CS ') to generate, and wherein the duty cycle control circuit is configured to determine the on-time of the switching signal (S ON ) depending on the difference between the error signal (V E ) and the second current detection signal (V CS ') to change. [15] Method which features: Detection of an output voltage (Vo) at a power conversion circuit and provision of a corresponding voltage detection signal (V) VS ); Detecting a current that corresponds to an inductance current (i) flowing through an inductor (Lo) of the power conversion circuit L ) can be detected, and providing a corresponding current detection signal (V CS ); Determining an error signal (V) E ) based on the voltage sensing signal (V VS ) and a reference voltage (V REF ); Generating at least one pulse-frequency modulated switching signal (S ON ) using an oscillator (11'), wherein the oscillator (11') provides the switching signal (S) for pulse frequency modulation operation of the power conversion circuit ON ) is generated as a sequence of pulses with a pulse repetition frequency (fsw), and wherein the switching signal (S ON ) from the error signal (V E ) and the current sensing signal (V CS depends on; Detect when the pulse repetition rate (fsw) exceeds a frequency threshold (f TH ) reaches or exceeds, where the current sensing signal (V CS ) is provided by a first current sensing circuit (CS), which – in order to activate and deactivate current feedback – in response to the detection that the pulse repetition frequency (f) SW ) the frequency threshold (f TH) has reached or exceeded, is activated or connected to the oscillator (11') and otherwise is deactivated or disconnected from the oscillator (11'). [16] Method according to claim 15, wherein the pulse repetition rate (fsw) is determined by the difference (V) E - V CS ) between the error signal (V E ) and the current sensing signal (V CS depends. [17] Method according to any one of claims 15 to 16, wherein the oscillator generates a signal that is based on the difference (V E - V CS ) between the error signal (V E ) and the current sensing signal (V CS ) depends, integrates until the integrated value reaches a threshold after an integration time; where the integration time determines the pulse repetition rate. [18] Method according to any one of claims 15 to 17, wherein the pulse repetition rate (fsw) is set to a maximum value (f SW,max ) is restricted.

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