POWER CONVERSION DEVICE

Abstract

Power conversion device (1) with a high-potential line (11H) and a low-potential line (11L), an upper branch semiconductor device (2H) connected to the high potential line, a sub-branch semiconductor device (2L) connected in series with the upper-branch semiconductor device (2H) and connected to the low-potential line, and a capacitor (3) which is connected between the high potential line and the low potential line, wherein from the upper branch semiconductor device and the lower branch semiconductor device connected in series, the upper branch semiconductor device forms a parallel circuit body (20) configured from two or more switching elements (2) connected in parallel to each other, and / or the lower branch semiconductor device forms a parallel circuit body (20) configured from two or more switching elements (2) connected in parallel to each other, in the upper branch semiconductor device and the Sub-branch semiconductor device connected in series, a return flow element (21) in the parallel circuit body is provided to allow current flow from a low-potential line side to a high-potential line side, The switching elements that form the parallel circuit body are controlled in such a way that the switching-off times are different from each other. a last-off element (22) that switches off last, and a non-last-off element (23) as the other element among the switching elements that form the parallel circuit body, an inductance of a closed last-off circuit (101) in which current flows through the last-off element, the return element in an opposite branch opposite to the last-off element, and the capacitor, is smaller than the inductance of a closed non-last-off circuit (102) in which current flows through the non-last-off element connected in parallel to the last-off element, the return element in an opposite branch opposite to the last-off element, and the capacitor, wherein the parallel body of the upper branch semiconductor device comprises the last-off element, the non-last-off element and the return element, and the parallel body of the lower branch semiconductor device comprises the last-off element, the non-last-off element and the return element, the last-off element, the non-last-off element and the reflux element in the upper-branch semiconductor device are mounted on a common upper-branch module (50H) as a single common semiconductor device, and the last-off element, the non-last-off element and the reflux element in the sub-branch semiconductor device are mounted on a common sub-branch module (50L) as a single common semiconductor device, the common upper branch module and the common lower branch module are each configured such that two power connections (551, 552) project from a module body (550), and the inductance of a wiring path in the module body that connects the power terminals via the last-off element is smaller than the inductance of a wiring path in the module body that connects the power terminals via the non-last-off element, wherein the common upper branch module and the common lower branch module are configured such that the two power terminals project from the module body in the same direction, and a center position (C) in a base section of the two power terminals is closer to the last-off element than to the non-last-off element in a direction in which the last-off element and the non-last-off element are arranged.

Description

Background (Technical Field)

[0001] The present disclosure relates to a power conversion device, and more precisely a power conversion device configured from upper-branch semiconductor devices (semiconductor devices on an upper branch) and lower-branch semiconductor devices (semiconductor devices on a lower branch) connected in series between a high-potential line and a low-potential line. (Description of the state of the art)

[0002] US Patent 2016 / 0191046A discloses a power converter in which each branch (upper and lower branch) contains a hybrid switch with first and second switching devices of different designs. The first and second switching devices are each controlled by first and second control signals, respectively, which have unequal duty cycles when the two switching devices are to supply a current within a first current range.

[0003] US Patent 2010 / 0171473A1 discloses a power converter in which a first high-side MOSFET is connected in parallel to a second high-side MOSFET via an inductor. When current begins to flow, the first high-side MOSFET turns on earlier. A recovery current from the body diode of a low-side MOSFET flows through the inductor and the first high-side MOSFET, thus reducing the rate at which the current changes over time. Subsequently, the second high-side MOSFET turns on for main current, and the first high-side MOSFET turns off to suppress a recovery current, causing the former to experience a current leakage. When the second high-side MOSFET turns off to stop the current flow, no voltage spike is caused by the inductor.

[0004] Another power conversion device is known in which upper-branch semiconductor devices and lower-branch semiconductor devices are connected in series between a high-potential line and a low-potential line. For example, Japanese patent literature, such as Japanese Patent No. JP 5 805 513 B2, discloses a power conversion device in which each of the upper-branch semiconductor devices and each of the lower-branch semiconductor devices is configured from two switching elements connected in parallel (hereinafter referred to as a parallel circuit body). In particular, the patent literature described above discloses a configuration in which two switching elements contained in the parallel circuit body are controlled to be switched off at different times.

[0005] However, according to the patent literature described above, a technique for effectively reducing switching losses when controlling the shifting of the switch-off times for the two switching elements is not proposed. In particular, a switching element that is subsequently switched off in the two parallel-connected switching elements causes a current change in the main circuit, thereby causing a switching loss. Accordingly, if the inductance of the closed circuit is high when the current change occurs, the switching loss cannot be efficiently reduced. SUMMARY

[0006] The present disclosure was obtained in view of the circumstances described above and provides a power conversion device that is capable of effectively reducing any switching loss thereof.

[0007] This problem is solved by a power converter as specified in claim 1.

[0008] Advantageous embodiments are specified in the dependent patent claims.

[0009] According to the power conversion device described above, the inductance of the closed last-off circuit described above is lower than the inductance of the closed non-last-off circuit described above. Thus, the switching loss can be effectively reduced.

[0010] As described above, a power conversion device can be provided according to the above-described design which is capable of effectively reducing the switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings show: Fig. 1 a circuit diagram illustrating a power conversion device according to a first embodiment of the present disclosure, Fig. 2 an explanatory diagram illustrating a closed last-off circuit and a closed non-last-off circuit when considering a switching operation of an upper-branch semiconductor device according to the first embodiment, Fig. 3 an explanatory illustration demonstrating a closed last-off circuit and a closed non-last-off circuit when considering a switching operation of a sub-branch semiconductor device according to the first embodiment, Fig. 4 a time-series diagram illustrating switching operations of a last-off element and a non-last-off element according to the first embodiment, Fig. 5 a time-lapse diagram illustrating the switching operations of the last-off element and the non-last-off element according to the second embodiment, Fig. 6 a circuit diagram illustrating a power conversion device according to a third embodiment, Fig. 7 an explanatory illustration demonstrating a closed last-off circuit and a closed non-last-off circuit when considering a switching operation of an upper-branch semiconductor device according to the third embodiment, Fig. 8 an explanatory illustration demonstrating a closed last-off circuit and a closed non-last-off circuit when considering a switching operation of a sub-branch semiconductor device according to the third embodiment, Fig. 9 a circuit diagram illustrating a power conversion device according to a fourth embodiment, Fig. 10 a circuit diagram illustrating a power conversion device according to a fifth embodiment, Fig. 11 a circuit diagram illustrating part of a power conversion device according to a sixth embodiment, Fig. 12 a front view illustrating a last-off module according to a sixth embodiment, Fig. 13 a front view illustrating a non-last-off module according to the sixth embodiment, Fig. 14 a top view of part of the power conversion device according to the sixth embodiment, Fig. 15 a top view illustrating part of the power conversion device with part of a busbar according to the sixth embodiment, Fig. 16 a front view illustrating a connection state between an upper branch module, a lower branch module and a busbar according to the sixth embodiment, Fig. 17 an explanatory illustration demonstrating a closed last-off circuit and a closed non-last-off circuit when considering a switching operation of an upper-branch semiconductor device according to a seventh embodiment, Fig. 18 an explanatory illustration demonstrating a closed last-off circuit and a closed non-last-off circuit when considering a switching operation of an upper-branch semiconductor device according to the seventh embodiment, Fig. 19 a front view illustrating a common module as a last-off module according to the seventh embodiment, Fig. 20 a front view illustrating a common module as a non-last-out module according to the seventh embodiment, Fig. 21 a cross-sectional view extending along a line XXI-XXI of Fig. 19 taken, Fig. 22 a top view illustrating part of a power conversion device according to the seventh embodiment, Fig. 23 an explanatory illustration demonstrating a closed last-off circuit and a closed non-last-off circuit when considering a switching operation of an upper-branch semiconductor device according to an eighth embodiment, Fig. 24 an explanatory illustration demonstrating a closed last-off circuit and a closed non-last-off circuit when considering a switching operation of a sub-branch semiconductor device according to the eighth embodiment, Fig. 25 a front view illustrating a common leg module according to the eighth embodiment, Fig. 26 a cross-sectional view extending along a line XXVI-XXVI of Fig. 25 taken, Fig. 27 a circuit diagram illustrating part of a power conversion device according to a ninth embodiment, Fig. 28 a circuit diagram illustrating a first wiring path and a second wiring path in the module body according to the ninth embodiment, Fig. 29 a front view illustrating a common upper branch module according to the ninth embodiment, and Fig. 30 a cross-sectional view extending along a line XXX-XXX from Fig. 29 has been taken. DETAILED DESCRIPTION OF PREFERRED EXAMPLES (First example)

[0012] With reference to Fig. 1, Fig. 2, Fig. 3 to Fig. Section 4 describes exemplary embodiments of a power conversion device.

[0013] As it is in Fig. Figure 1 shows a power conversion device 1 according to the first embodiment, comprising a high-potential line 11H, a low-potential line 11L, an upper-branch semiconductor device 2H connected to the high-potential line 11H, a lower-branch semiconductor device 2L, and a capacitor 3. The lower-branch semiconductor device 2L is connected in series with the upper-branch semiconductor device 2H. The capacitor 3 is connected between the high-potential line 11H and the low-potential line 11L.

[0014] At least one of the upper-branch semiconductor device 2H or the lower-branch semiconductor device 2L, connected in series, forms a parallel circuit body 20, which is provided with two or more switching elements connected in parallel. In the series-connected upper-branch semiconductor device 2H and the lower-branch switching semiconductor device 2L, a return flow element 21 is provided at least in an opposite side branch opposite the parallel circuit body 20 to allow current flow from the low-potential line 11L to the high-potential line 11H.

[0015] As it is in Fig. As shown in Figure 4, the plurality of switching elements 2 that form the parallel circuit body 20 are controlled such that their switch-off times differ. Among these switching elements 2 that form the parallel circuit body 20, a last-off element 22 and a non-last-off element 23 are identified. The last-off element 22 switches off last, and the non-last-off element 23 is the other switching element 2. In other words, within the plurality of switching elements 2 of the parallel circuit body 20, switch-off times for the switching elements are controlled such that a specific switching element 2 is controlled to switch off last. This specific switching element 2 is then designated as the last-off element 22, and the other switching element 2 is designated as the non-last-off element 23.

[0016] As it is in Fig. 2 and Fig. As shown in Figure 3, the closed last-off circuit 101 is defined as a closed circuit in which current flows through the last-off element 22, the return element 21 (contained in the opposite branch to the last-off element 22), and the capacitor 3. The closed non-last-off circuit 102 is defined as a closed circuit path in which current flows through the non-last-off element 23 (connected in parallel to the last-off element 22), the return element 21 (contained in the branch opposite to the last-off element 22), and the capacitor 3. The inductance of the closed last-off circuit 101 is smaller than the inductance of the closed non-last-off circuit 102.

[0017] As it is in Fig. As shown in Figure 1, in the power conversion device 1 according to the first embodiment, each of the upper-branch semiconductor device 2H and the lower-branch semiconductor device 2L forms the parallel circuit body. Furthermore, each parallel circuit body 20 is configured from two switching elements connected in parallel to each other. These two switching elements 2 are configured from different types of semiconductor devices. In particular, the switching elements 2 that form the parallel circuit body 20 are composed of SiC MOSFETs (i.e., metal-oxide-semiconductor field-effect transistors made of silicon carbide) and Si IGBTs (i.e., silicon-based insulated-gate bipolar transistors).

[0018] As it is in Fig. As shown in Figure 1, three legs are provided, each leg being configured with a parallel circuit body 20 composed of the upper branch semiconductor device 2H and a parallel circuit body 20 composed of the lower branch semiconductor device 2L, connected in series. Furthermore, the capacitor 3 and the three legs are connected in parallel between the high-potential line 11H and the low-potential line 11L. Each leg has the same configuration. In particular, the three legs between the upper branch semiconductor device 2H and the lower branch semiconductor device 2L are connected to respective phase electrodes of a three-phase rotating alternating current (AC) machine 42, namely a U-phase electrode, a V-phase electrode, and a W-phase electrode, via output wiring 12U, 12V, and 12W.It should be noted that the high-potential line 11H is connected to the positive electrode of the direct current (DC) power source 41, and the low-potential line 11L is connected to the negative electrode of the DC power source 41. Thus, the power conversion device 1 is configured to convert DC power from the DC power source 41 into three-phase AC power by switching the switching element 2 on or off, thereby driving the rotating electric machine 42. Furthermore, the power conversion device 1 is configured to convert the AC power generated by the rotating electric machine 42 into DC power as regenerative power.

[0019] According to the present embodiment, the last-off element 22 is configured as a MOSFET, and the non-last-off element 23 is configured as an IGBT. The MOSFET also includes a parasitic diode that serves as the reverse-flow element 21, allowing current to flow from the low-potential side 11L to the high-potential side 11H. Alternatively, the MOSFET can serve as the reverse-flow element 21 by performing synchronous rectification, in which the MOSFET is switched on during reverse operation. In either case, according to the present embodiment, a single MOSFET serves as both the last-off element 22 and the reverse-flow element 21.

[0020] As described, in the power conversion device 1, the respective switching elements 2 are controlled such that they are on and off at a predetermined time. The multitude of switching elements 2, which form the respective parallel circuit body 20, switch on and off approximately synchronously with each other. In other words, each branch of the parallel circuit body 20 of the multitude of switching elements 2 is configured such that the resistance value in the respective branches can be reduced, thereby reducing the circuit loss. As described in Fig. As shown in Figure 4, in each parallel circuit body, 20 switch-off times between two switching elements 2 are offset from one another. In particular, the last-off element 22 switches off after the non-last-off element 23 has switched off. Fig. Figure 4 shows the solid line S22 On-Off times (On-Off timing) of the last-off element 22 and shows the solid line S23 On-Off times (On-Off timing) of the non-last element 23.

[0021] According to the present embodiment, the plurality of switching elements 2, which form the parallel circuit body 20, are further controlled such that their switch-on times are offset from one another. Then, the last-off element 22 in the plurality of switching elements 2, which form the parallel circuit body 20, is controlled to switch on first. According to the present embodiment, as described in Fig. As shown in 4 (S22), the last-off element 22 turns on first and turns off last.

[0022] Therefore, immediately after the last-off element 22 is switched on and immediately before the last-off element 22 is switched off, current flows only through the last-off element 22 in the switching elements 2 of the parallel circuit body 20. Therefore, when the last-off element 22 switches on and off, a change in current occurs at the last-off element 22, which causes a recovery current or return current to flow through the last-off element 22 and the return element 21 in the opposite branch.

[0023] In this respect, a closed circuit 10U in the power conversion circuit is used for illustration. The closed circuit 10U is configured with a leg connected to the U-phase output wiring 12U, the high-potential line 11H, the low-potential line 11L, and the capacitor 3. The closed circuit 10U is in Fig. 2 and Fig. Figure 3 shows that a phenomenon similar to the closed circuit 10U described above will occur in a closed circuit configured with a leg connected to the V-phase output wiring 12V, the high-potential line 11H, the low-potential line 11L, and capacitor 3. Likewise, a similar phenomenon will occur in the closed circuit configured with a leg connected to the W-phase output wiring 12W, the high-potential line 11H, the low-potential line 11L, and capacitor 3.

[0024] For example, when the last-off element 22 of the upper-branch semiconductor device is switched off, a reverse current iF begins to flow through the reverse-flow element 21 (parasitic diode in the MOSFET according to the present embodiment) of the lower branch to return the energy stored in the inductance of the rotating electrical machine 42 to the power source 41. At this time, as described in Fig. As shown in Figure 2, a current change occurs in the closed circuit 10U, which connects the return element 21 of the lower branch semiconductor device 2L, the last-off element 22 of the upper branch semiconductor device 2H, the high-potential line 11H, the capacitor 3, and the low-potential line 11L. Thus, by reducing the inductance of the closed last-off circuit 101, a voltage surge due to the turn-off operation can be reduced. Furthermore, by reducing the inductance of the closed last-off circuit 101, a higher switching speed can be achieved, so that the switching loss due to the turn-off operation can also be reduced.

[0025] When the last-off element 22 of the upper-branch semiconductor device 2H is switched on, a reverse bias is applied to the return element 21 of the lower-branch semiconductor device 2L, through which current has flowed from the low-potential side 11L to the high-potential side 11H. Thus, a recovery current iR is instantaneously generated at the return element 21 of the lower-branch semiconductor device 2L, which flows to the low-potential side 11L. As shown in Fig. As shown in Figure 2, in the closed circuit 10U, the recovery current iR flows through a closed circuit that connects the reverse current element 21 of the lower branch semiconductor device 2L (parasitic diode of the MOSFET according to the present embodiment), the low-potential line 11L, the capacitor 3, the high-potential line 11H, and the last-off element 22 of the upper branch semiconductor device 2H in that order. In other words, the recovery current iR described above flows through the closed circuit, which is the same as the closed last-off circuit 101 described above, in a direction opposite to the reverse current iF. The surge voltage is then generated in response to a decrease in the recovery current. Therefore, lowering the inductance of the closed last-off circuit 101 is effective in reducing the surge voltage upon turn-on.

[0026] Thus, according to the present embodiment, reducing the inductance of the closed last-off circuit 101 is effective in lowering the switching losses of the last-off element 22 during turn-on and turn-off. In contrast, the inductance of the closed circuit 102, which includes the non-last-off element 23, i.e., the inductance of a closed circuit that runs through the return element 21 of the lower-branch semiconductor device 2L (parasitic diode of the MOSFET according to the present embodiment), the non-last-off element 23 of the upper-branch semiconductor device 2H, the high-potential line 11H, the capacitor 3, and the low-potential line 11L, rarely affects the switching loss.

[0027] In this respect, according to the present embodiment, the inductance of the closed last-off circuit 101 is set such that it is lower than that of the closed non-last-off circuit 102.

[0028] According to the present embodiment, when focusing on the switching operation of the sub-branch semiconductor device 2L, as described in Fig. As shown in Figure 3, the closed last-off circuit 101 is defined as a closed loop circuit comprising the last-off element 22 of the sub-branch semiconductor device 21 and the return element 21 (parasitic diode of the MOSFET according to the present embodiment) of the upper-branch semiconductor device 2H. The closed non-last-off circuit 102 is defined as a closed loop circuit comprising the non-last-off element 23 of the sub-branch semiconductor device 2L and the return element 21 (parasitic diode of the MOSFET according to the present embodiment) of the upper-branch semiconductor device 2H. Similarly, the relationship between them is defined such that the inductance of the closed last-off circuit 101 is smaller than that of the closed non-last-off circuit 102.

[0029] It should be noted that the turn-off time of switching element 2 is defined as the point in time at which a controlled current (i.e., current between drain and source or current between collector and emitter according to the present embodiment) flowing through switching element 2 is switched off. Switching element 2 repeatedly switches on and off in response to the on / off signal transmitted from the control unit. However, the turn-off time of switching element 2 does not coincide with the point in time at which the on / off signal switches off from the on state. In other words, the controlled current is switched off when the on / off signal from the control unit switches off from the on state and the gate voltage of switching element 2 begins to decrease to reach a predetermined threshold. This point in time is referred to as the turn-off time of switching element 2.

[0030] In contrast, the turn-on time of the switching element 2 is defined as the point in time at which the controlled current (i.e., current between drain and source or current between collector and emitter according to the present embodiment) begins to flow through the switching element 2. Likewise, the turn-on time of the switching element 2 does not necessarily coincide with the point in time at which the on / off signal from the control unit turns on from the off state. In particular, when the on / off signal turns on from the off state and the gate voltage applied to the switching element 2 begins to increase to reach a predetermined threshold, the controlled current begins to flow. This point in time is referred to as the turn-on time of the switching element 2.

[0031] Accordingly, the off-signal times for the non-last-off element 23 and the last-off element 22 from the control unit can be set to be the same by setting the gate resistance value of the non-last-off element 23 to be lower than that of the last-off element 22. It becomes clear that the off-signal time for the last-off element 22 from the control unit can be delayed relative to the off-signal for the non-last-off element 23.

[0032] The effects and advantages of the present embodiment are described below. In the power conversion device 1 described above, the inductance of the closed last-off circuit 101 is set such that it is smaller than that of the closed non-last-off circuit 102. Thus, the switching loss can be effectively reduced.

[0033] In a circuit configuration of the power conversion device 1 described above, a reverse current iF begins to flow through a reverse current element 21 in a branch opposite to the last-off element 22 when the last-off element 22 switches off. This results in a current change across the closed last-off circuit 101. The voltage spike caused by the reverse current iF flowing through the closed last-off circuit 101 is reduced to minimize the switching loss. In this respect, the inductance of the closed last-off circuit 101 in the power conversion device 1 is set to be smaller than that of the closed non-last-off circuit 102. Thus, the switching loss can be effectively reduced.

[0034] Furthermore, the last-off element 22 is controlled such that it is switched on first among the multitude of switching elements 2 that form the parallel circuit body 20. This effectively reduces the voltage surge upon switch-on.

[0035] The multitude of switching elements 2, which form the parallel circuit body 20, is configured from a SiC MOSFET and a Si IGBT. Thus, two types of semiconductor elements are used to effectively reduce switching losses, thereby reducing losses in the branches.

[0036] In particular, according to the present embodiment, the last-off element 22 is configured as a SiC MOSFET. This is because the last-off element 22 uses a SiC MOSFET, which can achieve a fast switching speed (on-off time), thus further reducing the switching loss. In contrast, a residual current flows in the Si IGBT device when it turns off. Accordingly, switching losses due to residual current can be reduced if a Si IGBT is not used for the last-off element 22. Similarly, a Si IGBT is used for the non-last-off element 23, and a SiC MOSFET is used for the last-off element 22, thereby reducing switching losses more effectively.

[0037] As described above, according to the present embodiment, a power conversion device can be provided which is capable of effectively reducing switching losses.

[0038] It should be noted that, unlike the first embodiment described above, the last-off element can be configured as a Si IGBT and the non-last-off element as a SiC MOSFET. In this case, the SiC MOSFET can be used as an auxiliary switching element 2. Thus, since the size of a relatively expensive SiC MOSFET can be easily reduced, a cost reduction of the power conversion device can be achieved. Conversely, since the last-off element is configured as a Si IGBT, the switching loss is likely to be a problem. However, by using a configuration in which the inductance of the closed last-off circuit is set to be smaller than that of the closed non-last-off circuit, the switching loss can be reduced.This means that if the last-off element is configured from a Si-IGBT and the non-last-off element is configured from a SiC-MOSFET, an increase in switching loss can be suppressed and a cost reduction can also be achieved.

[0039] According to the first embodiment described above, two switching elements 2 are connected in parallel to form the parallel circuit body. The parallel circuit body can be configured with three or more switching elements 2 connected in parallel. In this case as well, one switching element 2 that switches off last among the three or more switching elements 2 is designated as the last-off element, and the remaining two or more switching elements 2 are designated as non-last-off elements. The switch-off times among the two or more non-last-off elements can be offset from each other. In this case, the inductance of the closed circuit path passing through the non-last-off element is preferably adjusted such that the slower the switch-off times of the non-last-off element, the lower the inductance of the closed circuit. (Second embodiment)

[0040] According to the second embodiment, as described in Fig. As shown in Figure 5, the switch-off time of the last-off element 22 is controlled such that it is shifted to a time earlier than the switch-on time of the non-last-off element 23. It should be noted that the switch-off time of the last-off element 22 is the same as that according to the first embodiment, in which the switch-off time of the last-off element 22 is set to a time later than the switch-off time of the non-last-off element 23. It should be noted that the same reference numerals used in previous embodiments represent similar elements as in the previous embodiments, unless otherwise specified.

[0041] According to the present embodiment, the switching loss during turn-on is not reduced; however, the switching loss during turn-off can be effectively reduced, similar to the first embodiment. For the switching loss, a change in current during turn-off significantly influences the switching loss. Thus, assuming that the switching loss during turn-off can be reduced, the power loss of the power conversion device 1 according to the second embodiment can also be effectively reduced.

[0042] A recovery current in the reverse current element 21 during switch-on can be suppressed by using a Schottky blocking diode or the like. In particular, a sufficient breakdown voltage can be ensured and a recovery current can be suppressed more effectively by using a Schottky blocking diode made of SiC. In this case, similar to the present embodiment, without considering the switching loss during switch-on, a power loss in the power conversion device 1 can be sufficiently reduced by adjusting the switch-off time and the inductance of the closed last-off circuit 101.

[0043] Furthermore, control can be implemented in such a way that the switch-on times of the last-off element and the non-last-off element are set so that they are the same. (Third embodiment)

[0044] According to the third embodiment, as described in Fig. 6, Fig. 7 to Fig. As shown in Figure 8, a diode 210 other than the switching element 2 is used as a reverse-flow element 21. In particular, the diode 210 is connected in reverse parallel to the MOSFET and the IGBT, which form the parallel body 20.

[0045] For diode 210, a PIN diode made of Si or a Schottky blocking diode made of SiC can be used.

[0046] As it is in Fig. 7 and Fig. As shown in Figure 8, according to the present embodiment, the closed last-off circuit 101 is defined as a closed circuit path that passes through the last-off element 22, the diode 210, which is arranged in a branch opposite to the last-off element 22, and the capacitor 3. The closed non-last-off circuit 102 is defined as a closed circuit path that passes through the non-last-off element 23, which is connected in parallel to the last-off element 22, the diode 210, which is arranged in a branch opposite to the last-off element 22, and the capacitor 3.

[0047] In particular, when focusing on the switching operation of the upper branch semiconductor device 2H, as described in Fig. Figure 7 shows that the closed last-off circuit 101 is defined as a closed circuit comprising the last-off element 22 of the upper-branch semiconductor device 2H and the diode 210 of the lower-branch semiconductor device 2L. Furthermore, the closed non-last-off circuit 102 is defined as a closed circuit comprising the non-last-off element 23 of the upper-branch semiconductor device 2H and the diode 210 of the lower-branch semiconductor device 2L.

[0048] In contrast, if the focus is on the switching operation of the sub-branch semiconductor device 2L, as described in Fig. As shown in Figure 8, the closed last-off circuit 101 is defined as a closed circuit comprising the last-off element 22 of the sub-branch semiconductor device 2L and the diode 210 of the upper-branch semiconductor device 2H. Furthermore, the closed non-last-off circuit 102 is defined as a closed circuit comprising the non-last-off element 23 of the sub-branch semiconductor device 2L and the diode 210 of the upper-branch semiconductor device 2H. Similar to the first embodiment, the inductance of the closed last-off circuit 101 is smaller than that of the closed non-last-off circuit 102. Other configurations are the same as those shown in the first embodiment.

[0049] Similarly, according to the present embodiment, practical effects similar to those of the first embodiment can be obtained. It should be noted that an RC-IGBT, in which an IGBT and a diode are integrated as a single element, can be used to achieve a similar circuit configuration to that of the present embodiment. (Fourth example)

[0050] As it is in Fig. As shown in Figure 9, a power conversion device 10 according to the fourth embodiment provides a converter comprising an upper-branch semiconductor device 2H and a lower-branch semiconductor device 2L. The upper-branch semiconductor device 2H and the lower-branch semiconductor device 2L are each configured, similarly to the first embodiment, from a parallel circuit body 20 in which two switching elements 2 are connected in parallel. The two switching elements 2 are a MOSFET and an IGBT.

[0051] The parallel circuit body 20 of the upper branch semiconductor device 2H and the parallel circuit body 20 of the lower branch semiconductor device 2L are connected in series. One leg is composed of two parallel circuit bodies 20 connected in series. This leg is connected in parallel to the capacitor 3 between the high-potential line 11H and the low-potential line 11L.

[0052] The wiring between the upper branch semiconductor device 2H and the lower branch semiconductor device 2L is connected via an inductor 43 to the positive electrode of a DC power source 410. A filter capacitor 44 is provided such that one end of it is connected between the inductor 43 and the positive electrode of the DC power source 410, and the other end is connected to the low-potential line 11L. The power conversion device 10 according to the present embodiment controls the upper and lower branch semiconductor devices 2H and 2L such that they are switched on and off appropriately, thereby raising the voltage of the DC power source 410, and the raised voltage is output to an electrical load (not shown) connected between the high-potential line 11H and the low-potential line 11L.Furthermore, the power conversion device 10 reduces a high voltage supplied from the electrical load side. An inverter and a rotating electrical machine, as introduced according to the first embodiment, can be connected to the power conversion device as the electrical load.

[0053] Similarly, in the power conversion device 10 according to the present embodiment, the inductance of the closed last-off circuit 101 with the last-off element 22 is smaller than the inductance of the closed non-last-off circuit 102 with the non-last-off element 23. It should be noted that Fig. Figure 9 illustrates an example of the closed last-off circuit 101 and the closed non-last-off circuit 102, which should be used for comparison. Other configurations are the same as those according to the first embodiment, and similar operational effects can be obtained.

[0054] Similar to the embodiments described above, the present embodiment can be modified in various ways such that the parasitic diode of a MOSFET, a MOSFET used for synchronous rectification, a diode connected in parallel to the switching element 2, or a diode contained in an RC-IGBT can be used as the backflow element 21. (Fifth example)

[0055] As it is in Fig. As shown in Figure 10, the power conversion device 10 according to the present embodiment is configured such that the upper branch semiconductor device 2H is composed of a diode 210 as the return element 21. In other words, only the diode 210 is provided in the upper branch without the switching element 2. The lower branch semiconductor device 2L is configured as a parallel circuit body 20, which is composed of two switching elements 2. The power conversion device 10 according to the present embodiment serves as a converter that performs only a boost operation. The power conversion device 10 according to the present embodiment can be used as a boost converter for fuel cell batteries.

[0056] According to the present embodiment, the closed last-off circuit 101 is a closed circuit comprising the last-off element 22, which is contained in the parallel circuit body 20, the diode 210 as the upper-branch semiconductor device 2H, and the capacitor 3. The closed non-last-off circuit 102 is a closed circuit comprising the non-last-off element 23, which is contained in the parallel circuit body 20, the diode 210 as the upper-branch semiconductor device 2H, and the capacitor 3.

[0057] For diode 210, a PIN diode made of silicon or a Schottky blocking diode made of silicon carbide (SiC) can be used, for example. Alternatively, a MOSFET or the like can be used for diode 210. Other configurations are the same as those according to the first embodiment. The present embodiment achieves the same practical effects as the first embodiment. (Sixth embodiment example)

[0058] As it is in Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15 to Fig. As shown in Figure 16, according to the sixth embodiment, the switching elements 2 and the return element 21 are mounted on the semiconductor module (52H, 53H, 52L, 53L). In particular, according to the present embodiment, the last-off element 22, the non-last-off element 23, and the return element 21 are mounted on the semiconductor module. As shown in Figure 16, the switching elements 2 and the return element 21 are mounted on the semiconductor module. Fig. 11, Fig. 12 to Fig. As shown in Figure 13, the last-off element 22 and the non-last-off element 23 are attached to the last-off module 52 and the non-last-off module 53, which are independent modules, meaning they are independent of each other. In other words, a semiconductor module on which the last-off element 22 is attached is the last-off module 52, and a semiconductor module on which the non-last-off element 23 is attached is the non-last-off module 53.

[0059] According to the present embodiment, both the upper branch semiconductor device 2H and the lower branch semiconductor device 2L are mounted on the upper branch module 5H and the lower branch module 5L, which are independent semiconductor modules. In other words, the last-off element 22 of the upper branch semiconductor device 2H, the non-last-off element 23 of the upper branch semiconductor device 2H, and the last-off element 22 of the lower branch semiconductor device 2L are mounted on independent semiconductor modules.According to the present embodiment, the semiconductor module on which the last-off element 22 of the upper-branch semiconductor device 2H is mounted is designated as a semiconductor module 52H, the semiconductor module on which the non-last-off element 23 of the upper-branch semiconductor device 2H is mounted is designated as a semiconductor module 53H, the semiconductor module on which the last-off element 22 of the lower-branch semiconductor device 2L is mounted is designated as a semiconductor module 52L, and the semiconductor module on which the non-last-off element 23 of the lower-branch semiconductor device 2L is mounted is designated as a semiconductor module 53L.

[0060] The closed last-off circuit 101 and the closed non-last-off circuit 102 each comprise semiconductor modules, capacitor 3, and busbars 61, 62, and 63. The total inductance of the busbars 61, 62, and 63 contained in the closed last-off circuit 101 is less than that of the busbars 61, 62, and 63 contained in the closed non-last-off circuit 102. It should be noted that the closed last-off circuit 101 and the closed non-last-off circuit 102, which are in Fig. Figure 11 shows the closed last-off circuit and the closed non-last-off circuit, respectively, which should be compared when focusing on the switching operation of the last-off element 22 of the upper branch semiconductor device 2H.

[0061] The upper branch module 5H and the lower branch module 5L are connected to each other by means of an intermediate busbar 63. Furthermore, the upper branch module 5H is connected to the capacitor 3 by means of a high-potential busbar 61, which forms the high-potential line 11H. The lower branch module 5L is connected to the capacitor 3 by means of a low-potential busbar 62, which forms the low-potential line 11L. The total inductance of the high-potential busbar 61, the low-potential busbar 62, and the intermediate busbar 63 contained in the closed last-off circuit 101 is less than the total inductance of the high-potential busbar 61, the low-potential busbar 62, and the intermediate busbar 63 contained in the closed non-last-off circuit 102.

[0062] As it is in Fig. As shown in Figure 11, the inductance of the high-potential busbar 61 contained in the closed last-off circuit 101 is defined as L11, the inductance of the low-potential busbar 62 contained in the closed last-off circuit 101 is defined as L12, and the inductance of the intermediate busbar 63 contained in the closed last-off circuit 101 is defined as L13. Furthermore, the inductance of the high-potential busbar 61 contained in the closed non-last-off circuit 102 is defined as L21, the inductance of the low-potential busbar 62 contained in the closed non-last-off circuit 102 is defined as L22, and the inductance of the intermediate busbar 63 contained in the closed non-last-off circuit 102 is defined as L23. The relationship L11 + L12 + L13 < L21 + L22 + L23 is satisfied.In particular, according to the present embodiment, the conditions L11 < L21 and L13 < L23 are satisfied. In the respective closed circuits, although inductance may be present at other locations, inductance is present at L11 < L21. Fig. Figure 11 merely illustrates the focused inductance components. The same applies to other figures.

[0063] The specific structure of the power conversion device 1 according to the present embodiment is in Fig. 12, Fig. 13, Fig. 14, Fig. 15 to Fig. 16 illustrates how it is in Fig. As shown in Figure 14, the power conversion device 1 is equipped with the semiconductor modules 52H, 53H, 52L and 53L, which are arranged therein. As shown in Fig. 12, Fig. 13, Fig. 14, Fig. 15 to Fig. As shown in Figure 16, each of the semiconductor modules is configured from a module body 550, which is shaped in a card form, and two power terminals 551 and 552, which project from the module body 550 in a direction perpendicular to its thickness direction X. Furthermore, as shown in Fig. 12 and Fig. As shown in Figure 13, the semiconductor module has a control terminal 54 that projects from the module body 550 on a side opposite the power terminals 551 and 552. It should be noted that, for simplicity, the direction in which the control terminal 54 and the power terminals 551 and 552 project is defined as a height direction Z. Furthermore, for simplicity, a direction perpendicular to both the thickness direction X and the height direction Z is defined as a width direction Y.

[0064] As it is in Fig. As shown in Figure 14, two upper branch modules 5H, that is, the semiconductor modules 52H and 53H, are arranged in the thickness direction X. Furthermore, two lower branch modules 5L, that is, the semiconductor modules 52L and 53L, are arranged in the thickness direction X.

[0065] In contrast, two last-off modules 52, that is, the semiconductor modules 52H and 52L, are arranged in the lateral direction Y. Furthermore, two non-last-off modules 53, that is, the semiconductor modules 53H and 53L, are arranged in the lateral direction Y. Furthermore, two non-last-off modules 53, that is, the semiconductor modules 53H and 53L, are arranged in the lateral direction Y.

[0066] Capacitor 3 is arranged such that it is layered on these semiconductor modules 52H, 53H, 52L, and 53L in the thickness direction X. The semiconductor modules 52H and 52L beneath the four semiconductor modules 52H, 53H, 52L, and 53L described above—that is, the last-off modules 52—are arranged closer to capacitor 3 compared to the locations where semiconductor modules 53H and 53L—that is, the non-last-off modules 53—are arranged. In other words, the last-off modules 52 are arranged closer to capacitor 3 compared to the locations of the non-last-off modules 53, which are connected in parallel to the last-off modules 52.

[0067] As it is in Fig. 15 and Fig. As shown in Figure 16, the semiconductor modules 52H, 53H, 52L, and 53L are connected to the capacitor 3 via the power terminals 551 and 552, respectively, through the high-potential bus 61 and the low-potential bus 62. Furthermore, the upper branch module 5H (52H, 53H) and the lower branch module 5L (52L, 53L) are connected via the output bus 63 via the power terminals 552 and 551, respectively. As described, the last-off modules 52 (52H, 52L) are located closer to the capacitor 3 compared to the last-off modules 53 (53H, 53L).

[0068] Accordingly, the length of a current path between the last-off modules 52 (52H, 52L) and the capacitor 3 via the high-potential busbar 61 is shorter than the distance of a current path between the non-last-off modules 53 (53H, 53L) and the capacitor 3 via the high-potential busbar 61. Likewise, the distance of a current path between the last-off modules 52 (52H, 52L) and the capacitor 3 via the low-potential busbar 62 is shorter than the distance of a current path between the non-last-off module 53 (53H, 53L) and the capacitor 3 via the low-potential busbar 62.

[0069] As it is in Fig. 14 and Fig. As shown in Figure 15, the semiconductor modules 52H, 53H, 52L, and 53L are stacked in the thickness direction X together with cooling tubes 71, which cool the semiconductor modules 52H, 53H, 52L, and 53L. Each of the semiconductor modules 52H, 53H, 52L, and 53L contacts the cooling tubes 71 at both of their larger surfaces in the thickness direction X. The cooling tubes 71 are coupled to each other near each other at both ends in the width direction Y. Furthermore, the cooling tube 71, which is provided on one side in the stacking direction (i.e., the thickness direction X), has a coolant inlet tube 721, which introduces a coolant, and a coolant outlet tube 722, which ejects the coolant. The capacitor 3 contacts the cooling tube 71, which is provided on one side in the stacking direction. Capacitor 3 is located adjacent to semiconductor modules 52H and 52L via cooling tube 71.

[0070] In Fig. 14 and Fig. Figure 15 illustrates only the semiconductor modules 52H, 53H, 52L, and 53L that form one leg of the power conversion device 1. The semiconductor modules 52H, 53H, 52L, and 53L, which form the other two legs, can be viewed on the opposite side with respect to the one shown in Figure 15. Fig. 14 and Fig. The layering shown in 15 in the thickness direction X above the capacitor 3 is layered in between. Similar to the one in Fig. 14 and Fig. In the semiconductor modules 52H, 53H, 52L, and 53L shown in Figure 15, the semiconductor modules 52H, 53H, 52L, and 53L, which form the other two legs, can be stacked alternately with the cooling tubes 71. Furthermore, for these semiconductor modules 52H, 53H, 52L, and 53L, the last-off module 52 (52H, 52L) is located closer to the capacitor 3 than the non-last-off module 53 (53H, 53L) among the semiconductor modules 52H, 53H, 52L, and 53L, which forms the common leg. Other configurations are the same as according to the first embodiment.

[0071] According to the present embodiment, the inductances of the busbars 61, 62, 63 between the semiconductor modules and the capacitor 3 can be adjusted such that the inductance of the closed last-off circuit 101 is smaller than that of the closed non-last-off circuit 102. Therefore, it is not necessary to adjust inductances in the internal structure of the semiconductor module; for example, it is not necessary to adjust for differences in the inductances within the semiconductor module. In other words, the structures of the respective semiconductor modules 52H, 53H, 52L, 53L can be approximately the same.Furthermore, the inductances of the current paths are set such that they differ between the high potential current rail 61 and the low potential current rail 62, whereby the inductance of the closed last-off circuit 101 can easily be made small without complicating the wiring of the current rails 61, 62 and 63.

[0072] The last-off module 52 is arranged such that it is closer to the capacitor 3 than the non-last-off module 53. Thus, the semiconductor modules 52H, 53H, 52L, and 53L are arranged in a suitable manner, thereby readily reducing the inductance of the closed last-off circuit 101. Additionally, similar practical effects to those of the first embodiment can be obtained. (Seventh example)

[0073] As it is in Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21 to Fig. As shown in Figure 22, according to the seventh embodiment, the upper branch semiconductor devices 2H and the lower branch semiconductor devices 2L are mounted on common modules 520 and 530, in which these upper and lower branch semiconductor devices are mounted together on the same semiconductor module.

[0074] The common modules 520 and 530 are connected to the capacitor 3 via the high-potential busbar 61, which forms the high-potential line 11H, and the low-potential busbar 11L, which forms the low-potential line 11L. The total inductance of the high-potential busbar 61 and the low-potential busbar 62 contained in the closed last-off circuit 101 is less than the total inductance of the high-potential busbar 61 and the low-potential busbar 62 contained in the closed non-last-off circuit 102.

[0075] As it is in Fig. 17 and Fig. As shown in Figure 18, the inductance of the high-potential busbar 61 between the capacitor 3 and the common module 520, in which the last-off element 22 is located, is defined as L11. The inductance of the low-potential busbar 62 between the capacitor 3 and the common module 520, in which the last-off element 22 is located, is defined as L12. The inductance of the high-potential busbar 61 between the capacitor 3 and the common module 530, in which the non-last-off element 23 is located, is defined as L21. The inductance of the low-potential busbar 62 between the capacitor 3 and the common module 530, in which the non-last-off element 23 is located, is defined as L22.

[0076] As it is in Fig. As shown in Figure 17, when considering the closed last-off circuit 101 and the closed non-last-off circuit 102, which should be compared when focusing on the switching operation of the upper branch semiconductor device 2A, a condition of L11 + L12 < L21 + L12 is satisfied. Furthermore, as shown in Fig. Figure 18 shows that when considering the closed last-off circuit 101 and the closed non-last-off circuit 102, which should be compared when focusing on the switching operation of the sub-branch semiconductor device 2L, a condition L11 + L12 < L11 + L22 is satisfied. Thus, when considering this overall, a condition L11 < L21 and L12 < L22 is preferably satisfied.

[0077] As it is in Fig. 19, Fig. 20 to Fig. As shown in Figure 21, the common modules 520 and 530 are equipped with the upper-branch semiconductor devices 2H and the lower-branch semiconductor devices 2L. Each common module 520 and 530 also has a high-potential terminal 55H and a low-potential terminal 55L as power terminals, and furthermore an output terminal 553. The high-potential terminal 55H is connected to the upper-branch semiconductor device 2H in the module body 550. The low-potential terminal 55L is connected to the lower-branch semiconductor device 2L in the module body 550. The output terminal 553 is connected to both the upper-branch semiconductor device 2H and the lower-branch semiconductor device 2L. The high-potential terminal 55H, the low-potential terminal 55L, and the output terminal 553 are designed to project from the module body 550.

[0078] The high-potential connection 55H, the low-potential connection 55L, and the output connection 553 extend from the module body 550 in the same direction in the vertical direction Z. Furthermore, as shown in Fig. As shown in Figure 21, in the common module 520, the upper branch semiconductor device 2H is arranged between two electrode plates 554 and 555, which are arranged such that they face each other via a spacer 56. Similarly, the lower branch semiconductor device 2L is arranged between two electrode plates 556 and 557, which are arranged such that they face each other via a spacer 56. The electrode plates 554 and 556, as well as the switching element 2, the switching element 2 and the spacer 56, and the electrode plates 555 and 557 are connected to each other by soldering. Thus, one layering structure (i.e., a layering) is composed of the upper branch semiconductor device 2H and two electrode plates 554 and 555 and the spacer 56, and another layering is composed of the lower branch semiconductor device 2L and two electrode plates 556 and 557 and the spacer 56.

[0079] Two pairs of layers are integrated into a resin section 57 to form a single common module 520. One electrode plate 554, layered on the upper branch semiconductor device 2A, is connected to the high-potential terminal 55H. One electrode plate 557, layered on the lower branch semiconductor device 2L, is connected to the low-potential terminal 55L. The other electrode plate 555, layered on the upper branch semiconductor device 2H, and the other electrode plate 556, layered on the lower branch semiconductor device 2L, are electrically connected to each other. These plates are electrically connected to the output terminal 553.

[0080] The four electrode plates 554, 555, 556, and 557 described above are exposed to both principal surfaces of the common module 520 in the thickness direction X and serve as heat-radiating plates. It should be noted that electrode plate 554, which is connected to the high-potential terminal 55H, and electrode plate 557, which is connected to the low-potential terminal 55L, are exposed to opposite surfaces of the common module 520. Furthermore, two electrode plates 555 and 556, which are electrically connected to the output terminal 553, are exposed to opposite surfaces of the common module 520. In addition, the other common module 530 has a similar structure to the common module 520 described above, except that the type of semiconductor element differs from that of the common module 520.

[0081] The common modules 520 and 530 are present, with each module forming one leg. Among these is, as shown in Fig. As shown in Figure 19, a common module 520 is the last-off module 52, to which the last-off element 22 is attached, and, as shown in Fig. As shown in Figure 20, the other common module 530 is the non-last-off module 53, to which the non-last-off element 23 is attached. As shown in Fig. As shown in Figure 22, the power conversion device 1 is configured from two common modules 520 and 530, which are stacked in the thickness direction X. The common module 520, as the last-off module 52, is closer to the capacitor 3 than the common module 520, as the non-last-off module 53. Other configurations are the same as those according to the sixth embodiment.

[0082] According to the present embodiment, since the upper-branch semiconductor device 2H and the lower-branch semiconductor device 2L are mounted on a corresponding common module, that is, the common module 520 or 530, the size of the power conversion device 1 can be readily reduced. Furthermore, the last-off element 22 and the return-flow element 21 in the opposite branch are mounted on a single common module 520, 530, so that the inductance of the closed last-off circuit 101 can be effectively minimized. Moreover, according to the present embodiment, operational effects are achieved that are similar to those according to the sixth embodiment. (Eighth example)

[0083] According to the eighth embodiment, as described in Fig. 23, Fig. 24, Fig. 25 to Fig. Figure 26 shows semiconductor elements in two parallel circuit bodies 20 forming one leg, attached to a common leg module 500.

[0084] According to the present embodiment, as shown in Fig. As shown in Figure 23, the parallel body 20 of the upper branch semiconductor device 2H comprises the last-off element 22, the non-last-off element 23, and the return element 21. The parallel body 20 of the lower branch semiconductor 2L comprises the last-off element 22, the non-last-off element 23, and the return element 21. The last-off element 22, the non-last-off element 23, and the return element 21 in the upper branch semiconductor device 2H and the last-off element 22, the non-last-off element 23, and the return element 21 in the lower branch semiconductor device 2L are mounted on the common leg module 500 as a single common semiconductor module. It should be noted that a MOSFET serves as the last-off element 22 and the return element 21.

[0085] As it is in Fig. As shown in Figure 25, the common leg module 500 is configured such that the high potential terminal 55H, which is connected to the upper branch semiconductor device 2H, the low potential terminal 55L, which is connected to the lower branch semiconductor device 2L, and the output terminal 553, which is connected to the upper branch semiconductor device 2H and the lower branch semiconductor device 2L, project from the module body 550.

[0086] Two wiring paths 501 and 502 in the module body 550 are described below. Specifically, the first wiring path 501 is defined as a path connecting the high-potential terminal 55H and the low-potential terminal 55L, passing through the last-off elements 22 and the return element 21, which belong to opposite branches. The second wiring path 502 is defined as a path connecting the high-potential terminal 55H and the low-potential terminal 55L, passing through the non-last-off elements 23 and the return element 21, which belong to opposite branches. In this respect, the total inductance of the first wiring path 501 is adjusted to be less than the total inductance of the second wiring path 502.

[0087] As it is in Fig. As shown in Figure 23, when focusing on the switching operation of the upper branch semiconductor device 2H, the inductance of the first wiring path 501 can be expressed by L15 + L16 + L17. The second wiring path 502 can be expressed by L25 + L26 + L17. That is, L15 + L16 + L17 < L25 + L26 + L17. In particular, according to the present embodiment, L15 < L25, L16 < L26.

[0088] L15 is defined as an inductance between the high-potential terminal 55H and the last-off element 22 of the upper-branch semiconductor device 2H. L16 is defined as an inductance of a wiring connection from the last-off element 22 of the upper-branch semiconductor device 2H to the return element 21 of the lower-branch semiconductor device 2L via the electrode plates 555 and 556, which have the same potential as that of the output terminal 553. L17 is defined as an inductance of a wiring connection between the return element 21 of the lower-branch semiconductor device 2L and the low-potential terminal 55L. L25 is defined as an inductance of a wiring connection between the high-potential terminal 55H and the last-off element 22 of the upper-branch semiconductor device 2H.L26 is defined as an inductance of a wiring from the non-last-off element 23 of the upper branch semiconductor device 2H to the return element 21 of the lower branch semiconductor device 2L via the electrode plates 555 and 556, which have the same potential as that of the output terminal 553.

[0089] The following is a case with reference to Fig. Figure 24 describes the switching operation of the sub-branch semiconductor device 2L. In this case, the inductance of the first wiring path 501 can be expressed as L15 + L16 + L17. The inductance of the second wiring path 502 can be expressed as L15 + L28 + L27. This means that L15 + L16 + L17 < L15 + L28 + L27 is satisfied. In particular, according to the present embodiment, L16 < L28 and L16 < L26 are satisfied.

[0090] It should be noted that L15 is the inductance of a wiring connection between the high-potential terminal 55H and the return element 21 of the sub-branch semiconductor device 2H. L16 is defined as an inductance from the return element 21 of the upper-branch semiconductor device 2H to the last-off element 22 of the sub-branch semiconductor device 2L via the electrode plates 555 and 526, which have the same potential as that of the output terminal 553. L17 is defined as the inductance of a wiring connection between the last-off element 22 of the sub-branch semiconductor device 2L and the low-potential terminal 55L. L27 is defined as the inductance of the wiring connection between the non-last-off element 23 of the sub-branch semiconductor device 2L and the low-potential terminal 552.L28 is defined as the inductance of the wiring from the return element 21 of the upper branch semiconductor device 2H to the non-last-off element 23 of the lower branch semiconductor device 2L via the electrode plates 555 and 556, which have the same potential as that of the output terminal 553. It should be noted that L15, L16, and L17 are similar between the case when the focus is on the switching operation of the lower branch semiconductor device 2L and the case when the focus is on the switching operation of the upper branch semiconductor device 2H, so the same reference numerals are used.

[0091] As described, in the module body 550 of the common leg module 500, the inductance of the current path passing through the last-off element 22 and the return element 21, and the inductance of the current path passing through the non-last-off element 23 and the return element 21, are set such that they are different from each other.

[0092] As it is in Fig. 25 and Fig. As shown in Figure 26, the common leg module 500 has four switching elements 2, which form two pairs of parallel circuit bodies 20. In other words, the module body 550 of the common leg module 500 has two pairs of parallel circuit bodies 20, each comprising the last-off element 22 and the non-last-off element 23. The last-off element 22 and the non-last-off element 23, which form the parallel circuit body 20 of the upper branch semiconductor device 2H, are connected in parallel by means of the electrode plates 554 and 555. The last-off element 22 and the non-last-off element 23, which form the parallel circuit body 20 of the lower branch semiconductor device 2L, are connected in parallel by means of the electrodes 556 and 557.

[0093] The common leg module 500 has two last-off elements 22 and two non-last-off elements 23 arranged along a single direction. Specifically, the two last-off elements 22 and the two non-last-off elements 23 are arranged in a single row in the width direction Y. The two last-off elements 22 are positioned between the non-last-off elements 23. Since the return element 21 is configured from part of the MOSFET together with the last-off element 22, the return elements 21 are also located between the two non-last-off elements 23.

[0094] Similar to the common modules 520 and 530 shown according to the seventh embodiment, jump as shown in Fig. As shown in Figure 25, in the common leg module 500, the high-potential connection 55H, the low-potential connection 55L, and the output connection 553 extend from the module body 550 in the same direction in the vertical direction Z. However, the high-potential connection 55H and the low-potential connection 55L are located closer to the center of the module body 550 in the horizontal direction Y than the output connection 553. In particular, the high-potential connection 55H and the low-potential connection 55L are located closer to the center of the module body 550 in the horizontal direction Y than the two non-last-off elements 23. When viewed from the thickness direction X, the high potential terminal 55H is located in a position that overlaps the last-off element 22 of the upper branch semiconductor device 2H in the height direction Z, and the high potential terminal 55L is located in a position that overlaps the last-off element 22 of the lower branch semiconductor device 2L in the height direction Z.

[0095] With this arrangement, a current path through the high-potential terminal 55H, the last-off element 22 of the upper-branch semiconductor device 2H, the return-flow element 21 contained in the last-off element 22 of the lower-branch semiconductor device 2L, and the low-potential terminal 55L can be effectively shortened. Thus, the inductance of this current path can be reduced. This current path is defined as the first wiring path 501 described above. Accordingly, it is likely that the inductance of the closed last-off circuit 101 will be reduced.

[0096] Similarly, a current path can be effectively shortened by passing through the high-potential terminal 55H, the return flow element 21 contained in the last-off element 22 of the sub-branch semiconductor device 2H, the last-off element 22 of the sub-branch semiconductor device 2L, and the low-potential terminal 55L. Other configurations are similar to those according to the first embodiment.

[0097] According to the present embodiment, since the semiconductor elements contained in the two parallel circuit bodies 20 forming one leg are attached to the common leg module 500 as a single semiconductor module, the power conversion device 1 can be smaller. Furthermore, the last-off element 22 and the return-flow element 21 in the opposite branch are attached to a common leg module 500, which effectively reduces the inductance of the closed last-off circuit 101.

[0098] Furthermore, the inductance of the current path forming part of the closed last-off circuit 101 is reduced in the common module 500. Thus, when assembling the power conversion device 1, the inductance of the closed last-off circuit 101 can be readily reduced. Additionally, two last-off elements 22 are arranged between two non-last-off elements 23. With this arrangement, as described above, the inductance of the closed last-off circuit 101 can be effectively reduced. Moreover, similar operational effects to those of the first embodiment can be obtained. (Ninth example)

[0099] As it is in Fig. 27, Fig. 28, Fig. 29 to Fig. As shown in Figure 30, according to the ninth embodiment, a parallel circuit body 20 is attached to a common semiconductor module, that is, a common upper branch module 50H and a common lower branch module 50L.

[0100] As it is in Fig. As shown in Figure 27, the parallel body 20 of the upper branch semiconductor device 2H comprises the last-off element 22, the non-last-off element 23, and the return element 21. The parallel body 20 of the lower branch semiconductor device 2L comprises the last-off element 22, the non-last-off element 23, and the return element 21. The last-off element 22, the non-last-off element 23, and the return element 21 of the upper branch semiconductor device 2L are attached to the common upper branch module 50H as a single common semiconductor module. The last-off element 22, the non-last-off element 23, and the return element 21 of the lower branch semiconductor device 2L are attached to the common lower branch module 50L as a single common semiconductor module.

[0101] As it is in Fig. As shown in Figure 29, each of the common upper branch module 50H and the common lower branch module 50L is configured such that two power terminals 551 and 552 project from the module body 550. In the module body 550, as shown in Fig. As shown in Figure 28, the following wiring paths 503 and 504 are taken into account. The first wiring path 593 connects two power terminals 551 and 552 via the last-off element 22. The second wiring path 504 connects the two power terminals 551 and 552 via the non-last-off element 23. It should be noted that the total inductance of the first wiring path 503 is set such that it is smaller than the total inductance of the second wiring path 504.

[0102] As it is in Fig. As shown in Figure 28, the inductance of the first wiring path 503 can be expressed as L15 + L16, and the inductance of the second wiring path 504 can be expressed as L25 + L26. This means that L15 + L16 < L25 + L26. L15 is defined as the inductance of a wiring between the power terminal 551 on the high-potential side and the last-off element 22. L16 is defined as the inductance of a wiring between the power terminal 551 on the low-potential side and the last-off element 22. L25 is defined as the inductance of a wiring between the power terminal 551 on the high-potential side and the last-off element 23. L26 is defined as the inductance between the power terminal 552 on the low-potential side and the non-last-off element 23.

[0103] In particular, for the common upper branch module 50H and the common lower branch module 50L in the respective module bodies 550, the inductance of the current path through the last-off element 22 and the inductance of the current path through the non-last-off element 23 are set such that they differ from each other.

[0104] The common upper branch module 50H and the common lower branch module 50L have the same structure. Therefore, the common upper branch module 50H is used to explain its structure. As shown in Fig. 29 and Fig. As shown in Figure 30, the common upper branch module 50H is provided with two switching elements that form the parallel circuit body 20. In particular, the two switching elements 2 are connected in parallel by two electrode plates 558 and 559.

[0105] In other words, the last-off element 22 and the non-last-off element 23 are supported in the thickness direction X by the two electrode plates 558 and 559. The last-off element 22 and the non-last-off element 23 are arranged in the width direction Y.

[0106] As it is in Fig.As shown in Figure 29, in the common upper branch module 50H, two power terminals 551 and 552 project from the module body 550 in the same direction. The center position C in the base section of the power terminals 551 and 552 is closer to the last-off element 22 than to the non-last-off element 23 in the direction in which the last-off element 22 and the non-last-off element 23 are arranged, i.e., the width direction Y. The return element 21 is configured together with the last-off element in the MOSFET. Thus, the center position C in the base section of the two power terminals 551 and 552 is closer to the return element 21 than to the non-last-off element 23.

[0107] This arrangement allows a wiring path connecting the two power terminals 551 and 552 via the last-off element 22 to be shortened. As a result, the inductance of the current path can be reduced. This current path is also referred to as the first wiring path 503 described above. Accordingly, the inductance of the closed last-off circuit 101 is likely to be reduced. Other configurations are the same as those according to the first embodiment.

[0108] According to the present embodiment, a single parallel circuit body 20 is attached to a common semiconductor module, that is, the common upper branch module 50H or the common lower branch module 50L. Therefore, the size of the power conversion device 1 can easily be made small.

[0109] In the common upper branch module 50H or the common lower branch module 50L, the inductance of the current path, which is part of the closed last-off circuit 101, is reduced. Accordingly, when assembling the power conversion device 1, the inductance of the closed last-off circuit 101 can be readily reduced. Furthermore, the same operational effects as those according to the first embodiment can be obtained.

[0110] According to the sixth and seventh embodiments, the inductance of the closed last-off circuit 101 is set such that it is smaller than that of the closed non-last-off circuit 102. Furthermore, according to the eighth and ninth embodiments, configurations are used in which the inductance of the closed last-off circuit 101 is set such that it is smaller than that of the closed non-last-off circuit 102 through the busbars 61, 62, and 63. However, this is not limited to the techniques described above; other techniques can be used as long as the inductance of the closed last-off circuit 101 is set such that it is smaller than that of the closed non-last-off circuit 102.

Claims

[1] Power conversion device (1) with a high-potential line (11H) and a low-potential line (11L), an upper branch semiconductor device (2H) connected to the high potential line, a sub-branch semiconductor device (2L) connected in series with the upper-branch semiconductor device (2H) and connected to the low-potential line, and a capacitor (3) which is connected between the high potential line and the low potential line, wherein from the upper branch semiconductor device and the lower branch semiconductor device connected in series, the upper branch semiconductor device forms a parallel circuit body (20) configured from two or more switching elements (2) connected in parallel to each other, and / or the lower branch semiconductor device forms a parallel circuit body (20) configured from two or more switching elements (2) connected in parallel to each other, in the upper branch semiconductor device and the Sub-branch semiconductor device connected in series, a return flow element (21) in the parallel circuit body is provided to allow current flow from a low-potential line side to a high-potential line side, The switching elements that form the parallel circuit body are controlled in such a way that the switching-off times are different from each other. a last-off element (22) that switches off last, and a non-last-off element (23) as the other element among the switching elements that form the parallel circuit body, an inductance of a closed last-off circuit (101) in which current flows through the last-off element, the return element in an opposite branch opposite to the last-off element, and the capacitor, is smaller than the inductance of a closed non-last-off circuit (102) in which current flows through the non-last-off element connected in parallel to the last-off element, the return element in an opposite branch opposite to the last-off element, and the capacitor, wherein the parallel body of the upper branch semiconductor device comprises the last-off element, the non-last-off element and the return element, and the parallel body of the lower branch semiconductor device comprises the last-off element, the non-last-off element and the return element, the last-off element, the non-last-off element and the reflux element in the upper-branch semiconductor device are mounted on a common upper-branch module (50H) as a single common semiconductor device, and the last-off element, the non-last-off element and the reflux element in the sub-branch semiconductor device are mounted on a common sub-branch module (50L) as a single common semiconductor device, the common upper branch module and the common lower branch module are each configured such that two power connections (551, 552) project from a module body (550), and the inductance of a wiring path in the module body that connects the power terminals via the last-off element is smaller than the inductance of a wiring path in the module body that connects the power terminals via the non-last-off element, wherein the common upper branch module and the common lower branch module are configured such that the two power terminals project from the module body in the same direction, and a center position (C) in a base section of the two power terminals is closer to the last-off element than to the non-last-off element in a direction in which the last-off element and the non-last-off element are arranged. [2] Power conversion device according to claim 1, wherein the switching elements that form the parallel circuit body are controlled in such a way that the switching times are different from each other, and The last-off element is a switching element that is controlled to be switched on first among the switching elements that form the parallel circuit body. [3] Power conversion device according to claim 1 or 2, wherein the switching elements forming the parallel circuit body are configured from a SiC MOSFET and a Si IGBT. [4] Power conversion device according to claim 3, wherein the last-off element is configured from a SiC MOSFET and the non-last-off element is configured from a Si IGBT. [5] Power conversion device according to claim 3, wherein the last-off element is configured from a Si IGBT and the non-last-off element is configured from a SiC MOSFET.

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