Ripple compensator, data driver circuit with the ripple compensator and semiconductor device with the ripple compensator

Abstract

Semiconductor device comprising: a data driver circuit (110; 410; 810; 910; 1010) configured to receive input data (DATA_IN), to receive a first power supply voltage (VDDint) via a first node (a), and to generate output data (DATA_out) by driving the input data (DATA_IN); and a ripple compensator (120; 420; 500; 841_1; 941_1; 1020) connected to the first node (a) and configured to receive the input data (DATA_IN) in parallel with the data driver circuit (110; 410; 810; 910; 1010), to generate a compensation current (Iaprc) corresponding to a structure of the input data (DATA_IN), and to provide the compensation current (Iaprc) to the first node (a) to reduce a ripple of the first power supply voltage (VDDint), wherein the ripple compensator (420; 1010) has the following: a first transistor (MN1) connected between a second power supply voltage (VDD) and a second node (b) and having a diode connection structure; a buffer (421_1) configured to receive the input data (DATA_IN); and a compensation capacitance device (Ccp) connected between the second node (b) and an output terminal of the buffer (421_1), wherein the compensation current (Iaprc) is generated based on a level difference between a voltage applied to the first node (a) and a voltage of the second node (b), the level of which increases according to a rising transition of the input data (DATA_IN), wherein the compensation capacitance device comprises a variable compensation capacitance device (1021) having one or more capacitors for adjusting, in response to a control signal (Ctrl[1:L]), a capacitance of the variable compensation capacitance device (1021) with respect to an increase in the voltage level of the second node (b), wherein the semiconductor device further comprises: a level detector (1030) configured to detect a level of the first power supply voltage (VDDint) supplied to the first node (a); and a capacitance controller (1040) configured to generate the control signal (Ctrl[1:L]) according to a result of the detection.

Description

BACKGROUNDThe inventive concept relates to a ripple compensator, and more particularly, to a ripple compensator for reducing ripple of a power supply voltage, a data driving circuit including the ripple compensator, and a semiconductor device including the ripple compensator.Generally, a semiconductor device may include a circuit block for processing a signal and for operating in a range between a power supply voltage and a ground voltage. As an example, the semiconductor device may include a plurality of circuit blocks as signal processing units. For example, a data driving circuit provided in the semiconductor device may generate output data in a range between the power supply voltage and the ground voltage in response to input data.The circuit block is driven by a power supply voltage having a predetermined level, and a switching current may be generated during signal processing of the circuit block. In this case, the switching current may cause a ripple in the power supply voltage due to an impedance effect of a distributed power network (PDN= Power Distributed Network= Verteilt power network) such as a package model of a semiconductor device. When a ripple occurs in the power supply voltage, signal processing characteristics may be deteriorated.JP H07-99 772 A discloses the following: In the initial state, a node A and a node C are provided with an electric potential of a power source, and a node D is provided with an electric potential of a ground. Then, an MIS transistor in a precharge circuit is made conductive and an MIS transistor is kept non-conductive so that an electric potential of a node E is equal to that of the ground, whereby an MIS transistor is made conductive and a node B is precharged to an electric potential equal to the current source. When the electric potential of the node C is changed to that of the ground, the electric potential of a node D is equalized to that of the power source. When the electric potential of the node A is changed to that of the ground, the electric potential of the node E is equalized to that of the power source, the output of a delay circuit changes time-delayed to the electric potential of the power source, and the electric potential of the node B rises, so that a high electric potential is obtained at the node D.US 5 124 574 A discloses the following: The semiconductor integrated circuit of the invention comprises a circuit for generating a high voltage or a low voltage exceeding the voltage range between the power source potential and the ground potential, and a circuit for generating a plurality of internal signals to reduce the time difference of mutual transition timings between a plurality of internal signals when the power source potential supplied from the outside is increased, wherein the circuit is configured such that the absolute value of the high voltage or the low voltage is reduced by using the plurality of internal signals. In such a configuration, the absolute value of the high or low voltage can be automatically reduced when an excessive power source potential near the maximum rated potential exceeding the standard power source potential is supplied from the outside. As a result, a malfunction or breakdown of the gate oxide film due to the application of a strong electric field in the PN junction can be securely prevented, so that the reliability of the semiconductor integrated circuit can be improved.SUMMARYIt is an object of the present disclosure to provide a semiconductor device, a data driving circuit, and a ripple compensator that ensure a reliable supply voltage.This object is achieved by the independent claims.The inventive concept provides a ripple compensator capable of improving signal processing characteristics by reducing a ripple of a power supply voltage, a data driving circuit including the ripple compensator, and a semiconductor device including the ripple compensator.According to an aspect of the inventive concept, there is provided a semiconductor device including: a data driving circuit configured to receive input data, to receive a first power supply voltage via a first node, and to generate output data by driving the input data; and a ripple compensator connected to the first node and configured to receive the input data in parallel with the data driving circuit, to generate a compensation current corresponding to a structure of the input data, and to provide the compensation current to the first node to reduce a ripple of the first power supply voltage.According to another aspect of the inventive concept, there is provided a data driving circuit including: one or more data drivers configured to receive input data, receive a first power supply voltage via a first node, and generate output data through an operation of processing a signal whose level changes between the first power supply voltage and the ground voltage; and a ripple compensator coupled to the first node via a path for carrying a compensation current, the ripple compensator comprising at least one buffer for receiving the input data and a compensation capacitance device (for example, a capacitor) connected to an output terminal of the buffer, wherein the compensation capacitance device is configured to vary a voltage level of a second node in response to a transition of the input data and to transmit the compensation current to the first node based on a level difference between a voltage of the first node and a voltage of the second node.According to another aspect of the inventive concept, there is provided a ripple compensator connected to a first node of a circuit block that generates a consumption current according to a structure of input data, the ripple compensator including: a first diode connected between a node to which a first power supply voltage is applied and a compensation node; a buffer configured to receive the input data in parallel with the circuit block and operated by a second power supply voltage; and a compensation capacitance device connected between an output terminal of the buffer and the compensation node, wherein the ripple compensator is configured to supply to the circuit block a compensation current generated based on a voltage level difference between the compensation node and the first node of the circuit block.According to still another aspect of the inventive concept, an apparatus includes: a data processing circuit having a first node configured to receive a first power supply voltage and further having at least one data input configured to receive input data, the data processing circuit generating a ripple voltage on the first power supply voltage in response to changes in the input data; and a ripple compensator having a data input configured to receive the input data in parallel with the data processing circuit and an output connected to the first node, the ripple compensator configured to process the input data to generate a compensation signal and to provide the compensation signal to the first node to reduce the ripple voltage on the first power supply voltage.BRIEF DESCRIPTION OF THE DRAWINGSEmbodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIG. 1 is a block diagram of an example embodiment of a semiconductor device. FIG. 2 is a block diagram of an embodiment of a semiconductor system. FIG. 3 is a block diagram of an example embodiment of a data processing system including an application processor. FIGS. 4 and 5 are a block diagram and a circuit diagram, respectively, of an embodiment of a semiconductor device including a ripple compensator. FIG. 6 is a waveform diagram illustrating waveforms of various signals of the ripple compensator shown in FIG. 5. FIG. 7 is a waveform diagram illustrating an example in which a ripple of a power supply voltage is decreased in a case where an embodiment of a ripple compensator is applied. FIGS. 8 and 9 are flowcharts of an example embodiment of a method of operating a data driver circuit. FIG. 10 is a circuit diagram of an example embodiment of a ripple compensator. FIG. 11 is a circuit diagram of another exemplary embodiment of a ripple compensator. FIG. 12 is a circuit diagram of another exemplary embodiment of a ripple compensator including PMOS transistors. FIG. 13 is a block diagram of a semiconductor device showing an example of ripple compensation in a case where input data corresponds to parallel data. FIG. 14 is a block diagram of a semiconductor device in which a ripple compensator is applied to circuit blocks operating at different frequencies; and FIG. 15 is a block diagram of a semiconductor device that performs an adaptive ripple compensation operation using a variable compensation capacitance device.DETAILED DESCRIPTION OF THE EMBODIMENTSHereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.FIG. 1 is a block diagram of an example embodiment of a semiconductor device 100.The semiconductor device 100 may include one or more circuit blocks (for example, a complementary metal oxide semiconductor (CMOS) logic element or block or a serial link, etc.) operating at an operating voltage between a power supply voltage and a ground voltage to process a signal. As an example, the semiconductor device 100 may include, as one circuit block, a receiver that processes data received from outside the semiconductor device 100 and provides the processed data to another circuit block inside the semiconductor device 100. Also, the semiconductor device 100 may include, as the circuit block, a transmitter that processes data generated inside the semiconductor device 100 and provides the processed data to the outside of the semiconductor device 100. In addition, the semiconductor device 100 may include various other circuit blocks that process input data supplied according to various frequencies. With the knowledge that the circuit block consumes current due to a switching current, the circuit block may be referred to as a "power consumption circuit" in the following embodiments.Referring to FIG. 1, the semiconductor device 100 may include a circuit block 110 and a ripple compensator 120. The circuit block 110 is a signal processing circuit that performs signal processing according to a predetermined function. When the circuit block 110 receives input data DATA_IN and processes the input data DATA_IN, the circuit block 110 may be defined as a "data driving circuit" or a "data processing circuit".The circuit block 110 receives the input data DATA_IN and generates output data DATA_OUT having a level change between a first power supply voltage VDDint and a ground voltage through a signal processing operation. As an example, the circuit block 110 may include a CMOS logic element or a circuit such as a data driver, and may generate output data DATA_OUT having a logic low level or a logic high level according to a structure of the input data DATA_IN.The ripple compensator 120 may also receive the input data DATA_IN provided to the circuit block 110. As an example, the input data DATA_IN may be provided in parallel to the circuit block 110 and the ripple compensator 120, and the edge (or transition) timing of the input data DATA_IN received by the circuit block 110 and the edge timing of the input data DATA_IN received by the ripple compensator 120 may be substantially the same as the other. Here and throughout this application, when times, timings, voltages, levels, etc. are referred to as "substantially" the same as others or substantially equal to each other, it means that the times, timings, voltages, levels, etc. are the same as the others within manufacturing tolerances due to variations in processes, components, tolerances, etc.The ripple compensator 120 may receive a second power supply voltage VDD, and the second power supply voltage VDD may correspond to a power supply voltage different from the first power supply voltage VDDint. According to an embodiment, a voltage generator (not shown) for generating power supply voltages at different voltage levels may be provided in the semiconductor device 100, and the first power supply voltage VDDint and the second power supply voltage VDD may be different from each other. The first power supply voltage VDDint and the second power supply voltage VDD may be electrically isolated from each other.In addition, two or more different external power sources may be provided for the semiconductor device 100, and the semiconductor device 100 may generate a plurality of power supply voltages by using received external power sources. According to an embodiment, the first power supply voltage VDDint and the second power supply voltage VDD may be power supply voltages generated using different external power sources. Alternatively, the first power supply voltage VDDint and the second power supply voltage VDD may be power supply voltages generated using the same external power source. The first power supply voltage VDDint and the second power supply voltage VDD may have the same voltage level or substantially the same voltage level as the other, or may have different voltage levels from each other.The semiconductor device 100 may be supplied with a power supply current (for example, an AC+DC power supply current Ipmic) from an external power management integrated circuit (PMIC=Power Management Integrated Circuit=Power Management Integrated Circuit) (not shown). The first power supply voltage VDDint used as a driving voltage of the circuit block 110 may be applied to a power supply voltage node "a" connected to or associated with the circuit block 110. The level of the first power supply voltage VDDint may be influenced by the power supply current Ipmic and an impedance component in the semiconductor device 100. In this case, when a consumption current Iint generated in the circuit block 110 is supplied from the power supply current Ipmic, the level of the power supply current Ipmic may be drastically decreased depending on the structure of the input data DATA_IN. As a result, a ripple can be generated in the first power supply voltage VDDint. In order to improve the signal processing characteristics of the circuit block 110, the ripple of the first power supply voltage VDDint should be reduced regardless of the data structure of the input data DATA_IN.The ripple compensator 120 may provide a compensation signal (e.g., an alternating current (AC) compensation current Iaprc) to the circuit block 110 via the power supply voltage node "a" to reduce the ripple of the first supply voltage VDDint. Generally, the input data DATA_IN has data transition intervals therein when data level transitions occur in the input data DATA_IN (see, for example, FIG. 5 described below). In that case, the ripple compensator 120 may be configured to provide the compensation signal (e.g., compensation current Iaprc) to the first node "a" only during the data transition intervals. That is, according to an embodiment, the ripple compensator 120 may selectively provide the compensation current Iaprc to the circuit block 110 when a transition of the input data DATA_IN occurs. Accordingly, the consumption current Iint corresponding to the structure of the input data DATA_IN may be generated in the circuit block 110, and the consumption current Iint may be supplied from the compensation current Iaprc generated in the ripple compensator 120. Advantageously, a level of the alternating current consumed by the circuit block (e.g., data driving circuit) 110 and a level of the compensation current Iaprc generated by the ripple compensator 120 are substantially equal to each other.As an operation example, the ripple compensator 120 may receive the input data DATA_IN, detect an edge (a rising edge or a falling edge) of the input data DATA_IN, and output a compensation current Iaprc to the circuit block 110 based on a detection result. Alternatively, as another operation example, the ripple compensator 120 may include at least one node (for example, a compensation node) whose voltage level fluctuates in accordance with a level transition of the input data DATA_IN, and may provide a compensation current Iaprc generated due to a level difference between a voltage of the compensation node and the first power supply voltage VDDint to the circuit block 110.According to the above exemplary embodiment, since the consumption current Iint generated in the circuit block 110 can be supplied from the compensation current Iaprc of the ripple compensator 120 using a separate power supply voltage VDD, the fluctuation level of the power supply current Ipmic can be decreased, and thus the ripple of the first power supply voltage VDDint can be decreased. In addition, since the compensation current Iaprc can be selectively supplied to the circuit block 110 only when a transition of the input data DATA_IN is generated, the ripple of the first power supply voltage VDDint can be reduced via a compensation operation that is performed a relatively small percentage of time and in which an additional large power consumption or generation is not required.In addition to the circuit block 110 shown in FIG. 1, the semiconductor device 100 may include a plurality of circuit blocks as a predetermined signal processing unit. According to an embodiment, some of the circuit blocks may operate at different operating frequencies from other circuit blocks. According to an embodiment, a ripple compensator 120 may be arranged corresponding to each of circuit blocks. In this case, since the ripple compensator 120 receives the same input data as that of a circuit block arranged correspondingly thereto, the ripple compensator 120 can perform a compensation operation corresponding to an operation frequency of each circuit block.In the above-described embodiment, the configuration shown in FIG. 1 corresponds to a semiconductor device, and the circuit block 110 corresponds to a data driving circuit. However, various configurations may be variously defined in various embodiments. For example, the configuration shown in FIG. 1 may correspond to a data driver circuit, the circuit block 110 may correspond to a data driver, and the ripple compensator 120 may be included in the data driver circuit. Alternatively, the circuit block 110 may correspond to a data driver circuit or a data driver, and the ripple compensator 120 may be disposed outside the data driver circuit or the data driver.FIG. 2 is a block diagram of an embodiment of a semiconductor system. In FIG. 2, the semiconductor system may correspond to a memory system 200, and the memory system 200 may include a memory controller 210 and a memory device 220.The storage device 220 may include one of various memories. For example, the memory device 220 may include a volatile memory, and the volatile memory may be a dynamic random access memory (DRAM=dynamic random access memory), such as a dual data rate synchronous random access memory (DDR SDRAM=double data rate synchronous dynamic random access memory=synchronous dual data rate random access memory), a low power dual data rate (LPDDR=low power double data rate=low power dual data rate) SDRAM, a graphics dual data rate (GDDR= graphics double data rate= graphic dual data rate) SDRAM, or a dynamic random access memory (RDRAM=Rambus Dynamic random access memory).Alternatively, the storage device 220 may include a nonvolatile memory that maintains stored data even when power is turned off. As an example, the nonvolatile memory may include a NAND flash memory or a NOR flash memory, or may include any of various nonvolatile memories such as a magnetic random access memory (MRAM= Magnet Random Access Memory= Magnetischer Random Access Memory), a resistor RAM (RRAM= Rest RAM=Resistor RAM), a ferroelectric RAM (FRAM=Ferro Electric RAM=ferroAl RAM), and a phase transition memory (PCM=Phase Change Memory=Phase Transition Memory).The memory controller 210 may include control logic 211 and a first interface circuit 212, and may provide various signals to the memory device 220 via a first interface circuit 212 and control memory operations such as a write operation and a read operation to the memory device 220. For example, the memory controller 210 may provide a command CMD for controlling a memory operation to the memory device 220 via the first interface circuit 212. Similarly, the memory controller 210 may provide a clock signal CLK to the memory device 220 via the first interface circuit 212 and may also provide write data DATA_W to the memory device 220 or receive read data DATA_R from the memory device 220.The memory device 220 may include a memory cell array 221 and a second interface circuit 222. The memory device 220 may receive the command CMD and the clock signal CLK from the memory controller 210 via the second interface circuit 222. The memory device 220 may also receive the write data DATA_W or provide the read data DATA_R to the memory controller 210 via the second interface circuit 222.According to an embodiment, each of the first interface circuit 212 and the second interface circuit 222 may include a data driving circuit (not shown) for processing data to be transmitted or transmitted data. According to the above-described embodiment, in order to reduce a ripple of a power supply voltage generated in the data driving circuit, the first interface circuit 212 may include a first ripple compensator 212_ 1, and the second interface circuit 222 may include a second ripple compensator 222_ 1.According to an embodiment, the first interface circuit 212 may include a plurality of data driving circuits, and the first ripple compensator 212_ 1 may be arranged corresponding to each of the data driving circuits. The second interface circuit 222 may include a plurality of data driving circuits, and the second ripple compensator 222_ 1 may be disposed corresponding to each of the data driving circuits. In addition, each of the first interface circuit 212 and the second interface circuit 222 may include circuit blocks for processing the command CMD and the clock signal CLK, and the first ripple compensator 212_ 1 and the second ripple compensator 222_ 1 may be arranged corresponding to the circuit blocks for processing the command CMD and the clock signal CLK.According to an embodiment, the first interface circuit 212 may include a data transmitter as a data driver circuit, and the first ripple compensator 212_ 1 may be arranged corresponding to the data transmitter. In a data write operation, the write data DATA_W in the memory controller 210 may be provided in parallel to the data transmitter and the first ripple compensator 212_ 1, and the first ripple compensator 212_ 1 may detect an edge of the write data DATA_W and thus provide a compensation current to a power supply voltage node of the data transmitter. That is, the first ripple compensator 212_ 1 may selectively provide a compensation current to the power supply voltage node of the data transmitter when a transition occurs according to a structure of the write data DATA_W.The second interface circuit 222 of the memory device 220 may include a data receiver as a data driving circuit, and the write data DATA_W provided from the memory controller 210 may be provided in parallel to the data receiver and the second ripple compensator 222_ 1. The second ripple compensator 222_ 1 may detect an edge of the write data DATA_W and thus provide a compensation current to a power supply voltage node of the data receiver of the second interface circuit 222.Similarly, in the case of a data read operation, the second interface circuit 222 of the memory device 220 may include a data transmitter as a data driver circuit, and the read data DATA_R read from the memory cell array 221 of the memory device 220 may be provided in parallel for the data transmitter and the second ripple compensator 222_ 1. The second ripple compensator 222_ 1 may detect an edge of the read data DATA_R and thus provide a compensation current to a power supply voltage node of the data transmitter. The first interface circuit 212 of the memory controller 210 may include a data receiver for receiving the read data DATA_R and a first ripple compensator 212_ 1 corresponding to the data receiver. The read data DATA_R may be provided in parallel to the data receiver and the first ripple compensator 212_ 1, and the compensation current generation operation according to the above-described embodiments may be performed.FIG. 3 is a block diagram of an embodiment of a data processing system 300 that includes an application processor 310.As an example of a semiconductor device for driving data, the application processor 310 may communicate with one or more peripheral devices, and the application processor 310 may be implemented as a system-on-chip (SoC=System on Chip= System). The data processing system 300 may include a storage device 320 and a radio frequency (RF= Radio Frequency= Funkfrequenz) chip 330 as one or more peripheral devices, and an application processor 310. Although not shown in FIG. 3, other types of peripheral devices may be further included in the data processing system 300. The data processing system 300 of FIG. 3 may be any of various electronic devices. As an example, the data processing system 300 may be a personal computer (PC), a data server, a network-attached storage (NAS= Net-attached storage= Netz-attached storage), an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device may be a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA= Personal Digital Assistant= Persönliche Digital Assistant), a digital enterprise assistant (EDA= Ent Digital Assistant= Digitaler enterprise Assistant, a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP= Portable Multimedia Player= Tragbare Multimedia Player), a personal navigation device (PND= Personal Navigation Device= Persönliche Navigation Device), an MP3 player, a handheld game console, an e-book, a portable device, or the like.The SoC may include a system bus (not shown) that operates according to a protocol having a predetermined standard bus specification, and may include various intelligent property blocks (IP blocks=IP blocks) connected to the system bus. As a standard specification of the system bus, an Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) protocol may be employed. Examples of a bus type of the AMBA protocol may include an Advanced High-Performance Bus (AHB), an Advanced Peripheral Bus (APB), an Advanced eXtensible Interface (AXI), AXI4, AXI Coherency Extensions (ACE), and the like. Other types of protocols such as uNet from SONICs Inc., CoreConnect from IBM, and Open Core Protocol from OCP-IP may also be used.The application processor 310 may include a memory controller 311. Similarly, application processor 310 may further include a modem module 312, and may be referred to as a ModAP when application processor 310 performs a modem function. In addition, the application processor 310 may further include one or more Intelligent Property cores (hereinafter referred to as "IPs") 313.The memory control unit 311 may interface with the storage device 320, and the modem module 312 may interface with the RF chip 330 as an external chip. The memory control unit 311 may include a first interface circuit 311_ 1, and the first interface circuit 311_ 1 may include a ripple compensator 311_ 11 according to the embodiment described above. Similarly, the modem module 312 may include a second interface circuit 312_ 1, and the second interface circuit 312_ 1 may include a second ripple compensator 312_ 11 according to the embodiment described above. Although not shown, the IP 313 may also interface with an external device, and a ripple compensator according to an embodiment of the inventive concept may be provided in the IP 313.The memory device 320 may include a third interface circuit 321 that interfaces with the application processor 310, and the third interface circuit 321 may include a third ripple compensator 321_ 1 according to the embodiment described above. The RF chip 330 may include a fourth interface circuit 331 interfacing with the application processor 310, and the fourth interface circuit 331 may include a fourth ripple compensator 331_ 1 according to the embodiment described above.The first ripple compensator 311_ 11 of the memory control unit 311 and the third ripple compensator 321_ 1 of the memory device 320 may perform a ripple compensation operation according to the embodiment described above in connection with signal processing of at least one of various signals related to a memory operation. For example, the first interface circuit 311_ 1 of the memory control unit 311 may include one or more data driving circuits for driving data DATA (for example, write data DATA), and the first ripple compensator 311_ 11 may be arranged corresponding to each of the data driving circuits. Similarly, the third interface circuit 321 of the memory device 320 may include one or more data driving circuits for driving data DATA (for example, read data DATA), and the third ripple compensator 321_ 1 may be disposed corresponding to each of the data driving circuits of the memory device 320.The second interface circuit 312_ 1 of the modem module 312 may transmit or receive a baseband signal to or from the RF chip 330. As an example, the second interface circuit 312_ 1 of the modem module 312 may transmit or receive baseband data DATA and a clock signal CLK to or from the RF chip 330. According to an embodiment of the inventive concept, the second interface circuit 312_ 1 may include one or more data driving circuits for processing baseband data DATA, and the second ripple compensator 312_ 11 may be disposed corresponding to each of the data driving circuits of the second interface circuit 312_ 1. Similarly, the fourth interface circuit 331 may include one or more data driving circuits for processing baseband data DATA transmitted or received to or from the modem module 312, and the fourth ripple compensator 331_ 1 may be arranged corresponding to each of the data driving circuits of the RF chip 330.Hereinafter, specific examples of an embodiment of a ripple compensator will be described. FIGS. 4 and 5 are a block diagram and a circuit diagram, respectively, of a semiconductor device 400 including an embodiment of a ripple compensator.Referring to FIG. 4, the semiconductor device 400 may include a data driving circuit 410 as a circuit block in which a consumption current Iint is generated as described above, and a ripple compensator 420 disposed corresponding to the data driving circuit 410. The data driving circuit 410 may perform a signal processing operation on input data DATA_IN and generate output data DATA_OUT whose voltage level may be changed between a first power supply voltage VDDint applied to a power supply voltage node "a" and a ground voltage. A power supply current Ipmic may be supplied to the data driving circuit 410 via the power supply voltage node "a", and the consumption current Iint of the data driving circuit 410 may be generated according to a structure of the input data DATA_IN. When the input data DATA_IN has an irregular structure, a level of the power supply current Ipmic may fluctuate irregularly, thereby causing a ripple in which a level of the first power supply voltage VDDint fluctuates.The ripple compensator 420 may receive the input data DATA_IN and a second power supply voltage VDD. The second power supply voltage VDD may be a voltage generated separately from the first power supply voltage VDDint provided to the data driving circuit 410 as in the above-described embodiment. The ripple compensator 420 may include a compensation node "b" placed therein, and may include an amplifier 421 for amplifying a level of a compensation voltage Vcp applied to the compensation node "b". The ripple compensator 420 may further include one or more circuit devices for controlling a current direction of the compensation current Iaprc. As an example, in FIG. 4, the ripple compensator 420 may include a second diode connected between the second power supply voltage VDD and the compensation node "b", and a first diode connected between the compensation node "b" and the power supply voltage node "a". Accordingly, the compensation current Iaprc may be transmitted in one direction from the ripple compensator 420 to the power supply voltage node "a".The input data DATA_IN may have a logic low state or a logic high state according to a data structure, and the compensation voltage Vcp may have a level corresponding to the second power supply voltage VDD. The amplifier 421 may perform an amplification operation according to a structure of the input data DATA_IN. For example, the amplifier 421 may amplify a level of the compensation voltage Vcp in response to a time point at which the input data DATA_IN varies from a logic low state to a logic high state. Accordingly, a level difference may occur between an amplified compensation voltage Vcp and the first power supply voltage VDDint, and a compensation current Iaprc according to the level difference may be provided to the power supply voltage node "a". That is, even when a consumption current Iint is generated in the data driving circuit 410 according to the structure of the input data DATA_IN, variation in the level of the power supply current Ipmec by the compensation current Iaprc can be reduced, and thus, a ripple of the first power supply voltage VDDint can be reduced or eliminated. Advantageously, a level of the alternating current consumed by the data driving circuit 410 and a level of the compensation current Iaprc generated by the ripple compensator 420 are substantially equal to each other. In this case, the consumption current Iint is supplied at least partially by the compensation current Iaprc generated by the ripple compensator 420.A more specific configuration and operation of the ripple compensator of FIG. 4 will be described with reference to FIGS. 5 and 6. FIG. 6 is a waveform diagram illustrating waveforms of various signals according to the ripple compensator shown in FIG. 5.Referring to FIG. 5, the data driving circuit 410 may include one or more data drivers 411 receiving input data DATA_IN, and data drivers 411 may be connected between the first power supply voltage VDDint and the ground voltage. In FIG. 5, a parasitic resistance component Rpar and a parasitic capacitor component Cpar formed in the data driving circuit 410 are further shown.The semiconductor device 400 may be implemented as a semiconductor package, and an LRC component according to a package model PKG model may be present. A resistance component Rpkg, an inductance component Lpkg, and a capacitance component Cpkg according to the package model PKG model is shown in FIG. 5, and a power supply current Ipmic according to a voltage VDDpm from an external power source may be provided to the data driving circuit 410 via the power supply voltage node "a". When a consumption current Iint is generated in the data driving circuit 410 as described above, a ripple may occur in the first power supply voltage VDDint applied to the power supply voltage node "a" primarily due to the inductance component Lpkg of the package model PKG model.According to an embodiment, the ripple compensator 420 may be electrically connected to the power supply voltage node "a", and an electrical path from the ripple compensator 420 to the power supply voltage node "a" may be referred to as a compensation path. The ripple compensator 420 may include first and second transistors MN 1 and MN 2, and the amplifier 421 may include one or more buffers 421_ 1 and a compensation capacitance device (e.g., capacitor Ccp). The second power supply voltage VDD may be provided to the compensation node "b" via the first transistor MN 1, which is a diode-connected transistor. The compensation node "b" may be connected to the power supply voltage node "a" via the second transistor MN 2. The second power supply voltage VDD provided to the ripple compensator 420 may be used as a driving voltage for driving the buffer 421_ 1.The ripple compensator 420 may generate a compensation current (or a compensation charge) Iaprc by using the second power supply voltage VDD different from the first power supply voltage VDDint, which is a driving voltage of the data driving circuit 410, and may compensate a ripple of the first power supply voltage VDDint by supplying the compensation current Iaprc to the power supply voltage node "a". In addition, the ripple compensator 420 may generate a compensation current by a charge pump method using the buffer 421_ 1 and the compensation capacitor Ccp.As an operation example, when a threshold voltage of the first transistor MN 1 corresponds to Vth 1, the compensation voltage Vcp applied to the compensation node "b" has a level corresponding to VDD-Vth 1. When a voltage level of the input data DATA_IN transitions from a logic low to a logic high at a rising edge of the input data DATA_IN, a voltage level of an output node "c" of the buffer 421_ 1 (or an electrode of the compensation capacitor Ccp) may increase. For example, when the buffer 421_ 1 is operated by the second power supply voltage VDD, a voltage level of the output node "c" may increase by the level of the second power supply voltage VDD. In addition, a voltage level of the compensation node "b" may increase by the compensation capacitor Ccp. For example, the compensation voltage Vcp may increase to a level corresponding to VDD-Vth1+VDD. This can be referred to as a charge pump operation. Accordingly, due to a voltage level difference between the power supply voltage node "a" and the compensation node "b", the compensation current Iaprc may be provided to the data driving circuit 410 via the second transistor NM 2 and the power supply voltage node "a".Thereafter, when the voltage level of the input data DATA_IN transitions from a logic high to a logic low at a falling edge of the input data DATA_IN, the level of the compensation voltage Vcp may return to VDD-Vth 1, and thus the supply of the compensation current Iaprc to the power supply voltage node "a" may be stopped.FIG. 6 illustrates waveforms of various signals corresponding to the operation described in the embodiment of FIG. 5. As shown in FIG. 6, the consumption current Iint of the data driving circuit 410 may increase at the rising edge of the input data DATA_IN, and thus a ripple of the first power supply voltage VDDint may be caused. However, the level of the compensation voltage Vcp may vary based on a structure of the input data DATA_IN according to an embodiment of the inventive concept, and thus the compensation current Iaprc may be generated. According to the embodiment described above, an instantaneous AC current consumed by the data driving circuit 410 may not be supplied from the power supply current Ipmic, but may be supplied from the compensation current Iaprc generated by the ripple compensator. Thus, the fluctuation level of the power supply current Ipmic can be decreased, and the ripple of the first power supply voltage VDDint can be decreased.In the embodiment of FIG. 5, the second power supply voltage VDD provided to one electrode of the first transistor MN 1 is used as a driving voltage of the buffer 421_ 1. However, the embodiment of the inventive concept is not limited thereto. For example, a power supply voltage provided for one electrode of the first transistor MN 1 and a power supply voltage used as the driving voltage of the buffer 421_ 1 may be different types of power supply voltages, and voltage levels of the power supply voltages may be different from each other.FIG. 7 is a waveform diagram illustrating an example in which a ripple of a power supply voltage is decreased in a case where a ripple compensator is applied.Referring to FIGS. 5 and 7, the size of the compensation capacitor Ccp may determine the amount of the compensation current Iaprc provided to the power supply voltage node "a". FIG. 7 illustrates waveforms representing the degree of ripple generated in the power supply voltage according to the size (or capacitance) of the compensation capacitor Ccp. For example, a wave characteristic in the case where the capacitance corresponds to 0 pF, C1, C1+α, or C1+2α is illustrated in FIG. 7.In the waveform diagram shown in FIG. 7, the horizontal axis represents time and the vertical axis represents the level of the power supply voltage VDDint. First, the case where the capacitance corresponds to 0 pF corresponds to a case where a ripple compensator is not applied. In this case, as shown in FIG. 7, the amount of ripple generated in the first power supply voltage VDDint may be relatively large. On the other hand, when the ripple compensator is applied, the amount of ripple generated in the first power supply voltage VDDint may be reduced. For example, when a compensation capacitor Ccp having a relatively small capacitance C 1 is applied, the amount of ripple compensation provided by the compensation current Iaprc may be relatively small, and thus the degree of reduction of a ripple generated in a first power supply voltage VDDint may be relatively small. On the other hand, when a compensation capacitor Ccp having a relatively large capacitance C1+2α is applied, the compensation amount provided by the compensation current Iaprc may be relatively large, and thus the degree of reduction of a ripple generated in the first power supply voltage VDDint may be relatively large. The magnitude of a ripple generated in the first power supply voltage VDDint may vary depending on a package model of a semiconductor device and the like. Thus, the magnitude of a ripple generated in the first power supply voltage VDDint may be measured by a test before shipping the semiconductor device, and the capacitance of the compensation capacitor Ccp may be determined based on the measurement result.FIGS. 8 and 9 are flowcharts of an embodiment of a method of operating a data driving circuit. In explaining the embodiment of FIGS. 8 and 9, it is assumed that the data driving circuit includes a data driver and a ripple compensator according to the above-described embodiment.Referring to FIG. 8, input data may be provided to a data driving circuit (operation S 11). The input data may be provided to a data driver in the data driver circuit, and the data driver may generate a consumption current according to a structure of the input data. In addition, the input data may be provided in parallel to a ripple compensator associated with or connected to the data driver of the data driver circuit (operation S 12). Since the same data is provided in parallel to the data driver and the ripple compensator, the ripple compensator can detect an edge according to the structure of the received input data (operation S 13) from which a timing at which a change (for example, increase) in the consumption current is generated in the data driver can be detected.The ripple compensator may include a circuit that performs switching according to the structure of the input data, and may also include a current source that generates a compensation current (or a compensation charge) and provides the compensation current to a power supply voltage node of the data driver. According to an embodiment, the ripple compensator may include a switch that is turned on or off in response to an edge of the input data. More specifically, when a large amount of consumption current is generated at a rising edge of the input data in the data driver, the switch of the ripple compensator may turn on the compensation current in response to the rising edge of the input data. That is, the ripple compensator may turn on the compensation current and provide the compensation current to the power supply voltage node of the data driver (operation S 14).Referring to FIG. 9, input data may be provided to a data driving circuit (also referred to as a power consumption circuit) (operation S 21). The input data may be provided to a data driver in the driver circuit. In addition, the input data may be provided in parallel to a ripple compensator in the data driving circuit (operation S 22). Also, the ripple compensator may include one or more buffers and may be provided with a power supply voltage (for example, an external power supply voltage) different from a power supply voltage of the data driver. The external power supply voltage may be applied to a compensation node in the ripple compensator (operation S 23). In FIG. 9, the compensation node is referred to as a first node in the ripple compensator.The ripple compensator may generate a compensation current based on a charge pump operation. As an example, the ripple compensator may include a compensation capacitor connected to the compensation node, and a voltage level of the compensation node may increase based on a charge pump operation according to a structure of input data provided to the ripple compensator (operation S 24). In addition, according to the charge pump operation, the level of a voltage of the compensation node may be higher than that of a voltage applied to a power supply voltage node of the data driver. Accordingly, a voltage level difference may occur between the compensation node and the power supply voltage node of the data driver, and a compensation current according to the voltage level difference may be provided to the power supply voltage node.As described above, according to embodiments of the inventive concept, a consumption current generated in a power consumption circuit may be supplied via a compensation current generated due to a different type of power supply. In addition, since a ripple of a power supply voltage according to the embodiment described above can be reduced, a ripple compensator according to an embodiment of the inventive concept can be employed in various types of logic circuits for processing data, for example, a serializer, a driver, and a clock and data recovery (CDR= Clock and Data Recovery= Clock and Data Recovery) circuit, etc.Various circuit implementations of an embodiment of a ripple compensator and a semiconductor device including the ripple compensator will be described below.FIG. 10 is a circuit diagram of an embodiment of a ripple compensator 500.Referring to FIG. 10, the ripple compensator 500 may be electrically connected to various circuit blocks provided in a semiconductor device. For example, the ripple compensator 500 may be connected to a node of a power supply line that transmits a power supply voltage to the circuit blocks. The ripple compensator 500 may also include a current source 510 and a switch 520, and a compensation current Iaprc from the current source 510 may be provided for a corresponding circuit block (or a circuit block in which a ripple is to be compensated) via the switch 520. The ripple compensator 500 may be driven by a power supply voltage VDD, and the power supply voltage VDD may correspond to a power supply voltage different from a power supply voltage (not shown) used in a corresponding circuit block.Similar to the embodiment described above, the ripple compensator 500 may receive the same input data DATA_IN as a corresponding circuit block. In addition, the switch 520 may perform a switching operation corresponding to a data structure of the input data DATA_IN. For example, in response to a rising edge of the input data DATA_IN, the switch 520 may be changed from an off state to an on state. In addition, when the switch 520 is turned on, the compensation current Iaprc may be provided from the current source 510 for a corresponding circuit block, and a consumption current of the circuit block generated at a time substantially the same as a time at which the switch 520 is turned on may be supplied from the compensation current Iaprc.In the embodiment shown in FIG. 10, the switch 520 is described as being turned on in response to a rising edge of the input data DATA_IN. However, the embodiment of the inventive concept is not limited thereto. As an example, the switch 520 may be implemented such that the switch 520 is turned on in response to a falling edge of the input data DATA_IN. Alternatively, an additional switch (not shown) may be further provided, and thus, the switch 520 may be implemented such that the switch 520 is turned on on on both a rising edge and a falling edge of the input data DATA_IN. When power consumption in a circuit block occurs during both a rising transition and a falling transition of the input data DATA_IN, ripple during both the rising transition and the falling transition of the input data DATA_IN may be compensated.FIG. 11 is a circuit diagram of a ripple compensator 600 according to another exemplary embodiment of the inventive concept.Referring to FIG. 11, the ripple compensator 600 may include various switching devices for generating a compensation current according to the above-described embodiment. As an example, the ripple compensator 600 may include one or more buffers (or inverters), one or more compensation capacitors Ccp 1 and Ccp 2, one or more NMOS transistors MN 1, MN 2, and MN 3, a capacitor Ccap connected to a high voltage node "c" to which a high voltage is applied, and one or more PMOS transistors MP 1 and MP 2 for the driving current and driving current, respectively. As an example, the ripple compensator 600 may include a buffer 611 that receives a low frequency clock signal and an inverter 612 connected to an output of the buffer 611. As an example, each of the one or more NMOS transistors MN 1, MN 2, and MN 3 may have a diode connection structure, and may also be connected in series between a power supply voltage VDD and the high voltage node "c". A node of a first compensation capacitor, i.e., the compensation capacitor Ccp 1, may be connected to a node between the NMOS transistors MN 1 and MN 2, and a node of a second compensation capacitor, i.e., the compensation capacitor Ccp 2, may be connected to a node between the NMOS transistors MN 2 and MN 3.As in the above-described embodiment, a boost operation can be performed by the compensation capacitors Ccp 1 and Ccp 2 according to a driving operation of the buffer 611 and the inverter 612, and thus the level of a voltage VDDhigh applied to the high voltage node "c" can increase. A compensation current Iaprc may be generated by a first PMOS transistor, i.e., the PMOS transistor MP 1 functioning as a current source, and the compensation current Iaprc may be provided to a corresponding circuit block by a switching operation of a second PMOS transistor, i.e., the PMOS transistor MP 2, which is in response to input data DATA_IN, and thus may reduce a ripple generated in a power supply voltage of the circuit block.FIG. 12 is a circuit diagram of a ripple compensator 700 using PMOS transistors according to another embodiment of the inventive concept.Referring to FIG. 12, the ripple compensator 700 may include first and second PMOS transistors MP 1 and MP 2, and the ripple compensator 700 may also include one or more buffers 711 and a compensation capacitor Ccp. Each of the first and second PMOS transistors MP 1 and MP 2 may have a diode connection structure, and a power supply voltage VDD may be provided to a compensation node "b" via the first PMOS transistor MP 1. The compensation node "b" may also be connected to a power supply voltage node of a corresponding circuit block via the second PMOS transistor MP 2.According to the embodiment shown in FIG. 12, since the level of the threshold voltage of the first and second PMOS transistors MP 1 and MP 2 is lower than that of the NMOS transistors, a decrease in the level of a compensation voltage applied to the compensation node "b" can be minimized. In addition, the level of the compensation voltage by the compensation capacitor Ccp may increase, and a decrease in a current level of a compensation current Iaprc transmitted through the second PMOS transistor MP 2 may be minimized.FIG. 13 is a block diagram of a semiconductor device 800 showing an example of ripple compensation in a case where input data corresponds to parallel data. In FIG. 13, an example in which input data DATA_IN corresponds to 20-bit parallel data is illustrated. However, the same principles described below may be applied when the number of bits of parallel data is more than or less than 20.Referring to FIG. 13, the semiconductor device 800 may include various circuit blocks, for example, a logic circuit 810, a serializer 820, and a driver 830. In addition, the semiconductor device 800 may include one or more ripple compensators according to the embodiments described above, and an example in which a ripple compensator is arranged corresponding to each data bit is shown in FIG. 13. Accordingly, the semiconductor device 800 may further include first to twentieth ripple compensators 841_ 1 to 841_ 20.The driver 830 may correspond to the data driver or the data driver circuit in the above-described embodiment. Logic circuit 810 may receive input data DATA_IN corresponding to 20-bit parallel data IN[ 0] to IN[ 19], and may be operated by a relatively low operating frequency. For example, logic circuit 810 may receive input data DATA_IN over twenty data lines, and each of the data lines may have a data structure according to corresponding input data DATA_IN. That is, the input data DATA_IN provided by the twenty data lines may have different data structures for each data line.According to an embodiment, first to twentieth ripple compensators 841_ 1 to 841_ 20 may be arranged corresponding to the 20-bit parallel data IN[ 0] to IN[ 19], and each of first to twentieth ripple compensators 841_ 1 to 841_ 20 may provide a compensation current Iaprc for a circuit block that processes input data DATA_IN of a corresponding data line. For example, the logic circuit 810 may include twenty circuit blocks to process the 20-bit parallel data IN[0] to IN

[19] , respectively, and each of the first to twentieth ripple compensators 841_ 1 to 841_ 20 may compensate a ripple of a power supply voltage generated in a corresponding circuit block. That is, the first to twentieth ripple compensators 841_ 1 to 841_ 20 may respectively provide compensation currents Iaprc[0-19] for corresponding circuit blocks at different timings.Serializer 820 may receive and process the 20-bit parallel data IN[ 0] to IN[ 19] to generate serial data. That is, serializer 820 may sequentially provide data bit by bit to driver 830. The driver 830 may generate output data DATA_OUT through the processing operation according to the embodiments described above.In the example shown in FIG. 13, 20-bit parallel data IN[0] to IN

[19] have been described. However, according to an embodiment of the inventive concept, M ripple compensators may be arranged according to a logic circuit for processing M-bit parallel data. According to another embodiment, fewer than M ripple compensators may be arranged corresponding to some of the parallel M-bit data.FIG. 14 is a block diagram of a semiconductor device 900 in which a ripple compensator is applied to circuit blocks operating at different frequencies.Referring to FIG. 14, the semiconductor device 900 may include a logic circuit 910, a serializer 920, and a driver 930, and as in the embodiment described above, the logic circuit 910 is assumed to receive input data DATA_IN corresponding to 20-bit parallel data IN[ 0] to IN[ 19]. Serializer 920 may receive and process the 20-bit parallel data IN[ 0] to IN[ 19] to generate serial data. As an example, the serializer 920 may generate serial data corresponding to differential data INP and INN. Accordingly, the serializer 920 may provide serial data to the driver 930 via two data lines carrying the differential data INP and INN.As in the embodiment described above, the semiconductor device 900 may further include first to twentieth ripple compensators 941_ 1 to 941_ 20 corresponding to a logic circuit 910 for processing the 20-bit parallel data IN[ 0] to IN[ 19]. The 20-bit parallel data IN[ 0] to IN[ 19] may be provided to first to twentieth ripple compensators 941_ 1 to 941_ 20, and each of the first to twentieth ripple compensators 941_ 1 to 941_ 20 may provide a compensation current to the logic circuit 910 according to a structure of corresponding data.The semiconductor device 900 may further include first and second ripple compensators 951_ 1 and 951_ 2 corresponding to the driver 930 for processing the differential data INP and INN. The first ripple compensator 951_ 1 may receive the first differential data INN and may generate a compensation current according to the above-described embodiments according to a structure of the first differential data INN. The second ripple compensator 951_ 2 may receive the second differential data INP and may generate a compensation current according to the above-described embodiments according to a structure of the second differential data INP. The driver 930 may generate output data DATA_OUT (OUTP / OUTN) by a processing operation on the differential data INP and INN.The differential data INP and INN may have complementary logic levels, and thus the first and second ripple compensators 951_ 1 and 951_ 2 may alternately provide compensation currents for respective circuit blocks. As an example, the driver 930 may include a first circuit block for processing the first differential data INN and a second circuit block for processing the second differential data INP, and the first circuit block and the second circuit block may alternately receive compensation currents. In addition, logic circuit 910 may operate at a relatively low frequency while driver 930 may operate at a relatively high frequency.According to the embodiment, as described above, each of the first and second ripple compensators 951_ 1 and 951_ 2 may be implemented in a module form and arranged corresponding to each circuit block, and thus ripple compensation may be performed on circuit blocks operating at different frequencies.FIG. 15 is a block diagram of a semiconductor device 1000 that performs an adaptive ripple compensation operation using a variable compensation capacitance device.The magnitude of a compensation current may be adjusted according to the capacitance of a compensation capacitor used to increase a voltage level of a compensation node, as in the embodiment described above. Referring to FIG. 15, the semiconductor device 1000 may include a data driving circuit 1010 and a ripple compensator 1020, and may further include a level detector 1030 that detects a voltage level of a first power supply voltage VDDint applied to a power supply voltage node "a", and a capacitance controller 1040 that generates control signals Ctrl[1:L] for adjusting the capacitance of a compensation variable capacitance device 1021.The ripple compensator 1020, and in particular the variable compensation capacitance device 1021, may include one or more compensation capacitors and switches SW 1 to SWL corresponding thereto. Although not shown in FIG. 15, the ripple compensator 1020 may include one or more buffers (not shown) for receiving input data DATA_IN, and the level of a compensation voltage Vcp applied to a compensation node "b" may increase according to a structure of the input data DATA_IN. In addition, the increase degree of the level of the compensation voltage Vcp may be adjusted according to the capacitance of the compensation variable capacitance device 1021, and accordingly, the level of a compensation current Iaprc may be adjusted.According to an embodiment, the level detector 1030 may detect the level of the first power supply voltage VDDint periodically or aperiodically, and the degree of ripple generated in the first power supply voltage VDDint may be determined according to a detection result. According to an embodiment, the level detector 1030 may detect the level of the first power supply voltage VDDint via a test process during an initial operation of the semiconductor device 1000, and the capacitance controller 1040 may generate the control signals Ctrl[1:L] based on a detection result. Switches SW 1 to SWL provided in the ripple compensator 1020, and particularly in a compensation variable capacitance device 1021, may be controlled to be turned on or off based on the control signals Ctrl[ 1:L], and a ripple compensation operation according to the embodiments described above may be performed according to the capacitance adjusted by the control signals Ctrl[ 1:L] during a subsequent normal operation of the semiconductor device 1000.The ripple compensator, the data driving circuit including the ripple compensator, and the semiconductor device including the ripple compensator according to the embodiments described above may prevent an increase in complexity of a circuit design and / or may reduce a ripple of a power supply voltage adaptively for structures of input data.

Claims

A semiconductor device, comprising: a data driving circuit (110; 410; 810; 910; 1010) configured to receive input data (DATA_IN), to receive a first power supply voltage (VDDint) via a first node (a), and to generate output data (DATA_out) by driving the input data (DATA_IN); and a ripple compensator (120; 420; 500; 841_1; 941_1; 1020) connected to the first node (a) and configured to generate the input data (DATA_IN) in parallel with the data driving circuit (110; 410; 810; 910; 1010) for generating a compensation current (Iaprc) corresponding to a structure of the input data (DATA_IN) and providing the compensation current (Iaprc) to the first node (a) for reducing a ripple of the first power supply voltage (VDDint), the ripple compensator (420; 1010) comprising: a first transistor (MN1) connected between a second power supply voltage (VDD) and a second node (b) and having a diode connection structure; a buffer (421_1) configured to receive the input data (DATA_IN); and a compensation capacitance device (Ccp) connected between the second node (b) and an output terminal of the buffer (421_1), wherein the compensation current (Iaprc) is generated based on a level difference between a voltage applied to the first node (a) and a voltage of the second node (b) whose level increases according to a rising transition of the input data (DATA_IN), the compensation capacitance device comprising a compensation variable capacitance device (1021) comprising one or more capacitors for adjusting, in response to a control signal (Ctrl[1:L]), a capacitance of the compensation variable capacitance device (1021) related to a rise of the voltage level of the second node (b), the semiconductor device further comprising: a level detector (1030) configured to detect a level of the first power supply voltage (VDDint) supplied to the first node (a); and a capacitance controller (1040) configured to generate the control signal (Ctrl[1:L]) according to a result of the detection.The semiconductor device according to claim 1, wherein the ripple compensator (120; 420; 500; 810; 910; 1020) is configured to generate the compensation current (Iaprc) only when a transition occurs in the structure of the input data (DATA_IN).The semiconductor device according to claim 1 or 2, wherein the data driving circuit (110; 410; 810; 910; 1010) consumes an alternating current at a timing of a rising edge of the input data (DATA_IN), and the ripple compensator (120; 420; 500; 841_1; 941_1; 1020) generates the compensation current (Iaprc) in synchronization with a rising edge of the input data (DATA_IN).The semiconductor device according to claim 3, wherein a level of the alternating current consumed by the data driving circuit (110; 410; 810; 910; 1010) and a level of the compensation current (Iaprc) generated by the ripple compensator (120; 420; 500; 841_1; 941_1; 1020) are equal to each other.The semiconductor device of claim 1, wherein the buffer (421_1) is operated by a third power supply voltage, wherein a voltage level of the second node (b) has a level corresponding to the second power supply voltage when the input data (DATA_IN) corresponds to a logic low, and rises to a level corresponding to a sum of the second power supply voltage (VDD) and the third power supply voltage minus a threshold voltage of the first transistor (MN1) when the input data (DATA_IN) transitions to a logic high.The semiconductor device according to claim 5, wherein the second power supply voltage (VDD) and the third power supply voltage have a same level with each other.The semiconductor device according to any one of claims 1 to 6, further comprising: a second transistor (MN2) connected between the first node (a) and the second node (b) and having a diode connection structure, wherein the compensation current (Iaprc) is provided for the first node (a) via the second transistor (MN2).The semiconductor device according to any one of claims 1 to 7, wherein the data driving circuit (810; 910) includes N drivers for driving the input data (DATA_IN) corresponding to parallel data, and wherein the semiconductor device (800; 900) further includes additional (N-1) ripple compensators (841_2 to 841_20; 941_2 to 941_20) for a total number of N ripple compensators, and wherein the N ripple compensators are arranged corresponding to the N drivers, where N is an integer equal to or greater than two.The semiconductor device according to any one of claims 1 to 7, further comprising: a logic circuit (810; 910) configured to receive a second power supply voltage as a driving voltage, wherein the logic circuit (810; 910) comprises N circuit blocks that receive parallel data (DATA_IN) from outside the semiconductor device (800; 900), wherein N is an integer equal to or greater than two; a serializer (820; 920) configured to convert parallel data output from the logic circuit (810; 910) into serial data, and to provide the serial data as the input data to the data driving circuit (830; 930); and additional (N-1) ripple compensators (841_2 to 841_20; 941_2 to 941_20) for a total number of N ripple compensators (841_1 to 841_20; 941_1 to 941_20), and wherein the N ripple compensators (841_1 to 841_20; 941_1 to 941_20) are arranged corresponding to the N circuit blocks, and are configured to receive the parallel data (DATA_IN) from outside the semiconductor device in parallel with the logic circuit (810; 910) to reduce a ripple of the second power supply voltage according to a consumption current in each of the N circuit blocks.The semiconductor device according to any one of claims 1 to 7, wherein the input data includes differential data (INP, INN) having logic levels complementary to each other, wherein the data driving circuit (930) includes a first data driver and a second data driver (INP, INN) corresponding to the differential data (INP, INN), wherein the ripple compensator (951_1) is disposed corresponding to the first data driver, and further includes a second ripple compensator (951_2) disposed corresponding to the second data driver.The semiconductor device according to any one of claims 1 to 10, wherein the semiconductor device comprises an application processor (310) comprising one or more Intelligent Property (IP) blocks (313), wherein the data driving circuit and the ripple compensator are arranged in the IP blocks (313).A data driver circuit comprising: one or more data drivers configured to receive input data (DATA_IN), to receive a first power supply voltage (VDDint) via a first node (a), and to generate output data (DATA_OUT) via an operation for processing a signal whose level changes between the first power supply voltage (VDDint) and a ground voltage; and a ripple compensator (120; 420; 1020) coupled to the first node (a) via a path for carrying a compensation current (Iaprc), wherein the ripple compensator (120; 420; 1020) comprises a buffer (421_1) for receiving the input data (DATA_IN) and a compensation capacitance device (Ccp), which is connected to an output terminal of the buffer (421_1), wherein the compensation capacitance device (Ccp) is configured to vary a voltage level of a second node (b) in response to a transition of the input data (DATA_IN), and to transmit the compensation current (Iaprc) to the first node (a) based on a level difference between a voltage of the first node (a) and a voltage of the second node (b), wherein the compensation capacitance device (Ccp) comprises one or more capacitors for adjusting a capacitance of the compensation capacitance device (Ccp), wherein the capacitance is adjusted based on a detection result of a voltage level of the first node (a).The data driving circuit according to claim 12, wherein the ripple compensator (120; 420; 1020) is driven by a second power supply voltage (VDD) different from the first power supply voltage (VDDint), the first power supply voltage (VDDint) and a power supply current (Ipmic) from an external power source are provided for the first node (a), and a consumption current (Iint) is generated in the data driver depending on a structure of the input data (DATA_IN), the consumption current (Iint) being supplied at least partially by the compensation current generated by the ripple compensator (120; 420; 1020).The data driving circuit of claim 13, wherein the ripple compensator (120; 420; 1020) further comprises a first transistor (MN1) connected between the second power supply voltage (VDD) and the second node (b), and a second transistor (MN2) connected between the second node (b) and the path for carrying the compensation current (Iint), wherein the compensation capacitance device (Ccp) is connected between the output terminal of the buffer (421_1) and the second node (b).The data driving circuit according to claim 14, wherein each of the first and second transistors (MN1, MN2) has a diode connection structure.The data driver circuit of claim 14, wherein the second power supply voltage (VDD) has a first level Lev1, the buffer (421_1) is driven by a third power supply voltage having a second level Lev2, and the first transistor (MN1) has a first threshold voltage level Vth1, wherein a voltage level of the second node (b) corresponds to Lev1-Vth1 when the input data (DATA_IN) is in a logic low state and rises to Lev1+Lev2-Vth1 when the input data (DATA_IN) transitions to a logic high.A ripple compensator (420) to be connected to a first node (a) of a circuit block (110) generating a consumption current (Iint) according to a structure of input data (DATA_IN), the ripple compensator (420) comprising: a first diode connected between a node (a) to which a first power supply voltage (VDDint) is applied and a compensation node (b); a buffer (421_1) configured to receive the input data (DATA_IN) in parallel with the circuit block and operated by a second power supply voltage (VDD); and a compensation capacitance device (Ccp) connected between an output terminal of the buffer (421_1) and the compensation node (b), wherein the ripple compensator (420) is configured to supply to the circuit block a compensation current (Iaprc) generated based on a voltage level difference between the compensation node (b) and the first node (a) of the circuit block, wherein the compensation capacitance device (Ccp) comprises one or more capacitors for adjusting a capacitance of the compensation capacitance device (Ccp), wherein the capacitance is adjusted based on a detection result of a voltage level of the first node (a).The ripple compensator of claim 17, wherein the first node (a) of the circuit block is a node on a line for providing a driving voltage (VDDint) to the circuit block.The ripple compensator according to claim 17 or 18, further comprising a second diode connected between the compensation node (b) and the second power supply voltage VDD of the circuit block, wherein each of the first and second diodes is a transistor (MN1, MN2) having a diode connection structure.The ripple compensator according to any one of claims 17 to 19, wherein the buffer (421_1) is configured to increase a voltage level of the output terminal by a level of the second power supply voltage (VDD) in response to a rising edge of the input data (DATA_IN), wherein the compensation capacitance device (Ccp) is configured to increase a voltage level of the compensation node (b) by the level of the second power supply voltage (VDD) in response to an increase in the voltage level of the output terminal, wherein the compensation current (Iaprc) has a level according to a voltage level difference between the compensation node (b) whose voltage level is increased and the first node (a) of the circuit block.The ripple compensator according to any one of claims 17 to 20, wherein the first power supply voltage (VDDint) and the second power supply voltage (VDD) are substantially the same as the other, respectively, and are different from a driving voltage (of the buffer 421_1) provided for the circuit block.

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