Interference-preventing input / output circuits and methods for their operation

Abstract

Circuit (100) connected to an input / output contact pad (190), comprising: a first level switch (121) which is set up to generate a data signal (I_up); a second level slider (122) which is configured to generate an output activation signal (OE_up), wherein the first level slider is controlled by a first power-on control signal (POC1) and the second level slider (121, 122) is controlled by a second power-on control signal (POC2); a gating circuit (300, 500) configured to generate the first and second power-on control signals (POC1, POC2) and to control a signal sequence of the first and second power-on control signals (POC1, POC2) such that the first power-on control signal (POC1) allows the first level shifter (121) to generate the data signal (I_up) before the second power-on control signal (POC2) allows the second level shifter (122) to generate the output activation signal (OE_up); and a control logic circuit (126) which is connected to the first level slider (121) and the second level slider (122) and is configured to drive the input / output contact pad (190) to a voltage level based on the data signal (I_up) and the output activation signal (OE_up).

Description

BACKGROUND

[0001] Integrated circuit (IC) chips, or semiconductor dies, are typically encapsulated in a package to protect the circuitry formed on the die from external elements. An IC chip includes contact pads formed on it. Connecting wires or other electrical connectors are used to electrically connect the contact pads to corresponding pins or traces of the IC package. The contact pads can be power supply pads for supply voltage connections and input / output (I / O) pads for connecting to input and output signals of the integrated circuit. An I / O circuit is a circuit connected to an I / O contact pad of a chip and configured to exchange input and / or output signals with other chips in the IC system.

[0002] One circuit is known, for example, from US 2010 / 0 013 518 A1, in which block signals are provided for the control of level slides.

[0003] A noise pulse is an unwanted transition state that occurs before a signal stabilizes at its intended value. Noise pulses pose a serious problem for an I / O circuit, for example, during circuit startup. A key factor influencing the noise pulse problem in an I / O circuit is the signal sequence of a data signal and an output activation signal within the I / O circuit. In a conventional approach, the signal sequence is controlled by system-level signals, which is unsuitable for high-speed circuit operations. Another conventional approach requires the external addition of a power-on control (POC) mechanism to control the I / O circuit in tristate and avoid crowbar currents during startup.For this external POC method, purchasers of the integrated circuit must modify their system design to control the POC behavior themselves, which is a significant effort for the purchasers. Therefore, existing I / O circuits are not entirely satisfactory with regard to noise pulse prevention. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The manifestations of this revelation are best understood from the following detailed description in conjunction with the accompanying figures. It should be noted that various elements are not necessarily shown to scale. In fact, the dimensions and geometries of the various elements may be enlarged or reduced as desired to clarify the description. The same reference numbers denote identical elements throughout the description and in the drawings. Fig. Figure 1 illustrates an exemplary block diagram of a circuit connected to an input / output contact pad, according to some embodiments of the present disclosure. Fig. Figure 2A illustrates an example of circuit behavior during startup. Fig. Figure 2B illustrates another example of circuit behavior during startup. Fig. Figure 3 illustrates an exemplary gating circuit in an input / output circuit according to some embodiments of the present disclosure. Fig. Figure 4 illustrates an exemplary layout of a gating circuit in an input / output circuit according to some embodiments of the present disclosure. Fig. Figure 5 illustrates another exemplary gating circuit in an input / output circuit according to some embodiments of the present disclosure. Fig. Figure 6 illustrates an exemplary circuit behavior during the startup of an input / output circuit according to some embodiments of the present disclosure. Fig. Figure 7 illustrates an example of detailed circuit behavior during the startup of an input / output circuit according to some embodiments of the present disclosure. Fig. Figure 8 illustrates an exemplary block diagram of another circuit connected to an input / output contact pad, according to some embodiments of the present disclosure. Fig. Figure 9 is a flowchart illustrating an exemplary method for preventing interference pulses in a circuit connected to an input / output contact pad according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF EXAMPLE EXECUTIONS

[0005] The following disclosure presents various embodiments for realizing different features of the subject matter of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in this disclosure.This repetition serves to simplify and clarify and, as such, does not establish any relationship between the various described embodiments and / or configurations.

[0006] Furthermore, for the sake of simplicity, spatial relationship terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatial relationship terms are intended to encompass orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or exhibiting other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.Terms such as "attached", "fastened" and "connected" refer to a relationship in which structures are attached or affixed to one another either directly or indirectly via intervening structures, and include both movable and rigid attachments or relationships, unless explicitly described otherwise.

[0007] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as they are normally understood by a person skilled in the art in the field to which this disclosure belongs. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted in a manner consistent with their meaning in the context of the relevant field and this disclosure, and not in an idealized or overly formal sense, unless otherwise defined herein.

[0008] Detailed reference will now be made to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and in the description to refer to the same or similar parts.

[0009] The present disclosure provides various embodiments for interference pulse-preventing input / output circuits and methods for preventing interference pulses in I / O circuits. In some embodiments, a gating circuit is provided to control the signal sequence of a data signal and an output activation signal in the I / O circuit to prevent any interference pulse from occurring, particularly when a core circuit to which the I / O circuit is connected and the I / O circuit are accordingly powered on or switched on, i.e., to ensure that no interference pulse occurs during a power-up procedure of the I / O circuit.For example, the I / O circuit includes a first level shifter configured to generate the data signal, a second level shifter configured to generate the output activation signal, and control logic configured to drive an input / output contact pad to a desired voltage level based on the data signal and the output activation signal.

[0010] To ensure the correct signal sequence of the data signal and the output activation signal, some embodiments employ two separate (first and second) power-on control signals to control the first and second level shifters, respectively. The gating circuit can generate the data signal and the output activation signal and can control their signal sequence to ensure that: the first power-on control signal allows the first level shifter to generate the data signal before the second power-on control signal allows the second level shifter to generate the output activation signal. In this way, no interference pulse occurs during the I / O circuit startup process because the data signal is ready and active before the output activation signal is ready and active.

[0011] In one embodiment of the present teaching, the gating circuit comprises a first transistor controlled by the data signal, a second transistor controlled by the power-on control signal, which is a logical inversion or complement of the first power-on control signal, and a first inverter configured to generate the second power-on control signal based on the outputs of the first and second transistors. The structure of the gating circuit ensures that the second power-on control signal is generated based on whether the data signal has reached a stable logic state, thereby preventing interference pulses in the I / O circuit.

[0012] In another embodiment of the present teaching, the gating circuit comprises a series circuit with an even number of inverters connected in series. The series circuit receives the first turn-on control signal as an input signal and generates the second turn-on control signal as an output signal. The even number is chosen to be high enough to ensure that the second turn-on control signal is generated after the data signal has reached a stable logic state.

[0013] The present disclosure is applicable to any I / O circuit, e.g., a general purpose input / output (GPIO) circuit in an integrated chip. In some embodiments, the power-on control signal is generated by an internal block of the IC chip, so that purchasers of the IC chip do not have to expend any additional effort to control the signal sequence. Furthermore, the gating circuit disclosed herein occupies only a small area compared to the total area of ​​the I / O circuit, and thus has minimal or no area impact on the I / O circuit. Moreover, the gating circuit has no voltage effect on the normal operation of the I / O circuit and thereby avoids interference pulses during the startup of the I / O circuit.According to some embodiments of the present teaching, the I / O circuit comprises one or more further gating circuits which are configured to generate more power-on control signals and to control a signal sequence of all power-on control signals, based on a predetermined design, to ensure a desirable temporal sequence of signals in the I / O circuit.

[0014] Fig. Figure 1 illustrates an exemplary block diagram of a circuit 100 connected to an input / output contact pad 190, according to some embodiments of the present disclosure. According to one embodiment, the circuit 100 can be part of a chip in an IC system. The chip can communicate with other chips in the system via the I / O contact pad 190, controlled by the I / O circuit 100. As shown in Figure 1, the circuit 100 is connected to an input / output contact pad 190, which is controlled by the I / O circuit 100. Fig. As shown in Figure 1, the circuit 100 comprises two sections: a core section 110 with a first voltage domain and an I / O section 120 with a second voltage domain.

[0015] In this example, the core section 110 includes a first buffer 111, which receives an input data signal I and generates a smoothed data signal with the same voltage level as the input data signal I. The input data signal I can be generated by a core circuit connected to the first buffer 111. The core circuit (not shown) performs a core function of the chip according to the customer design. The core circuit generates the input data signal I to output data to another chip via the I / O contact pad 190. The input data signal I generated by the core circuit has a voltage within a core domain, e.g., 0 V to 0.75 V.

[0016] In this example, core section 110 also includes a second buffer 112, which receives an output activation signal OE and generates a smoothed OE signal with the same voltage level as the output activation signal OE. The output activation signal OE is also generated by the core circuit connected to the second buffer 112. The core circuit generates the output activation signal OE to control data output to another chip via the I / O contact pad 190. The output activation signal OE generated by the core circuit has a voltage within the core domain, e.g., 0 V to 0.75 V.

[0017] In this example, the I / O section 120 includes a first level shifter 121, which is connected to the first buffer 111 and receives the smoothed data signal from the first buffer 111. The first level shifter 121 can shift the smoothed data signal from the core voltage domain to an I / O voltage domain, e.g., from 0 V to 1.98 V. In this example, the I / O voltage domain is higher than the core voltage domain, so the first level shifter 121 can shift the smoothed data signal from a low voltage state to a high voltage state. That is, the first level shifter 121 is a level-up shifter in this example. The shift operation on the first level shifter 121 is controlled by a power-on control (POC) signal POC1 123. The shift operation is performed after being triggered by the POC1 signal 123. That means a change of state (e.g.(from a high voltage state to a low voltage state) of the POC1 signal 123 enables the first level shifter 121 to shift the smoothed data signal from the core voltage domain into the I / O voltage domain and generate a high-level data signal I_up within the I / O voltage domain. The high-level data signal I_up is to be sent to or output via the I / O contact pad 190 to another chip.

[0018] In this example, the I / O section 120 also includes a second level shifter 122, which is connected to the second buffer 112 and receives the smoothed OE signal from the second buffer 112. The second level shifter 122 can shift the smoothed OE signal from the core voltage domain to the I / O voltage domain, e.g., from 0 V to 1.98 V. In this example, the I / O voltage domain is higher than the core voltage domain, so the second level shifter 122 can shift the smoothed OE signal from a low voltage state to a high voltage state. That is, the second level shifter 122 is a level-up shifter in this example. The shift operation on the second level shifter 122 is controlled by a power-on control (POC) signal POC2 124. The shift operation is performed after being triggered by the POC2 signal 124. That means a change of state (e.g.(from a high voltage state to a low voltage state) of the POC2 signal 124 enables the second level shifter 122 to shift the smoothed OE signal from the core voltage domain into the I / O voltage domain and generate a high-level OE signal OE_up within the I / O voltage domain. The high-level OE signal OE_up is used to control the data output of the high-level data signal I_up to another chip via the I / O contact pad 190.

[0019] The POC1 signal 123 and the POC2 signal 124 are two separate signals that can control the level shifts of the first level slider 121 and the second level slider 122, respectively. A gating circuit (in Fig. The gating circuit (not shown in Figure 1), which will be described in detail later, can be used to control a signal sequence of the POC1 signal 123 and the POC2 signal 124. Similarly, the gating circuit can also control a signal sequence of the high-level data signal I_up and the high-level OE signal OE_up. Specifically, the gating circuit can ensure that the high-level OE signal OE_up is generated after the high-level data signal I_up has been generated and a stable logic state has been reached, in order to prevent interference pulses from occurring during a circuit startup procedure. During a startup procedure, the voltage of the I / O circuit and the voltage of the core circuit are increased. This can occur when the integrated circuit on the chip is powered on and begins to operate. After the startup procedure, the circuit begins normal operations.The POC1 signal 123 and the POC2 signal 124 do not affect the normal operations of the circuit because they are kept in a low logic state and allow the first level shifter 121 and the second level shifter 122 to operate normally.

[0020] In this example, the I / O section 120 also includes a control logic circuit 126, which is connected to the first level slider 121 and the second level slider 122 and is configured to drive the I / O contact pad 190 to a voltage level based on the data signal I_up and the output activation signal OE_up. That is, the control logic circuit 126 can output the data signal I_up via the I / O contact pad 190 in response to the output activation signal OE_up. Specifically, if the output activation signal OE_up is not acknowledged, the control logic circuit 126 is in a tristate mode and does not drive the I / O contact pad 190. When the output activation signal OE_up is acknowledged, the control logic circuit 126 drives the I / O contact pad 190 to a voltage level and / or a logical state corresponding to the data signal I_up.

[0021] Although in Fig. Not shown in Figure 1, the circuit 100 can also include an input buffer located in the I / O section 120 to receive an input signal from another chip via the I / O contact pad 190 and drive the input signal to a level shifter in the core section 110. The level shifter can shift the input signal from the I / O voltage domain to the core voltage domain so that the core circuit receives the input signal with the correct voltage domain.

[0022] During a startup process, two possible scenarios can occur in the I / O circuit. Fig. Figure 2A illustrates an example of the I / O circuit's behavior according to a first scenario during a startup procedure. As shown in Fig. As shown in Figure 2A, during the ramp-up process, the I / O voltage 202 of I / O section 120 initially rises to a high voltage state within the I / O voltage domain. The POC voltage 206 rises along with the I / O voltage 202. Then, the core voltage 204 of core section 110 rises to a high voltage state within the core voltage domain. During the core voltage 204 ramp-up process, the POC voltage 206 is reduced to a low voltage state. In this example, a POC signal is used to enable shift operations on both the first level shifter 121 and the second level shifter 122 after the POC voltage 206 reaches a low voltage state. That is, in response to the low voltage state of the POC voltage 206, the first level shifter 121 and the second level shifter 122 begin to operate normally as level-up shifters to raise the voltage levels of the I_up signal 210 and 212 respectively.to shift the OE_up signal 220 upwards. Here, the same POC signal acts as a gating signal for both the first level shifter 121 and the second level shifter 122 before the voltages are ready. There is no control over the timing of the POC signal entering the first level shifter 121 and the second level shifter 122. Although generated as a single signal, the POC signal can enter the first level shifter 121 and the second level shifter 122 at different times, so the I_up signal 210 and the OE_up signal 220 can rise to a high voltage state at different times.

[0023] For example, in the scenario that is in Fig. As shown in Figure 2A, the I_up signal 210 rises from the low voltage state L to the high voltage state H at time t1, while the OE_up signal 220 rises from the low voltage state L to the high voltage state H at time t2 after time t1. In this case, no noise pulse occurs during startup because the contact pad voltage 230 of the I / O contact pad 190 rises smoothly from a reference voltage state Z to a high voltage state H along with the rise in the voltage of the OE_up signal 220. This is because the I_up signal 210 has reached a stable high voltage state before the OE_up signal 220 rises to the high voltage state, so that when the OE_up signal 220 reaches the high voltage state to be confirmed, the contact pad voltage 230 of the I / O contact pad 190 is driven directly to a high voltage state according to the stable high voltage state of the I_up signal 210.

[0024] Fig. Figure 2B illustrates another exemplary circuit behavior of the I / O circuit according to a second scenario during a startup procedure. As shown in Fig. As shown in Figure 2B, the I / O voltage 202 of I / O section 120 initially rises to a high voltage state within the I / O voltage domain during the ramp-up process. During the core voltage ramp-up process 204, the POC voltage 206 is reduced to a low voltage state. Similar to the first scenario, this example uses a POC signal to enable shift operations on both the first level shifter 121 and the second level shifter 122 after the POC voltage 206 reaches a low voltage state. That is, in response to the low voltage state of the POC voltage 206, the first level shifter 121 and the second level shifter 122 begin operating normally as level-up shifters to shift the voltage levels of the I_up signal 210 and the OE_up signal 220 upwards, respectively.As described above, the same POC signal acts as a gating signal for both the first level slider 121 and the second level slider 122 before the voltages are ready; and there is no control over the timing of the POC signal entering the first level slider 121 and the second level slider 122. Although generated as a single signal, the POC signal can enter the first level slider 121 and the second level slider 122 at different times, so that the I_up signal 210 and the OE_up signal 220 can rise to a high voltage state at different times.

[0025] For example, in the scenario that is in Fig. As shown in Figure 2B, the OE_up signal 220 rises from the low voltage state L to the high voltage state H at time t1, while the I_up signal 210 rises from the low voltage state L to the high voltage state H at time t2 after time t1. In this case, a noise pulse 250 occurs during startup because the contact pad voltage 230 of the I / O contact pad 190 initially forms a voltage spike and then rises with the increase in the voltage of the I_up signal 210 from a reference voltage state Z to a high voltage state H. This is because the I_up signal 210 rises to the high voltage state after the OE_up signal 220 rises to the high voltage state, so that when the OE_up signal 220 reaches the high voltage state to be confirmed, the contact pad voltage 230 of the I / O contact pad 190 is not directly driven to the high voltage state, since the I_up signal 210 is still at a low voltage.In this case, the OE signal drives an incorrect I_up state into the I / O contact pad. Subsequently, when the I_up signal 210 rises to the high voltage at t2, the contact pad voltage 230 of the I / O contact pad 190 is driven to the high voltage state according to the high voltage state of the I_up signal 210.

[0026] To prevent this interference pulse 250 as in Fig. 2B to avoid and to ensure that the circuit behavior during a startup procedure is always the same as in the first scenario in Fig. 2A, the present teaching discloses various embodiments of a gating circuit for generating two separate POC signals for controlling the first level slider 121 or the second level slider 122 and for controlling the signal sequence of the two separate POC signals.

[0027] Fig. Figure 3 illustrates an example gating circuit 300 in an input / output circuit, e.g., circuit 100 in Fig. 1, according to some embodiments of the present disclosure. As in Fig. As shown in Figure 3, the gating circuit 300 comprises six transistors 341, 342, 343, 344, 345, 346 and two inverters 332, 334. The gating circuit 300 includes a first transistor 341 and a second transistor 342 (e.g., an n-type MOSFET and a p-type MOSFET, respectively), which are jointly controlled by a logic inversion of the first turn-on control signal POC1 310. In this example, if the logic inversion of the POC1 signal 310 is inverted again when it enters the first transistor 341, the first transistor is effectively controlled by the POC1 signal 310. The gating circuit 300 includes a third transistor 343, which is connected to the second transistor 342 and is controlled by a logic inversion of the signal I 304. The gating circuit 300 includes a fourth transistor 344 (e.g. an n-type MOSFET) which is controlled by the signal I_up 306.The gating circuit 300 includes a fifth transistor 345 (e.g. an n-type MOSFET) which is connected to the fourth transistor 344 and is controlled by the signal I 302.

[0028] The gating circuit 300 includes a first inverter 331, which is configured to generate the second turn-on control signal POC2 320 based on the outputs of one or more of the six transistors. The gating circuit 300 also includes a second inverter 332, which is connected between the first transistor 341 and the first inverter 331. The gating circuit 300 further includes a sixth transistor 346, which is connected to the fifth transistor 345 and is controlled by an output signal from the second inverter 332.

[0029] With this exemplary gating circuit structure 300, the second turn-on control signal POC2 320 is activated after the first turn-on control signal POC1 is activated. In this example, the POC1 signal is first activated, i.e., switched from a high voltage state to a low voltage state. Correspondingly, the logic inversion of the first turn-on control signal POC1 is applied as an input signal to the first transistor 341 and the second transistor 342, switching from a low voltage state to a high voltage state. Then, the first transistor 341 is switched off and the second transistor 342 is switched on. Thus, the input to the second inverter 332 is switched from a high voltage state to a low voltage state. Then, the input to the first inverter 331 is switched from a low voltage state to a high voltage state.Accordingly, the output of the first inverter 331 is switched from a high voltage state to a low voltage state, i.e., the second turn-on control signal POC2 320 is activated. Therefore, signal POC2 320 is activated after signal POC1 is activated. The third transistor 343, the fourth transistor 344, the fifth transistor 345, and the sixth transistor 346 can help control the gating circuit 300. For example, by connecting the control terminal of the sixth transistor 346 to the output of the second inverter 332, the drain terminal of the fourth transistor 344 is stabilized after the turn-on process.

[0030] In the example above, the first level shifter 121 begins to operate normally as a level-up shifter to raise the voltage level of the I_up signal 306 as soon as the POC1 signal is activated and switched to a low-voltage state. Similarly, the second level shifter 122 begins to operate normally as a level-up shifter to raise the voltage level of the OE_up signal 306 as soon as the POC2 signal is activated and switched to a low-voltage state. Since the structure of the gating circuit 300 ensures that the POC2 signal 320 is activated after the POC1 signal is activated, it also ensures that the OE_up signal is generated or raised in response to the POC2 signal 320 after the I_up data signal is generated or raised in response to the POC1 signal, thus preventing interference pulses from occurring during a startup procedure.According to various embodiments of the present teachings, one or more components (transistors or inverters) of the gating circuit 300 can be removed or replaced without affecting the temporal dependence between the two POC signals, so that the gating circuit 300 can still prevent interference pulses from occurring during the startup procedure.

[0031] Fig. Figure 4 illustrates an example layout of a gating circuit, e.g., the 300 gating circuit in Fig. 3, in an input / output circuit according to some embodiments of the present disclosure. As in Fig. As shown in Figure 4, the layout can include an n-type metal oxide semiconductor (NMOS) 410 and an n-type metal oxide semiconductor (PMOS) 420, as illustrated by example. The layout in Fig. 4 comprises an oxide diffusion (OD) layer 430, a polysilicon (PO) layer 432 formed over the OD layer 430, and a metal-over-oxide (MD) layer 434 formed over the OD layer 430. Various components of the gating circuit 300 in Fig. 3 are marked at corresponding sections of the layout. For example, transistor 341 is implemented on the PMOS section 420; while transistors 342, 343, 344, 345, and 346 are implemented on the NMOS section 410. The first inverter 331 comprises both an NMOS part 331.N, implemented on the NMOS section 410, and a PMOS part 331.P, implemented on the PMOS section 420. Similarly, the second inverter 332 comprises both an NMOS part 332.N, implemented on the NMOS section 410, and a PMOS part 332.P, implemented on the PMOS section 420. The layout further includes a metal null (Mo) layer 436, which is formed on the PO layer and the MD layer 434. and comprises a metal-one (M1) layer 438 formed on the molybdenum layer 436. Both the molybdenum layer 436 and the M1 layer 438 include metal conductors that connect the various components of the gating circuit. As in Fig. As shown in Figure 4, an I / O power supply pin (VDDPST) in the PMOS section 420 is connected to the Mo layer 436; while a ground reference pin (VSS) in the NMOS section 410 is connected to the M1 layer 438.

[0032] The logical complement of the POC1 signal 310 and the POC2 signal 320 are controlled such that they exhibit a specific time-dependent relationship, as described above, based on the exemplary layout shown in Fig. Figure 4 illustrates this. In one embodiment, the layout of the gating circuit occupies only an area smaller than a predetermined percentage (e.g., 0.5%, 1%, etc.) of the total area of ​​the I / O circuit. Thus, the gating circuit has little or no impact on the implementation area of ​​the I / O circuit. The Fig. The layout shown in Figure 4 is just one example of how to implement the 300 gating circuit. Fig. 3 and according to different embodiments of the present teaching, other layouts can be used to implement the gating circuit 300 in Fig. 3 to realize.

[0033] Fig. Figure 5 illustrates another example gating circuit 500 in an input / output circuit, e.g., circuit 100 in Fig. 1, according to some embodiments of the present disclosure. As in Fig. As shown in Figure 5, the gating circuit 500 in this example comprises a series connection with an even number of inverters 510, 520 connected in series. The series connection receives the first turn-on control signal POC1 123 as an input signal and generates the second turn-on control signal POC2 124 as an output signal. The even number of inverters can provide a time delay between the POC1 signal 123 and the POC2 signal 124 and ensure a corresponding logic state between the POC1 signal 123 and the POC2 signal 124. In one embodiment, the even number can be chosen to be high enough to ensure a sufficient time delay between the POC1 signal 123 and the POC2 signal 124 so that the POC2 signal 124 is generated after the POC1 signal 123 has reached a stable logic state.

[0034] According to some embodiments of the present teaching, the I / O circuit comprises one or more further gating circuits, each of which has a structure like those described in Fig. 3 or Fig. Figure 5 illustrates this. These gating circuits are designed to generate POC signals and control the sequence of all POC signals based on a predefined design to ensure a desirable timing sequence of signals in the I / O circuit. The desired timing sequence can apply to one or more signals other than the data signal and the output activation signal.

[0035] Fig. Figure 6 illustrates an example of circuit behavior during the startup of an input / output circuit, e.g., circuit 100 in Fig. 1, according to some embodiments of the present disclosure. As in Fig. As shown in Figure 6, the I / O voltage 602 of I / O section 120 initially rises to a high voltage state within the I / O voltage domain during the startup process. The first POC voltage of POC1 606 and the second POC voltage of POC2 608 rise along with the I / O voltage 602. In this example, two separate POC signals, POC1 and POC2, are used to enable shift operations on the first level shifter 121 and the second level shifter 122, respectively, as shown in Figure 6. Fig. Figure 1 shows that, in response to a low voltage state of the POC1 signal 606, the first level shifter 121 begins to operate normally as a level-up shifter to raise the voltage level of the I_up signal 610; and in response to a low voltage state of the POC2 signal 608, the second level shifter 122 begins to operate normally as a level-up shifter to raise the voltage level of the OE_up signal 620.

[0036] After the I / O voltage 602 rises to a high voltage state, the core voltage 604 of core section 110 rises to a high voltage state within the core voltage domain. During the process of increasing the core voltage 604, the POC voltage of POC1 606 is reduced to a low voltage state, e.g., due to a control signal from the gating circuit. In response to the low voltage state of the POC1 signal 606, the first level shifter 121 begins to operate normally as a level-up shifter to raise the voltage level of the I_up signal 610. As shown in Fig. As shown in Figure 6, the I_up signal 610 rises from the low voltage state L to the high voltage state H after the POC1 606 has been lowered to the low voltage state.

[0037] As described above, the gating circuit controls the timing for generating the two POC signals: POC1 signal 606 and POC2 signal 608. POC1 signal 606 is generated at a low voltage before POC2 signal 608 is generated at a low voltage. Thus, POC1 signal enters the first level switch 121 to enable the generation of I_up signal 610, before POC2 signal enters the second level switch 122 to enable the generation of OE_up signal 620. Here, the two POC signals act as gating signals for the first level switch 121 and the second level switch 122, respectively, before the voltages are ready.

[0038] As in Fig. As shown in Figure 6, after the I_up signal 610 reaches a stable high voltage state H, the POC2 signal 608 is lowered to the low voltage state to trigger the normal operation of the second level shifter 122. The second level shifter 122 then shifts the voltage level of the OE_up signal 620 from the low voltage state L to the high voltage state H. As described above, this time-dependent relationship between the POC1 signal 606 and the POC2 signal 608 ensures that no interference pulse can occur during the I / O circuit startup process.Specifically, according to this embodiment, the temporal signal sequence of the I / O circuit comprises the following sequence: the POC1 signal is activated by lowering it to a low voltage state, the I_up data signal is activated by raising it to a high voltage state, the POC2 signal is activated by lowering it to a low voltage state, and the OE_up signal is activated by raising it to a high voltage state.

[0039] Fig. Figure 7 illustrates an example of detailed circuit behavior during the startup of an input / output circuit, e.g., circuit 100 in Fig. 1, according to some embodiments of the present disclosure. As in Fig. As shown in Figure 7, the I / O voltage 702 initially rises to a high voltage state within the I / O voltage domain during the startup process. The first POC voltage of POC1 706 and the second POC voltage of POC2 708 follow the I / O voltage 702 and also rise to the high I / O voltage domain. In this example, two separate POC signals, POC1 and POC2, are used to enable shift operations on the first level shifter 121 and the second level shifter 122, respectively, as shown in Figure 7. Fig. Figure 1 illustrates this. That is, in response to a low voltage state of the POC1 signal 706, the first level shifter 121 begins to operate normally as a level-up shifter to raise the voltage level of the I_up signal 710; and in response to a low voltage state of the POC2 signal 708, the second level shifter 122 begins to operate normally as a level-up shifter to raise the voltage level of the OE_up signal 720.

[0040] After the I / O voltage 702 rises to a high voltage state, the core voltage 704 of core section 110 rises to a high voltage state within the core voltage domain. During the process of increasing the core voltage 704, the POC voltage of POC1 706 is reduced to a low voltage state, for example, due to a control signal from the gating circuit. The circuit behavior within section 790 is shown in more detail in the corresponding enlarged view 792. As shown in the detailed view 792, in response to the low voltage state of the POC1 signal 706, the voltage level of the I_up signal 710 is increased to a high voltage state. In this example, the first level shifter 121 moves the data signal I 711 from a low core voltage domain 0.75 V to a high I / O voltage domain 1.8 V, so that it becomes the level-high data signal I_up 710.

[0041] As described above, the gating circuit controls the timing for generating the two POC signals: POC1 signal 706 and POC2 signal 708. POC1 signal 706 is generated at a low voltage before POC2 signal 708 is generated at a low voltage. Thus, POC1 signal enters the first level switch 121 to enable the generation of I_up signal 710, before POC2 signal enters the second level switch 122 to enable the generation of OE_up signal 720. Here, the two POC signals act as gating signals for the first level switch 121 and the second level switch 122, respectively, before the voltages are ready.

[0042] As shown in the enlarged view 792, after the POC1 signal is reduced to a low voltage state, the POC2 signal 708 is reduced to a low voltage state to trigger the normal operation of the second level shifter 122. Then, in response to the low voltage state of the POC2 signal 708, the voltage level of the OE_up signal 720 is increased to a high voltage state. In this example, the second level shifter 122 moves the OE signal 721 from a low core voltage domain of 0.75 V to a high I / O voltage domain of 1.8 V, thus becoming the high-level OE signal OE_up 720.As described above, this time-dependent relationship between the POC1 signal 706 and the POC2 signal 708 ensures that no disturbance pulse can occur at the contact pad voltage 730 during the I / O circuit startup procedure, as the high-level OE signal OE_up 720 is activated to reach the high voltage state after the high-level data signal I_up 710 is activated to reach the high voltage state.

[0043] As in Fig. As shown in Figure 7, the time interval from the voltage change of the POC1 signal 706 to the voltage change of the POC2 signal 708 is approximately 30 nanoseconds, which is much shorter than a typical startup time, e.g., 100 microseconds. Therefore, the disclosed control of the timing of the POC1 signal 706 and the POC2 signal 708 does not affect the startup time of the I / O circuit.

[0044] Fig. Figure 8 illustrates an exemplary block diagram of another circuit 800 connected to an input / output contact pad, according to some embodiments of the present disclosure. According to one embodiment, the circuit 800 can be part of a chip in an IC system. The chip can communicate with other chips in the system via the I / O contact pad 890, controlled by the I / O circuit 800. As shown in Fig. As shown in Figure 8, the circuit 800 comprises two sections: a core section 810, which has a first voltage domain, and an I / O section 820, which has a second voltage domain.

[0045] In this example, the core section 810 includes a first buffer 811, which receives an input data signal I and generates a smoothed data signal with the same voltage level as the input data signal I. The input data signal I can be generated by a core circuit connected to the first buffer 811. The core circuit (not shown) performs a core function of the chip according to the customer's design. The core circuit generates the input data signal I to output data to another chip via the I / O contact pad 890. The input data signal I generated by the core circuit has a voltage within a core domain, e.g., 0 V to 0.75 V.

[0046] In this example, the core section 810 also includes a second buffer 812, which receives an output activation signal OE and generates a smoothed OE signal with the same voltage level as the output activation signal OE. The output activation signal OE is also generated by the core circuit connected to the second buffer 812. The core circuit generates the output activation signal OE to control data output to another chip via the I / O contact pad 890. The output activation signal OE generated by the core circuit has a voltage within the core domain, e.g., 0 V to 0.75 V.

[0047] In this example, the I / O section 820 includes a first level shifter 821, which is connected to the first buffer 811 and receives the smoothed data signal from the first buffer 811. The first level shifter 821 can shift the smoothed data signal from the core voltage domain to an I / O voltage domain, e.g., from 0 V to 1.98 V. In this example, the I / O voltage domain is higher than the core voltage domain, so the first level shifter 821 can shift the smoothed data signal from a low voltage state to a high voltage state. That is, the first level shifter 821 is a level-up shifter in this example. The shift operation on the first level shifter 821 is controlled by a POC signal 823. The shift operation is performed after a trigger by the POC signal 823. That is, a change in state (e.g.,(from a high voltage state to a low voltage state) of the POC signal 823 enables the first level shifter 821 to shift the smoothed data signal from the core voltage domain to the I / O voltage domain and generate a high-level data signal I_up within the I / O voltage domain. The high-level data signal I_up is to be sent to or output from another chip via the I / O contact pad 890.

[0048] In this example, the I / O section 820 also includes a second level shifter 822, which is connected to the second buffer 812 and receives the smoothed OE signal from the second buffer 812. The second level shifter 822 can shift the smoothed OE signal from the core voltage domain to the I / O voltage domain, e.g., from 0 V to 1.98 V. In this example, the I / O voltage domain is higher than the core voltage domain, so the second level shifter 822 can shift the smoothed OE signal from a low voltage state to a high voltage state. That is, the second level shifter 822 is a level-up shifter in this example. The shift operation on the second level shifter 822 is also controlled by the POC signal 823. The shift operation is performed after being triggered by the POC signal 823. That means a change of state (e.g.(from a high voltage state to a low voltage state) of the POC signal 823 allows the second level shifter 822 to shift the smoothed OE signal from the core voltage domain into the I / O voltage domain, generating a high-level OE signal OE_up within the I / O voltage domain. This high-level OE signal OE_up is used to control the data output of the high-level data signal I_up to another chip via the I / O contact pad 890.

[0049] Although the same POC signal serves as a gating signal for both the first level shifter 821 and the second level shifter 822 before the voltages are ready, the I / O section 820 also includes a delay circuit 825, which is connected to the second level shifter 822 and is configured to generate a delayed OE_up signal based on the OE_up signal output by the second level shifter 822. In this embodiment, the delay circuit 825 includes a capacitor C_OE connected to an output of the second level shifter 822. The capacitor C_OE can be configured to have a capacitance high enough to ensure that the delayed OE_up signal is generated after the data signal I_up has reached a stable logic state.Accordingly, the delay circuit 825 can control the delay of the high-level OE signal OE_up to enter the control logic circuit 126 with a high voltage state after the high-level data signal I_up enters the logic circuit 126 with a stable high voltage logic state, in order to prevent interference pulses from occurring during an I / O circuit startup procedure. According to various embodiments, the delay circuit 825 can have a structure that differs from that shown in [reference]. Fig. The 8 shown differs, and still achieves a time delay effect for the high-level OE signal OE_up. For example, the 825 delay circuit can exhibit a time delay effect based on at least one of: a resistor, a capacitor, a transistor, a diode, and a timer.

[0050] In this example, the I / O section 820 also includes a control logic circuit 826, which is connected to the first level slider 821 and the second level slider 822 and is configured to drive the I / O contact pad 890 to a voltage level based on the data signal I_up and the delayed OE_up signal. That is, the control logic circuit 826 can output the data signal I_up via the I / O contact pad 890 in response to the delayed OE_up signal. Specifically, if the delayed OE_up signal is not acknowledged, the control logic circuit 826 is in a tristate mode and does not drive the I / O contact pad 890. When the delayed OE_up signal is acknowledged, the control logic circuit 826 drives the I / O contact pad 890 to a voltage level and / or a logic state corresponding to the data signal I_up. Although in Fig. Not shown, circuit 800 may also include an input buffer located in I / O section 820 to receive an input signal from another chip via I / O contact pad 890 and drive the input signal to a level shifter in core section 810. The level shifter can shift the input signal from the I / O voltage domain to the core voltage domain for the core circuit to receive the input signal with the correct voltage domain.

[0051] Fig. Figure 9 is a flowchart illustrating an exemplary method 900 for preventing interference pulses in a circuit connected to an input / output contact pad, according to some embodiments of the present disclosure. In operation 902, a first power-on control (POC) signal is connected to a first level shifter in an input / output circuit. In operation 904, a first input signal is shifted from a first voltage domain to a second voltage domain to generate a data signal in response to the first POC signal. In operation 906, a second POC signal is connected to a second level shifter in the input / output circuit. In operation 908, a second input signal is shifted from the first voltage domain to the second voltage domain to generate an output activation signal in response to the second POC signal.In operation 910, an input / output contact pad is driven to a voltage based on the data signal and the output activation signal. The sequence of operations described in... Fig. The representations in Figure 9 can be modified according to various embodiments of the present disclosure.

[0052] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Circuit (100) connected to an input / output contact pad (190), comprising: a first level switch (121) which is set up to generate a data signal (I_up); a second level slider (122) which is configured to generate an output activation signal (OE_up), wherein the first level slider is controlled by a first power-on control signal (POC1) and the second level slider (121, 122) is controlled by a second power-on control signal (POC2); a gating circuit (300, 500) configured to generate the first and second power-on control signals (POC1, POC2) and to control a signal sequence of the first and second power-on control signals (POC1, POC2) such that the first power-on control signal (POC1) allows the first level shifter (121) to generate the data signal (I_up) before the second power-on control signal (POC2) allows the second level shifter (122) to generate the output activation signal (OE_up); and a control logic circuit (126) which is connected to the first level slider (121) and the second level slider (122) and is configured to drive the input / output contact pad (190) to a voltage level based on the data signal (I_up) and the output activation signal (OE_up). [2] Circuit (100) according to claim 1, wherein: the first level shifter (121) is configured to receive a first input signal on a first voltage domain and, in response to the first turn-on control signal (POC1), to shift the first input signal to a second voltage domain in order to generate the data signal (I_up); and the second level shifter (122) is configured to receive a second input signal on the first voltage domain and, in response to the second power-on control signal (POC2), shift the second input signal to the second voltage domain to generate the output activation signal (OE_up). [3] Circuit (100) according to claim 2, wherein the second voltage domain is higher than the first voltage domain. [4] Circuit (100) according to claim 2 or 3, wherein the circuit has a first buffer (111) connected to the first level shifter (121), wherein the first buffer (111) is configured to receive and smooth an input data signal, and wherein the first level shifter (121) is configured to receive the smoothed input data signal as the first input signal. [5] Circuit (100) according to any of the preceding claims, wherein the gating circuit (300) comprises: a first transistor (344) which is controlled by the data signal (I_up); a second transistor (342) which is controlled by a signal that is a logical inversion of the first power-on control signal (POC1); and a first inverter (331) which is configured to generate the second power-on control signal (POC2) based on outputs of the first transistor (344) and the second transistor (341), so that the second power-on control signal (POC2) is generated based on whether the data signal (I_up) has reached a stable logic state. [6] Circuit (100) according to claim 5, wherein the gating circuit (300) further comprises: a second inverter (332) which is connected between the second transistor (342) and the first inverter (331); a third transistor (345) which is connected to the first transistor and is controlled by an input signal from the first level shifter (121); a fourth transistor (343) which is connected to the first transistor and is controlled by a signal which is a logical inversion of the input signal of the first level shifter; a fifth transistor (341) which is connected to the second transistor and is controlled by the first power-on control signal (POC1); and a sixth transistor (346) which is connected to the first transistor (344) and is controlled by an output signal from the second inverter (332). [7] Circuit (100) according to one of the preceding claims, wherein: the gating circuit (500) comprises a series circuit which has an even number of inverters (510, 520) connected in series; The series circuit receives the first power-on control signal (POC1) as an input signal and generates the second power-on control signal (POC2) as an output signal; and the even number is high enough to ensure that the second power-on control signal (POC2) is generated after the first power-on control signal (POC1) allows the first level slider (121) to generate the data signal (I_up). [8] Circuit (100) according to one of the preceding claims, wherein the gating circuit (300, 500) occupies an area which is less than 1% of the total area of ​​the circuit (100). [9] Circuit (100) according to one of the preceding claims, wherein the gating circuit (300, 500) does not affect the performance of the circuit (100) according to a method of starting up the circuit. [10] Circuit (100) according to one of the preceding claims, further comprising a further gating circuit which is configured to generate a further switch-on control signal and to control a signal sequence of all switch-on control signals on the basis of a predetermined design. [11] Circuit (100) according to one of the preceding claims, wherein the control logic circuit (126) is configured to drive the input / output contact pad (190) to a voltage level corresponding to the data signal (I_up) when the output activation signal (OE_up) is acknowledged. [12] Circuit (800) connected to an input / output contact pad (890), comprising: a first level switch (821) which is set up to generate a data signal (I_up); a second level slider (822) configured to generate an output activation signal (OE_up), wherein the first and second level sliders (821, 822) are controlled by a power-on control signal (POC); and a delay circuit (825) connected to the second level shifter (122) and configured to generate a delayed output activation signal based on the output activation signal (OE_up), wherein the delay circuit (825) includes a capacitor connected to an output of the second level shifter (822), and wherein the capacitor has a capacitance high enough to ensure that the delayed output activation signal is generated after the data signal (I_up) has reached a stable logic state; and a control logic circuit (826) which is connected to the first level slider (821) and the second level slider (822) and is configured to drive the input / output contact pad (890) to a voltage level based on the data signal (I_up) and the delayed output activation signal. [13] Circuit (800) according to claim 12, wherein: the first level shifter (821) is configured to receive a first input signal on a first voltage domain and, in response to the first power-on control signal (POC), to shift the first input signal to a second voltage domain in order to generate the data signal (I_up); and The second level shifter is configured to receive a second input signal on the first voltage domain and, in response to the second power-on control signal (POC), shift the second input signal to the second voltage domain to generate the output activation signal (OE_up). [14] Circuit (800) according to claim 13, wherein the second voltage domain is higher than the first voltage domain. [15] Circuit (800) according to one of claims 12 to 14, wherein the delayed output activation signal is generated after the data signal (I_up) has been generated. [16] Circuit (800) according to one of claims 13 to 15, wherein the circuit has a first buffer (811) connected to the first level shifter (821), wherein the first buffer (811) is configured to receive and smooth an input data signal, and wherein the first level shifter (821) is configured to receive the smoothed input data signal as the first input signal. [17] Method for preventing interference pulses in a circuit (100) connected to an input / output contact pad (190), comprising: Connecting a first power-on control signal (POC1) to a first level slider (121) in the circuit (100); In response to the first power-on control signal (POC1), a first input signal is shifted from a first voltage domain to a second voltage domain to generate a data signal (I_up); Connecting a second power-on control signal (POC2) to a second level slider (122) in the circuit (100); In response to the second power-on control signal (POC2), a second input signal is shifted from the first voltage domain to the second voltage domain to generate an output activation signal (OE_up), wherein during a circuit startup procedure (100), the output activation signal (OE_up) is generated after the data signal (I_up) has reached a stable logic state; and Driving the input / output contact pad (190) to a voltage level based on the data signal (I_up) and the output activation signal (OE_up). [18] Method according to claim 17, wherein the second stress domain is higher than the first stress domain. [19] Method according to one of claims 17 or 18, further comprising: Generating the first power-on control signal (POC1); and Generating the second power-on control signal (POC2) after a time period that begins when the first power-on control signal (POC1) is generated, wherein the time period is within a procedure of starting up the circuit (100). [20] Method according to any one of claims 17 to 19, wherein the second power-on control signal (POC2) is generated by a gating circuit (300, 500), wherein the gating circuit is configured to control a signal sequence of the first power-on control signal (POCl) and the second power-on control signal (POC2).

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